S COTT T HORESON

540.522.1512 sthoreson@outlook.com

P R O C E S S , Y I E L D O R F A I L U R E A N AL Y S I S E N G I N E E R

P RO FE S S IO N AL S UMM AR Y
Sharp, innovative process and yield engineering professional with wide-ranging experience in the production
process accompanied by actively pursuing a degree in IT networking (scheduled graduation Dec. 2015). Strong
leadership and project management skills. Adept in Yield Enhancement (YE) for high-volume production fabrications
(FAB), R&D product integration, process development and equipment integration. Extensive background in statistical
data mining and statistical analysis. Proven track record of determining root-cause failures and implementing corrective
actions. Skilled at leading large teams of engineers and technicians to improve efficiency and throughput, writing
procedures to run high-volume part types through critical process steps, and leading Continuous Improvement Project
(CIP) teams in key Statistical Process Control (SPC) metrics. Effective communication skills.

ARE AS

OF

S T RE NG T H

In-depth Statistical Knowledge

Design of Experiments
Parametric Structure Design
Statistical Process Control (SPC)

Yield Enhancement (YE)

Defect Pareto Analysis
Data Mining
Technical Algorithms

Failure Analysis (Physical/Electrical)

Cycle-Time Reduction
Metrology Data Analysis
Best Process Techniques

N O T AB L E A C C O M P L I S H M E N T S

Increased tier-1 chip production 5% by heading a team of more than 10 engineers to develop a critical-level process
flow for a 17,000 300mm wafer-out fabrication (FAB).

Boosted circuit pack performance and part yields 5% by developing technical algorithms for a critical process
control of an automated Applied Material E3 R2R system.

Enhanced production yield 10-20% by initiating new processes through Special Work Requests (SWR)
implementation and analysis.

Saved $750,000 in new tool FAB costs by establishing new business rules on tool faults.
Decreased FAB tool downtime 10 days by designing new parametric structure to eliminate multiple FAB defects.

Reduced the amount of wafers scrapped for de-processing and increased Pareto data approximately 1 day by
implementing new Defect Pareto system used in a 30,000 wafer-out FAB.

E D U C AT I O N
Associate of Applied Science, Information Systems Technology (Networking), scheduled graduation Dec. 2015
Germanna Community College, Locust Grove, VA
Bachelor of Science, Engineering Physics, 1997
North Dakota State University, Fargo, ND
Professional Training:
Practical UNIX Stanford University, 2015
Six Sigma Certified Aveta Business Institute, 2014
Microsoft Excel II Germanna Community College, 2014
Project Management Essentials Germanna Community College, 2014
Introduction to C++ Boise State University, 2000
Electromagnetic Theory National Technology University, 1999

SCOTT THORESON

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P RO FE S S IO N AL E X P E R IE NCE
MICRON TECHNOLOGY

1998 2013

Process Engineer and Process Owner Engineer (Manassas, VA: 2008 2013)

Served as regular point-of contact in Dry Etch implementing Design of Experiments (DoE) and running wafers
through Special Work Requests (SWR).

Boosted shift certification in-process training 24% by effectively heading shift training and development for 5
engineers and 15 technicians.

Developed Best Known Methods (BKM) publication that identified corrective actions following Statistical
Process Control (SPC) out-of-control conditions.

Built new etch process recipes on Applied Material Dry Etch tools and established time tables to implantation
using Primavera Projects.

Generated projects and followed through with Research & Development on the introduction of new Flash and
Dynamic Random Access Memory (DRAM) part types in a 15,000 wafer-out 300mm FAB.

Authored best process technique manuals for manufacturing in high-volume 24/7 FABs.

Increased FAB yield and reduced cycle-time by creating and implementing a new process using DoE methods.

Defined business rules for optimizing tool sets to achieve maximum throughput and quality.

Created a fault-evaluation tool for highlighting better yields at probe (wafer) and test (packaged parts).

Yield Enhancement Engineer (Boise, ID: 1998 2008)

Headed multiple 7-engineer teams on corrective actions required for Flash and DRAM part types running
through a 30,000 wafer-out FAB.

Developed Lot Map Records minimizing wafer scrap at Probe and accounting for the die lost.

Established yield enhancement procedures for de-processing failing die on IRLabs Infrared Emission
Microscope (IREM), including back-grind of wafers to 10mil and de-capsulation.

Drove new parametric tests at probe to implement new probe bin definitions.

Implemented new YE Automated Pareto system to determine die out from probe and stabilize line yield.

Enhanced defect monitoring by driving RDA Klarity defect and ESDA Probe bitmaps merger.

Identified multiple root cause fails including reticle designs that eliminated fails (in-line and at probe).

Educated more than 50 engineers and technicians on Probe/Parametric testing techniques and device physics.

Created multiple scripts in JMP and Yield3 for data extraction.

Authored YE documents identifying Electrical Failure Analysis (EFA) of new part types on NexTest Maverick.

Oversaw daily Yield monitoring and SWR team to define best known processes.

Extracted/captured data through Physical Failure Analysis (PFA) and EFA setting Critical Dimension (CD) limits.