Verilog

(Basic Concepts)
1

3.1 (Lexical
Conventions)
Verilog C Verilog
(token)
(Comments)
(Delimiters) (Numbers)
(Strings)
(IIdentidiers) (Keywords)

3.1 (Lexical
Conventions)
3.1.1 (Whitespace)
: (Blank spaces \b) (Tabs
\t) (Newlines \n)
Verilog

3.1.2 (Comment)
(Readability)
(Documentation). : //
(One-line
Comment), /* */ (MultipleLine),
a=b &&
/*This
/*This
/*This

c;//This is a cone-line comment

is a multiple line Cooment
*/
is /* an illegal comment */
is //a legal comment */

3.1.3 (Operators)
: (Unary) (Binary)
(Ternary)

,
a=~b;
// ~ b
a=b && c // && b c
a=b ? c:d // ? b,c d
3.1.4 (Number specification)
Verilog (Sized), (Unsized)

 (Sized numbers)
<size><base format> <number>
<Size> (Bits) <base format>
(Bits) <base format>
(d D) (h H)
(b B) (o O),

4b1111 //
12habc //
16d255 //

4-bit
12-bit
16-bit

(Unsized numbers)
<size>
( 32 ) <base
format>
23456 // 32 bits
hc3 // 32 bits

o21 // 32 bits

xz
x z x

0 x z
1 0

12h13x // 12-bit ;

6hx // 6-bit
32bz // 32-bit
6

 (Negative numbers)
<size>

-8d3 //
-6sd3 //
4d-2 //

8-bit
(Signed Integer)

(Underscore characters) (Question marks)

_

? z ,
12b1111_0000_1010 // 12b111100001010
4b10?? // 4b10zz
7

3.1.5

(Strings)

Hello Verilog World //

a/b //
3.1.6 (Identifers) (Keywords)

( )

reg value ; //reg value

input clk; //input clk

3.2 (Data Types)

3.2.1 (value set)
Verilog (Value Level) 3-1
0 1 (Strengths) 3-2

0 (False)

1 (True)

(Unknown Value)

(High Impedance) (Floating

State)
3-1
9

supply

Driving

storng

Driving

pull

Driving

large

Storage

weak

Driving

medium

Storage

small

Storage

highz

High
impedance

3-2
10


(Driver) (Conflicts)
1. strong1 weak0
strong1
( strong1 )
2. strong1 strong0 x(
)
3. (Trireg Nets)
large medium small

11

3.2.2 (Nets)

3-1 a g1 b AND c

b
c

g1

3-1

12

 wire
z ( trireg x)
x
Net Wire
wire Verilog net
wire a;

// a

wire b,c; // b c
wire d=1b0;
// d 0
13

3.2.3 (registers)

Verilog

(hold)
Verilog

reg reset;
// (hold)
initial

//

begin
reset =1b1;

// reset 1

#100 reset=1b0;// 100 reset 0

end

14

3.2.4 (Vectors)
wire a
//
wire [7 0] bus
// 8-bit
wire [31 0] busA, busB, busC
//3 32-bit
reg clock //
reg [0 40] virtual_addr
// 41 bits

busA [7]
// A
bus [2:0]
//
bus [0:2]
virtual_addr [0:1] //
15

2.3.5
(Integer Real
and Time Register Data Types)

integer reg
integer
(counting)
32 reg (Unsigned) integer
(Signed)

real ( 3e6

) 0

time
16
(Simulation Time) 64bits

3.2.6 (Arrays)

<array_name>[<subscript>]

17

integer count[0:7] ;
//8
reg bool[31:0] ;
//32
time chk_point [1:100] ;
//100
reg [4:0] port_id [0:7];
//8 5
integer matrix [4:0] [0:255] ;
//
reg [63:0] array_4d [15:0] [7:0] [7:0] [255:0] ;
//
wire [7:0] w_array2 [5:0] ;
//6 8
wire w_array1[7:0] [5:0] ;
18
// 42


(Element)

count[5]=0;// count
chk_point[100]=0;
// chk_point
port_id[3]=0;
// port_id ( )
matrix [1][0]=33559;
// matix [1][0] 33559
array_4d [0][0][0][0][15:00]=0;
// array_4d [0][0][0][0]

// [15:0]
port_id=0;
//
matrix [1]=0;
// [1][0] [1][255] 19

3.2.7 (Memories)
Verilog
(Word) Bit
Bits
n 1Bit n Bits
(Subscript)

reg mem1bit [0:1023] ;

// mem1bit 1k
reg [7:0] membyte [0:1023];
// membyte 1k

membyte [511] // 511

20

3.2.8 (Parameters)
Verilog parameter

Parameter port_id =5
// port_id 5
Parameter cache_line_width =256
// cache_line_width 256
Parameter signed [15 0] WIDTH
// WIDTH
21

 defparam

Verilog 2001 localparam

defparam

localparam state1
state2
state3
state4

=
=
=
=

4b0001
4b0010
4b0100
4b1000
22

3.2.9 (Strings)

(reg)

3-3
reg [8*18:1] string_value // 18

initial
string_value=Hello Verilog World //

\n

\t

%%

\\

\
3-3

\ooo

1-3 23

3.3 (System Tasks)

(Compiler Directives)
Verilog
3.3.1

(System Tasks)

$<keyword>
IEEE 1364-2001

(Displaying information)
$display

24

 $display (p1,p2,p3,..,pn);
p1 p2 p3 pn
$display C printf
$display $display

(Format
Specifications List) 3-4
1364-2001

25


%d or %D

%b

or

%B

%s

or

%S

%h

or

%H

%c

or

%C

ASCII

%m

or

%v

or

%M ( )
%V

%o

or

%O

%t

or

%e

or

%T
%E

%f

or

%g

or

%F
%G
3-4

26

 3-3

//
%display (Hello Verilog World)
-- Hello Verilog World
//
%display ($time)
--230
// 1fe0000001c 200
reg [0 40] virtual
$display(At time %d virtual adderess is %h,$time,
virtual_adder);
--At time 200 virtual adderess is 1fe0000001c
// port_id 5
reg [0 40] port_id
$display(ID of the port is %b, port_id);
--ID of the port is 00101
27

// x
// 10xx
reg [3 0] bus
$display(Bus value is %b,bus);
--Bus value is 10xx
// top p1

//
$display(This string is displayed from %m level
of hierarchy)
--This string is displayed from top.p1 level of
hierarchy

28

 3.2.9

3-4

//
$display(This is a \n multiline string with a
%% sign)
-- This is a
-- multiline string with a % sign
//

29

 (Monitoring information)
Verilog
$monitor
$monitor(p1,p2,p3,,pn);
p1 p2 p3 pn
$display $monitor
$display

$monitor
$monitor $monitor

$monitor $monitoron $monitoroff

$monitoron
$monitoroff
30

$monitoron $monitor
$monitoroff $monitor
$monitoron
$monitoron $monitoroff

$monitor
$monitor $time

statement)
// 3-5

clock (Monitor
reset
//Clock 5 reset 10

//
initial
begin
$monitor ($time,Value of signals clock = %b
reset=%b,click,reset);

31

Partial output of the monitor

-- 0
Value of signals clock
-- 5 Value of signals clock
-- 10 Value of signals clock

statement
= 0 reset = 1
= 1 reset = 1
= 0 reset = 0

(Stopping) (Finishing)
$stop;

$stop

$finish;

32

 3-6

// 100
// 1000
initial
// 0
begin
clock = 0
reset = 1
#100 $stop // 100
#900 $finish // 1000
end

33

3.3.2 (Complier
Directives)
Verilog <keyword>
define
include
define
define (text macro) C
#define
Verilog

34

 3-7 define
//
// WORD_SIZE
define WORD_SIZE 32
// s $stop
define s $stop;
//
define WORD_REG reg [31 0]
// WORD_REG reg32;
// 32-bit

35

 include
include include
C #include

3-8

include

// header.v design.v
//
include header.v

<Verilog code in file design.v>

36

3.4 (Summary)
Verilog C

Verilog

Verilog

define include
Verilog

37