Professional Documents
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Circuits
Jan M. Rabaey
AAnantha
Design
Perspective
Chandrakasan
Borivoje Nikolic
Designing Sequential
Logic Circuits
November 2002
Digital Integrated Circuits2nd
Sequential Circuits
Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
Next state
D
CLK
2 storage mechanisms
positive feedback
charge-based
Digital Integrated Circuits2nd
Sequential Circuits
Naming Conventions
In
our text:
Sequential Circuits
Latch
stores data when
clock is low
D Q
D Q
Clk
Clk
Clk
Clk
Register
stores data when
clock rises
Sequential Circuits
Latches
Positive Latch
In
Negative Latch
Out
In
CLK
clk
clk
In
In
Out
Out
Out
CLK
Out
Out
stable follows In
Out
Out
stable follows In
Sequential Circuits
Latch-Based Design
N latch is transparent
when = 0
P latch is transparent
when = 1
N
Latch
Logic
P
Latch
Logic
Digital Integrated Circuits2nd
Sequential Circuits
Timing Definitions
CLK
t
tsu
D
thold
DATA
STABLE
tc 2
Register
Q
CLK
DATA
STABLE
Sequential Circuits
Characterizing Timing
tD 2
D
Clk
tC 2
Clk
Register
Digital Integrated Circuits2nd
tC 2
Latch
Sequential Circuits
FFs
LOGIC
tp,comb
Also:
tcdreg + tcdlogic > thold
tcd: contamination
delay = minimum
delay
Sequential Circuits
V o1 =V i2
Vi2
V o1
V o2
V o2 =V i1
V i1
V o2
A
V i2 =V o1
C
B
V i1 =V o2
Sequential Circuits
V i2 5 V o1
V i2 5 V o1
Meta-Stability
B
V i1 5 V o2
B
V i1 5 V o2
Sequential Circuits
CLK
Q
CLK
D
CLK
CLK
Sequential Circuits
Mux-Based Latches
Negative latch
Positive latch
(transparent when CLK=
0)
(transparent
when CLK= 1
1
D
0
CLK
Q Clk Q Clk In
Digital Integrated Circuits2nd
Q
D
1
CLK
Q Clk Q Clk In
Sequential Circuits
Mux-Based Latch
CLK
Q
CLK
D
CLK
Digital Integrated Circuits2nd
Sequential Circuits
Mux-Based Latch
CLK
QM
CLK
QM
CLK
CLK
NMOS only
Digital Integrated Circuits2nd
Non-overlapping clocks
Sequential Circuits
Master-Slave (Edge-Triggered)
Register
Slave
Master
0
1
D
QM
D
QM
Q
CLK
CLK
Sequential Circuits
Master-Slave Register
Multiplexer-based latch pair
I2
T2
I3
I5
T4
I4
T3
I6
QM
I1
T1
CLK
Sequential Circuits
Clk-Q Delay
2.5
Volts
CLK
1.5
0.5
2 0.5
0
tc 2
tc 2
q(lh)
0.5
1
1.5
time, nsec
q(hl)
2.5
Sequential Circuits
Setup Time
3.0
3.0
Q
2.5
QM
D
2.0
Volts
Volts
2.0
1.5
2.5
CLK
1.0
I 2 2 T2
0.5
CLK
1.0
QM
0.5
0.0
2 0.5
0
1.5
I 2 2 T2
0.0
0.2
0.4
0.6
time (nsec)
0.8
2 0.5
0
0.2
0.4
0.6
time (nsec)
0.8
Sequential Circuits
T1
CLK
CLK
I1
I2
T2
CLK
I3
I4
Sequential Circuits
CLK
CLK
Q
A
B
CLK
CLK
(a) Schematic diagram
CLK
CLK
(b) Overlapping clock pairs
Sequential Circuits
0
1
1
1
0
0
1
0
Forbidden State
Sequential Circuits
Cross-Coupled NAND
Added clock
Cross-coupled NANDs
S
VDD
M2
M4
Q
CLK
M6
M5
M1
M3
M8
CLK
M7
Sequential Circuits
Sizing Issues
2.0
3
Q
S
W = 0.5 m
W = 0.6 m
W = 0.7 m
Volts
Q (Volts)
1.5
1.0
W = 0.8 m
0.5
W = 0.9 m
0.0
2.0
2.5
3.0
W/L 5 and 6
3.5
4.0
(a)
W= 1 m
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time (ns)
(b)
Transient response
Sequential Circuits
Storage Mechanisms
Dynamic (charge-based)
Static
CLK
CLK
Q
CLK
CLK
CLK
Sequential Circuits
CLK
Sequential Circuits
1.05tC 2
tC 2
tSu
tD 2
tH
Sequential Circuits
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Clock
TSetup-1
t=0
Time
Time
Sequential Circuits
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Clock
TSetup-1
t=0
Time
Time
Sequential Circuits
Inv2
SM
D1
QM
Clk-Q Delay
Inv1
CP
TClk-Q
TSetup-1
Data
Clock
TSetup-1
t=0
Time
Time
Sequential Circuits
Inv2
SM
D1
Clk-Q Delay
QM
Inv1
TClk-Q
CP
TSetup-1
Data
Time
Clock
TSetup-1
t=0
Time
Sequential Circuits
Inv2
SM
D1
Clk-Q Delay
TClk-Q
QM
Inv1
CP
TSetup-1
Data
Time
Clock
TSetup-1
t=0
Time
Sequential Circuits
D1
Inv2
Clk-Q Delay
QM
Inv1
CP
0
TClk-Q
THold-1
Clock
Data
THold-1
t=0
Time
Sequential Circuits
Time
D1
Inv2
Clk-Q Delay
QM
Inv1
CP
0
TClk-Q
THold-1
Clock
Data
THold-1
t=0
Time
Sequential Circuits
Time
D1
Inv2
Clk-Q Delay
QM
Inv1
CP
TClk-Q
THold-1
Clock
Data
THold-1
t=0
Time
Sequential Circuits
Time
TG1
SM
D1
D
Inv1
Inv2
Clk-Q Delay
QM
TClk-Q
CP
THold-1
Clock
Data
THold-1
t=0
Time
Sequential Circuits
Time
D1
Inv2
Clk-Q Delay
QM
TClk-Q
Inv1
CP
THold-1
Clock
Data
THold-1
t=0
Time
Sequential Circuits
Time
CLK
VDD
VDD
M2
M6
M4
D
CLK
M3
M1
CLK
X
M8
Q
CL1
CLK
M7
CL2
M5
Master Stage
Sequential Circuits
Insensitive to Clock-Overlap
VDD
VDD
VDD
VDD
M2
M6
M2
M6
M4
0
X
M8
Q
D
1
M1
(a) (0-0) overlap
M5
M3
Q
1
M1
M7
M5
Sequential Circuits
CLK
Reference
CLK
CLK
log
REG
REG
CLK
REG
CLK
Out
REG
log
REG
REG
CLK
REG
REG
Pipelining
Out
CLK
CLK
Pipelined
Sequential Circuits
VDD
VDD
VDD
Out
In
CLK
CLK
In
CLK
CLK
Positive latch
Negative latch
(transparent when CLK= 1)
(transparent when CLK= 0)
Digital Integrated Circuits2nd
Sequential Circuits
VDD
VDD
In1
PUN
VDD
In2
Q
In
CLK
CLK
PDN
Q
CLK
CLK
In1
AND latch
Sequential Circuits
TSPC Register
VDD
M3
CLK
VDD
VDD
M6
M9
Y
CLK
M2
M1
CLK
M5
M4
Q
Q
CLK
M8
M7
Sequential Circuits
Pulse-Triggered Latches
An
Alternative
Approach
Ways to design an edge-triggered sequential ce
Pulse-Triggered Latch
Master-Slave
Latches
Data
L1
L2
D Q
D Q
Clk
Clk
Data
Clk
L
D Q
Clk
Clk
Sequential Circuits
Pulsed Latches
VDD
VDD
M3
M6
CLK
VDD
Q
D
CLKG
M2
CLKG
M1
(a) register
M5
M4
MP
CLKG
MN
Sequential Circuits
Pulsed Latches
Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 :
CLK
P1
P3
M6
M3
D
M2
M1
P2
M5
M4
Sequential Circuits
Volts
2.0
1.5
1.0
0.5
CLK
CLKD
0.0
20.5
0.0
Digital Integrated Circuits2nd
0.2
0.4
0.6
time (ns)
0.8
1.0
Sequential Circuits
Latch-Based Pipeline
CLK
CLK
In
CLK
Out
C1
C2
C3
CLK
CLK
Compute F
compute G
Sequential Circuits
Out
OH
ou t
V OL
VM+
Vi n
Sequential Circuits
Vin
VM
VM
t0
t 0 + tp
Sequential Circuits
M2
Vin
M4
Vout
X
M1
M3
Sequential Circuits
2.5
2.0
2.0
VM1
1.5
1.0
1.5
1.0
VM2
0.5
0.0
0.0
k=1
k=2
0.5
0.5
1.0
1.5
Vin (V)
2.0
2.5
k=3
k=4
0.0
0.0
0.5
1.0
1.5
Vin (V)
2.0
2.5
Sequential Circuits
Out
M2
X
M5
VDD
M1
Sequential Circuits
Multivibrator Circuits
R
S
Bistable Multivibrator
flip-flop, Schmitt Trigger
T
Monostable Multivibrator
one-shot
Astable Multivibrator
oscillator
Sequential Circuits
Transition-Triggered Monostable
In
DELAY
td
Out
td
Sequential Circuits
In
Out
(a) Trigger circuit.
In
VM
Out
t
t1
(b) Waveforms.
t2
Sequential Circuits
N-1
Ring Oscillator
3.0
2.5
V1 V3 V5
Volts
2.0
1.5
1.0
0.5
0.0
20.5
0.0
0.5
1.0
1.5
time (ns)
Sequential Circuits
Relaxation Oscillator
Out1
I2
I1
Out2
C
Int
T = 2 (log3) RC
Digital Integrated Circuits2nd
Sequential Circuits
VDD
M6
M4
Schmitt Trigger
restores signal slopes
M2
In
M1
Iref
Vcontr
M3
M5
Iref
tpH L (nsec)
6
4
2
0.0
0.5
1.5
V co ntr (V)
2.5
Sequential Circuits
V o1
in1
v1
in2
v2
v3
v4
V ctrl
delay cell
V1 V2 V 3 V4
2.0
1.5
1.0
0.5
0.0
2 0.5
0.5
1.5
2.5
time (ns)
3.5
Sequential Circuits