Full ADDER:

---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date: 14:11:48 02/26/2015
-- Design Name:
-- Module Name: fuladder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library
declaration if using
-- arithmetic functions with Signed or
Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library
declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity fuladder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end fuladder;
architecture Behavioral of fuladder is
begin
s <= (a xor b) xor ci;
co <= ((a xor b) and ci) or (a and b);
end Behavioral;
4 bit ADDER:
---------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date: 14:10:31 02/26/2015
-- Design Name:
-- Module Name: Adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--

-- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto
0);
B : in STD_LOGIC_VECTOR (3 downto
0);
cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3
downto 0);
cout : out STD_LOGIC);
end Adder;
architecture Behavioral of Adder is
component fuladder is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
ci : in STD_LOGIC;
s : out STD_LOGIC;
co : out STD_LOGIC);
end component;
signal s1, s2, s3 :STD_LOGIC;
begin
add1: fuladder port map
(a => A(0),
b => B(0),
ci=> cin,
s => Sum(0),
co=> s1);
add2: fuladder port map
(a => A(1),
b => B(1),
ci=> s1,
s => Sum(1),
co=> s2);
add3: fuladder port map
(a => A(2),
b => B(2),
ci=> s2,
s => Sum(2),
co=> s3);
add4: fuladder port map
(a => A(3),
b => B(3),
ci=> s3,
s => Sum(3),
co=> cout);
end Behavioral;
DFF:
---------------------------------------------------------------------------------- Company:

-- Engineer:
--- Create Date: 15:54:00 02/24/2015
-- Design Name:
-- Module Name: DFF - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library
declaration if using
-- arithmetic functions with Signed or
Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library
declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
--rst : in STD_LOGIC;
y : out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin
process(d,clk)
begin
if (clk' event and clk = '1') then
y<=d;
end if;
end process;
end Behavioral;
Parallel out:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ParallelOut is
Port ( q : in STD_LOGIC;
yout : inout STD_LOGIC_VECTOR (3
downto 0);
clock : in STD_LOGIC);
end ParallelOut;
architecture Behavioral of ParallelOut is
component DFF is

Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out
STD_LOGIC);
end component;
begin
Map0: DFF port map
(d=>q,
clk=>clock,
y=>yout(3));
Map1: DFF port map
(d=>yout(3),
clk=>clock,
y=>yout(2));
Map2: DFF port map
(d=>yout(2),
clk=>clock,
y=>yout(1));
Map3: DFF port map
(d=>yout(1),
clk=>clock,
y=>yout(0));
end Behavioral;
BCD to Excess 3:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Excess3 is
Port ( qin : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
qout : out STD_LOGIC_VECTOR (3
downto 0));
end Excess3;
architecture Behavioral of Excess3 is
signal s : STD_LOGIC_VECTOR (3 downto 0);
component Adder is
Port ( A : in STD_LOGIC_VECTOR (3 downto
0);
B : in STD_LOGIC_VECTOR (3 downto
0);
cin : in STD_LOGIC;
Sum : out STD_LOGIC_VECTOR (3
downto 0);
cout : out STD_LOGIC);
end component;
component ParallelOut is
Port ( q : in STD_LOGIC;
yout : inout STD_LOGIC_VECTOR (3
downto 0);
clock : in STD_LOGIC);
end component;
begin
m1: ParallelOut port map
(
q=>qin,
yout=>s,
clock=>clk
);
m2: Adder port map
(
A=>s,

B=>"0011",
cin=>'0',
Sum=>qout);

end Behavioral;