Memory Interfacing 8.1 Introduction Memory is an integral part of a microprocessor system, and in this chapter, we will discuss how to interface a memory device with the microprocessor. The memory interfacing circuit is used to access memory quite frequently to read instruction codes and data stored in memory. This read/write operations are monitored by control signals. The microprocessor activates these signals when it wants to read from and write into memory. In this chapter we will sce memory structure and its requirements, concepts in memory interfacing and interfacing examples. 8.2 Terminology and Operations Memories are made up of registers. Each register in the memory is one storage location. Each location is identified by an address. The number of storage locations can vary from a few in some memories to hundreds of thousand in others. Each location can accommodate one or more bits. Generally, the total number of bits that a memory can store is its capacity. Most of the types the capacity is specified in terms of bytes (group of eight bits) Each register consists of storage elements (flip-flops or capacitors in semiconductor memories and magnetic domain in magnetic storage), each of which stores one bit of data. A storage clement is called a cell. The data stored in a memory by a process called writing and are retrieved from the memory by a process called reading, Fig. 8.1 illustrates in a very simplified way the concept of write, read, address and storage capacity for a generalized memory. (8-1)Microprocessor 8-2 Memory Interfacing Storage Coils Acos Lf sais ° 0 2f + [o]ofo]— 10% Wing Data —> Roading Dara witht) os {a) Write operation (b) Read operation Fig. 8.1 8.3 Memory Structure and its Requirements As mentioned earlier, read/write memories consist of an array of registers, in which each register has unique address. The size of the memory is N x M as shown in Fig. 8.2(a) where N is the number of registers and M is the word length, in number of bits. EPROM 4096 x8 (2) Logic diagram for RAM Fig. 82 {b) Logic diagram for EPROM ig. 8.Microprocessor 8-3 Memory Interfacing Example 1: If memory is having 12 address lines and 8 data lines, then Number of registers/memory locations = 2N = 217 = 4096 Word length = M bit = 8 bit Example 2: If memory has 8192 memory locations, then it has 13 address lines, ‘The Table 8.1 summarizes the memory capacity and address lines required for memory interfacing. Memory Capacity Address Lines Required 1K = 1024 memory locations 10 2K = 2048 memory locations 1 4K = 4096 memory locations 12 8K = 8192 memory locations 13 18K = 16384 memory locations 14 32K = 32768 memory locations 15 64K = 65536 memory locations 16 Table 8.1 As shown in the Fig. 8.2 (a) memory chip has 12 address lines Ag-Ayy, one chip select (C8), and two control lines, read (RD) to enable output buffer and write (WR) to enable the input buffer. The internal decoder is used to decode the address lines. Fig, 8.2 (b) shows the logic diagram of a typical EPROM (Erasable Programmable Read-Only Memory) with 4096 (AK) registers. It has 12 address lines Ay-A,,, one chip select (C3), one Read control signal. Since EPROM is a read only memory, it does not require the (WR) signal 8.4 Basic Concepts in Memory Interfacing For interfacing memory devices to microprocessor 8086/88 following important points are to be kept in mind. 1. Microprocessor 8086/88 can access Mbytes memory since address bus is 20-bit. But it is not always necessary to use full IMbytes address space. The total memory size depends upon the application. 2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data memory. When both, EPROM and RAM are used, the total address space IMbytes is shared by them.Microprocessor 8-4 Memory Interfacing 3. The individual capacities of program memory and data memory depend on the application. 4, It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple RAMs as per the requirement of application. 5, We can place EPROM/RAM anywhere in full IMbytes address space. But program memory (EPROM) should be located at last memory page so that the starting address FFFFOH will lie within the program memory range. To provide facility to set addresses in the interrupt vector table we must provide RAM at page 0 of memory. So that the interrupt vector table lie with the read/write memory range. It is not always necessary to locate EPROM and RAM in consecutive memory addresses. However, it is advised to do that. While interfacing memory to 8086 we have to provide odd and even banks of memory, Even bank is selected when Ay = 0 and odd bank is selected when BHE = 0. Odd and even banks are not required for interfacing memory to 8088. ‘The memory interfacing requires to : © Select the chip Identify the register * Enable the appropriate bufter. Microprocessor system includes memory devices and I/O devices. It is important to note that microprocessor can communicate (read/write) with only one device at a time, since the data, address and control buses are common for all the devices. In order to communicate with memory or I/O devices, it is necessary to decode the address from the microprocessor. Due to this each device (memory or I/O) can be accessed independently. » N 8.4.1 Address Decoding Techniques 1) Absolute decoding 2) Linear decoding 3) Block decoding 1) Absolute Degoding : In absolute decoding technique the memory chip is selected only for the specified logic level on the address lines; no other logic levels can select the chip. Fig 8.3 shows the memory interface with absolute decoding. Two 8K EPROMs (2764) are used to provide even and odd memory banks. Control signals BHE and Ag are used to enable outputs of odd and even memory banks respectively, As each memory chip has 8K memory locations, thirteen address lines are required to address each locations, independently. All remaining address lines are used to generate an unique chip select signal. This addressing technique is normally used in large memory systems.Microprocessor 8-5 Memory Interfacing DATA Bus Fig. 8.3 Absolute decoding 2) Linear Decoding : In small systems, hardware for the decoding logic can be eliminated by using only required number of addressing lines (not all). Gther lines are simply ignored. This technique is referred as linear decoding or partial decoding. Fig 8.4 shows the addressing of 16K RAM (6264) with linear decoding. Control signals BHE and Ay are used to enable odd and even memory banks, respectively. The address line A,, is used to select the RAM chips. When A,, is low, chip is selected, otherwise it is disabled. The status of Ay, to Ary does not affect the chip selection logic. This gives you multiple addresses (shadow addresses). This technique reduces the cost of decoding circuit, but it has drawback of multiple addresses. DATA BUS Fig. 8.4 Linear decodingMicroprocessor 8-6 Memory Interfacing 3) Block Decoding : In a microcomputer system the memory array is often consists of several blocks of memory chips. Each block of memory requires decoding circuit. To avoid separate decoding for each memory block special decoder IC is used to generate chip select signal for each block. Fig, 8.5 shows the block decoding technique using 74138, 3 : 8 decoder. Fig. 8.5 Block decoding 8.4.2 Memory Interfacing Examples imp Example 8.1: Design an 8088 based system with the following specifications 1) 8088 in minimum mode ii) 8 Kbyte EPROM iti) 8 Kbyte RAM Draw the complete schematic of the design indicating all the address selected, decoders used, etc, Solution ; As RAM and EPROM are 8 Kbyte, 13 address lines are required from Ag to Aux The remaining address lines are used for address decoding circuitry. The address lines Ag to Ay and Ay, to Ajs are latched using IC 74373 (octal latch) and ALE signal. Fig. 8.6 shows the interface between 8088 and two memory chips.8-7 Memory Interfacing Microprocessor MO} 20! MBA wna sty 2 (wwe) p9zo vty 40-°0 30 uM 2 (wouaa) +922 %v2tv 40-0 30 SLeSTrL Apeay 12S9N ID wo! uM oe SLES TL Fig. 8.6 Interfacing 8 K RAM and 8 K EPROM with 8088 in minimum modeMicroprocessor 8-8 Memory Interfacing Memory Map Ay Au Arr Ar| Ais Are An Au|An Aw Ap AalAr Aa As AlAs Az Ar Aol Address | Memory 1144 1 0]0 0 0 0/0 0 0 0J0 0 0 Cc} FEOOOH | Start EPROM 1 144 44 FFFFFH | End EPROM 0 1 0 Fi 14 4/4 4°14 949 1491 1 1 1 0]0 0 0 0/000 OJ0 0 0 0) 1E000H | Stat RAM {4 4 4 49/9 49:4 441 4914 4/4 1 1 1] SFFFFH End RAM wmm> Example 8.2: Design an 8086 based system with the following specifications. 1) 8086 in minimum mode. ii) 64 Kbyte EPROM iii) 6£ Kiyte RAM Draw the complete schematic of the design indicating address map. eoss Solution ; The 8086 is a 16 bit microprocessor. It can access 16 bit data simultaneously. For interfacing memory module to 8086 CPU, it is necessary to have odd and even memory banks. This can be achieved by using two 32 Kbyte EPROMs and two 32 byte RAMs, one for odd bank and another for even bank. As 32 Kbyte RAM and EPROM need 15 address lines, A; to Ays lines are used. Ay and BHE are used to select even and odd memory banks respectively. Fig. 8.7 shows the interface between 8086 and two memory chips. Memory Map : BHE |Ato Awe At Ase|Ats Ate Ars Ara|Ann Aw Ar Ar|Ar As As Ac/Aa Az Ar Ao| Address | Memory 4/1 1 1:1/0 0 0 0}0 O 0 0/0 0 O O}0 O 0 O |FOOCOH Even aft 4 4 444 4 1 444 4 4-441 1 :4:°444 14 10 [FFFFFH EPROM1 ofo 11 4/0 0 9 0/0 0 0 0fo00 0/0 o 0 olFoon | oad ofo rasta tt t[4 44 tft444]t 1 1 4 FFRFFH | EPROMZ + foo 1 t/0 0 0 ofo 0 0 ofo 00 ol0 0 0 0 [00H | Even + foo 4 t]a 44 tie 44 i{t 44 4]1 41 ofsrrren | Rat © }/o9 0 41 1/0 0 0 0/0 0 © 0/0 0 O OJ0 O O 4 }30001H Odd ojo ot tfa tt tft tt tits 1 4{t 4 14 frrreH | RAM2Memory Interfacing Microprocessor ees te so (roves oseza wm tyty 4a%a 20 ‘2 (wove) eszza wan ly Ha40 30 kniowaa) esziz Sly toa 30 32 (wowes) eszuz “y'y Sg%a 30 (ereuestez Fig. 8.7 Interfacing 64 K RAM and 64 K EPROM with 8086 in minimum modeMicroprocessor 8-10 Memory Interfacing wm Example 8.3: Design an 8083 based system with the following specifications. i) 8088 in maximum mode ii) 64 Kbyte EPROM iti) 64 Kbyte RAM Draw the complete schematic of the design indicating address map. Solution : In the maximum mode, memory and I/O read/write, address latch enable (ALE), Data Enable (DEN), Data transmit/receive (DT/R) signals must be decoded externally using bus controller 8288. Fig 8.8 shows the memory interface with 8088 in the maximum mode. For interfacing 64 Kbyte EPROM and 64 Kbyte RAM memory two 32 Kbyte EPROMs and two 32 Kbyte RAMs are used. As 32 Kbyte RAM and EPROM need 15 address lines, Ag to Ay, lines are used, Remaining address lines are used for address decoding logic. Memory Map : Ary Ate Any Are[Ars Ate Ars Arz|At Aro Ay An|Ar Ay Ap Ac As Az Ar 144 11/4 0 0 0f/o 000 14 4afaa rats tag Address Mamory Feoo0H | EPROMt FFFFFH ° ° ° e ° ° 14100 1.9 0 0/0 0 0 O}0 Oo oO 0/0 o oO O| Da0OGH | EPROM2 140 441 ttt tt ttt tt t]t 1 1 4 | OFFFFH oo 1 4.9 0 0/0 0 o o]o 0 o ofa © oO | 38000H RAMI oo 1404 444 4 4 444 4 4 444 1 4 4] SFRFFH o 10 1000/0000 0 0 | 58000H RAM2 010 4444/1 444 11 | SFFFFH ‘am Example 8.4: Design an 8086 based system with the following specifications. #) 8086 in maximum mode ii) 64 Kbyte EPROM iti) 64 Kbyte RAM Draw the complete schematic of the design indicating address map. Solution : The 8086 is a 16 bit microprocessor. It can access 16 bit data simultaneously. For interfacing memory module to 8086 CPU, it is necessary to have odd and even memory banks. This can be achieved by using two 32 Kbyte EPROMs and two 32 Kbyte RAMs, one for odd bank and another for even bank. In the maximum mode, memory and I/O read/write, address latch enable (ALE), Data Enable (DEN), Data transmit/receive (DT/R) signals must be decoded externally using bus controller 8288, Fig 8.9 (See Fig. 8.9 on page 8-12.) shows the memory interface with 8086 in the maximum mode. As 32 Kbyte RAM and EPROM need 15 address lines, Ay to Ays lines are used. A, and BHE are used to select even and odd memory banks respectively.8-11 Memory Interfacing Microprocessor seis aig] est Aa, 4 5 ¥ ‘ a, 2 # oy Ra ies o 8 iy ay gu apy av 3 = 3 33 = 3 2 32 Sy vreee (we) sszz9- (ww) 95279 (wouds) 95722 (nouda) 95722 07D war "dy 4060 30 a Fv2y 4090 30 nyy faa 30 |] "viv Fa% a | STOuNODSNE see SMO | al ovoy 3% uot Ear ‘DOH DOs Suny, Daw '§ Suan =" ae 3 — S| mee neq wo ‘o we 21 oS eee e fly wanaosNrtL 5 i vi Y ‘ (eezaieassrre tg a Ps ease °qy tow y tg XVUNEY Fig. 8.8 Interfacing 64 K RAM and 64 K EPROM with 8088 in maximum modeMicroprocessor 8-12 Memory Interfacing Ree OE DyDis AAs 27256 (EPROM) 7ALS373(2) | 82822) Fig. 8.9 Interfacing 64 K RAM and 64 K EPROM with 8086 in maximum modeMicroprocessor 8-13 Memory Interfacing Memory Map : HBHE|Aye Ans Arr Aus[Ais Au Aro ArzlAn1 Aro Av Ar [Ar Ay As Ay [Aa Az Ar Aa| Address | Address 4/144 470 6 6 0/6 060 0/0 00 OJ/0 000 oat Even 4f4o44 444 4 4 4/4 4 1 444 1 4 = 1114 14 1 0] FFFFEH)| EPROM 071 14 1/0 0 0 O}0 9 0 O}09 9 oO O]O oO © 1] FOOOIH Odd O}1 14 4141 41:9 44/1 41:1 4141 1:1 141 1 1 1 FFFFFH) | EPROM2 1]0 0 1 1/0 0 0 O]0 0 0 O]/0 OO O/0 0 O 0] 30000H Even sfooas]s 44 4]1 44 441441 4]4 11 O| aFrreH ojo 01 41/0 0 0 OJ09 6 0 0 0 0 G/0 0 O 14 | 30001H ojo o 4 4471 41 4 441 4:4 =944 4-4 141 1 1 1 | SFFFFH. Mm Example 8.5: Design an 8086 based microprocessor system with the following specifications i) 8086 Microprocessor working at 8 MHz ii) 32 Kbyte EPROM using 16 KB devices iti) 64 Kbyte SRAM using 16 KB devices Explain the design and show the memory map. [May-2005, Dec.-2008] Solution : The 8086 is a 16 bit microprocessor. It can access 16 bit data simultaneously. For interfacing memory module to 8086 CPU, it is necessary to have odd and even memory banks. This can be achieved by using two 16 Kbytes EPROMs and four 16 K bytes RAMs. As 16 Kbyte RAM and EPROM need 14 address lines, A, to Aj, lines are used. Ay and BHE are used to select even and odd memory banks respectively. Fig 8.10 shows the interface between 8086 and two memory chips. Momory Map : BHE|Au Aus Aur Ave[Ats Ave Ans Ars|Aiv At Ar AalAr Ae A Ac/As Ar Ar As| Addross | Memory 1+ ]1 1 4 1/0 0 @ ofo oo ofo oa of0 o o Of Fa0dH | Even 1 14064444 4 8 114 1 -1:449 1-49-4454 1 1 0} FFFFEH | EPROM1 of1 1 0 1/0 0 @ ofo 0 o ofo 00 o[0 0 o 4| Deon | oad ols 1 oft 14 t]4 1 4 tft 4 4{1 4 4 1] DFFFFH | EPROMZ 1/0 0 4 4/1 0 @ 0/0 0 0 0/0 Oo O}0 oO O Of 38000H Even tfoo + sft st tft tals + 4/1 4 1 of sFrFEH | RAM o/0 0 4 171 0 @ 0/0 G6 0 0J/0 00 0/0 GO O 1] 38001H Odd ojo o 4 441 4 4 444 4 4-449 4 4-441 4 1 1) SFFFFH RAMI 1 {0 1 0 171 0 0 0J/0 0 0 O}0 0 O O/0 oO O Of} S8000H Even tio so tts 4 tifa tt ilitt aft 4 1 0] SeerEH | RAM2 o}9 1 0 1/1 0 G@ O}0 0 0 0/0 0 O OJO O O 4} SB8001H Odd ojo sorts st sta atte ts tft 4 4 1] sorreH | RamaMicroprocessor 8-14 Memory Interfacing s =k = & ByDy AAn (EPROM) 1648 OE DE O5Di5 ArAry (EPROM) 1648, 7aLs37342) Fig. 8.10 Interfacing 64 K RAM and 64 K EPROM with 8086 in minimum modeMicroprocessor 8-15 Memory Interfacing 8.4.3 DRAM Interfacing In section 5.4.2, we have scen that DRAM needs refreshing after every 2 ms or 4 ms. On the other hand, DRAM contains more memory cells as compared to static RAM per unit area and they are available in much larger sizes : upto 16M x 1. In this section we see the interfacing of DRAM to the processor, ie. DRAM memory system. Let us see the pin connection for a typical 64 K x 4 DRAM (TMS4464). We know that, to address 64 K memory registers we require 16 address lines. But in DRAM to reduce total number of address lines, address is given in two phases. This allows DRAM to multiplex lower address and higher address. The DRAM TMS4464 (64Kx4) has eight address lines (Ay - A;). When column address strobe (CAS) is low these address lines give column address and when row address strobe (RAS) is low these address lines give row address. First, Ay = Ay are placed on the address bus and strobed into an internal row latch by asserting RAS. Then, the address lines A, - Ays are placed on the same eight address inputs and strobed into an internal cotumn latch by asserting CAS. Pin Definitions Address lines ‘Column address strobe Data lines RAS. Row address strobe Voo ++5V supply Ww ‘Write enable Ground (TMS4464) a) Pin diagram [b) Pin definitions (a) gt (>) Fig. 8.14 Therefore, 16-bit address gets latched into two internal. 8-bit latches. The internally latched 16-bit access the contents of one of the 4-bit memory locations. Fig, 8.12 shows the circuit for multiplexing Ay - Ay and Ag - Ays address lines. Here, RAS line is used to strobe row address into the DRAM. When RAS is low row address is strobed and when RAS is high column address is strabed into the DRAM.Microprocessor 8-16 Memory Interfacing 74187 Fig.-8.12 Address multiplexer for 64 x 4 DRAM (TMS4464) 8.4.4. DRAM Controller - Inte! 8203 The Intel 8203 is 64 K and 16 K DRAM controller. It is a 40 pin IC ; uses + 5 V supply. It provides all signals required to control 64K or 16 K DRAMs in a microcomputer system. It is capable of directly addressing and driving up to 64 devices without external drivers. It provides multiplexed addresses, address strobes, refresh logic and refresh/access arbitration. It is fully compatible with 8080A, 8085A, Intel 8088 and Intel 8086 family of microprocessors. It contains refresh timer and refresh counter. It had two modes of operation; one for 64 K DRAM and the other for 16 K DRAM. 8.4.4.1 Pin Description The Fig, 8.13 shows the pin diagram of Intel 203 and the Table 8.2 gives the pin description of Intel 8203.Microprocessor 8-17 Memory Interfacing Yoe aN a ius my9Pa 1KEER REFROMALE Pes Fos, a aR mR ve os FRS,(04) BOP (AH) Baty) FAS, (O0T}) Fig. 8.13 Pin Pin | Type Name and Function No AL 6 1 | Address low > CPU address inputs used to generate memory row address. AL 8 1 AL, 10 1 AL, 2 1 Aly 14 1 Als 16 1 Aly 18 ‘Microprocessor 8-18 Memory Interfacing AH 5 1 | Address high : CPU address inputs used to generate memory column address. AH, 4 1 AH, 3 ' AH, 2 ' AH, 1 1 AH, 39 1 AH 38 1 ro — By/ALy 24 1 | Bank setect inputs : Used to gate the appropriate RAS output for a memory cycle. B,/OR, option used to select the Advanced Read Mode. (Not available in 64 K mode.) When in 64 K RAM Mode, pins 24 and 25 operate as the AL, and ‘AH, address inputs. ByOP, 25 ' AH, PCS. 33 ' Protected chip select : Used to enable the memory read_and write inputs. Once a cycle is started, it will not abort even if PCS goes, inactive before cycle completion. WR 3 t Memory write request. RD/S1 a2 1 | Memory read request : S1 function used in Advanced Road Made selected by OR (pin 25). REFRQ/ALE| 34 1 | External refresh request : ALE function used in Advanced Read mode, selected by OR (pin 25). CUT 7 ° Output of the multiplexer : These outputs are designed to drive the addresses of the Dynamic RAM array. (Not that the OUTo-7 pins do not require inverters or drivers for proper operation.) oun 9 ° Ute " ° OUT 13 ° ‘OUT 15 ° OUT: 7 ° oc 19 ° WE 28 © | Write enable : Drives the Write Enable inputs of the Dynamic RAM array. ‘CAS a7 © | Column address strobe : This output is used to latch the Column Address into the Dynamic RAM array.