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Understand design goals and tradeoffs in flip-flops and how they are
measured
Be able to describe operation of a wide range of flips and recognize how the
roles of individual transistors determine operation
Motivation
Revision
Ck
Ck
D-Latch:
level-sensitive
Tracks data while clock high
Stores data while clock low
D-Flip-flop
edge-sensitive
Stores data on clock edge
tSetUp
thold
tclock-Q
taperture
Ck
D
tSetUp
thold
tclock-Q
taperture
tD-Q
Edge-Triggered Flip-Flops
Created from latches:
Two styles:
skew
Goal:
Goals
Timing Closure:
Goal:
Register
Q1
D1
Comb
Logic
clock
Register
D2
tLogic-delay
+/-tskew
Q2
clock
tset-up
thold tskew
tskew
clock
D2
tck-Q-max + tlogic-max tck-Q-min-tlogic-min
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
skew
clock
skew
Q
Note : Latches have this property for signals that arrive after clock
rising edge!
Incorporate logic into flip-flop
And remove from before/after flip-flop
Other
Flip-Flop Basics
Generic Flip-Flop:
Sampler
Static:
storage
Output
Dynamic:
etc.
Sampling Stage:
Output Stage:
10
V1
V1
V3
V3
V1
V2
Stable operating point
V2
V1
Qualitative View:
Energy
V2
V2
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
11
Noise Margin
Add noise at one input:
V2
V1
Assume nominal V2 =1
V1
Vn
V1
Size of boxes
determine NMs
V1
Small Vn
V2
V2
Unity gain
Large Vn
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
V2
12
Can replace
INV with logic
Basic Latches
To store a logic level (change state):
Some Methods:
Clk
D
clk
Q
S
NOR RS latch
13
Latch Basics
Other Methods To Change State:
p2
p1
D
n1
n3
n4
n5
D
clk
clk
n2
n6
V1
RH inverter (D=0)
LH inverter (D=1)
Negative Voltage Margin
Write
V2
14
skew
Goals :
15
Timing
Tradeoff between tclock-Q and tsu / thold:
tclock-Q
thold
tSU
Why?
D
clk
clock
D
Q
Q
X
16
Aggressive tsu:
Failure:
Clock
D
Q
tsu tck-Q
One point on
curve on previous page
tsu tck-Q
Another point
<tsu
Failure!
NOT a valid tsu
17
Project Characterization
T_hold
Failure:
Good:
Ck
Ck
Q
<thold
Failure!
NOT a valid thold
thold
Good! (NO change in Q due to D)
thold
18
Timing
Objective : Minimize tD-Q = tSU + tclock-Q
Often results in negative setup time
tSU
clock
D
Q
Forbidden
400
tD-Q
tclock-Q
tD-Q
(ps)
350
300
250
tSU(ps)
19
tSU
clock
D
400
350
Forbidden
Hold
Hold period:
300
Hold period
(no transitions
allowed)
250
20
clk
Vinv
Vt
clk
Vt
T2 open
T1 open
Q
Q
T1
Clk
T2
Clk
21
C2MOS
TSPC
Transmission Gate
DCVS
Single Transistor Clock
Hybrid Latch Flip-flop
Semi Dynamic Flip-flop
Sense Amp Flip Flop
K6 Flip Flop
Comparisons
22
Common Questions
How is the signal sampled on the clock 0 1 transition?
What determines:
tsetup ?
thold ?
tck-Q ?
23
C2MOS Flip-Flop
Edge triggered Master-Slave device:
Tri-state inverter
Clock Buffer
24
C2MOS Operation
Track (ck = 0)
=on
Tracking input
Track (ck 1)
Sampling input
25
Timing
What determines t_setup and t_hold?
clk
ckb
ck
tsu
26
D
clk
clk
D
clk
SN
PP
SP
PP
27
SP + SP + SN + SN
D
clk
b
a
Observation:
SP stage simply inverts a while clk lo
Not needed if Q OK..
Note, nodes a, b, Q float for part of clock
period
Watch for inadvertant charge sharing
Note can put logic in PU and PD chains
clk
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
28
Operation
D=0, clk=0
ck 1
1
clk
x1
clk
Note: a/b floats high or low (x0, x1)
x0
clk
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
29
Operation
D=1, clk=0
ck 1
1
x1
clk
clk
Note: a/b floats high or low (x0, x1)
x1
x0
clk
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
30
TSPC Issues
Timing:
31
Clock Slope
Example : Sensitivity of TSPC flip-flop:
p2
D
a
p1
n1
clk
Possible failure:
D remains high
a low when clock low
clock
b
Q
p1 off
before p2 on
Possible Fixes :
p1 & p2
On
32
Clock Load
High
Power
Low
low power feedback
Positive setup
33
DCVS
True Single Phase Clocked Latch
DSTC and SSTC
Pulse-triggered Latches:
HLFF
DSFF
SAFF
ETL
34
Variants:
Static RAM style Latch
p2
p1
n3
n1
n5
n4
clk
n2
Simple DCVS:
Latch or flip-flop?
Dynamic or static?
Latch
p1
Dynamic
p2
D
n1
n5
D
clk
clk
n2
n6
35
DCVS
Combine to make Master-Slave Flip-flop
p5
p2
p1
Q
p3
p4
n3
n1
D
n6
n7
n4
n5
D
clk
n2
36
Operation
Clock = low:
clk
Master turned on
One of n1 or n5 turned on
n1 or n5 overpowers latch
p2
p1
p4
p3
Clock high
p5
n1
D
n7
n6
n3
n5
n4
D
clk
n2
Master
Slave
37
Operation
Ck=0; D=1
clk
p5
p1
p2
Q
p4
p3
n3 n4
n1
n6
n7
n5
clk
n2
Master
Slave
38
Operation
Ck1; D=1
clk
p5
Float Hi
p1
p2
Q
p4
p3
n3 n4
n1
Q Q=0
n6
n7
n5
clk
n2
Master
Slave
39
Operation
Ck=1; D0
(expect to see no transition)
clk
p5
p1
p2
Q
p4
p3
n3 n4
n1
D
n6 off
Q Q=0
n6
n7
n5 off
n5
clk
n2
Master
Slave
40
DCVS
clk
p4
e.g. 0 held:
D has not changed:
p3
p5
p2
p1
Q
n3
n1
n4
D
Q
n5
clk
1
D has changed:
n2
Vdd path
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
41
Operation
Ck=0; D=1
Ck1; D=1
clk
clk
p4
HI
p3
p2
p1
Q
n3
n1
n4
p4
p5
D
Q
n5
HI
p3
p5
p2
p1
Q
n3
n1
n4
D
Q
Q=1
n5
clk
clk
n2
n2
42
Operation
Ck0; D=1 (latch event)
clk
p4
HI
p3
p2
p1
Q
n3
n1
n4
HI
p4
p5
D
Q
n5
Q=1
p3
p5
p2
p1
Q
n3
n1
n4
D
Q
Q=1
n5
clk
clk
n2
n2
43
clk
Q
Q
D
D
clk
clk
clk
Q
Q
A
B
clk
44
p1
p5
p4
p5
p2
p3
n1
n9
p2
n3
n10
p4
n4
n4
n5
n6
n8
n2
n1
(Dynamic)
p6
n2
n3
(Semi-static)
Min. sizes. Ensures static
operation if D changes while
clk high.
45
operation
Ck=0; D=1
Ck1; D=1
p1
p1
p4
p4
p5
p5
p2
p2
p3
p3
n3
n3
n1
n2
n1
n2
46
Operation
Ck=1; D->0
p1
p4
p5
p2
p3
n3
n1
n2
47
Operation
Ck=0; D=1
Ck1; D=1
p3
p3
p5
p5
p6
Hi
n9
p2
Lo
n4
n1
n5
n2
n9
n10
p2
p4
n6
n4
n3
n1
n10
p4
Lo
n8
p6
n5
n2
n6
n8
n3
48
Operation
Ck=1; D 0
p3
p5
Lo
p2
p6
n9
n10
p4
n4
n1
n5
n2
n6
n8
n3
49
Pulse-triggered Latch
Principle of Operation:
p1
p3
p2
n3
p4
n6
Storage
n5
n2
n1
Master
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
n4
Slave
50
HLFF
Operation:
Absorbs skew
Fully static (retains Q)
Negative setup
Allows cycle stealing
Can add logic
thold c.f. tD-Q
Precharge
(clock low)
Precharge
(clock high)
p1
p3
p2
n1
p4
n4
Storage
n2
n3
D high
n5
n6
D low
51
HLFF Operation
Basic Structure
Clock Low
Precharge X
Clock High
After thold
p1
n1
n2
n3
p2
X
p3
p4
n4
n5
n6
tsu:
Can be negative
Criteria:
52
Operation
Ck=0; D=1
Ck1; D=1
p1
p2
p3
p1
p4
p2
p3
p4
Q=1
X
n1
n4
n1
n4
n2
n5
n2
n5
n3
n6
n3
n6
= turning off
= turning on
53
Operation
Ck=1; X precharges
p1
n1
Ck=1; D0
p2
p3
p4
Q=1
n4
p2weak
p3
p1
n1
p4
Q=1
n4
n2
n5
n2
n5
n3
n6
n3
n6
54
Operation
Ck=0; D=0
Ck1; D=0
p1
n1
p2
p3
p4
p2weak
p3
p1
n4
n1
p4
Q=0
n4
n2
n5
n2
n5
n3
n6
n3
n6
55
Operation
Ck=1; X precharges
p1
n1
Ck=1; D1
weak p3 reduces dip in X, as a result of
charge-sharing through n2, making
sure p4 does not turn on
p2
p3
p4
Q=1
p1
n5
n3
n6
p2
p3
Q=1
p4
n4
n2
weak
n1
n4
n2
n5
n3
n6
56
HLFF Waveforms
charge share X to nfet n1
p1
p2
p3
p4
n1
n4
n2
n5
n3
n6
57
p1
p2
n1
n4
n2
n5
n3
58
SDFF
Operation
p1
X
N1
n1
p2
n4
n2
n5
n3
Clk = low :
X precharged to
Clk hi :
D=0 :
1, N1 is ON
After thold if D 1:
D=1:
N1 is off : No change
After thold if D 0:
No P/G connection on LHS X latched low by X-coupled inverters)
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
59
Operation
Ck=0; D=1
Ck1; D=1
p1
p1
1
n1
n3
1 0
p2
Q=1
n1
1
n2
p2
n4
n2
n5
0 1
n4
n5
n3
60
Operation
Ck=1; D0
D=1; Ck0
p1
0
n1
1
n2
p2
Q=1
p1
0 1
n1
n4
1
n2
n5
p2
Q=1
n4
n5
n3
n3
61
Operation
Ck=0; D=0
Ck1; D=0
p1
1
n1
1
n2
p1
p2
n4
n1 10
n5
n2
n3
0 1
p2
Q=0
n4
n5
n3
62
Operation
Ck=1; D1
Ck0
p1
1
n1
0
n2
p2
1
n4
Q=0
p1
1
n1
n2
n5
n3
1
0
p2
Q=0
1
n4
n5
n3
63
64
Clocked T
DiffAmp
Storage
65
Operation
Ck=0; D=1
Ck1; D=1
0
1
Data stored in latch at top center
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html
66
Operation
Ck=1; D0
Ck0; D=1
2
0
0 4
0
1
Mn5 prevents change in latch
0 4
RS latch unaffected as S, R = 1
67
SAFF Timing
Ck->1
tsu
tforbidden
N3 is sufficiently off to prevent full transition
but on enough to start one
Tck-Q
68
SAFF
69
70
Modified SAFF
71
K6 ETL
p1
p2
p3
n1
p4
n3
n2
n4
72
Operation
Clock Low:
p1
p3
n1
n2
p2
Nothing
p4
Clock Hi
n3
n4
Pulsed output!
-Must ensure output pulse
is sufficiently wide
D or Db sampled onto Q or Qb
by clock pulse
An input of NOR 1
rst Lo, 3 INV delays later
q, qb Hi
rst off
Self reset, Why?
Reduces clock load
73
74
StrongArm
K6
Sense
Amp
SDFF
75
HLFF
PowerPC
C2MOS
76
Delay Comparison
77
78
79
General Characteristics
80
81
82
Capture tradeoff:
-Power Delay product
(=Energy.Delay at constant fclk)
83