Top Level Entity (Xilinx ISE VHDL Code):

----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:

11:18:40 04/28/2014

-- Design Name:
-- Module Name:

top_level - Behavioral

-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top_level is
Port ( clk : in STD_LOGIC;
floorin : in STD_LOGIC_VECTOR (7 downto 0);
floorout : out STD_LOGIC_VECTOR (7 downto 0));
end top_level;

architecture Behavioral of top_level is

-- declaration of KCPSM3 (always use this declaration to call
-- up PicoBlaze core)
component kcpsm3
port (address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
-------------------------------------------------------------------------- declaration of program memory (here you will specify the entity name
-- as your .psm prefix name)
component ele
port (address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end component;
-------------------------------------------------------------------------- Signals used to connect PicoBlaze core to program memory and I/O logic

signal address : std_logic_vector(9 downto 0);

signal instruction : std_logic_vector(17 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal in_port : std_logic_vector(7 downto 0);
signal t1 : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt_ack : std_logic;
signal reset : std_logic;
-- the following input is assigned an inactive value since it is
-- unused in this example
signal interrupt : std_logic :='0';
-------------------------------------------------------------------------- Start of circuit description
begin
-- Instantiating the PicoBlaze core
processor: kcpsm3
port map (address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
reset => reset,
clk => clk);

-- Instantiating the program memory

program: ele

port map (address => address,

instruction => instruction,
clk => clk);

-- Connect I/O of PicoBlaze

---------------------------------------------------------------------------- KCPSM3 Define input ports
------------------------------------------------------------------------- The inputs connect via a pipelined multiplexer
input_ports: process(clk)
begin
if(port_id="00000000") then
if (floorin(0)='0' ) then
in_port<="00000000";
end if;
if (floorin(0)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00000001") then
if (floorin(1)='0' ) then
in_port<="00000000";
end if;
if (floorin(1)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00000010") then
if (floorin(2)='0' ) then
in_port<="00000000";
end if;
if (floorin(2)='1' ) then

in_port<="00000001";
end if;
end if;
if(port_id="00000011") then
if (floorin(3)='0' ) then
in_port<="00000000";
end if;
if (floorin(3)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00000100") then
if (floorin(4)='0' ) then
in_port<="00000000";
end if;
if (floorin(4)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00000101") then
if (floorin(5)='0' ) then
in_port<="00000000";
end if;
if (floorin(5)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00000110") then
if (floorin(6)='0' ) then
in_port<="00000000";
end if;
if (floorin(6)='1' ) then

in_port<="00000001";
end if;
end if;
if(port_id="00000111") then
if (floorin(7)='0' ) then
in_port<="00000000";
end if;
if (floorin(7)='1' ) then
in_port<="00000001";
end if;
end if;
if(port_id="00001000") then
if (t1="00000000") then
if (floorin(7 downto 1)="0000000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000001") then
if (floorin(7 downto 2)="000000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000010") then
if (floorin(7 downto 3)="00000") then
in_port<="00000000";
else
in_port<="00000001";
end if;

end if;
if (t1="00000011") then
if (floorin(7 downto 4)="0000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000100") then
if (floorin(7 downto 5)="000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000101") then
if (floorin(7 downto 6)="00") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000110") then
if (floorin(7)='0') then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000111") then
in_port<="00000000";
end if;

end if;

if(port_id="00001001") then
if (t1="00000000") then
in_port<="00000000";
end if;
if (t1="00000001") then
if (floorin(0)='0') then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000010") then
if (floorin(1 downto 0)="00") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000011") then
if (floorin(2 downto 0)="000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000100") then
if (floorin(3 downto 0)="0000") then
in_port<="00000000";
else

in_port<="00000001";
end if;
end if;
if (t1="00000101") then
if (floorin(4 downto 0)="00000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000110") then
if (floorin(5 downto 0)="000000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
if (t1="00000111") then
if (floorin(6 downto 0)="0000000") then
in_port<="00000000";
else
in_port<="00000001";
end if;
end if;
end if;
end process input_ports;
------------------------------------------------------------------------- KCPSM3 Define output ports
------------------------------------------------------------------------- adding the output registers to the processor at address 80 hex
output_ports: process(clk)
begin

if (port_id="00010000") then
floorout <= out_port;
end if;
if (port_id="00010001") then
t1 <= out_port;
end if;
end process output_ports;

end Behavioral;

KCPSM3 Assembly Code:

LOAD sa,00 ; current floor
LOAD sb,00 ; direction 00 up, 01 down
l0:OUTPUT sa,10
INPUT s0,00
COMPARE s0,00
JUMP Z,l01
LOAD sf,99

LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l02
l01: LOAD sf,99
LOAD sf,99
l02: CALL p1
LOAD sb,00
ADD sa,01

l1: OUTPUT sa,10

INPUT s1,01

COMPARE s1,00
JUMP Z,l11
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l12
l11: LOAD sf,99
LOAD sf,99
l12:CALL p1
COMPARE sb,00
JUMP Z,l13

LOAD se,02
AND se,sd
COMPARE se,00
JUMP Z,l14
SUB sa,01
JUMP l0
l14: LOAD sb,00
ADD sa,01
JUMP l2
l13: LOAD se,01
AND se,sd
COMPARE se,00
JUMP Z, l15
ADD sa,01
JUMP l2
l15: LOAD sb,01
SUB sa,01
JUMP l0

l2: OUTPUT sa,10

INPUT s2,02
COMPARE s2,00
JUMP Z,l21
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99

LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l22
l21: LOAD sf,99
LOAD sf,99
l22:CALL p1
COMPARE sb,00
JUMP Z,l23
LOAD se,02
AND se,sd
COMPARE se,00
JUMP Z,l24
SUB sa,01
JUMP l1
l24: LOAD sb,00
ADD sa,01
JUMP l3
l23: LOAD se,01
AND se,sd

COMPARE se,00
JUMP Z, l25
ADD sa,01
JUMP l3
l25: LOAD sb,01
SUB sa,01
JUMP l1

l3: OUTPUT sa,10

INPUT s3,03
COMPARE s3,00
JUMP Z,l31
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99

LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l32
l31: LOAD sf,99
LOAD sf,99
l32:CALL p1
COMPARE sb,00
JUMP Z,l33
LOAD se,02
AND se,sd
COMPARE se,00
JUMP Z,l34
SUB sa,01
JUMP l2
l34: LOAD sb,00
ADD sa,01
JUMP l4
l33: LOAD se,01
AND se,sd
COMPARE se,00
JUMP Z, l35
ADD sa,01
JUMP l4
l35: LOAD sb,01
SUB sa,01
JUMP l2

l4: OUTPUT sa,10

INPUT s4,04
COMPARE s4,00

JUMP Z,l41
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l42
l41: LOAD sf,99
LOAD sf,99
l42:CALL p1
COMPARE sb,00
JUMP Z,l43
LOAD se,02

AND se,sd
COMPARE se,00
JUMP Z,l44
SUB sa,01
JUMP l3
l44: LOAD sb,00
ADD sa,01
JUMP l5
l43: LOAD se,01
AND se,sd
COMPARE se,00
JUMP Z, l45
ADD sa,01
JUMP l5
l45: LOAD sb,01
SUB sa,01
JUMP l3

l5: OUTPUT sa,10

INPUT s5,05
COMPARE s5,00
JUMP Z,l51
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99

LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l52
l51: LOAD sf,99
LOAD sf,99
l52:CALL p1
COMPARE sb,00
JUMP Z,l53
LOAD se,02
AND se,sd
COMPARE se,00
JUMP Z,l54
SUB sa,01
JUMP l4
l54: LOAD sb,00
ADD sa,01
JUMP l6
l53: LOAD se,01
AND se,sd
COMPARE se,00

JUMP Z, l55
ADD sa,01
JUMP l6
l55: LOAD sb,01
SUB sa,01
JUMP l4

l6: OUTPUT sa,10

INPUT s6,06
COMPARE s6,00
JUMP Z,l61
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99

LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l62
l61: LOAD sf,99
LOAD sf,99
l62:CALL p1
COMPARE sb,00
JUMP Z,l63
LOAD se,02
AND se,sd
COMPARE se,00
JUMP Z,l64
SUB sa,01
JUMP l5
l64: LOAD sb,00
ADD sa,01
JUMP l7
l63: LOAD se,01
AND se,sd
COMPARE se,00
JUMP Z, l65
ADD sa,01
JUMP l7
l65: LOAD sb,01
SUB sa,01
JUMP l5

l7: OUTPUT sa,10

INPUT s7,07
COMPARE s7,00

JUMP Z,l71
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
LOAD sf,99
JUMP l72
l71: LOAD sf,99
LOAD sf,99
l72: CALL p1
LOAD sb,01
SUB sa,01
JUMP l6

p1:
OUTPUT sa, 11
INPUT sc,08
COMPARE sc,00
JUMP Z,p11
JUMP p13
p11: INPUT sc,09
COMPARE sc,00
JUMP Z, p12
LOAD sd,02 ;right empty left full
RETURN
p12: JUMP p1
p13: INPUT sc,09
COMPARE sc,00
JUMP Z,p14
LOAD sd,03 ;both right and left full
RETURN
p14:LOAD sd,01 ;right full,left empty
RETURN

Simulation:

Schematic: