Professional Documents
Culture Documents
23 April 2003
Bobby Nazief (nazief@cs.ui.ac.id)
Qonita Shahab (niet@cs.ui.ac.id)
bahan kuliah: http://www.cs.ui.ac.id/kuliah/iki10230/
MEMORY HIERARCHY
Disk
HUGE capacity (virtually limitless)
VERY slow: runs on order of milliseconds
so how do we account for this gap?
Me
mor
Memory (DRAM)
y
Kapasitas jauh lebih besar dari registers, lebih kecil
Hier
dari disk (tetap terbatas)
arc
Access time ~50-100 nano-detik, jauh lebih cepat
hy
dari disk (mili-detik)
(2/4
) Mengandung subset data pada disk (basically
portions of programs that are currently being run)
Higher
Levels in
memory
hierarchy
Lower
Level 1
Level 2
Increasing
Distance
from Proc.,
Decreasing
cost / MB
Level 3
...
Level n
Me
mor
Youre writing a term paper (Processor) at a
y in Doe
table
Hier
Doe
arcLibrary is equivalent to disk
hy
essentially limitless capacity
Ana
very slow to retrieve a book
logy
Table is memory
:
smaller capacity: means you must return book when
Libr
table fills up
ary
easier and faster to find a book there once youve
(1/2
) already retrieved it
Me
mor
yOpen books on table are cache
smaller capacity: can have very few open books
Hier
arc fit on table; again, when table fills up, you must
close a book
hy
much, much faster to retrieve data
Ana
logy
Illusion created: whole library open on the
:tabletop
Libr
Keep as many recently used books open on
ary table as possible since likely to use again
Also keep as many books on table as possible,
(2/2
) since faster than going to library
Why hierarchy
works
The Principle of Locality:
Program access a relatively small portion of
the address space at any instant of time.
Probability
of reference
Address Space
2^n - 1
Upper Level
Memory
Lower Level
Memory
Blk X
From Processor
Blk Y
10
Processor
Control
Speed (ns): 1s
Size (bytes): 100s
On-Chip
Cache
Registers
Datapath
Second
Level
Cache
(SRAM)
Main
Memory
(DRAM)
10s
100s
Ks
Ms
Secondary
Storage
(Disk)
Tertiary
Storage
(Disk)
10,000,000s 10,000,000,000s
(10s ms)
(10s sec)
Gs
Ts
11
12
13
Cache
14
Cache
Cache
Memory-I/O
Memory-I/Obus
bus
Memory
Memory
I/O
I/O
controller
controller
disk
Disk
disk
Disk
I/O
I/O
controller
controller
I/O
I/O
controller
controller
Display
Display
Network
Network
15
Wh
at is
Kecil, storage cepat untuk meningkatkan
a
average
access time dibandingkan memori
cac
Memanfaatkan
spatial & temporal locality
he?
Sebenarnya cache terlihat pada hirarkis
penyimpanan
Registers a cache on variables software
managed
First-level cache a cache on second-level cache
Second-level cache a cache on memory
Memory a cache on disk (virtual memory)
16
Cache Design
Bagaimana organisasi cache? (ingat: cache
akan menerima alamat memori dari
prosesor, tidak ada perubahan pada
rancangan prosesor ada/tanpa cache).
Bagaimana melakukan mapping (relasi)
antara alamat memori dengan cache (ingat:
prosesor hanya melihat memory byte
addressable)
Bagaimana mengetahui elemen data tsb
berada di cache (hit) atau tidak ada (miss)
(ingat: cache jauh lebih kecil dari main
memory)?
17
To Processor
Cache
Main
Memory
Blk X
From Processor
Blk Y
Hit
18
Direct Mapping
Memory
Address Memory
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Cache
Index
0
1
2
3
4ByteDirect
MappedCache
Associative Mapping
Memory
Address Memory
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Cache
Index
0
1
2
3
4ByteAssociative
MappedCache
20
Set-Associative Mapping
Memory
Address Memory
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Cache
Index
0
1
2
3
4ByteSetAssociative
MappedCache
0
1
Cache
Set
21
Address Mapping
22
Example: Direct-Mapped
Masalah: multiple alamat memori map ke
indeks blok yang sama!
Bagaimana kita mengetahui apakah alamat blok
yang diinginkan berada di cache?
Harus ada identifikasi blok memori dikaitkan
dengan alamat
index
to
select
block
byte
offset
within
block
23
25
Dire
ctMap
Index: (~index into an array of blocks)
diperlukan untuk menentukan blok yang mana
ped
pada cache (rows yang mana)
Cac
cache mempunyai 16 KB = 214 bytes
he
blok mempunyai 24 bytes (4 words)
Exa
mpl
rows/cache = # blocks/cache (sebab setiap rows
e # terdiri
dari satu blok)
(2/3 =
bytes/cache / bytes/row
)
14
4
=
2 bytes/cache / 2 bytes/row
=
210 rows/cache
diperlukan 10 bit untuk menentukan indeks pada
rows dari cache
26
4 bits offset
10 bit index
18 bit tag
Struktur cache:
1.
2.
3.
4.
27
Cache
Index
0000000000
0000000001
0000000010
0000000011
28
Replacement Algorithms
Berlaku bagi:
Associative Mapping
Set-Associative Mapping
29