1
Power Semiconductor
Devices
Version 2 EE IIT, Kharagpur 1
Lesson
1
Power Electronics
Version 2 EE IIT, Kharagpur 2
Introduction
This lesson provides the reader the following:
Power Electronics is the art of converting electrical energy from one form to another in an
efficient, clean, compact, and robust manner for convenient utilisation.
• Power semiconductor devices  their physics, characteristics, drive requirements and their
protection for optimum utilisation of their capacities,
• Power converter topologies involving them,
• Control strategies of the converters,
• Digital, analogue and microelectronics involved,
• Capacitive and magnetic energy storage elements,
• Rotating and static electrical devices,
• Quality of waveforms generated,
• Electro Magnetic and Radio Frequency Interference,
Fig. 1.2 Typical Bipolar transistor based (a) linear (common emitter) (voltage)
amplifier stage and (b) switching (power) amplifier
230 V
230 V
Fig. 1.4 (a) A Linear regulator and (b) a switching regulator solution of the specification
above
The linear solution, Fig. 1.4 (a), to this quite common specification would first step down the
supply voltage to 12012 V through a power frequency transformer. The output would be
rectified using Power frequency diodes, electrolytic capacitor filter and then series regulated
using a chip or a audio power transistor. The tantalum capacitor filter would follow. The balance
of the voltage between the output of the rectifier and the output drops across the regulator device
which also carries the full load current. The power loss is therefore considerable. Also, the step
down ironcore transformer is both heavy, and lossy. However, only twicelinefrequency ripples
appear at the output and material cost and technical knowhow required is low.
In the switching solution Fig. 1.4 (b) using a MOSFET driven flyback converter, first the line
voltage is rectified and then isolated, steppeddown and regulated. A ferritecore highfrequency
(HF) transformer is used. Losses are negligible compared to the first solution and the converter is
extremely light. However significant high frequency (related to the switching frequency) noise
appear at the output which can only be minimised through the use of costly 'grass' capacitors.
The Power MOSFET burst into the scene commercially near the end seventies. This device
also represents the first successful marriage between modern integrated circuit and discrete
power semiconductor manufacturing technologies. Its voltage drive capability – giving it again a
higher gain, the ease of its paralleling and most importantly the much higher operating
frequencies reaching upto a few MHz saw it replacing the Bipolar also at the sub10 KW range
mainly for SMPS type of applications. Extension of VLSI manufacturing facilities for the
MOSFET reduced its price visàvis the Bipolar also. However, being a majority carrier device
its onstate voltage is dictated by the RDS(ON) of the device, which in turn is proportional to about
VDSS2.3 rating of the MOSFET. Consequently, highvoltage MOSFETS are not commercially
viable.
Improvements were being tried out on the SCR regarding its turnoff capability mostly by
reducing the turnon gain. Different versions of the Gateturnoff device, the Gate turnoff
Thyristor (GTO), were proposed by various manufacturers  each advocating their own symbol
for the device. The requirement for an extremely high turnoff control current via the gate and
the comparatively higher cost of the device restricted its application only to inverters rated above
a few hundred KVA.
The lookout for a more efficient, cheap, fast and robust turnoffable device proceeded in
different directions with MOS drives for both the basic thysistor and the Bipolar. The Insulated
Gate Bipolar Transistor (IGBT) – basically a MOSFET driven Bipolar from its terminal
characteristics has been a successful proposition with devices being made available at about 4
KV and 4 KA. Its switching frequency of about 25 KHz and ease of connection and drive saw
it totally removing the Bipolar from practically all applications. Industrially, only the MOSFET
has been able to continue in the sub – 10 KVA range primarily because of its high switching
frequency. The IGBT has also pushed up the GTO to applications above 25 MVA.
Presently there are few hybrid devices and Intelligent Power Modules (IPM) are marketed by
some manufacturers. The IPMs have already gathered wide acceptance. The 4500 V, 1200 A
Version 2 EE IIT, Kharagpur 7
IEGT (injectionenhanced gate transistor) of Toshiba or the 6000 V, 3500 A IGCT (Integrated
Gate Commutated Thyristors) of ABB which are promising at the higher power ranges.
However these new devices must prove themselves before they are accepted by the industry at
large.
Silicon carbide is a wide band gap semiconductor with an energy band gap wider than about
2 eV that possesses extremely high thermal, chemical, and mechanical stability. Silicon carbide
is the only wide band gap semiconductor among gallium nitride (GaN, EG = 3.4 eV), aluminum
nitride (AlN, EG = 6.2 eV), and silicon carbide that possesses a highquality native oxide suitable
for use as an MOS insulator in electronic devices The breakdown field in SiC is about 8 times
higher than in silicon. This is important for highvoltage power switching transistors. For
example, a device of a given size in SiC will have a blocking voltage 8 times higher than the
same device in silicon. More importantly, the onresistance of the SiC device will be about two
decades lower than the silicon device. Consequently, the efficiency of the power converter is
higher. In addition, SiCbased semiconductor switches can operate at high temperatures
(~600 C) without much change in their electrical properties. Thus the converter has a higher
reliability. Reduced losses and allowable higher operating temperatures result in smaller heatsink
size. Moreover, the high frequency operating capability of SiC converters lowers the filtering
requirement and the filter size. As a result, they are compact, light, reliable, and efficient and
have a high power density. These qualities satisfy the requirements of power converters for most
applications and they are expected to be the devices of the future.
Ratings have been progressively increasing for all devices while the newer devices offer
substantially better performance. With the SCR and the pindiodes, so called because of the
sandwiched intrinsic ‘i’layer between the ‘p’ and ‘n’ layers, having mostly linecommutated
converter applications, emphasis was mostly on their static characteristics  forward and reverse
voltage blocking, current carrying and overcurrent ratings, onstate forward voltage etc and also
on issues like paralleling and series operation of the devices. As the operating speeds of the
devices increased, the dynamic (switching) characteristics of the devices assumed greater
importance as most of the dissipation was during these transients. Attention turned to the
development of efficient drive networks and protection techniques which were found to enhance
the performance of the devices and their peak power handling capacities. Issues related to
paralleling were resolved by the system designer within the device itself like in MOSFETS,
while the converter topology was required to take care of their series operation as in multilevel
converters.
The range of power devices thus developed over the last few decades can be represented as a
tree, Fig. 1.5, on the basis of their controllability and other dominant features.
UNCONTROLLED CONTROLLED
Power Diodes
diF /dt
t0 t1 t2 SNAPPY
SOFT
Q1 Q2
Δ to
IRM
VRM
Fig. 1.6 Typical turnoff dynamics of a soft and a 'snappy' diode'
Silicon Power diodes are the successors of Selenium rectifiers having significantly improved
forward characteristics and voltage ratings. They are classified mainly by their turnoff
(dynamic) characteristics Fig. 1.6. The minority carriers in the diodes require finite time  trr
(reverse recovery time) to recombine with opposite charges and neutralise. Large values of Qrr (=
Q1 + Q2)  the charge to be dissipated as a negative current when the and diode turns off and trr
(= t2  t0)  the time it takes to regain its blocking features, impose strong current stresses on the
controlled device in series. Also a 'snappy' type of recovery of the diode effects high di/dt
voltages on all associated power device in the converter because of load or stray inductances
present in the network. There are broadly three types of diodes used in Power electronic
applications:
Linefrequency diodes: These PIN diodes with generalpurpose rectifier type applications, are
available at the highest voltage (~5kV) and current ratings (~5kA) and have excellent over
current (surge rating about six times average current rating) and surgevoltage withstand
capability. They have relatively large Qrr and trr specifications.
Schottky rectifiers: These are the fastest rectifiers being majority carrier devices without any
Qrr.. However, they are available with voltage ratings up to a hundred volts only though current
ratings may be high. Their conduction voltages specifications are excellent (~0.2V). The freedom
from minority carrier recovery permits reduced snubber requirements. Schottky diodes face no
competition in low voltage SPMS applications and in instrumentation.
Converter grade or Phase Control thyristors These devices are the work horses of the
Power Electronics. They are turned off by natural (line) commutation and are reverse biased at
least for a few milliseconds subsequent to a conduction period. No fast switching feature is
desired of these devices. They are available at voltage ratings in excess of 5 KV starting from
about 50 V and current ratings of about 5 KA. The largest converters for HVDC transmission are
built with seriesparallel combination of these devices. Conduction voltages are device voltage
rating dependent and range between 1.5 V (600V) to about 3.0 V (+5 KV). These devices are
unsuitable for any 'forcedcommutated' circuit requiring unwieldy large commutation
components.
The dynamic di/dt and dv/dt capabilities of the SCR have vastly improved over the years
borrowing emitter shorting and other techniques adopted for the faster variety. The requirement
for hard gate drives and di/dt limting inductors have been eliminated in the process.
Inverter grade thyristors: Turnoff times of these thyristors range from about 5 to 50 μsecs
when hard switched. They are thus called fast or 'inverter grade' SCR's. The SCR's are mainly
used in circuits that are operated on DC supplies and no alternating voltage is available to turn
them off. Commutation networks have to be added to the basic converter only to turnoff the
SCR's. The efficiency, size and weight of these networks are directly related to the turnoff time,
tq of the SCR. The commutation circuits utilised resonant networks or charged capacitors. Quite
a few commutation networks were designed and some like the McMurrayBedford became
widely accepted.
The IGBT
It is a voltage controlled fourlayer device with the advantages of the MOSFET driver
and the Bipolar Main terminal. IGBTs can be classified as punchthrough (PT) and nonpunch
through (NPT) structures. In the punchthrough IGBT, a better tradeoff between the forward
voltage drop and turnoff time can be achieved. Punchthrough IGBTs are available up to about
1200 V. NPT IGBTs of up to about 4 KV have been reported in literature and they are more
robust than PT IGBTs particularly under short circuit conditions. However they have a higher
forward voltage drop than the PT IGBTs. Its switching times can be controlled by suitably
shaping the drive signal. This gives the IGBT a number of advantages: it does not require
protective circuits, it can be connected in parallel without difficulty, and series connection is
possible without dv/dt snubbers. The IGBT is presently one of the most popular device in view
of its wide ratings, switching speed of about 100 KHz a easy voltage drive and a square Safe
Operating Area devoid of a Second Breakdown region.
The GTO
The GTO is a power switching device that can be turned on by a short pulse of gate current and
turned off by a reverse gate pulse. This reverse gate current amplitude is dependent on the anode
current to be turned off. Hence there is no need for an external commutation circuit to turn it off.
Because turnoff is provided by bypassing carriers directly to the gate circuit, its turnoff time is
short, thus giving it more capability for highfrequency operation than thyristors. The GTO
symbol and turnoff characteristics are shown in Fig. 30.3. GTOs have the I2t withstand
capability and hence can be protected by semiconductor fuses. For reliable operation of GTOs,
the critical aspects are proper design of the gate turnoff circuit and the snubber circuit.
Cycloconverter,
AC to AC ACPAC, AC of desired frequency and/or
~
Matrix
converter
magnitude from generally line
AC ~
Thus separate isolated power supplies are also required for each Power device in the
converter (the ones having a common Control Terminal  say the Emitter in an IGBT  may
require a few less). There are functionally two types of isolators: the pulse transformer which
can transmit after isolation, in a multidevice converter, both the unshaped signal and power and
optical isolators which transmit only the signal. The former is sufficient for a SCR without
isolated power supplies at the secondary. The latter is a must for practically all other devices.
Fig. 1.7 illustrates to typical drive circuits for an IGBT and an SCR.
Vref
COMPARATOR TIMER
Fig. 1.7 Simple gatedrive and protection circuit for a standalone IGBT and a SCR
1. Overcurrent;
2. di/dt;
3. Voltage spike or overvoltage;
4. dv/dt ;
5. Gateunder voltage;
6. Over voltage at gate;
7. Excessive temperature rise;
8. Electrostatic discharge;
Semiconductor devices of all types exhibit similar responses to most of the stresses, however
there are marked differences. The SCR is the most robust device on practically all counts. That it
has an I2t rating is proof that its internal thermal capacities are excellent. A HRC fuse, suitably
selected, and in coordination with fast circuit breakers would mostly protect it. This sometimes
becomes a curse when the cost of the fuse becomes exorbitant. All transistors, specially the BJT
and the IGBT is actively protected (without any operating cost!) by sensing the Main Terminal
voltage, as shown in Fig. 1.7. This voltage is related to the current carried by the device. Further,
the transistors permit designed gate current waveforms to minimise voltage spikes as a
consequence of sharply rising Main terminal currents. Gate resistances have significant effect on
turnon and turnoff times of these devices  permitting optimisation of switching times for the
reduction of switching losses and voltage spikes.
Ans: a) MOSFET; b) SCR; c) MOSFET; d) MOSFET; e) SCR ; (f) GTO; (g) IGBT
Qs#2 An SCR requires 50 mA gate current to switch it on. It has a resistive load and is supplied
from a 100 V DC supply. Specify the Pulse transformer details and the circuit following it, if the
driver circuit supply voltage is 10 V and the gatecathode drop is about 1 V.
Ans: The most important ratings of the Pulse transformer are its voltsecs rating, the isolation
voltage and the turns ratio.
The voltsecs is decided by the product of the primary pulsevoltage multiplied by the period for
which the pulse is applied to the winding
The Pulse transformer may be chosen as: 1:1, 450 μVs, Visol = 2.5 KV, IM = 150 mA
The circuit shown in Fig. 1.7 may be used. Diodes 1N4002
Series resistance
= (Supply voltage – drive transistor drop – gatecathode drop)/100mA
= (10 –1 –1) / 100 E3
= 80 Ohm
= 49 or 57 Ohm (nearest available lower value)
1. Draw the spatial distribution of charge density, electric field and electric potential in a
step junction pn diode.
2. Calculate the voltage drop across a forward biased diode for a given forward current and
viceverse.
3. Identify the constructional features that distinguish a power diode from a signal level
diode.
4. Differentiate between different reverse voltage ratings found in a Power Diode speciation
sheet.
5. Identify the difference between the forward characteristic of a power diode and a signal
level diode and explain it.
6. Evaluate the forward current specifications of a diode for a given application.
7. Draw the “Turn On” and “Turn Off” characteristics of a power diode.
8. Define “Forward recovery voltage”, “Reverse recovery current” “Reverse Recovery
charge” as applicable to a power diode.
2.1 Introduction
Power semiconductor diode is the “power level” counter part of the “low power signal diodes”
with which most of us have some degree of familiarity. These power devices, however, are
required to carry up to several KA of current under forward bias condition and block up to
several KV under reverse biased condition. These extreme requirements call for important
structural changes in a power diode which significantly affect their operating characteristics.
These structural modifications are generic in the sense that the same basic modifications are
applied to all other low power semiconductor devices (all of which have one or more pn
junctions) to scale up their power capabilities. It is, therefore, important to understand the nature
and implication of these modifications in relation to the simplest of the power devices, i.e., a
power semiconductor diode.
Fig 2.1: Space change density the electric field and the electric potential in side a pn
junction under (a) thermal equilibrium condition, (b) reverse biased condition,
(c) forward biased condition.
When an external voltage is applied with p side move negative then the n side the junction is
said to be under reverse bias condition. This reverse bias adds to the height of the potential
barrier. The electric field strength at the junction and the width of the space change region (also
called “the depletion region” because of the absence of free carriers) also increases. On the other
hand, free minority carrier densities (np in the p side and pn in the n side) will be zero at the edge
of the depletion region on either side (Fig 2.1 (b)). This gradient in minority carrier density
causes a small flux of minority carriers to defuse towards the deletion layer where they are swept
immediately by the large electric field into the electrical neutral region of the opposite side. This
will constitute a small leakage current across the junction from the n side to the p side. There
will also be a contribution to the leakage current by the electron hole pairs generated in the space
change layer by the thermal ionization process. These two components of current together is
called the “reverse saturation current Is” of the diode. Value of Is is independent of the reverse
voltage magnitude (up to a certain level) but extremely sensitive to temperature variation.
When the applied reverse voltage exceeds some threshold value (for a given diode) the reverse
current increases rapidly. The diode is said to have undergone “reverse break down”.
Reverse break down is caused by "impact ionization" as explained below. Electrons accelerated
by the large depletion layer electric field due to the applied reverse voltage may attain sufficient
knick energy to liberate another electron from the covalent bonds when it strikes a silicon atom.
The liberated electron in turn may repeat the process. This cascading effect (avalanche) may
produce a large number of free electrons very quickly resulting in a large reverse current. The
power dissipated in the device increases manifold and may cause its destruction. Therefore,
operation of a diode in the reverse breakdown region must be avoided.
Exercise 2.1
(i) The width of the space charge region increases as the applied ______________ voltage
increases.
(ii) The maximum electric field strength at the center of the depletion layer increases
with _______________ in the reverse voltage.
(iii) Reverse saturation current in a power diode is extremely sensitive to ___________
variation.
Version 2 EE IIT, Kharagpur 6
(iv) Donor atoms are _____________________ carrier providers in the p type and
_________________ carrier providers in the n type semiconductor materials.
(v) Forward current density in a diode is __________________________ proportional to the
life time of carriers.
Answer: (i) Reverse, (ii) increase, (iii) temperature, (iv) Minority Majority, (v) inversely
(2) A pn junction diode has a reverse saturation current rating of 50 nA at 32°C. What
should be the value of the forward current for a forward voltage drop of 0.5V. Assume VT =
KT/q at 32°C = 26 mv.
Answer
⎛ V ⎞
I F = I s ⎜ e VT  1 ⎟ , Is = 5×108 A, VT = 26×103 V V = 0.5V
⎝ ⎠
∴ I F = 11.24 Am ps.
di
(3) For the diode of Problem2 calculate the dynamic ac resistance ra c = F d v F at 32°C and a
forward voltage drop of 0.5V.
Answer:
⎛ VF VT ⎞ diF Is VF
iF = Is ⎜ e 1⎟ ∴ = e VT
⎝ ⎠ dVF VT
N ow I s = 5 × 10 8 A , V F = 0.5V ,
3
VT = 26 ×10 V at 32o C
V
dVF V  F
∴ = ra c = T e V T = 2 .3 1 3 m Ω
diF Is
(b)
Fig. 2.3: Diagram of a power; (a) circuit symbol (b) photograph; (c) schematic cross
section.
To arrive at the structure shown in Fig 2.3 (c) a lightly doped n epitaxial layer of specified width
(depending on the required break down voltage) and donor atom density (NdD) is grown on a
heavily doped n+ substrate (NdK donor atoms.Cm 3) which acts as the cathode. Finally the pn
junction is formed by defusing a heavily doped (NaA acceptor atoms.Cm3) p+ region into the
epitaxial layer. This p type region acts as the anode.
Impurity atom densities in the heavily doped cathode (Ndk .Cm 3) and anode (NaA.Cm 3) are
approximately of the same order of magnitude (10 19 Cm 3) while that of the epitaxial layer (also
called the drift region) is lower by several orders of magnitude (NdD ≈ 10 14 Cm3). In a low
power diode this drift region is absent. The Implication of introducing this drift region in a power
diode is explained next.
As in the case of a low power diode the applied reverse voltage is supported by the depletion
layer formed at the p+ n metallurgical junction. Overall neutrality of the space change region
dictates that the number of ionized atoms in the p+ region should be same as that in the n region.
However, since NdD << NaA, the space charge region almost exclusively extends into the n drift
Fig 2.4: Electric field strength in reverse biased power Diodes; (a) Nonpunch through
type; (b) punch through type.
In nonpunch through type diodes the electric field strength is maximum at the p+ n junction and
decrease to zero at the end of the depletion region. Where as, in the punch through construction
the field strength is more uniform. In fact, by choosing a very lightly doped n drift region,
Electric field strength in this region can be mode almost constant. Under the assumption of
uniform electric field strength it can be shown that for the same break down voltage, the “punch
through” construction will require approximately half the drift region width of a comparable “
non  punch through” construction.
Lower drift region doping in a “punch through” diode does not carry the penalty of higher
conduction lasses due to “conductivity modulation” to be discussed shortly. In fact, reduced
width of the drift region in these diodes lowers the onstate voltage drop for the same forward
current density compared to a nonpunch through diode.
Under reverse bias condition only a small leakage current (less than 100mA for a rated forward
current in excess of 1000A) flows in the reverse direction (i.e from cathode to anode). This
reverse current is independent of the applied reverse voltage but highly sensitive to junction
temperature variation. When the applied reverse voltage reaches the break down voltage, reverse
current increases very rapidly due to impact ionization and consequent avalanche multiplication
process. Voltage across the device dose not increase any further while the reverse current is
limited by the external circuit. Excessive power loss and consequent increase in the junction
temperature due to continued operation in the reverse brake down region quickly destroies the
diode. Therefore, continued operation in the reverse break down region should be avoided. A
typical IV characteristic of a power diode under reverse bias condition is shown in Fig 2.5.
A few other important specifications of a power Diode under reverse bias condition usually
found in manufacturer’s data sheet are explained below.
DC Blocking Voltage (VRDC): Maximum direct voltage that can be applied in the reverse
direction (i.e cathode positive with respect to anode) across the device for indefinite period of
time. It is useful for selecting freewheeling diodes in DCDC Choppers and DCAC voltage
source inverter circuits.
RMS Reverse Voltage (VRMS): It is the RMS value of the power frequency (50/60 HZ) since
wave voltage that can be directly applied across the device. Useful for selecting diodes for
controlled / uncontrolled power frequency line commutated AC to DC rectifiers. It is given by
the manufacturer under the assumption that the supply voltage may rise by 10% at the most. This
rating is different for resistive and capacitive loads.
Peak Repetitive Reverse Voltage (VRRM): This is the maximum permissible value of the
instantiations reverse voltage appearing periodically across the device. The time period between
two consecutive appearances is assumed to be equal to half the power cycle (i.e 10ms for 50 HZ
supply). This type of period reverse voltage may appear due to “commutation” in a converter.
Peak NonRepetitive Reverse Voltage (VRSM): It is the maximum allowable value of the
instantaneous reverse voltage across the device that must not recur. Such transient reverse
voltage can be generated by power line switching (i.e circuit Breaker opening / closing) or
lightning surges.
Fig. 2.6 shows the relationship among these different reverse voltage specifications.
Both Vj and VAK have negative temperature coefficient as shown in the figure.
Few other important specifications related to forward bias operation of power diode as found in
manufacturer’s data sheet are explained next.
Maximum RMS Forward current (IFRMS): Due to predominantly resistive nature of the
forward voltage drop across a forward biased power diode, RMS value of the forward current
determines the conduction power loss. The specification gives the maximum allowable RMS
value of the forward current of a given wave shape (usually a half cycle sine wave of power
frequency) and at a specified case temperature. However, this specification can be used as a
guideline for almost all wave shapes of the forward current.
Maximum Average Forward Current (IFAVM): Diodes are often used in rectifier circuits
supplying a DC (average) current to be load. In such cases the average load current and the diode
forward current usually have a simple relationship. Therefore, it will be of interest to know the
Fig 2.8: Derating curves for the forward current of a Power Diode.
Average Forward Power loss (PAVF): Almost all power loss in a diode occurs during forward
conduction state. The forward power loss is therefore an important parameter in designing the
cooling arrangement. Average forward power loss over a full cycle is specified by the
manufacturers as a function of the average forward current (IAVF) for different conduction angles
as shown in Fig 2.9.
Fig 2.9: Average forward power loss vs. average forward current of a power Diode.
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Surge and Fault Current: In some rectifier applications a diode may be required to conduct
forward currents far in excess of its RMS or average forward current rating for some duration
(several cycles of the power frequency). This is called the repetitive surge forward current of a
diode. A diode is expected to operate normally after the surge duration is over.
On the other hand, fault current arising due to some abnormality in the power circuit may have a
higher peak valve but exists for shorter duration (usually less than an half cycle of the power
frequency). A diode circuit is expected to be disconnected from the power line following a fault.
Therefore, a fault current is a non repetitive surge current. Power diodes are capable of
withstanding both types of surge currents and this capability is expressed in terms of two surge
current ratings as discussed next.
Peak Repetitive surge current rating (IFRM): This is the peak valve of the repetitive surge
current that can be allowed to flow through the diode for a specific duration and for specified
conditions before and after the surge. The surge current waveform is assumed to be half
sinusoidal of power frequency with current pulses separated by “OFF” periods of equal duration.
The case temperature is usually specified at its maximum allowable valve before the surge. The
diode should be capable of withstanding maximum repetitive peak reverse voltage (VRRM) and
Maximum allowable average forward current (IFAVM) following the surge. The surge current
specification is usually given as a function of the surge duration in number of cycles of the
power frequency as shown in figure 2.10
Fig 2.10: Peak Repetitive surge current VS time curve of a power diode.
In case the surge current is specified only for a fixed number of cycles ‘m’
then the surge current specification applicable to some other cycle number ‘n’ can be found from
the approximate formula.
m
I FRM \ n = I \ (2.4)
n FRM m
Peak NonRepetitive surge current (IFRM): This specification is similar to the previous one
except that the current pulse duration is assumed to be within one half cycle of the power
Fig. 2.11: Nonrepetitive surge current and surge current integral vs. current pulse width
characteristics of a power Diode.
Exercise 2.2
i. The ____________ region in a power diode increases its reverse voltage blocking
capacity.
ii. The maximum DC voltage rating (VRDC) of a power diode is useful for selecting
________________ diodes in a DCDC chopper.
iii. The reverse breakdown voltage of a Power Diode must be greater than
________________ .
iv. The iv characteristics of a power diode for large forward current is __________ .
v. The average current rating of a power diode _______________ with reduction in the
conduction angle due to increase in the current ___________________ .
vi. The derating curves of a Power diode provides relationship between the ______________
and the _________________ .
∫ i dt rating of a power diode is useful for selecting the ________________ .
2
vii.
Answer: (i) drift, (ii) free wheeling, (iii) VRSM, (iv) linear, (v) decrease, form factor, (vi)
IFAVM/IFRM, case temperature, (vii) protective fuse.
Answer: (a) During every positive half cycle of the supply the capacitor charges to the peak
value of the supply voltage. If the load disconnected the capacitor voltage will not change when
the supply goes through its negative peak as shown in the associated waveform. Therefore the
diode will be subjected to a reverse voltage equal to the peak to peak supply voltage in each
cycle. Hence, the required VRRM rating will be
(d) Peak surge current will flow through the circuit when the load is accidentally short circuited.
The peak surge current rating will be
2 × 230
I FSM = A = 162.64 A
2
The peak non repetitive surge current should not recur. Therefore, the protective fuse (to
be connected in series with the diode) must blow during the negative half cycle following the
fault. Therefore the maximum i2t rating of the fuse is
π
∫i
2
dt = ∫ I 2 F S M S in 2 w td w t = π I 2 F S m = 4 1 .5 5 × 1 0 3 A 2 s e c
M ax o 2
It is observed that the forward diode voltage during turn ON may transiently reach a significantly
higher value Vfr compared to the steady slate voltage drop at the steady current IF.
In some power converter circuits (e.g voltage source inverter) where a free wheeling diode is
used across an asymmetrical blocking power switch (i.e GTO) this transient over voltage may be
high enough to destroy the main power switch.
Vfr (called forward recovery voltage) is given as a function of the forward di/dt in the
manufacturer’s data sheet. Typical values lie within the range of 1030V. Forward recovery time
(tfr) is typically within 10 us.
Observed Turn OFF behavior of a Power Diode: Figure 2.13 shows a typical turn off
behavior of a power diode assuming controlled rate of decrease of the forward current.
During the period t5 large current and voltage exist simultaneously in the device. At high
switching frequency this may result in considerable increase in the total power loss.
Important parameters defining the turn off characteristics are, peak reverse recovery current (Irr),
reverse recovery time (trr), reverse recovery charge (Qrr) and the snappiness factor S.
Of these parameters, the snappiness factor S depends mainly on the construction of the diode
(e.g. drift region width, doping lever, carrier life time etc.). Other parameters are interrelated and
also depend on S. Manufacturers usually specify these parameters as functions of diF/dt for
different values of IF. Both Irr and Qrr increases with IF and diF/dt while trr increases with IF and
decreases with diF/dt.
Version 2 EE IIT, Kharagpur 19
The reverse recovery characteristics shown in Fig. 2.13 is typical of a particular type of diodes
called “normal recovery” or “soft recovery” diode (S>1). The total recovery time (trr) in this case
is a few tens of microseconds. While this is acceptable for line frequency rectifiers (these diodes
are also called rectifier grade diodes) high frequency circuits (e.g PWM inverters, SMPS)
demand faster diode recovery. Diode reverse recovery time can be reduce by increasing the rate
of decrease of the forward current (i.e, by reducing stray circuit inductance) and by using
“snappy” recovery (S<<1) diode. The problems with this approach are:
i) Increase of diF/dt also increases the magnitude of Irr
ii) Large recovery current coupled with ”snappy” recovery may give rise to current and
voltage oscillation in the diode due to the resonant circuit formed by the stray circuit
inductance and the diode depletion layer capacitance. A typical recovery characteristics
of a “snappy” recovery diode is shown in Fig 2.14 (a).
Fig. 2.14: Diode overvoltage protection circuit; (a) “Snappy recovery characteristics; (b)
Capacitive snubber circuit; (c) snubber characteristics.
Large reverse recovery current may lead to reverse voltage peak (Vrr) in excess of VRSM and
destroy the device. A capacitive protection circuit (also called a “snubber circuit) as shown in
Fig. 2.14 (b) may to used to restrict Vrr. Here the current flowing through Ll at the time of diode
current “snapping” is bypassed to Cs. Ll,Rs & Cs forms a damped resonance circuit and the initial
energy stored in Ll is partially dissipated in Rs, thereby, restricting Vrr . Normalized values of Vrr
as a function of the damping factor ξ with normalized Irr as a parameter is shown in Fig. 2.14(c).
However, it is difficult to correctly estimate the value of Ll and hence design a proper snubber
circuit. Also snubber circuits increase the overall power loss in the circuit since the energy stored
in the snubber capacitor is dissipated in the snubber resistance during turning ON of the diode.
Therefore, in high frequency circuits other types of fast recovery diodes (Inverter grade) are
preferred. Fast recovery diodes offer significant reduction in both Irr and trr (10%  20% of a
rectifier grade diode of comparable rating). This improvement in turn OFF performance,
however, comes at the expense of the steady state performance. It can be shown that the forward
voltage drop in a diode is directly proportion to the width of the drift region and inversely
proportional to the carrier life time in the drift region. On the other hand both Irr and trr increases
with increase in carrier life time and drift region width. Therefore if Irr and trr are reduced by
reducing the carrier life time, forward voltage drop increases. On the other hand, if the drift
Exerciser 2.3
i. Forward recovery voltage appears due to higher ohmic drop in the ______________ region
of a power diode in the beginning of the Turn On process.
ii. The magnitude of the forward recovery voltage is typically of the order of few
______________ of volts.
iii. The magnitude of the forward recovery voltage also depends on the _______________ of
the diode forward current.
iv. The reverse recovery charge of a power diode increases with the _______________ of the
diode forward current.
v. For a given forward current the reverse recovery current of a Power Diode ______________
with the rate of decrease of the forward current.
vi. For a given forward current the reverse recovery time of a Power diode ______________
with the rate of decrease of the forward current.
vii. A “snappy” recovery diode is subjected to _________________ voltage over shoot on
recovery.
viii. A fast recovery diode has _______________________ reverse recovery current and time
compared to a __________________ recovery diode.
ix. A Schottky diode has _______________ forward voltage drop and ______________ reverse
voltage blocking capacity.
x. Schottky diodes have no __________________ transient and very little
_________________ transient.
Answer: (i) drift, (ii) tens, (iii) rate of rise, (iv) magnitude, (v) increases, (vi) decreases, (vii)
large, (viii) lower, (ix) low, law, (x) Turn On, Turn Off.
2. In the buck converter shown the diode D has a lead inductance of 0.2μH and a reverse
recovery change of 10μC at iF =10A. Find peak current through Q.
diF 20
∴ = A S ec = 10 7 A S ec
dt .2 × 1 0 6
1 ⎛ diF ⎞ 2
Q rr = 1 I rr t rr = ⎜ ⎟ t rr
2 2 ⎝ dt ⎠
= 1 0 × 1 0 6 C
∴ t rr = 1 . 4 1 4 μ s
diF
∴ I rr = t rr = 1 4 . 1 4 A
dt
∴i =I +I = 24.14 A
Q peak L rr
2. A power diode have a reverse saturation current of 15μA at 32°C which doubles for
every 10° rise in temperature. The dc resistance of the diode is 2.5 mΩ. Find the forward
voltage drop and power loss for a forward current of 200 Amps. Assume that the
maximum junction temperature is restricted to 102°C.
VT = k T = 26 m v at 32 o C
q
3. In the voltage commutated chopper T & TA are turned ON alternately at 400 HZ. C is
initially charged to 200 V with polarity as shown. Find the IFRMS and VRRM ratings of DI
& DF.
5. What precaution must be taken regarding the forward recovery voltage of the free
wheeling diodes in a PWM voltage source inverter employing Bipolar Junction
Transistors of the npn type?
2. Since the reverse saturation current double with every 10°C rise in junction temperature.
1 0 2 3 2
Is 102o C
= 2 10
× Is 32o C
= 1 .9 2 m A
KT
Vt = = 26mv at 32 o C ∴ Vt at 102 o = 31.97mv
q
∴ V j fo r i F = 2 0 0 A is
iF
V j = Vt o
102 C
× ln = 0 .3 7 V
Is 102o C
i D I = I D IP S in ω n 0 ≤ ωn ≤ 7
w here I D IP = 200 C = 89.44 A
L
1
& ωn = = 22.36×103
LC
2 × 200 × C
TC = = 400μs
IL
At the end of charging DF turns ON and remains on till T is turned on again.
I DIP 140
∴ I FRMS For D I is = 10.58 Amps
2 5000
2100
I FRMS For D F is 20 = 12.96 Amps
5000
From figure VRRM for D I is 200 V
VRRM for D F is 400 V
5. Figure shows one leg of a PWM VSI using npn transistor and freewheeling diode.
1. Distinguish between, cut off, active, and saturation region operation of a Bipolar Junction
Transistor.
2. Draw the input and output characteristics of a junction transistor and explain their nature.
3. List the salient constructional features of a power BJT and explain their importance.
4. Draw the output characteristics of a Power BJT and explain the applicable operating
limits under Forward and Reverse bias conditions.
5. Interpret manufacturer’s data sheet ratings for a Power BJT.
6. Differentiate between the characteristics of an ideal switch and a BJT.
7. Draw and explain the Turn On characteristics of a BJT.
8. Draw and explain the Turn Off characteristics of a BJT.
9. Calculate switching and conduction losses of a Power BJT.
10. Design a BJT base drive circuit.
VCE
VCE
E (n) C (n) E (p) C (p)

iE VBE + i iC
C
iE VBE
iB B (p) B (n)
RC RC
VBB RB VBB
iB
VCC VCC
S
WBE 0
A
φCB
A
φBE A
0
φCB
S S φCB φ φBE
S
φBE φCB BE
S
x
A
φCB
0 φ 0 x WS
CB
S
WBE
φBE BE
S
φCB A
WCB WCB
A
WBE
A
WBE 0
WCB
0 0 0
WCB
WBE A WBE
WCB
JBE JCB JBE JCB
n SpB pSnB
If no external biasing voltages are applied (i.e.; VBB and VCC are open circuited) all transistor
currents must be zero. The transistor will be in thermal equilibrium condition with potential
barriers φοΒΕ and φCB o
at the base emitter and the base collector functions respectively.
O O
Corresponding depletion layer widths will be WBE and WCB . It is clear from the diagram that p
type carriers in the base region of an npn transistor are trapped in a “potential well” and cannot
escape. Similarly, in a pnp transistor p type carriers in the emitter and collector regions are
separated by a “potential hill”.
When biasing voltages are applied as shown in the figure, the base emitter junction (JBE)
becomes forward biased where as the base collector junction is reverse biased. Potential barrier
Α
and depletion layer width at JBE reduces to φΒΕ and WBE A
respectively. Both these quantities
increase at JCB ( φACB , WCB
A
) . As the potential barrier at JBE is reduced a large number of minority
A
carriers are introduced in to Base and the Emitter regions as shown in Fig. 3.1 ( PnE , n ApB for npn
As VBE is increased injected minority charge into the base region increases and so does the base
current and the collector current. For a fixed collector bias voltage VCC, the voltage VCB reduces
with increase in collector current due to increasing drop in the external resistance RC. Therefore,
the potential barrier at JCB starts reducing. At one point JCB becomes forward biased. The
potential barriers and depletion layer widths under this condition are indicated in Fig. 3.1 by
variables with a super script “s”. Due to forward biasing of JCB there will be minority carrier
injection into the base from this junction also as shown in Fig. 3.1. The total voltage drop
between collector and emitter will be the difference between the forward bias voltage drops at
JBE and JCB. Under this condition the transistor is said to be in the saturation region.
From the operating principle described above one can form a qualitative idea about the input (iB B
vs VBE) and output (iC Vs VCE) characteristics of a transistor. In the following section these
characteristics of an npn transistor will be discussed qualitatively. Similar explanation applies
to a pnp transistor.
When a biasing voltage VBB of appropriate polarity is applied across the junction JBE the
potential barrier at this junction reduces and at one point the junction becomes forward biased.
The current crossing this junction is governed by the forward biased pn junction equation for
a given collector emitter voltage. The base current iB is related to the recombination of minority
B
carriers injected into the base from the emitter. The rate of recombination is directly proportional
to the amount of excess minority carrier stored in the base. Since, in a normal transistor the
emitter is much more heavily doped compared to the base the current crossing JBE is almost
entirely determined by the excess minority carrier distribution in the base. Thus, it can be
concluded that the relationship between iB and VBE will be similar to the iv characteristics of a
B
pn junction diode. VCE, however have some effect on this characteristic. As VCE increases
reverse bias of JCB increases and the depletion region at JCB moves deeper into the base. The
effective base width thus reduces, reducing the rate of recombination in the base region and
hence the base current. Therefore iB for a given VBE reduces with increasing VCE as shown in
B
Fig. 3.2(a).
It has been mentioned before that only a fraction (denoted by the letter “∝”) of the total minority
carriers injected into the base reaches junction JCB where they are swept in to the collector region
by the large electric field at JCB. These minority carriers constitute the major component of the
total collector current. The other component of the collector current consists of the small reverse
saturation current of the reverse biased junction JCB.
But IE = IB + IC
B (3.2)
∝
By defining
β
1− ∝
IC = βIB + (β+1) Ics (3.4)
β is called the large signal common emitter current gain of the transistor and remains fairly
constant for a large range of IC, as shown in Fig. 3.2 (c). Fig: 3 (b) shows the complete out put
characteristics (ic vs VCE) of an npn transistor.
With VBB = 0 or negative there is little injected minority carrier into the base from the
emitter side. Therefore, iB = 0 and iC is negligibly small. The transistor is said to be in the “cut
B
As VBB is increased from zero, base current starts flowing. From equation (3.4) it will be
expected that the collector current should increase proportionately independent of VCE. However
Fig 3.2 (b) does indicate a slight increase in iC with VCE for a given iB. This is expected because
B
with increasing VCE a larger value of VBE will be required to maintain a given iB (Fig. 3.2 (a)).
B
Therefore, the component “∝IE” of collector current will increase. ICS is ,for all practical
purpose, independent of VCE. This is the active or “amplifier mode” of operation of a transistor.
In the active region as iB increases iC also increases. For a given value of VCC, VCE reduces with
B
increasing iC due to increased drop in an external load (i.e., Rc in Fig 3.1). At one point the
junction JCB becomes forward biased. VCE, now is just the difference between the voltages across
two forward biased junction JBE and JCB (a few handed milli volts). This is when the transistor
enters the saturation mode of operation. The ratio iC/iB at the onset of saturation is called βMin and
B
Saturation
vCE Active increasing
iB2
increasing iB1
iB = 0
vBE Cut off
vCE
(a) (b)
β
(c)
Fig. 3.2: Input and output characteristics of an n – p – n transistor.
(a) Input characteristics; (b) Output characteristics; (c) Current
gain[β] characteristics
Exercise 3.1
Exercise 3.2
Why does the collector current of a BJT in the active region increases with increasing collector
voltage for a given base current.
Answer: In the active region as the VCE voltage is increased the depletion layer width at the CB
junction increases and the effective base width reduces. Therefore, for a given VBE
recombination of minority carriers in the base region reduces and base current also
reduces. In order to main constant base current with increasing VCE, VBE must
increased. Therefore, for a constant base current the number of minority carriers in the
base region will increase and consequently, collector current will increase.
Exercise 3.3
∴ β = 7.95,
• A power BJT has a vertically oriented alternating layers of n type and p type
semiconductor materials as shown in Fig 3.3(a). The vertical structure is preferred for
power transistors because it maximizes the cross sectional area through which the on
state current flows. Thus, on state resistance and power lass is minimized.
• In order to maintain a large current gain “β” (and hence reduce base drive current) the
emitter doping density is made several orders of magnitude higher than the base region.
The thickness of the base region is also made as small as possible.
• In order to block large voltage during “OFF” state a lightly doped “collector drift region”
is introduced between the moderately doped base region and the heavily doped collector
region. The function of this drift region is similar to that in a Power Diode. However, the
doping density donation of the base region being “moderate” the depletion region does
penetrate considerably into the base. Therefore, the width of the base region in a power
transistor can not be made as small as that in a signal level transistor. This comparatively
larger base width has adverse effect on the current gain (β) of a Power transistor which
• Practical Power transistors have their emitters and bases interleaved as narrow fingers.
This is necessary to prevent “current crowding” and consequent “second break down”.
In addition multiple emitter structure also reduces parasitic ohmic resistance in the base
current path.
These constructional features of a Power BJT are shown schematically in Fig 3.3(a). Fig.3.3 (b)
shows the photograph of some community available Power transistors in different packages.
Emitter contact
Base
contact
n+ (emitter) n+ n+
p (Base)
n (Collector Drift)
n+ (Collector)
Exercise 3.4
Answer: (a) higher; (b) high reverse; (c) moderate; (d) low; (e) current crowding.
Exercise 3.5
What are the constructional features of a power transistor that affect the dc current gain?
iC
Hard Saturation
Quasi Saturation
iB10 Second break down limit
iB9
iB8
iB7 Active
iB6 Total Power dissipation limit
iB5
iB4
iB3
iB2 Increasing iB
Primary break down voltage
iB1
iB ≤ 0
ϑCE
Cut off
VSUS
VCE0 VCB0
(iB = 0) (iB < 0)
Fig. 3.4 Output ( ic – vCE ) characteristics of an n – p – n type Power Transistor
In the cut off region (iB ≤ 0) the collector current is almost zero. The maximum voltage between
B
collector and emitter under this condition is termed “Maximum forward blocking voltage with
base terminal open (iB = 0)” and is denoted by VCEO. For all practical purpose this is the
B
maximum voltage that can be applied in the forward direction (C positive with respect to E)
across a power transistor since a power transistor is expected to see any significant forward
voltage only with iB = 0. This blocking voltage can however be increased to a value VCBO by
B
keeping the emitter terminal open. In this case iB < o. Actually VCBO is the breakdown voltage of
the collector base junction. However, since the open base configuration is more common the
value of VCEO is used by the manufacturers as the maximum voltage rating of a power transistor.
Power transistors have poor reverse voltage withstanding capability due to low break down
voltage of the baseemitter junction. Therefore, reverse voltage (C negative with respect to E)
should not appear across a power transistor.
In the active region the ratio of collector current to base current (DC current Gain (β)) remains
fairly constant upto certain value of the collector current after which it falls off rapidly.
Manufacturers usually provide a graph showing the variation of β as a function of the collector
current for different junction temperatures and collector emitter voltages. This graph is useful for
designing the base drive of a Power transistor. Typically, the value of the dc current gain of a
Power transistor is much smaller compared to their signal level counterpart.
At still higher levels of collector currents the allowable active region is further restricted by a
potential failure mode called “the Second Break down”. It appears on the output characteristics
of the BJT as a precipitous drop in the collectoremitter voltage at large collector currents. The
collector voltage drop is often accompanied by significant rise in the collector current and a
substantial increase in the power dissipation. Most importantly this dissipation is not uniformly
spread over the entire volume of the device but is concentrated in highly localized regions. This
localized heating is a combined effect of the intrinsic non uniformity of the collector current
density distribution across the cross section of the device and the negative temperature
coefficient of resistively of minority carrier devices which leads to the formation of “current
filamements” (localized areas of very high current density) by a positive feedback mechanism.
Once current filaments are formed localized “thermal runaway” quickly takes the junction
temperature beyond the safe limit and the device is destroyed.
It is in the saturation region that the output characteristics of a Power transistor differs
significantly from its signal level counterpart. In fact the saturation region of a Power transistor
can be further subdivided into a quasi saturation region and a hard saturation region.
Appearance of the quasi saturation region in the output characteristics of a power transistor is a
direct consequence of introducing the drift region into the structure of a power transistor. In the
quasi saturation region the basecollector junction is forward biased but the lightly doped drift
region is not completely shorted out by excess minority carrier injection from the base. The
resistivity of this region depends to some extent on the base current. Therefore, in the quasi
saturation region, the base current still retains some control over the collector current although
the value of β decreases significantly. Also, since the resistivity of the drift region is still
significant the total voltage drop across the device in this mode of operation is higher for a given
collector current compared to what it will be in the hard saturation region.
In the hard saturation region base current looses control over the collector current which is
determined entirely by the collector load and the biasing voltage VCC. This behavior is similar to
what happens in a signal transistor except that the drift region of a power transistor continues to
offer a small resistance even when it is completely shorted out (by excess carrier injection from
the base). Therefore, for larger collector currents the collectoremitter voltage drop is almost
proportional to the collector current. Manufacturers usually provide the plots of the variation of
VCE (sat) vs. iC for different values of base current and junction temperature. Curves showing
the variation of VCE (sat) with iB for different values of iC and junction temperature are also
B
Applicable operating limits on a power transistors are compactly represented in two diagrams
called the Forward Bias Safe Operating Area (FBSOA) and the Reverse Bias Safe Operating
Area. (RBSOA) applicable to iB > 0 and iB ≤ 0 conditions respectively. Typical safe operating
B B
ICM
ICM
105sec
104sec
103sec
102sec
DC
Log ϑCE ϑCE
(a) VSUS (b) VCE0 VCB0
(VBE = 0) (VBE < 0)
Fig. 3.5: Safe operating areas of a Power Transistor.
(a) FBSOA; (b) RBSOA.
The horizontal upper limit of the FBSOA is determined by the maximum allowable collector
current (ICM) that should not be exceeded even as a pulse. Exceeding this current limit may cause
bonding wire or metallization of the wafer to vaporize or otherwise fail. Since a power transistor
does not have any appreciable reverse voltage blocking capacity they are usually not used in ac
circuits. However, if the collector current, for some reason is not dc or a pulse, the rms value of
the collector current waveform should not exceed this limit.
The next applicable limit in the FBSOA (green lines) corresponds to the restriction on the
maximum allowable power dissipation and maximum junction temperature. Since FBSOA is
shown on a loglog scale constant Power dissipation (Pd = VCE iC) limits appear as straight lines.
This limit is different for dc and pulsed operation due to the thermal time constant of the device.
The “DC” limit is applicable to the average power loss if the transistor remains continuously in
the conduction state (active, quasi saturation or saturation). On the other hand the pulsed power
dissipation limits are applicable to conduction duration up to the value marked on them (the
figures on the right of Fig 3.5 (a)). Pulsed power dissipation limits are specified for a low value
(1%2%) of duty cycle and are useful for shaping the switching trajectory of the transistor as will
be seen later.
The third limit of the FBSOA (red line) arises due to the “second break down” failure mode of
a Power transistor. It shows the limiting combinations of collector voltage and current so that
second break down does not occur. On the log –log scale of the FBSOA this limit also appears as
a straight limit. Like the maximum power dissipation limit, the second break down limit is also
different for “DC” and “Pulsed” operation of different pulse durations. The interpretation of the
pulse duration (marked on the right side of Fig 3.5 (a)) corresponding to a particular limit is also
same.
The final limit of the FBSOA corresponds to the forward biased avalanche break down voltage
(VSUS) of the transistor and appear as a vertical line in the FBSOA at VCE = VSuS
Version 2 EE IIT, Kharagpur 14
The FBSOA of a Power transistor is given at a specified case temperature. Both the maximum
power dissipation limit and the second break down limits are to be derated as per the derating
characteristics provided by the manufacturers when the case temperature exceeds the specified
value.
In contrast to the FBSOA, the RBSOA (Fig 3.5 (b)) is plotted on a linear scale and has a more
rectangular shape. RBSOA is a switching SOA since a transistor can not conduct current for any
appreciable duration under reverse biased condition. It essentially shows the limiting permissible
combinations of VCE & iC with base emitter junction reverse biased. The upper horizontal limit
corresponds to the maximum allowable collector current (ICM) and is same as that in the FBSOA.
The right hand side vertical limit corresponds the avalanche break down voltage of the transistor
with reverse bias. If the base terminal is open (i,e, iB = 0) then this voltage is VCEO. If a negative
B
voltage is applied across the BE junction the right hand side limit of the RBSOA increases
somewhat to the value VCBO at low value of the collector current.
In addition to the applicable limits on the output characteristics as represented in the FBSOA and
the RBSOA, limiting specification with respect to the base emitter junction is also provided by
the manufacturer. Typical specifications that are provided are
VEBO : This is maximum allowable reverse bias voltage across the BE junction
IBB : Maximum allowable average base current at a given case temperature.
IBM : Maximum allowable peak base current at a given case temperature and of
specified pulse duration.
The input characteristics (iB Vs VBE) at a given case temperature is also provided.
B
Exercise 3.6
Answer: (a) negligible; (b) active; (c) Quasi saturation, hard saturation; (d) Power
dissipation; (e) non uniformity.
• It can conduct only finite amount of current in one direction when “ON”
• It can block only a finite voltage in one direction.
• It has a voltage drop during “ON” condition
• It carries a small leakage current during OFF condition
• Switching operation is not instantaneous
• It requires non zero control power for switching
Of these the exact nature and implication of the first two has been discussed in some depth in the
previous section. The third and fourth non idealities give rise to power loss termed the
conduction power loss. In this section the nature and implications of the last two non idealities
will be discussed in detail.
Exercise 3.7
Answer: (a) two, one; (b) voltage drop, leakage current; (c) instantaneous.
iD
D IL
iC
+
RB iB
Q VCE
VBE

VBB
(a)
VBE
VBE sat
0 t
VBB  VBE(sat)
RB
iB
t
ic
id
IL IL
vCE
Pe VCC IL
vCE (sat) IL
(b)
Fig 3.6 Turn ON characteristics of a power transistor;
(a) Switching circuit, (b) Switching wave forms
The switching wave forms shown in Fig 3.6 (b) are the expanded and to some extent “idealized”
version of the actual waveforms that will be observed in a clamped inductive switching circuit as
shown in Fig.3.6 (a). Some simplifying assumptions have been made to draw these waveforms.
These are
Before t = 0, the transistor (Q) was in the “OFF” state. In order to utilize the increased break
down voltage (VCBO) the baseemitter junction of a Power Transistor is usually reverse biased
during OFF state. Under this condition only negligible leakage current flows through the
transistor. Power loss due to this leakage current is negligible compared to other components of
power loss in a transistor. Therefore, it is not shown in Fig 3.6 (b). The entire load current flows
through the diode and VCE is clamped to VCC (approximately).
To turn the transistor ON at t = 0, the base biasing voltage VBB changes to a suitable positive
value. This starts the process of charge redistribution at the baseemitter junction. The process is
akin to charging of a capacitor. Indeed, the reverse biased base emitter junction is often
represented by a voltage dependent capacitor, the value of which is given by the manufacturer as
a function of the baseemitter reverse bias voltage. The rising base current that flows during this
period can be thought of as this capacitor charging current. Finally at t = td the BE junction is
forward biased. The junction voltage and the base current settles down to their steady state
values. During this period, called the “Turn ON delay time” no appreciable collector current
flows. The values of iO and VCE remains essentially at their OFF state levels.
At the end of the delay time (td ON) the minority carrier density at the base region quickly
approaches its steady state distribution and the collector current starts rising while the diode
current (id) starts falling. At t = tdON + tri the collector current becomes equal to the load current
(and id becomes zero) IL. At this point D starts blocking reverse voltage and VCE becomes
unclamped. tri is called the current rise time of the transistor.
At the end of the current rise time the diode D regains reverse blocking capacity. The collector
voltage VCE which has so far been clamped to VCC because of the conducting diode “D” starts
falling towards its saturation voltage VCE (sat). The initial fall of VCE is rapid. During this period
the switching trajectory traverses through the active region of the output characteristics of the
transistor. At the end of this rapid fall (tfv1) the transistor enters “quasi saturation region”. The
fall of VCE in the quasi saturation region is considerably slower. At the end of this slow fall (tfv2)
the transistor enters “hard saturation” region and the collector voltage settles down to the
saturation voltage level VCE (sat) corresponding to the load current IL. Turn ON process ends
here. The total turn on time is thus, TSW (ON) = td (ON) + tri + tfv1 + tfv2.
Power loss occurs at all time during the operation of a power transistor. However, the collector
leakage current is usually negligibly small and power loss due it can be safely neglected in
comparison to the power loss during ON condition. Power loss occurs during Turning ON a
Power transistor due to simultaneous existence of nonzero VCE and ic during tri, tfv1, and tfv2. The
energy lost during these periods is called the Turn ON loss and given by the area under the Pl
curve in Fig 3.6 (b). The average Turn ON loss is obtained by dividing this area by (tri + tfv1 +
tfv2). For safe Turn ON this average power loss must be less than the limit set on the maximum
Turn ON time can be reduced by increasing the base current. However large base current
increases the quantity of excess carrier in the base and collector drift region which has to be
removed during Turn Off. As will be seen later this increases the Turn OFF time. The Turn ON
delay time can however be reduced by boosting the base current at the beginning of the Turn ON
process. This can be achieved by connecting a small capacitance across RB. This increases the
B
rate of rise of VBE & iB. Therefore, Turn ON delay time decreases. However, in steady state iB
B B
settle downs to a value determined by RB & VBB and no adverse effect on the Turn OFF time is
B
observed.
In figure 3.6 (b) the reverse recovery current of D has been neglected. If this current is not
negligible then for safe Turn ON operation the sum of the load current and the diode reverse
recovery current must be less than the ICM rating of the transistor. Thermal and second break
down limits must also be observed.
It should be noted that there is some power loss at the BE junction as well. This power loss
depends on the current gain of the transistor during hard saturation. Since current gain reduces
during saturation (typically between 5 to 10) this power loss may become significant.
Manufacturers usually provide the values of td (ON), tri, tfv as functions of ic for a given base
current and case temperature.
Exercise 3.8
a) For faster switching of a BJT _______________ carriers are to be swept quickly from the
________________ region.
b) The reverse biased base emitter junction can be represented as a ______________
dependent __________________.
c) In the quasi saturation region collectoremitter voltage falls at a ______________ rate.
d) Turn ON delay can be reduced by __________________ the rate of rise of the base
current.
Answer: (a) minority, base; (b) voltage, capacitor; (c) slow; (d) increasing.
VBB
iB
iC
id
IL IL
VCE
VCE(Sat)
VCC
Pe
t
ts trv1
trv2 tfi
(a)
ICM P’ FBSOA
P RBSOA
Forward recovery
Voltage of D
VCBO
log vCE
V(sus) VCEO
(b)
Fig. 3.7: Turn off, characteristics of a BJT.
(a) Switching wave forms
(b) Switching trajectory
The “Turn OFF” process starts with the base drive voltage going negative to a value VBB.
The baseemitter voltage however does not change from its forward bias value of VBE(sat)
immediately, due to the excess, minority carriers stored in the base region. A negative base
current starts removing this excess carrier at a rate determined by the negative base drive voltage
and the base drive resistance. After a time “ts” called the storage time of the transistor, the
remaining stored charge in the base becomes insufficient to support the transistor in the hard
saturation region. At this point the transistor enters quasi saturation region and the collector
voltage starts rising with a small slope. After a further time interval “trv1” the transistor completes
traversing through the quasi saturation region and enters the active region. The stored charge in
the base region at this point is insufficient to support the full negative base current. VBE starts
falling forward –VBB and the negative base current starts reducing. In the active region, VCE
increases rapidly towards VCC and at the end of the time interval “trv2” exceeds it to turn on D.
VCE remains clamped at VCC, thereafter by the conducting diode D. At the end of trv2 the stored
base charge can no longer support the full load current through the collector and the collector
current starts falling. At the end of the current fall time tfi the collector current becomes zero and
the load current freewheels through the diode D. Turn OFF process of the transistor ends at this
point. The total Turn OFF time is given by Ts (OFF) = ts + trv1 + trv2 + tfi
As in the case of “Turn ON” considerable power loss takes place during Turn OFF due to
simultaneous existence of ic and VCE in the intervals trv1, trv2 and tfi. The last trace of Fig 3.7 (a)
shows the instantaneous power loss profile during these intervals. The total energy last per turn
off operation is given by the area under this curve. For safe turn off the average power
dissipation during trv1 + trv2 + tfi should be less than the power dissipation limit set by the FBSOA
corresponding to a pulse width greater than trv1 + trv2 + tfi.
In this section and the precious one inductive load switching have been considered. However, if
the load is resistive. The freewheeling diode D will not be used. In that case the collector voltage
(VCE) and collector current (ic) will fall and rise respectively together during Turn ON and rise
and fall respectively together during Turn OFF. Other characteristics of the switching process
will remain same. The switching Power loss in this case will also be substantially lower.
Exercise 3.9
a) Turn OFF process in a BJT is associated with transition from the _______________
region to the ______________ region.
b) Negative _______________ current is required to remove excess charge carriers from the
______________ region of a BJT during Turn OFF process.
c) VCE increases rapidly in the ________________ region.
E ON =
1⎡
2 ⎣ ( )
VCC I L t ri + ( VCC + VCEf1 ) I L t fv1 + VCEf1 + VCE (sat ) I L t fv2 ⎤ ( 3.5 )
⎦
Where VCEf1 is the value of VCE at the end of the interval tfv1
Similarly
E OFF = 1 ⎡⎣( VCE ( sat ) + VCEr1 ) I L t rv1 + ( VCEr1 + VCC ) I L t rv2 + VCC I L t fi ⎤⎦ ( 3.6 )
2
If the switching frequency of the transistor is fSW, then the average switching power loss is given
by
For a given VCC and IL and base drive design, EON and EOFF are constant. Therefore, the
switching power loss is proportional to the switching frequency. Being a minority carrier device
a BJT has comparatively larger switching times (compared to some other devices broadly
categorized as transistors) and hence larger switching power loss for a given frequency. On the
other hand a BJT has the lowest ON state voltage drop VCE (sat) among all fully controlled
switches. Therefore, a BJT is suitable for switching large current at moderate (around a few
KHZ) switching frequency. At high frequency BJT based circuits tend to become inefficient due
to increased switching power loss.
Even without any restriction on the switching power loss the maximum switching frequency of a
BJT is limited by its Turn ON and Turn OFF times. The value of the maximum switching
frequency is given by
1
FSW ( Max ) = ( 3.10 )
TSW ( ON ) + TSW ( OFF )
For safe switching operation, however it is not sufficient to merely restrict the switching power
loss. It will be necessary to restrict the switching trajectory (an instantaneous plot of ic vs VCE
during switching with time as a parameter) within the FBSOA /RBSOA region corresponding to
a pulse width greater than TSW (ON) or TSW (OFF). Fig 3.7 (b) shows these switching trajectories
superimposed on the FBSOA /RBSOA. In this diagram the green line corresponds to the Turn
ON trajectory while the blue line corresponds to the Turn OFF trajectory. These trajectories are
rectangular in nature. Clearly full voltage (VCEO) or current rating (ICM) of the transistor can not
be utilized in such a trajectory. The situation becomes worse a when the reverse recovery current
and forward recovery voltage of D is considered. Switching aid circuits or “snubbers” (as they
are popularly known) are used to enhance the switching performance of a power transistor. They
serve two specific purpose.
• Shape the switching trajectory such that the voltage and current rating of a transistor can
be fully utilized.
IL
LS RS
iC
+ DS
Q VCE
RB iB CS

VBB +
(a)
logic
ICM
IL
RBSO
FBSO
A
Turn VCBO
on VCC
Turn off
log vCE
VCE(sus) VCEO
(b)
Fig. 3.8: Switching characteristics of a BJT with Snubber
(a) Clamped inductive switching circuit with snubber
(b) Switching trajectory.
Version 2 EE IIT, Kharagpur 25
Fig 3.8 (a) shows the same clamped inductive switching circuit of Fig 3.6 (a) but with the
snubber elements. The inductor LS connected between the load and the collector is the Turn ON
snubber. In decouples the collector from the supply voltage during Turn ON. Therefore, as the
junction VBE becomes forward biased VCE starts falling. At the same time ic also starts rising
towards IL. The resultant switching trajectory is shown by the solid green line in Fig 3.8 (b). This
should be compared with the unsnubbed Turn ON trajectory (broken green line). In the
unsnubbed case, the collector current rises to the maximum value before VCE starts falling from
VCC. VCC, therefore, must necessarily be smaller than VCE (SUS). In the snubber assisted
trajectory VCE falls substantially before ic rises to any appreciable value. Therefore, VCC can be
made larger than VCE(sat) and can be chosen closer to VCEO. Maximum collector current that can
be handled is also considerably higher (I L Max )
= ICM  Irr ( D ) . In the unsnubbed case
maximum IL is restricted essentially by the maximum power dissipation consideration and not by
ICM. LS also helps to reduce Irr (D) by restricting the rate of decrease of current through D. This
also helps to increase I L Max
RsCsDs constitute the Turn OFF snubber. This is popularly known as the “RCD snubber”.
During Turn OFF as the base drive of Q is removed ic starts falling and the remaining load
current is bypassed to Cs through Ds. Therefore, the collector voltage rises simultaneously giving
rise to the Turn OFF trajectory shown by the solid blue line in Fig 3.8 (b). At the end of the Turn
OFF process VCE shoots over VCC due to LsCs oscillation. However, by proper design VCE Max
can be restricted well below VCBO. Therefore, the turn OFF snubber circuit can effectively utilize
the enhanced voltage withstanding capability of a power transistor with base reverse biased.
Comparison of the switching trajectories with and with out snubber circuit makes it evident that
the snubber circuit can considerably enhance the voltage and current capacity utilization of a
Power transistor.
The area enclosed under the switching trajectories is a measure of the switching loss occurring in
the device at each switching. Therefore, it is evident from Fig 3.8 (b) that the snubber circuit
reduces the switching power loss inside the device considerably. However, it should be
emphasized that the total switching loss (device + snubber resistance) may not reduce. It is also
necessary to place the snubber components very close to the transistor since any stray inductance
in the Rs – Cs – Ds loop may give rise to an unacceptably large voltage spike across Q.
Components should also be chosen very carefully. Rs must be non inductive and the lead
inductances of Ds and Cs must be kept to a minimum Power loss in Rs can be considerably large
and its wattage should selected accordingly. To avoid excessive power loss in Rs, lossless
(regenerate) snubber circuits have been proposed.
Exercise 3.10
Exercise 3.11
What are the effects of introducing a drift region in the output iv characteristics of a power
transistor?
Answer: The drift region in a power transistor is introduced in order to block large forward
voltage. However, one effect of introducing the drift region is the appearance of a
“quasi saturation region” in the output iv characteristics of a power transistor. In the
quasi saturation state the drift region is not completely shorted out by “conductivity
modulation” by excess carriers from the base region. In offers a resistance which is a
function of the base current. Although the base current retain some control over
collector current in this state the value of dc current gain reduces substantially due to
increased effective base width.
Another effect of introducing the drift region is to make the VCE saturation voltage
depend linearly on the collector current in the hard saturation region due to the ohmic
resistance of the “conductivity modulated” drift region.
Exercise 3.12
Answer: (a) FBOSOA compactly represents the safe operating limits of a power transistor in
terms of maximum forward current, maximum forward voltage, maximum average &
instantaneous power dissipation and second break down limits. It is most useful in
designing the switching trajectory of a power transistor.
(b) This characteristics gives the amount of base current required so that the transistor
can operate in the saturation mode for a given collector current.
(c) After the base current is determined, this characteristics is used to design the base
drive circuit for a given base power source.
• The rate of rise of base current in the beginning of the turn on process determines the turn on
delay time.
• The magnitude of the base current during turn on decides the values of the voltage fall time,
current rise time and VCE (sat) for a given collector current.
Version 2 EE IIT, Kharagpur 27
• The negative base current during turn off determines the storage time, voltage rise time and
current fall time.
• A negative bias at the base also enhances the voltage withstanding capacity of a power
transistor.
From the discussion of the switching characteristics of a BJT it is evident that the base drive
voltage source should be bipolar and the base drive resistance should be different during turn
on and turn off. The following step by step procedure can be followed to arrive at the values.
• From the load current value (to be switched) and desired conduction power loss the desired
value of VCE (sat) is determined.
• Using the desired value of VCE (sat) for the given load current, the required value of forward
base current (iBP) and the corresponding VBE (sat) is obtained from the manufacturer’s data
sheet.
• The forward and reverse base drive voltages (VBB + & VBB ) are decided on the basis of the
availability of control power supply. These should be kept as low as possible in order to
reduce base drive power requirement.
• The forward base drive resistance RBP is given by
• Once iBP is known the turn on loss is fixed. The allowable turn off loss is determined by
subtracting the turn on loss for the desired total switching loss. The required current fall and
voltage rise times for the calculated turn off loss is determined for the given load current and
VCC.
• A suitable negative base current (iBN) to give the desired voltage rise time is determined from
the manufacturer’s data sheet.
• RBN is given
The resulting base drive circuit can be realized as shown in Fig 3.9
VBB +
RBP
R1
R3
From Q
Control
circuit Optocoupler
R2 RBN
Electrical
Isolation VBB 
Power transistors have low values of dc current gain (β) compared to their signal level
counterpart. Particularly, if a low value of VCE (sat) is desired at full load current, β can be as
low as 5. With such low gain large current switching becomes difficult since the base drive
circuit is required to handle about 20% of the full load current, Monolithic, Darlington connected
transistors can solve this problem. Fig 3.10 shows the circuit connection and the vertical cross
section of a Monolithic Darlington pair. The effective current gain of a Darlington pair is given
by
β = β Mβ D + β M + β D ( 3.13)
So that even when individual β’s are small effective β can still be quite large.
B IBD iCM
QD
iED
QM
iBM
D
E
(a)
B iED E
n+ n+
iBD iBM
p sio2 p’
n iCD n iCM
n+ n+
C
(b)
Fig 3.10: Monolithic Darlington connected power transistor.
(a) circuit diagram, (b) schematic cross section.
The major quantitative difference in the operating characteristics of a Power Darlington is due to
the fact that the main transistor can not go into hard saturation. The ON state voltage drop of the
drive transistor prevents forward biasing of the CB junction of the main transistor. Therefore,
the ON state power dissipation of the main transistor will be larger than that of an otherwise
comparable single BJT. The switching times will also be somewhat larger for the Darlington
transistor.
Exercise 3.13
A Power BJT is used to switch an inductive load carrying 20 A. The supply voltage is 200V,
switching frequency and duty cycle are 1 KHZ and 0.5 respectively. Switching times are as
follows. td = 1μs, tri = tfv1 = 8 μs, tfv2 = 0, ts = 12 μs, tfi = trv2 = 8 μs, trv1 = 0.
VCE sat = 1.0V at i c = 20 A
Calculate switching and conduction losses in the transistor.
Exercise 3.14
With reference to Fig. 3.9 determine the values of the base resistors RBP & RBN for the following
data
VBB+ = 10 volts, VBB = 10 V, IBP = 2.5 A, IBN = 1.5 A, VBE sat = 0.7 V , VCE sat (of
drive transistors) = 0.3 V
RL = 20Ω
RB
+
VBB = 12V
1. In the transistor switching circuit VBE sat = 0.75 V, VCE sat = 0.2 V 10 ≤ β ≤ 40 .
Find out the value of RB and Power requirement of the base source.
B
VCC = 200V
RL = 20Ω
D3
RB
+
D1 D2
VBB = 12V
50μs 50μs
∫∫ ∫∫ t
iC ∫∫
10 A
∫∫ ∫∫ t
td t ts tfi
ri
VCE ∫∫
200v 200v
∫∫ t
tfv trv
PSW (on) PSW (off)
Ploss
PCOND
4. Figure shows practical implementation of a power transistor base drive circuit. The
comparator has an output voltage swing of ± 12 V.
Also
For QP
VBE sat = 0.7V, VCE sat = 0.2V,
For QN
VBE sat =  0.7 V, VCE sat =  0.2 V,
For Q
VBE sat = 0.75 V. β Min = 10. Also it is desired that negative base current should be at least
equal to positive base current. β Min of QP & QN are same. Find the values of RBP, RBN and
R1
5. Explain why the dc current gain of a Power BJT is considerably lower compared to its Signal
level counterpart. What adverse effect does it have on the switching performance of a BJT?
Suggest one solution to this problem.
7. The pulsed FBSOA of a Power BJT is usually specified for a very low duty cycle. Then now
does it help to extend the usable voltage and current rating of a BJT?
ic
So required base current = = 1 amps
10
VBE sat = 0.75 volts ∴ R B = VBB  VBE sat = 11.25 Ω
Power drawn from base source is 12 × 1 = 12 watts.
2. In this case VCE = VBE sat + VD2 + VD1  VD3 = 1.45 volts . The transistor is not in saturation
since VCB is positive. So β = βmax = 40
200 1.45
IL = ic = = 9.93 Amps.
20
i
∴ i B = c = 0.25 Amps.
β
For maximum value of RB current through D3 will be zero
B
V V V V
So R B = BB D1 D2 BE sat = 39.4 Ω
iB
Power Drawn from base source is 12 × 0.25 = 3 watts.
Conduction power lass in 1st problem was 10 × 0.2 = 2 watts
Conduction power lass in this case is 9.93 × 1.45 = 14.4 watts
Note: This circuit is known as the antisaturation clamp or the “Baker’s clamp”.
RBP
IL = 50 A
iC1
iB1
QP
10 KΩ
Rl iE1
comp 0 A
B
QP
TTL iB
iE2
Pulse
E
QN
1.5v iB2
iC2
RBN
 12v
 15v
3. Figure shows switching waveforms of the transistor. Major difference with clamped inductive
switching waveform is that in this case rise and fall of ic & VCE are simultaneous. In the
interval t ri ( or t fv )
t
ic = 10 = 4×106 t
t ri
i c = 10 ⎛⎜1 t ⎞⎟ = 10 (1  4 × 105 t )
⎝ t fi ⎠
VCE = 200 t = 80 × 10 6 t
t rv
= 0.83 mJ
t fi 2.5×106
8×108 t (1 4×105 t ) dt
E SW ( OFF ) =
∫ o
VCE i c dt =
∫o
= 0.83 mJ
∴ E SW = E SW ( ON ) + E SW ( OFF ) = 1.66 mJ
∴ PSW = E SW × f SW = 1.66×103 × 10 × 103 = 16.6 watts.
Conduction loss occurs in the interval from the end of tri to the beginning of tfi
i BN = i E2 = i B2 + i C2
VBE  VBA + 12 12.05
i B2 = =
R1 R1
VBE  VEC2 + 15 15.55
i C2 = =
R BN R BN
12.05 15.55
So + ≥ 5
R1 R BN
5. The main reason for comparatively lower dc current gain in a power transistor is a relatively
thicker base region (a few tens of μm compared to a fraction of a μm incase of a signal
transistor). The thicker base region is required to withstand the large blocking voltage.
Unlike a power diode the doping density of the base region cannot be made very much large
compared to the lightly doped collector drift region since it will reduce “β” by increasing
minority carrier injection into the emitter. As a result the depletion layer at the CB junction
penetrates considerably in to the base region. The base width has to be larger than this
penetration depth. A thicker base leads to larger rate of recombination of minority carriers
injected by the emitter. Therefore, for a given collector current the required base current is
relatively high and the dc current gain is low.
A second reason for lowering of β arises from the “emitter crowding” effect where by the
collector current tends to “crowd” near specific regions of the emitter. In these localized high
current density regions β tends to fall off very sharply reducing the effective dc current gain.
Due to lower dc current gain the base current requirement of a power transistor switching
circuit increases. This requires a large base drive power supply and increased base drive
power loss.
This problem can be solved to some extent by using two power transistors connected in the
“Darlington configuration” as shown.
iBD
QD
βD iCM
βM QM
iED
i L = i CD + i CM
But i CD = β D i BD
i CM = β M i ED = β M ( i BD + i CD )
∴ i L = β Di BD + β Mi BD + β Mβ Di BD
= (β M + β D + β Mβ D ) i BD = β eqv i BD
Power Darlington has one problem, however. The main transistor (QM) does not go into hard
saturation due to VCE drop of QD. Therefore, the conduction loss is higher.
6. The voltage rating VSUS is the maximum allowable voltage across C & E when the transistor
is in active region with iB > 0 and collector current above a minimum value.
B
With both iB and iC greater than zero, there is considerable supply of minority carriers which
B
are accelerated by the large CB junction electric field to start avalanche breakdown at a
relatively lower voltage. Therefore, the voltage rating VSUS is the lowest of the three.
The rating VCEO is the maximum allowable voltage between C & E terminals when the
transistor is in cut off region with iB = 0 or iC is less than a specified value. Under this
B
condition the supply of minority carriers at the CB junction is much less compared to the
previous case. Therefore, avalanche breakdown of the CB junction occurs at a higher voltage.
Thus VCEO > VSUS.
The rating VCBO is the maximum allowable voltage between C & E terminals when the
transistor is in cut off with iB < 0 and iC less than a specified value. With iB = 0 the EB
B B
junction is still forward biased and there is small injection of minority carriers from the
emitter to the CB junction. However, with iB < 0 base emitter junction is reverse biased and
B
there is no supply of minority carriers to the CB junction from the emitter. Thus avalanche
In an inductive switching circuit using snubber the collector voltage falls considerably before
iC builds up to any significant level. This can be utilized to increase the usable steady state
blocking voltage of the transistor up to VCEO. Since VCE will go below VSUS before iC can
build up to the level where the rating VSUS becomes applicable.
Similarly during turn off, the overshoot in the VCE voltage can be accommodated in the
difference between VCBO and VCEO. Since during turn off iB < 0 and the voltage. overshoot
B
occurs with iC = 0 the applicable voltage limit will be VCBO and not VCEO. However,
precaution must be taken such that the voltage over shoot decays before iB becomes equal to
B
zero.
However, if a snubber circuit is not used the applicable voltage limit will always be VSUS
since in this case VCE does not fall till iC rises to its full value during turn ON. Similarly
during turn off iC does not fall till VCE rises to steady state blocking voltage level.
log iC
ICM
BP Pulsed
CP
CD DC BD
O
AD AP log vCE
7. The main difference between the DC and pulsed FBOSA is in the boundary corresponding to
maximum power dissipation and second break down. With only DC FBSOA the switching
trajectory has to be restricted to something similar to AD BD CD. However, with pulsed
FBSOA applicable limits of power dissipation and second break down increases
considerably. Both these limits require simultaneous existence of nonzero VCE & iC which for
a power transistor occurs only during switching. Therefore, the increases FBSOA can be
utilized and the switching trajectory improved to AP BP CP provided total switching time is
less than the pulse period for which the increased FBSOA is applicable.
• Explain the operating principle of a thyristor in terms of the “two transistor analogy”.
• Draw and explain the iv characteristics of a thyristor.
• Draw and explain the gate characteristics of a thyristor.
• Interpret data sheet rating of a thyristor.
• Draw and explain the switching characteristics of a thyristor.
• Explain the operating principle of a Triac.
From the construction and operational point of view a thyristor is a four layer, three terminal,
minority carrier semicontrolled device. It can be turned on by a current signal but can not be
turned off without interrupting the main current. It can block voltage in both directions but can
conduct current only in one direction. During conduction it offers very low forward voltage drop
due to an internal latchup mechanism. Thyristors have longer switching times (measured in tens
of μs) compared to a BJT. This, coupled with the fact that a thyristor can not be turned off using
a control input, have all but eliminated thyristors in high frequency switching applications
involving a DC input (i.e, choppers, inverters). However in power frequency ac applications
where the current naturally goes through zero, thyristor remain popular due to its low conduction
loss its reverse voltage blocking capability and very low control power requirement. In fact, in
very high power (in excess of 50 MW) AC – DC (phase controlled converters) or AC – AC
(cycloconverters) converters, thyristors still remain the device of choice.
A
p
n
G p
K n+ n+
(a) G
(c)
K
(b)
As shown in Fig 4.1 (b) the primary crystal is of lightly doped n type on either side of
which two p type layers with doping levels higher by two orders of magnitude are grown. As in
the case of power diodes and transistors depletion layer spreads mainly into the lightly doped n
region. The thickness of this layer is therefore determined by the required blocking voltage of the
device. However, due to conductivity modulation by carriers from the heavily doped p regions
on both side during ON condition the “ON state” voltage drop is less. The outer n+ layers are
formed with doping levels higher then both the p type layers. The top p layer acls as the “Anode”
terminal while the bottom n+ layers acts as the “Cathode”. The “Gate” terminal connections are
made to the bottom p layer.
As it will be shown later, that for better switching performance it is required to maximize
the peripheral contact area of the gate and the cathode regions. Therefore, the cathode regions are
finely distributed between gate contacts of the p type layer. An “Involute” structure for both the
gate and the cathode regions is a preferred design structure.
p p Q1 (α1)
J1
iC2 iC1
 
n n
IG
J2 (α2) Q2 G
p p n
G J2
n+ n+ J3 p
J3 IK
n+
K
G
K
K
(a) (b) (c)
a) Schematic construction,
b) Schematic division in component transistor
c) Equivalent circuit in terms of two transistors.
Let us consider the behavior of this p n p n device with forward voltage applied, i.e anode
positive with respect to the cathode and the gate terminal open. With this voltage polarity J1
& J3 are forward biased while J2 reverse biased.
Where ∝1 & ∝2 are current gains of Q1 & Q2 respectively while Ico1 & Ico2 are reverse
saturation currents of the CB junctions of Q1 & Q2 respectively.
I co1 + I co2 I co
IA = =
1 ( ∝1 + ∝ 2 ) 1 ( ∝1 + ∝ 2 )
( 4.5 )
Now as long as VAK is small Ico is very low and both ∝1 & ∝2 are much lower than unity.
Therefore, total anode current IA is only slightly greater than Ico. However, as VAK is increased
up to the avalanche break down voltage of J2, Ico starts increasing rapidly due to avalanche
multiplication process. As Ico increases both ∝1 & ∝2 increase and ∝1 + ∝2 approaches unity.
Under this condition large anode current starts flowing, restricted only by the external load
resistance. However, voltage drop in the external resistance causes a collapse of voltage across
the thyristor. The CB junctions of both Q1 & Q2 become forward biased and the total voltage
drop across the device settles down to approximately equivalent to a diode drop. The thyristor is
said to be in “ON” state.
Just after turn ON if Ia is larger than a specified current called the Latching Current IL, ∝1 and
∝2 remain high enough to keep the thyristor in ON state. The only way the thyristor can be
turned OFF is by bringing IA below a specified current called the holding current (IH) where
upon ∝1 & ∝2 starts reducing. The thyristor can regain forward blocking capacity once excess
stored charge at J2 is removed by application of a reverse voltage across A & K (ie, K positive
with respect A).
It is possible to turn ON a thyristor by application of a positive gate current (flowing from gate to
cathode) without increasing the forward voltage across the device up to the forward breakover
level. With a positive gate current equation 4.4 can be written as
IK = IA + IG ( 4.6 )
∝ 2 I G + I co
Combining with Eqns. 4.1 to 4.3 I A =
1 ( ∝1 + ∝ 2 )
( 4.7 )
Obviously with sufficiently large IG the thyristor can be turned on for any value of Ico (and hence
VAK). This is called gate assisted turn on of a Thyristor. This is the usual method by which a
thyristor is turned ON.
When a reverse voltage is applied across a thyristor (i.e, cathode positive with respect to anose.)
junctions J1 and J3 are reverse biased while J2 is forward biased. Of these, the junction J3 has a
very low reverse break down voltage since both the n+ and p regions on either side of this
junction are heavily doped. Therefore, the applied reverse voltage is almost entirely supported by
junction J1. The maximum value of the reverse voltage is restricted by
Since the p layers on either side of the n region have almost equal doping levels the avalanche
break down voltage of J1 & J2 are almost same. Therefore, the forward and the reverse break
down voltage of a thyristor are almost equal.Up to the break down voltage of J1 the reverse
current of the thyristor remains practically constant and increases sharply after this voltage.
Thus, the reverse characteristics of a thyristor is similar to that of a single diode.
If a forward voltage is suddenly applied across a reverse biased thyristor, there will be
considerable redistribution of charges across all three junctions. The resulting current can
become large enough to satisfy the condition ∝1 + ∝2 = 1 and consequently turn on the thyristor.
This is called dv turn on of a thyristor and should be avoided.
dt
Exercise 4.1
1) Fill in the blank(s) with the appropriate word(s)
Answers: (i) minority; (ii) one, both; (iii) break over, gate; (iv) holding, turn off;
(v) dv
dt
2. Do you expect a thyristor to turn ON if a positive gate pulse is applied under reverse bias
condition (i. e cathode positive with respect to anode)?
Answer: The two transistor analogy of thyristor shown in Fig 4.2 (c) indicates that when a
reverse voltage is applied across the device the roles of the emitters and collectors of the
constituent transistors will reverse. With a positive gate pulse applied it may appear that the
device should turn ON as in the forward direction. However, the constituent transistors have very
low current gain in the reverse direction. Therefore no reasonable value of the gate current will
satisfy the turn ON condition (i.e.∝1 + ∝2 = 1). Hence the device will not turn ON.
+ VAK 
A IA K
ig Ig
ig1 ig2 ig3 ig4
VBRR VBRF
IL
Is IH
VAK
ig4 > ig3 > ig2 > ig1 > ig = 0
VH
ig4 > ig3 > ig2 > ig1 > ig = 0
The circuit symbol in the left hand side inset defines the polarity conventions of the variables
used in this figure.
With ig = 0, VAK has to increase up to forward break over voltage VBRF before significant anode
current starts flowing. However, at VBRF forward break over takes place and the voltage across
the thyristor drops to VH (holding voltage). Beyond this point voltage across the thyristor (VAK)
remains almost constant at VH (11.5v) while the anode current is determined by the external
load.
The magnitude of gate current has a very strong effect on the value of the break over voltage as
shown in the figure. The right hand side figure in the inset shows a typical plot of the forward
break over voltage (VBRF) as a function of the gate current (Ig)
After “Turn ON” the thyristor is no more affected by the gate current. Hence, any current pulse
(of required magnitude) which is longer than the minimum needed for “Turn ON” is sufficient to
effect control. The minimum gate pulse width is decided by the external circuit and should be
long enough to allow the anode current to rise above the latching current (IL) level.
During reverse blocking if ig = 0 then only reverse saturation current (Is) flows until the reverse
voltage reaches reverse break down voltage (VBRR). At this point current starts rising sharply.
Large reverse voltage and current generates excessive heat and destroys the device. If ig > 0
during reverse bias condition the reverse saturation current rises as explained in the previous
section. This can be avoided by removing the gate current while the thyristor is reverse biased.
The static output iv characteristics of a thyristor depends strongly on the junction temperature as
shown in Fig 4.4.
VBRF IA
Tj =
150° 135° 25° 75° 125°
25° 75° 125° 150° Tj
VAK
E c d
Rg
ig
• S2 E Vg
Pgav ⎜Max
Load line
Pgm K
Vg min b e
h
S1
Vng •
f
g Ig max
Ig min Ig
Each thyristor has maximum gate voltage limit (Vgmax), gate current limit (Igmax) and maximum
average gate power dissipation limit ( Pgav Max ) . These limits should not be exceeded in order to
avoid permanent damage to the gate cathode junction. There are also minimum limits of Vg
(Vgmin) and Ig (Igmin) for reliable turn on of the thyristor. A gate non triggering voltage (Vng) is
also specified by the manufacturers of thyristors. All spurious noise signals should be less than
this voltage Vng in order to prevent unwanted turn on of the thyristor. The useful gate drive area
of a thyristor is then b c d e f g h.
Referring to the gate drive circuit in the inset the equation of the load line is given by
Vg = E  Rgig
The actual operating point will be some where between S1 & S2 depending on the particular
device.
For optimum utilization of the gate ratings the load line should be shifted forwards the Pgav Max
curve without violating Vg Max or IgMax ratings. Therefore, for a dc source E c f represents the
optimum load line from which optimum values of E & Rg can be determined.
It is however customary to trigger a thyristor using pulsed voltage & current. Maximum power
dissipation curves for pulsed operation (Pgm) allows higher gate current to flow which in turn
reduces the turn on time of the thyristor. The value of Pgm depends on the pulse width (TON) of
the gate current pulse. TON should be larger than the turn on time of the thyristor. For TON larger
The magnitude of the gate voltage and current required for triggering a thyristor is inversely
proportional to the junction temperature.
The gate cathode junction also has a maximum reverse (i.e, gate negative with respect to the
cathode) voltage specification. If there is a possibility of the reverse gate cathode voltage
exceeding this limit a reverse voltage protection using diode as shown in Fig 4.6 should be used.
A A
Rg
G
E E
K K
(a) (b)
Fig. 4.6: Gate Cathode reverse voltage protection circuit.
Exercise 4.2
1) Fill in the blank(s) with the appropriate word(s)
2) A thyristor has a maximum average gate power dissipation limit of 0.2 watts. It is triggered
with pulsed gate current at a pulse frequency of 10 KHZ and duly ratio of 0.4. Assuming the gate
cathode voltage drop to be 1 volt. Find out the allowable peak gate current magnitude.
0.4
TON = δ TS = δ = sec = 40 μs < 100 μs.
fs 10 4
Therefore, pulsed gate power dissipation limit Pgm can be used. From Equation 4.9
Peak repetitive off state forward voltage (VDRM): It refers to the peak forward transient
voltage that a thyristor can block repeatedly in the OFF state. This rating is specified at a
maximum allowable junction temperature with gate circuit open or with a specified biasing
resistance between gate and cathode. This type of repetitive transient voltage may appear across
a thyristor due to “commutation” of other thyristors or diodes in a converter circuit.
Peak nonrepetitive off state forward voltage (VDSM): It refers to the allowable peak value of
the forward transient voltage that does not repeat. This type of over voltage may be caused due to
switching operation (i.e, circuit breaker opening or closing or lightning surge) in a supply
network. Its value is about 130% of VDRM. However, VDSM is less than the forward break over
voltage VBRF.
Peak repetitive reverse voltage (VRRM): It specifies the peak reverse transient voltage that may
occur repeatedly during reverse bias condition of the thyristor at the maximum junction
temperature.
Peak nonrepetitive reverse voltage (VRSM): It represents the peak value of the reverse
transient voltage that does not repeat. Its value is about 130% of VRRM. However, VRSM is less
than reverse break down voltage VBRR.
VAK
VDWM VDRM VDSM VBRF
Maximum average current (Iav): It is the maximum allowable average value of the forward
current such that
Manufacturers usually provide the “forward average current derating characteristics” which
shows Iav as a function of the case temperature (Tc ) with the current conduction angle φ as a
parameter. The current wave form is assumed to be formed from a half cycle sine wave of power
frequency as shown in Fig 4.8.
80 φ = 60° φ
60 φ = 30°
40
20
0 ∫∫
60° 80° 100° 120° 140°
TC (°C)
Fig. 4.8: Average forward current derating characteristics
Maximum Surge current (ISM): It specifies the maximum allowable non repetitive current the
device can withstand. The device is assumed to be operating under rated blocking voltage,
forward current and junction temperation before the surge current occurs. Following the surge
the device should be disconnected from the circuit and allowed to cool down. Surge currents are
assumed to be sine waves of power frequency with a minimum duration of ½ cycles.
Manufacturers provide at least three different surge current ratings for different durations.
For example
I sM = 3000 A for 1 cycle
2
I sM = 2100 A for 3 cycles
I sM = 1800 A for 5 cycles
Alternatively a plot of IsM vs. applicable cycle numbers may also be provided.
Maximum Squared Current integral (∫i2dt): This rating in terms of A2S is a measure of the
energy the device can absorb for a short time (less than one half cycle of power frequency). This
rating is used in the choice of the protective fuse connected in series with the device.
Latching Current (IL): After Turn ON the gate pulse must be maintained until the anode
current reaches this level. Otherwise, upon removal of gate pulse, the device will turn off.
Holding Current (IH): The anode current must be reduced below this value to turn off the
thyristor.
Maximum Forward voltage drop (VF): Usually specified as a function of the instantaneous
forward current at a given junction temperature.
Version 2 EE IIT, Kharagpur 15
Average power dissipation Pav): Specified as a function of the average forward current (Iav) for
different conduction angles as shown in the figure 4.9. The current wave form is assumed to be
half cycle sine wave (or square wave) for power frequency.
Pav
φ = 180°
90°
60°
30°
iF
ωt
Iav
Fig. 4.9: Average power dissipation vs average forward current in a thyristor.
1 φ
I av =
2π ∫o F
i dθ ( 4.10 )
1 φ
Pav =
2π ∫o F F
v i dθ ( 4.11)
Gate voltage to trigger (VGT): Minimum value of the gate cathode forward voltage below
which reliable turn on of the thyristor can not be guaranteed. It is specified at the same break
over voltage as IGT.
Non triggering gate voltage (VGNT): Maximum value of the gatecathode voltage below which
the thyristor can be guaranteed to remain OFF. All spurious noise voltage in the gate drive circuit
must be below this level.
Peak reverse gate voltage (VGRM): Maximum reverse voltage that can appear between the gate
and the cathode terminals without damaging the junction.
Peak forward gate current (IGRM): The forward gate current should not exceed this limit even
on instantaneous basis.
Exercise 4.3
1) Fill in the blank(s) with the appropriate word(s)
i. Peak nonrepetitive over voltage may appear across a thyristor due to ________________
or ________________ surges in a supply network.
ii. VRSM rating of a thyristor is greater than the ________________ rating but less than the
________________ rating.
iii. Maximum average current a thristor can carry depends on the ________________ of the
thyristor and the ________________ of the current wave form.
iv. The ISM rating of a thyristor applies to current waveforms of duration ________________
than half cycle of the power frequency where as the ∫i2dt rating applies to current durations
________________ than half cycle of the power frequency.
v. The gate nontrigger voltage specification of a thyristor is useful for avoiding unwanted
turn on of the thyristor due to ________________ voltage signals at the gate.
Answer: (i) switching, lightning; (ii) VRRM, VBRR; (iii) case temperature, conduction
angle; (iv) greater, less; (v) noise
2. A thyristor has a maximum average current rating 1200 Amps for a conduction angle of 180°.
Find the corresponding rating for Φ = 60°. Assume the current waveforms to be half cycle sine
wave.
Answer: The form factor of half cycle sine waves for a conduction angle φ is given by
I
F.F = RMS =
1
2π
φ
∫ Sin θ dθ
o
2
=
(
π φ  1 Sin 2φ
2 )
Iav 1 φ 1 Cos φ
2π ∫ Sinθ dθ
o
iA
ig
t
Vi R
iA 0.9 ION
ION
0.1 ION Firing angle
t α Vi
vAK vAK iA
0.9 VON
VON
0.1 VON Expanded scale
t
tON
td tr tp
Fig. 4.10: Turn on characteristics of a thyristor.
Fig 4.10 shows the waveforms of the gate current (ig), anode current (iA) and anode cathode
voltage (VAK) in an expanded time scale during Turn on. The reference circuit and the associated
waveforms are shown in the inset. The total switching period being much smaller compared to
the cycle time, iA and VAK before and after switching will appear flat.
As shown in Fig 4.10 there is a transition time “tON” from forward off state to forward on state.
This transition time is called the thyristor turn of time and can be divided into three separate
intervals namely, (i) delay time (td) (ii) rise time (tr) and (iii) spread time (tp). These times are
shown in Fig 4.10 for a resistive load.
Rise time (tr): For a resistive load, “rise time” is the time taken by the anode current to rise from
10% of its final value to 90% of its final value. At the same time the voltage VAK falls from 90%
of its initial value to 10% of its initial value. However, current rise and voltage fall
characteristics are strongly influenced by the type of the load. For inductive load the voltage falls
faster than the current. While for a capacitive load VAK falls rapidly in the beginning. However,
as the current increases, rate of change of anode voltage substantially decreases.
If the anode current rises too fast it tends to remain confined in a small area. This can give rise to
local “hot spots” and damage the device. Therefore, it is necessary to limit the rate of rise of the
⎛ di ⎞
ON state current ⎜ A ⎟ by using an inductor in series with the device. Usual values of maximum
⎝ dt ⎠
allowable di A is in the range of 20200 A/μs.
dt
Spread time (tp): It is the time taken by the anode current to rise from 90% of its final value to
100%. During this time conduction spreads over the entire cross section of the cathode of the
thyristor. The spreading interval depends on the area of the cathode and on the gate structure of
the thyristor.
vAK vi
iA
t
t
vi
Expanded
Vrr scale
trr tgr
tq
The anode current becomes zero at time t1 and starts growing in the negative direction with the
same di A till time t2. This negative current removes excess carriers from junctions J1 & J3. At
dt
time t2 excess carriers densities at these junctions are not sufficient to maintain the reverse
current and the anode current starts decreasing. The value of the anode current at time t2 is called
the reverse recovery current (Irr). The reverse anode current reduces to the level of reverse
saturation current by t3. Total charge removed from the junctions between t1 & t3 is called the
reverse recovery charge (Qrr). Fast decaying reverse current during the interval t2 t3 coupled with
the di limiting inductor may cause a large reverse voltage spike (Vrr) to appear across the
dt
device. This voltage must be limited below the VRRM rating of the device. Up to time t2 the
voltage across the device (VAK) does not change substantially from its on state value. However,
after the reverse recovery time, the thyristor regains reverse blocking capacity and VAK starts
following supply voltage vi. At the end of the reverse recovery period (trr) trapped charges still
exist at the junction J2 which prevents the device from blocking forward voltage just after trr.
These trapped charges are removed only by the process of recombination. The time taken for this
recombination process to complete (between t3 & t4) is called the gate recovery time (tgr). The
time interval tq = trr + tgr is called “device turn off time” of the thyristor.
No forward voltage should appear across the device before the time tq to avoid its inadvertent
turn on. A circuit designer must provide a time interval tc (tc > tq) during which a reverse voltage
is applied across the device. tc is called the “circuit turn off time”.
As in the case of a diode the relative magnitudes of the time intervals t1 t2 and t2 t3 depends on
the construction of the thyristor. In normal recovery “converter grade” thyristor they are almost
equal for a specified forward current and reverse recovery current. However, in a fast recovery
“inverter grade” thyristor the interval t2 t3 is negligible compared to the interval t1 t2. This helps
reduce the total turn off time tq of the thyristor (and hence allow them to operate at higher
switching frequency). However, large voltage spike due to this “snappy recovery” will appear
across the device after the device turns off. Typical turn off times of converter and inverter
grade thyristors are in the range of 50100 μs and 550 μs respectively.
As has been mentioned in the introduction thyristor is the device of choice at the very highest
power levels. At these power levels (several hundreds of megawatts) reliability of the thyristor
power converter is of prime importance. Therefore, suitable protection arrangement must be
made against possible overvoltage, overcurrent and unintended turn on for each thyristor. At the
highest power level (HVDC transmission system) thyristor converters operate from network
voltage levels in excess of several hundreds of kilo volts and conduct several tens of kilo amps
of current. They usually employ a large number of thyristors connected in series parallel
combination. For maximum utilization of the device capacity it is important that each device in
this series parallel combination share the blocking voltage and on state current equally. Special
equalizing circuits are used for this purpose.
Exercise 4.4
1) Fill in the blank(s) with the appropriate word(s)
2. With reference to Fig 4.10 find expressions for (i) turn on power loss and (ii) conduction
power loss of the thyristor as a function of the firing angle ∝. Neglect turn on delay time and
spread time and assume linear variation of voltage and current during turn on period. Also
assume constant on state voltage VH across the thyristor.
Answer: (i) For a firing angle ∝ the forward bias voltage across the thyristor just before turn on
is
VON = 2Vi Sin ∝ ; Vi = RMS value of supply voltage.
Current after the thyristor turns on for a resistive load is
VON Vi
I ON = = 2 Sin ∝
R R
Neglecting delay and spread time and assuming linear variation of voltage and current during
turn on
2 Vi Sin ∝ t
ia =
R t ON
∴ Total switching energy loss
t ON 2Vi 2 t ON
⎛1  t ⎞ t
E ON = ∫ v ak i a dt =Sin 2 ∝ ∫ ⎜ dt
o R o ⎝ t ON ⎟⎠ t ON
2Vi 2 t ⎛ 2⎞ Vi 2
= Sin 2 ∝ ON ⎜1  ⎟ = Sin 2 ∝ t ON
R 2 ⎝ 3⎠ 3R
EON occurs once every cycle. If the supply frequency is f then average turn on power loss is
given by.
Vi 2
PON = E ON f = Sin 2 ∝ t ON f
3R
(ii) If the firing angle is ∝ the thyristor conducts for π∝ angle. Instantaneous current through the
device during this period is
2 Vi Sin ωt
ia = R ∝ <ωt≤ π
R
Where tON & VH have been neglected for simplicity.
2 Vi VH
∴ Average conduction power loss = PC = E cf =
2πR
(1 + Cos ∝ )
Fuse
i1
Vi
if
220 V
50 HZ
3. In the ideal single phase fully controlled converter T1 & T2 are fired at a firing angle ∝ after
the positive going zero crossing of Vi while T3 & T4 are fired ∝ angle after the negative going
zero crossing of Vi, If all thyristors have a turn off time of 100 μs, find out maximum allowable
value of ∝.
Answer: As T1 & T2 are fired at an angle ∝ after positive going zero crossing of Vi, T3 & T4 are
subjected to a negative voltage of –Vi. Since this voltage remain negative for a duration (π∝)
angle (after which –Vi becomes positive) for safe commutation
( π  Max) ≥ ωt off ∴ ∝ Max = 178.2 .
0
MT1
N2
MT2 N2
P2 G
P2
N3
N3 P2 N1
G P1
N1
MT1
N4 P1
(a)
(b)
MT2
Fig. 4.12: Circuit symbol and schematic construction of a Triac
(a) Circuit symbol (b) Schematic construction.
Since a Triac is a bidirectional device and can have its terminals at various combinations of
positive and negative voltages, there are four possible electrode potential combinations as given
below
The triggering sensitivity is highest with the combinations 1 and 3 and are generally used.
However, for bidirectional control and uniforms gate trigger mode sometimes trigger modes 2
and 3 are used. Trigger mode 4 is usually averded. Fig 4.13 (a) and (b) explain the conduction
mechanism of a triac in trigger modes 1 & 3 respectively.
IG N2 N3 IG
P2 P2
N1
N1
P1
P1 N4
MT2 MT2
(+) ()
(a) (b)
Fig. 4.13: Conduction mechanism of a triac in trigger modes 1
and 3
(a) Mode – 1 , (b) Mode – 3 .
In trigger mode1 the gate current flows mainly through the P2 N2 junction like an ordinary
thyristor. When the gate current has injected sufficient charge into P2 layer the triac starts
conducting through the P1 N1 P2 N2 layers like an ordinary thyristor.
In the trigger mode3 the gate current Ig forward biases the P2 P3 junction and a large number of
electrons are introduced in the P2 region by N3. Finally the structure P2 N1 P1 N4 turns on
completely.
VBO V
Ig = 0
Ig3 < Ig2 < Ig1
From a functional point of view a triac is similar to two thyristors connected in anti parallel.
Therefore, it is expected that the VI characteristics of Triac in the 1st and 3rd quadrant of the VI
plane will be similar to the forward characteristics of a thyristors. As shown in Fig. 4.14, with no
signal to the gate the triac will block both half cycle of the applied ac voltage provided its peak
value is lower than the break over voltage (VBO) of the device. However, the turning on of the
triac can be controlled by applying the gate trigger pulse at the desired instance. Mode1
triggering is used in the first quadrant where as Mode3 triggering is used in the third quadrant.
As such, most of the thyristor characteristics apply to the triac (ie, latching and holding current).
However, in a triac the two conducting paths (from MT1 to MT2 or from MT1 to MT1) interact
with each other in the structure of the triac. Therefore, the voltage, current and frequency ratings
of triacs are considerably lower than thyristors. At present triacs with voltage and current ratings
of 1200V and 300A (rms) are available. Triacs also have a larger on state voltage drop compared
to a thyristor. Manufacturers usually specify characteristics curves relating rms device current
and maximum allowable case temperature as shown in Fig 4.15. Curves relating the device
dissipation and RMS on state current are also provided for different conduction angles.
150
100
(RMS)
0 °C
20° 40° 60° 80° 100° 120°
Maximum allowable case temperature (TC)
Fig. 4.15: RMS ON state current Vs maximum case temperature.
The triac should be triggered carefully to ensure safe operation. For phase control application,
the triac is switched on and off in synchronism with the mains supply so that only a part of each
half cycle is applied across the load. To ensure ‘clean turn ON’ the trigger signal must rise
rapidly to provide the necessary charge. A rise time of about 1 μs will be desirable. Such a triac
gate triggering circuit using a “diac” and an RC timing network is shown in Fig 4.16.
R1
R
D1
R2
V1
C1 C
In this circuit as Vi increases voltage across C1 increases due to current flowing through load, R1,
R2 and C1. The voltage drop across diac D1 increases until it reaches its break over point. As D1
conducts a large current pulse is injected into the gate of the triac. By varying R2 the firing can
be controlled from zero to virtually 100%.
Exercise 4.5
1) Fill in the blank(s) with the appropriate word(s)
Answer: (i) bidirectional; (ii) anti parallel; (iii) positive, negative; (iv) first, third; (v) first,
positive, third, negative (vi) lower, interaction; (vii) RC shubbers; (viii) rise time,
small.
Th
15 V R
• •
N1 N2
iB
2. The thyristor Th is triggered using the pulse transformer shown in figure. The pulse
transformer operates at 10 KHZ with a duty cycle of 40%. The thyristor has maximum
average gate power dissipation limit of 0.5 watts and a maximum allow able gate voltage
limit of 10 volts. Assuming ideal pulse transformer, find out the turns ratio N1/N2 and the
value of R.
Fuse
i1
Vi
if
220 V
50 HZ
3. A thyristor full bridge converter is used to drive a dc motor as shown in the figure. The
thyristors are fired at a firing angle ∝ = 0° when motor runs at rated speed. The motor has
on armature resistance of 0.2 Ω and negligible armature inductance. Find out the peak
surge current rating of the thyristors such that they are not damaged due to sudden loss of
field excitation to the motor. The protective fuse in series with the motor is designed to
disconnect the motor within 1 cycle of fault. Find out the ∫ i 2 dt rating of the
2
thyristors.
4. Why is it necessary to maximize the peripheral contact area of the gate and the cathode
regions? A thyristor used to control the voltage applied to a load resistance from a 220v,

200V C
+ THA
20 A
200V

200V C
+ THA
20 A
200V
2. Figure shows the equivalent gate drive circuit of the thyristor. For this circuit one can write
E = R i g + Vg OR Vg = E  R i g
The diode D clamps the gate voltage to zero when E goes negative.
Pav
0.2
∴ Vg i g Max
== = 0.5 watts
δ
Max
0.4
For maximum utilization of the gate power dissipation limit the gate load line ie Vg = E – igR =
10 – igR should be tangent to the maximum power dissipation curve Vg ig = 0.5
∴ Vgo = 10  i go R
Vgo i go = 0.5
∴ i go 2 R  10 i go + 0.5 = 0
dv g  vg v
∴ R = = =  go
di g ( vgo,igo ) i g ( vgo,igo ) i go
v go v i 0.5
∴R = = go 2go = 2
i go i go i go
0.5
∴ i go 2 ×  10i go + 0.5 = 0 or 10i go = 1 or i go = 0.1
i go 2
0.5
∴ R = 0.5 2 = = 50 Ω
i go .01
Back emf.
Va
t
ia
(normal)
t
ia
(with field loss)
3. Figure shows the armature voltage (firm line) and armature current of the motor under normal
operating condition at rated speed. If there is a sudden loss of field excitation back emf will
become zero and armature current will be limited solely by the armature resistance.
220 2
The peak magnitude of the fault current will be = 1556(Amps) .
.2
It the thyristors have to survive this fault at least for 1 cycle (after which the fuse blows) IsM >
2
1556 Amps.
The fuse blows within 1 cycle of the fault occurring. Therefore the thyristors must withstand
2
the fault for at least 1 cycle.
2
2
Therefore, the i t rating of the thyristor should be
(1556 )
2
102
=
2 ∫
0
[1  Cos 200 π t ] dt
4. At the beginning of the turn on process the thyristor starts conducting through the area
adjacent to the gate. This area spreads at a finite speed. However, if rate of increase of anode
current is lager than the rate of increase of the current conduction are, the current density
increases with time. This may lead to thyristor failure due to excessive local heating. However, if
the contact area between the gate and the cathode is large a thyristor will be able to handle a
di
relatively large a without being damaged.
dt
di a
The maximum will occur when the thyristor is triggered at ∝ = 90°. Then
dt
di a
L = 2 × 220 Sin 90 0
dt
di a
Since = 50 × 10 6 A Sec
dt Max
2 × 220
L = = 6.22 × 10 6 H = 6.22 μH
min
⎛ di a ⎞
⎜ dt ⎟
⎝ ⎠ Max
VC toff 200 V
vTHM
dv / dt
t
iC
20 Amps.
t
ic 20
∴ C = = 6 = 4 × 10
8
F = 0.04 μF
Min dv 500×10
dt Max
The circuit turn off time is the time taken by the capacitor voltage to reach zero from an initial
value of 200v. This time must be greater than the turn off time of the device.
dv c
Now C = i c = 20
dt
20 × Δt
∴ Δv c = Δv = 200  0 = 200
c
Δt = t off
20 × 50 × 10 6
∴ 200 =
C
20 × 50 × 10 6
∴C = = 5 μF
200
For safe commutation of THM the higher value of C must the chosen
Like thyristor, the GTO is a current controlled minority carrier (i.e. bipolar) device. GTOs differ
from conventional thyristor in that, they are designed to turn off when a negative current is sent
through the gate, thereby causing a reversal of the gate current. A relatively high gate current is
need to turn off the device with typical turn off gains in the range of 45. During conduction, on
the other hand, the device behaves just like a thyristor with very low ON state voltage drop.
Several different varieties of GTOs have been manufactured. Devices with reverse blocking
capability equal to their forward voltage ratings are called “symmetric GTOs”. However, the
most poplar variety of the GTO available in the market today has no appreciable reverse voltage
(2025v) blocking capacity. These are called “Asymmetric GTOs”. Reverse conducting GTOs
(RCGTO) constitute the third family of GTOs. Here, a GTO is integrated with an antiparallel
freewheeling diode on to the same silicon wafer. This lesson will describe the construction,
operating principle and characteristic of “Asymmetric GTOs” only.
(a) G G
C C
(b) (c)
Fig. 5.1: Circuit symbol and schematic cross section of a GTO
(a) Circuit Symbol, (b) Anode shorted GTO structure,
(c) Buffer layer GTO structure.
Like a thyristor, a GTO is also a four layer three junction pnpn device. In order to obtain high
emitter efficiency at the cathode end, the n+ cathode layer is highly doped. Consequently, the
break down voltage of the function J3 is low (typically 2040V). The p type gate region has
conflicting doping requirement. To maintain good emitter efficiency the doping level of this
layer should be low, on the other hand, from the point of view of good turn off properties,
resistively of this layer should be as low as possible requiring the doping level of this region to
be high. Therefore, the doping level of this layer is highly graded. Additionally, in order to
optimize current turn off capability, the gate cathode junction must be highly interdigitated. A
3000 Amp GTO may be composed of upto 3000 individual cathode segments which are a
accessed via a common contact. The most popular design features multiple segments arranged in
concentric rings around the device center.
The maximum forward blocking voltage of the device is determined by the doping level and the
thickness of the n type base region next. In order to block several kv of forward voltage the
doping level of this layer is kept relatively low while its thickness is made considerably higher (a
few hundred microns). Byond the maximum allowable forward voltage either the electric field at
the main junction (J2) exceeds a critical value (avalanche break down) or the n base fully
depletes, allowing its electric field to touch the anode emitter (punch through).
The junction between the n base and p+ anode (J1) is called the “anode junction”. For good turn
on properties the efficiency of this anode junction should be as high as possible requiring a
heavily doped p+ anode region. However, turn off capability of such a GTO will be poor with
very low maximum turn off current and high losses. There are two basic approaches to solve this
problem.
In the first method, heavily doped n+ layers are introduced into the p+ anode layer. They make
contact with the same anode metallic contact. Therefore, electrons traveling through the base can
directly reach the anode metal contact without causing hole injection from the p+ anode. This is
the classic “anode shorted GTO structure” as shown in Fig 5.1 (b). Due to presence of these
“anode shorts” the reverse voltage blocking capacity of GTO reduces to the reverse break down
Version 2 EE IIT, Kharagpur 5
voltage of junction J3 (2040 volts maximum). In addition a large number of “anode shorts”
reduces the efficiency of the anode junction and degrades the turn on performance of the device.
Therefore, the density of the “anode shorts” are to be chosen by a careful compromise between
the turn on and turn off performance.
In the other method, a moderately doped n type buffer layer is juxtaposed between the n type
base and the anode. As in the case of a power diode and BJT this relatively high density buffer
layer changes the shape of the electric field pattern in the n base region from triangular to
trapezoidal and in the process, helps to reduce its width drastically. However, this buffer layer in
a conventional “anode shorted” GTO structure would have increased the efficiency of the anode
shorts. Therefore, in the new structure the anode shorts are altogether dispensed with and a thin
p+ type layer is introduce as the anode. The design of this layer is such that electrons have a high
probability of crossing this layer without stimulating hole injection. This is called the
“Transparent emitter structure” and is shown in Fig 5.1 (c).
Exercise 5.1
Answer: (i) current, minority; (ii) four, three; (iii) positive, negative; (iv) turn off, turn on; (v)
anode shorts.
From the “two transistor analogy” (Fig 5.2 (a)) of the GTO structure one can write.
i C1 = ∝p I A + ICBO1 ( 5.1)
i B1 = i C 2 = ∝n I k + ICBO2 ( 5.2 )
I k = I A + IG and IA = i B1 + i C1 ( 5.3)
∝n IG + ( iCBO1 + i CBO2 )
Combining I A = ( 5.4 )
1 ( ∝n + ∝p )
With applied forward voltage VAK less than the forward break over voltage both ICBO1 and ICBO2
are small. Further if IG is zero IA is only slightly higher than (ICBO1 + ICBO2). Under this condition
both ∝n and ∝p are small and (∝p + ∝n) <<1. The device is said to be in the forward blocking
mode.
To turn the device on either the anode voltage can be raised until ICBO1 and ICBO2 increases by
avalanche multiplication process or by injecting a gate current. The current gain ∝ of silicon
transistors rises rapidly as the emitter current increases. Therefore, any mechanism which causes
a momentary increase in the emitter current can be used to turn on the device. Normally, this is
done by injecting current into the p base region via the external gate contract. As ∝n + ∝p
approaches unity the anode current tends to infinity. Physically as ∝n + ∝p nears unity the device
starts to regenerate and each transistor drives its companion into saturation. Once in saturation,
all junctions assume a forward bias and total potential drop across the device becomes
approximately equal to that of a single pn diode. The anode current is restricted only by the
external circuit. Once the device has been turned on in this manner, the external gate current is
no longer required to maintain conduction, since the regeneration process is selfsustaining.
Reversion to the blocking mode occurs only when the anode current is brought below the
“holding current” level.
Exercise 5.2
Answer: (i) removed; (ii) holding; (iii) negatively, cathode; (iv) hot spot; (v) tail.
VAK
VBRF
vg
(a) (b)
Fig 5.3 (b) shows the gate characteristics of a GTO. The zone between the min and max curves
reflects parameter variation between individual GTOs. These characteristics are valid for DC and
low frequency AC gate currents. They do not give correct voltage when the GTO is turned on
dI
with high dia and G . VG in this case is much higher.
dt dt
IgQ
digQ
dt
Fig 5.4 shows the switching characteristics of a GTO and refers to the resistive dc load switching
circuit shown on the right hand side. When the GTO is off the anode current is zero and VAK =
Vd. To turn on the GTO, a positive gate current pulse is injected through the gate terminal. A
substantial gate current ensure that all GTO cathode segments are turned on simultaneously and
within a short time. There is a delay between the application of the gate pulse and the fall of
anode voltage, called the turn on delay time td. After this time the anode voltage starts falling
while the anode current starts rising towards its steady value IL. Within a further time interval tr
they reach 10% of their initial value and 90% of their final value respectively. tr is called the
current rise time (voltage fall time). Both td and maximum permissible on state di A are very
dt
much gate current dependent. High value of I gM and dig at turn on reduces these times and
dt
di
increases maximum permissible on state A . It should be noted that large value of ig (IgM)
dt
and dig are required during td and tr only. After this time period both vg and ig settles down to
dt
their steady value. A minimum ON time period tON (min) is required for homogeneous anode
current conduction in the GTO. This time is also necessary for the GTO to be able to turn off its
rated anode current.
A B C D
E
F
Optical
Fiber optic Control
cable Logic
Electrical
Optical 
Electrical
Converter (a)
+ A
R1 R2
C2
+ ON T1

G
OFF T2
 R3

+ K
(b)
Fig. 5.5: Gate drive circuit of a GTO.
(a) Block diagram,
(b) Circuit diagram of the output stage
In the block diagram of Fig 5.5 (a) it is assumed that there is a potential difference of several kVs
between the master control and individual gate units.
The ON and OFF pulses for a GTO is communicated to individual gate units through fiber optic
cables. These optical signals are converted to electrical signals by a optical electrical converter.
These electrical signals through the control logic then produces the ON and OFF signal for the
out put stage which in turn sends positive and negative gate current to the GTO. Depending on
the requirement the control logic may also supervise GTO conduction by monitoring the gate
cathode voltage. Any fault is relayed back via fiber optic cable to the master control. Power
supply for the Gate drive units are derived from a common power supply through a high
frequency SMPS (Blocks A, B & C) arrangement.
Fig 5.5 (b) shows the circuit implementation of the output stage. The top switch T1 sends positive
gate pulse to the GTO gate. At the instant of turn on of T1 ,C2 acts almost as a short circuit and
Version 2 EE IIT, Kharagpur 12
the positive gate current is determined by the parallel combination of R1 and R2. However, at
steady state only R1 determines the gate current IG.
The bottom switch T2 is used for biasing the GTO gate negative with respect to the cathode.
Since, relatively large negative gate current flows during turn off, no external resistance is used
in series with T2. Instead, the ON state resistance of T2 is utilized for this purpose. In practice, a
large number of switches are connected in parallel to obtain the required current rating of T2. A
low value resistance R3 is connected between the gate and the cathode terminals of the GTO to
ensure minimum forward blocking voltage.
Exercise 5.3
Answer: (i) latching, leakage; (ii) transistor; (iii) asymmetric; (iv) gate, high; (v) di/dt;
(vi) cathode, gate; (vii) current; (viii) current tail; (ix) current, voltage; (x)
forward blocking.
VRRM: It is the maximum repetitive reverse voltage the GTO is able to withstand. For all
asymmetric GTOs this value is in the range of 2030 V, since it is determined by the gate
cathode junction break down voltage. Due to the anode shorted structure of the GTO the anode –
base junction (J1) does not block any reverse voltage. Unlike VDRM, VRRM rating may be
exceeded for a short time without destroying the device. This “reverse avalanche” capability of
the GTO is useful in certain situations as explained in Fig 5.6.
VG1
IG1 IG1
VG1
IG1 IL VD
G1 D1 VG1
t
IL
VD ID2
VG2
VD IL
VG2 t
G2 D2 ID2 Vfr > VRRM
(a) (b)
IFAVM and IFRMS: These are maximum average and RMS on state current respectively. They are
specified at a given case temperature assuming half wave sinusoidal on state current at power
frequency.
IFSM: This is the maximum allowed peak value of a power frequency half sinusoidal non
repetitive surge current. The pulse is assumed to be applied at an instant when the GTO is
operating at its maximum junction temperature. The voltage across the device just after the surge
should be zero.
∫ i dt : This is the limiting value of the surge current integral assuming half cycle sine wave
2
surge current. The junction temperature is assumed to be at the maximum value before the surge
and the voltage across the device following the surge is assumed to be zero. The i2t rating of a
semiconductor fuse must be less than this value in order to protect the GTO. Plots of both IFSM
and ∫ i 2 dt as functions of surge pulse width are usually provided by the manufacturer.
VF : This is the plot of the instantaneous forward voltage drop vs instantaneous forward
current at different junction temperatures.
Pav : For some frequently encountered current waveforms (e.g. sine wave, square wave) the
plot of the average on state power dissipation as a function of the average on state current is
provided by the manufacturers at a given junction temperature.
IH: This is the holding current of the GTO. This current, in case of a GTO1 , is considerably
higher compared to a similarly rated thyristor. Serious problem may arise due to anode current
variation because the GTO may “unlatch” at an in appropriate moment. This problem can be
avoided by feeding a continuous current into the gate (called the “back porch” current) during
ON period of the device. This DC gate current should be about 20% higher than the gate trigger
current (IGT) at the lowest expected junction temperature.
di
crit : This is the maximum permissible value of the rate of change of forward current during
dt
turn on. This value is very much dependent on the peak gate current magnitude and the rate of
increase of the gate current. A substantial gate current ensures that all GTO cathode segments are
turned ON simultaneously and within a short time so that no local hot spot is created.
di
The g and IgM values specified in the operating conditions should, therefore, be considered as
dt
minimum values.
Vgt, Igt: Igt is the gate trigger current and Vgt , the instantaneous gate cathode voltage when Igt is
flowing into the gate. Igt has a strong junction temperature dependence and increases very rapidly
with reduced junction temperature. Igt merely specifies the minimum back porch current
necessary to turn on the GTO at a low di and maintain it in conduction.
dt
Vgrm: It is the maximum repetitive reverse gate voltage, exceeding which drives the gate
cathode junction into avalanche breakdown.
Igrm: It is the peak repetitive reverse gate current at Vgrm and Tj (max).
Igqm: It is the maximum negative turn off gate current. The gate unit should be designed to
di
deliver this current under any condition. It is a function of turn off anode current, g during
dt
turn off and the junction temperature.
EON : It is the energy dissipated during each turn on operation. Manufacturers specify them as
functions of turn on anode current for different turn on di/dt and anode voltage EON reduces with
increased IgM .
IFgqm : It is the maximum anode current that can be repetitively turned off by a negative gate
current. It can be increased by increasing the value of the turn off snubber capacitance which
limits the dv/dt at turn off. A large negative dig/dt during turn off also helps to increase IFgqm.
ts : The storage time ts is defined as the time between the start of negative gate current and
the decrease in anode current. High value of the turn off anode current and junction temperature
increases it while a large negative dig/dt during turn off decreases it.
tf : This is the anode current fall time. It can not be influenced much by gate control.
toff(min) : This is the minimum off time before the GTO may be triggered again by a positive
gate current. If the device is retriggered during this time, localized turn on may destroy it.
Exercise 5.4
i. A GTO can block rated forward voltage only when the gate is _______________ biased
with respect to the _______________.
ii. A GTO can operate in the reverse _______________ region for a short time.
iii. The holding current of a GTO is much _______________ compared to a thyristor.
iv. After a current surge the voltage across a GTO should be reduced to _______________.
v. The gate cathode impedance of a GTO is much _______________ compared to a
thyristor.
vi. The turn on di/dt capability of a GTO can be increased by in creasing the
_______________ magnitude of the gate current and _______________ during turn on.
vii. The turn on delay time and current rise time of a GTO can be reduced by increasing the
gate current _______________ and _______________ during turn ON.
viii. The maximum anode current that can be turned off repetitively can be increased by
increasing the turn off snubber _______________ and negative _______________.
Answer: (i) negatively, cathode; (ii) avalanche; (iii) larger; (iv) zero; (v) smaller; (vi)
peak, dig/dt; (vii) magnitude, dig/dt; (viii) capacitance, dig/dt.
Reference
1) “GTO and GCT product guide”, ABB semiconductors AG, 1997.
2) “GTO Thyristors” , Makoto Azuma and Mamora Kurata, Proceedings of the IEEE,
Vol.76, No. 4, April 1988, pp 419427.
3) “Power Electronics”, P. S. Bimbhra, Khanna Publlishers, 1993.
• The Gatecathode junction of a GTO is far more inter digitized compared to a thyristor.
Thousands of cathode segments, normally arranged in concentric rings around the device
center, from the cathode structure of a GTO. This highly inter digitized structure of the
GTO cathode ensures that any “current filament” formed during the turn off process of a
GTO is quickly extinguished.
• “Anode shorts” are introduced at the p+ type anode and n type base junction of a GTO.
“Anode shorts” consists of heavily doped n+ type region introduced inside the p+ type
anodes. They make direct contact with the anode metal plate and provide an alternate path
for the electrons traveling through the n base to reach the anode metal contact without
causing bole injection from the p+ anode. This helps to reduce the “tail current” during turn
off of a GTO.
• Highly inter digitized gatecathode structure of a GTO helps to enhance the turn on di/dt
capability of the device due to faster and more even spreading of the injected gate current
to adjacent cathodes.
• On the other hand, presence of anode shorts has adverse effect on the turn on performance
of a GTO. Referring to Fig 5.2 (a), introduction of anode shorts effectively reduces the
current gain ∝p of the top pnp transistor. This has the effect of increasing the latching
and holding current of a GTO compared to a thyristor. The minimum gate current required
to trigger a GTO also increases.
2. In the first quadrant of the output iv plane the steady state output characteristics of a GTO
appears to be similar to that of a thyristor. There are some important differences however.
• Both holding and latching current of a GTO are considerably higher compared to a
similarly rated thyrisstor.
• The minimum gate current require to trigger a GTO at a given forward blocking voltage is
higher compared to a thyristor.
• The forward leakage current of a GTO is considerably higher compared to a thyristor of
equal rating. In fact, if the gate current is not sufficient to turn on a GTO it may operate as
a high voltage low gain transistor with considerable anode current.
• A GTO can block rated forward voltage only when the gate voltage is negative with respect
to the cathode or at least the gate is connected to the cathode through a low value
resistance.
• In the reverse blocking region (i.e third quadrant of the output iv plane) an asymmetric
GTO has much lower reverse break down voltage (2030V) compared to a thyristors.
Exceeding this reverse voltage forces the GTO to operate in the “reverse avalanche” mode.
• Turn the GTO on with a large (310 times the minimum gate trigger current) positive gate
current pulse with high rate of rise.
• Maintain conduction of the GTO through out the ON period by injecting a positive “back
porch” gate current which is larger than the minimum gate trigger current.
• Turn the GTO off with a large negative gate current with high rate of fall. The peak
magnitude of the negative gate current should be at least 2025% of the maximum anode
current during turn off.
• Reinforce the blocking state of the device by applying a negative voltage to the gate with
respect to cathode for the entire off duration of the GTO.
Both the turn on delay time (td) and the voltage fall time (tr) of a GTO can be reduced by
increasing the peak positive gate current and its rate of rise during turn on. Energy loss per
turn on (EON) also reduces.
A large negative gate current during turn off with a stiff slope considerably reduces the
storage time (ts) and enhances maximum anode current turn off (IFgqm) capability.
4. The specifications of IFAVM and IFRMS are given with reference to power frequency half
cycle sine wave anode current. If the GTO is employed in a line commutated phase
controlled converter application then these specifications give the maximum allowable
average and RMS current through the device respectively. However, in most GTO
applications the current waveform is for removed from a sinusoidal shape and the
switching losses are a considerable part of the total power losses. IFAVM / IFRMS ratings, in
such cases, does not have any practical significance except for comparison of current
carrying capacity of different devices.
On the other hand, IFgqm rating of a GTO gives the maximum anode current that can be
repetitively turned off by gate control. This rating is usually lower than IFAVM / IFRMS. In
5. Eon is reduced by increasing the peak magnitude of the positive gate current during turn on.
Eoff is reduced by increasing the turn off snubber capacitance across the GTO.
Instructional Objectives
On completion the student will be able to
The reliance of the power electronics industry upon bipolar devices was challenged by the
introduction of a new MOS gate controlled power device technology in the 1980s. The power
MOS field effect transistor (MOSFET) evolved from the MOS integrated circuit technology. The
new device promised extremely low input power levels and no inherent limitation to the
switching speed. Thus, it opened up the possibility of increasing the operating frequency in
power electronic systems resulting in reduction in size and weight. The initial claims of infinite
current gain for the power MOSFET were, however, diluted by the need to design the gate drive
circuit to account for the pulse currents required to charge and discharge the high input
capacitance of these devices. At high frequency of operation the required gate drive power
becomes substantial. MOSFETs also have comparatively higher on state resistance per unit area
of the device cross section which increases with the blocking voltage rating of the device.
Consequently, the use of MOSFET has been restricted to low voltage (less than about 500 volts)
applications where the ON state resistance reaches acceptable values. Inherently fast switching
speed of these devices can be effectively utilized to increase the switching frequency beyond
several hundred kHz.
From the point of view of the operating principle a MOSFET is a voltage controlled
majority carrier device. As the name suggests, movement of majority carriers in a MOSFET is
controlled by the voltage applied on the control electrode (called gate) which is insulated by a
thin metal oxide layer from the bulk semiconductor body. The electric field produced by the gate
voltage modulate the conductivity of the semiconductor material in the region between the main
current carrying terminals called the Drain (D) and the Source (S). Power MOSFETs, just like
their integrated circuit counterpart, can be of two types (i) depletion type and (ii) enhancement
type. Both of these can be either n channel type or pchannel type depending on the nature of
the bulk semiconductor. Fig 6.1 (a) shows the circuit symbol of these four types of MOSFETs
along with their drain current vs gatesource voltage characteristics (transfer characteristics).
S S S
S
ID ID ID ID
(b)
From Fig 6.1 (a) it can be concluded that depletion type MOSFETs are normally ON type
switches i.e, with the gate terminal open a nonzero drain current can flow in these devices. This
is not convenient in many power electronic applications. Therefore, the enhancement type
MOSFETs (particularly of the nchannel variety) is more popular for power electronics
applications. This is the type of MOSFET which will be discussed in this lesson. Fig 6.1 (b)
shows the photograph of some commercially available nchannel enhancement type Power
MOSFETs.
Source
Gate conductor
FIELD OXIDE Gate oxide
n+ n+ n+ n+
p(body) p(body)
n (drain drift)
n+
Drain
(a)
Contact to source
Source
Conductor
Field oxide
Gate
Oxide
Gate
Conductor
Single
n MOSFET
Cell
n+ p n+ n+ p n+ n+
n
n+
(b)
Fig. 6.2: Schematic construction of a power MOSFET
(a) Construction of a single cell.
(b) Arrangement of cells in a device.
Version 2 EE IIT, Kharagpur 6
The two n+ end layers labeled “Source” and “Drain” are heavily doped to approximately the
same level. The p type middle layer is termed the body (or substrate) and has moderate doping
level (2 to 3 orders of magnitude lower than n+ regions on both sides). The n drain drift region
has the lowest doping density. Thickness of this region determines the breakdown voltage of the
device. The gate terminal is placed over the n and p type regions of the cell structure and is
insulated from the semiconductor body be a thin layer of silicon dioxide (also called the gate
oxide). The source and the drain region of all cells on a wafer are connected to the same metallic
contacts to form the Source and the Drain terminals of the complete device. Similarly all gate
terminals are also connected together. The source is constructed of many (thousands) small
polygon shaped areas that are surrounded by the gate regions. The geometric shape of the source
regions, to same extent, influences the ON state resistance of the MOSFET.
D D
S G MOSFET
Parasitic BJT
+ +
n p n
Body spreading Parasitic BJT
resistance
n G G
n+ Body diode
S S
D
One interesting feature of the MOSFET cell is that the alternating n+ n p n+ structure
embeds a parasitic BJT (with its base and emitter shorted by the source metallization) into
each MOSFET cell as shown in Fig 6.3. The nonzero resistance between the base and the
emitter of the parasitic npn BJT arises due to the body spreading resistance of the p type
substrate. In the design of the MOSFET cells special care is taken so that this resistance is
minimized and switching operation of the parasitic BJT is suppressed. With an effective
short circuit between the body and the source the BJT always remain in cut off and its
collectorbase junction is represented as an anti parallel diode (called the body diode) in
the circuit symbol of a Power MOSFET.
VGS1
Gate Electrode
Source
+++ ++++++++
Electrode
Si02
n+
n
(a)
VGS2
VGS2 > VGS1
Gate Electrode
Source
+++ ++++++++
Electrode
Si02
n+
Depletion layer
p Ionized boundary.
acceptor Free
electron
n
(b)
Depletion layer
boundary.
p
Ionized
n acceptor
(c)
Fig. 6.4: Gate control of MOSFET conduction.
(a) Depletion layer formation;
(b) Free electron accumulation;
(c) Formation of inversion layer.
The positive charge induced on the gate metallization repels the majority hole carriers from
the interface region between the gate oxide and the p type body. This exposes the
negatively charged acceptors and a depletion region is created.
Further increase in VGS causes the depletion layer to grow in thickness. At the same time
the electric field at the oxidesilicon interface gets larger and begins to attract free electrons
as shown in Fig 6.4 (b). The immediate source of electron is electronhole generation by
thermal ionization. The holes are repelled into the semiconductor bulk ahead of the
depletion region. The extra holes are neutralized by electrons from the source.
As VGS increases further the density of free electrons at the interface becomes equal to the
free hole density in the bulk of the body region beyond the depletion layer. The layer of
free electrons at the interface is called the inversion layer and is shown in Fig 6.4 (c). The
inversion layer has all the properties of an n type semiconductor and is a conductive path or
“channel” between the drain and the source which permits flow of current between the
drain and the source. Since current conduction in this device takes place through an n type
“channel” created by the electric field due to gate source voltage it is called “Enhancement
type nchannel MOSFET”.
The value of VGS at which the inversion layer is considered to have formed is called the
“Gate – Source threshold voltage VGS (th)”. As VGS is increased beyond VGS(th) the
inversion layer gets some what thicker and more conductive, since the density of free
electrons increases further with increase in VGS. The inversion layer screens the depletion
layer adjacent to it from increasing VGS. The depletion layer thickness now remains
constant.
Answer: (i) voltage, majority; (ii) off, on; (iii) SiO2, (iv) BJT, (v) inversion, threshold; (vi)
depletion, threshold.
2. What are the main constructional differences between a MOSFET and a BJT? What
effect do they have on the current conduction mechanism of a MOSFET?
Answer: A MOSFET like a BJT has alternating layers of p and n type semiconductors.
However, unlike BJT the p type body region of a MOSFET does not have an external
electrical connection. The gate terminal is insulated for the semiconductor by a thin layer of
SiO2. The body itself is shorted with n+ type source by the source metallization. Thus
minority carrier injection across the sourcebody interface is prevented. Conduction in a
MOSFET occurs due to formation of a high density n type channel in the p type body
region due to the electric field produced by the gatesource voltage. This n type channel
connects n+ type source and drain regions. Current conduction takes place between the
drain and the source through this channel due to flow of electrons only (majority carriers).
Where as in a BJT, current conduction occurs due to minority carrier injection across the
BaseEmitter junction. Thus a MOSFET is a voltage controlled majority carrier device
while a BJT is a minority carrier bipolar device.
n+
Source Channel Drift
region p resistance region
resistance iD resistance
n
Drain
n+ resistance
VGS(th) VGS
(b)
D (d)
When VGS is increased beyond vGS(th) drain current starts flowing. For small values of vDS
(vDS < (vGS – vGS(th)) iD is almost proportional to vDS. Consequently this mode of operation
is called “ohmic mode” of operation. In power electronic applications a MOSFET is
operated either in the cut off or in the ohmic mode. The slope of the vDS – iD characteristics
in this mode is called the ON state resistance of the MOSFET (rDS (ON)). Several physical
resistances as shown in Fig 6.5 (b) contribute to rDS (ON). Note that rDS (ON) reduces with
increase in vGS. This is mainly due to reduction of the channel resistance at higher value of
At still higher value of vDS (vDS > (vGS – vGS (th)) the iD – vDS characteristics deviates from
the linear relationship of the ohmic region and for a given vGS, iD tends to saturate with
increase in vDS. The exact mechanism behind this is rather complex. It will suffice to state
that, at higher drain current the voltage drop across the channel resistance tends to decrease
the channel width at the drain drift layer end. In addition, at large value of the electric field,
produced by the large Drain – Source voltage, the drift velocity of free electrons in the
channel tends to saturate as shown in Fig 6.5 (c). As a result the drain current becomes
independent of VDS and determined solely by the gate – source voltage vGS. This is the
active mode of operation of a MOSFET. Simple, first order theory predicts that in the
active region the drain current is given approximately by
Equation (6.3) is shown by a dotted line in Fig 6.5 (a). The relationship of Equation (6.1)
applies reasonably well to logic level MOSFETs. However, for power MOSFETs the
transfer characteristics (iD vs vGS) is more linear as shown in Fig 6.5 (d).
At this point the similarity of the output characteristics of a MOSFET with that of a BJT
should be apparent. Both of them have three distinct modes of operation, namely, (i)cut off,
(ii) active and (iii) ohmic (saturation for BJT) modes. However, there are some important
differences as well.
• Unlike BJT a power MOSFET does not undergo second break down.
• The primary break down voltage of a MOSFET remains same in the cut off and in
the active modes. This should be contrasted with three different break down
voltages (VSUS, VCEO & VCBO) of a BJT.
• The ON state resistance of a MOSFET in the ohmic region has positive temperature
coefficient which allows paralleling of MOSFET without any special arrangement
for current sharing. On the other hand, vCE (sat) of a BJT has negative temperature
coefficient making parallel connection of BJTs more complicated.
As in the case of a BJT the operating limits of a MOSFET are compactly represented in a
Safe Operating Area (SOA) diagram as shown in Fig 6.6. As in the case of the FBSOA of a
Log (iD)
IDM
105sec
Due to the presence of the anti parallel “body diode”, a MOSFET can not block any reverse
voltage. The body diode, however, can carry an RMS current equal to IDM. It also has a
substantial surge current carrying capacity. When reverse biased it can block a voltage
equal to VDSS.
For safe operation of a MOSFET, the maximum limit on the gate source voltage (VGS
(Max)) must be observed. Exceeding this voltage limit will cause dielectric break down of
the thin gate oxide layer and permanent failure of the device. It should be noted that even
static charge inadvertently put on the gate oxide by careless handling may destroy it. The
device user should ground himself before handling any MOSFET to avoid any static charge
related problem.
Exercise 6.2
Answer: (i) Cut off; (ii) vDS; (iii) decreases; (iv) vGS, vDS; (v) independent; (vi) second
break down; (vii) Positive, paralleling; (viii) linear; (ix) rDS (ON);
Gate oxide
+
n CGD
CGS CGD
p Drain body CGD1 idealized
depletion
CDS layer Actual
n
CGD2
n+
VGS – VGS (th) = VDS VDS
D
(a) (b)
D D D
S S S
(c)
Fig. 6.7: Circuit model of a MOSFET
(a) MOSFET capacitances
(b) Variation of CGD with VDS
(c) Circuit models.
Fig 6.7 (a) shows three important capacitances inherent in a MOSFET structure. The most
prominent capacitor in a MOSFET structure is formed by the gate oxide layer between the
gate metallization and the n+ type source region. It has the largest value (a few nano farads)
and remains more or less constant for all values of vGS and vDS. The next largest capacitor
(a few hundred pico forwards) is formed by the drain – body depletion region directly
below the gate metallization in the n drain drift region. Being a depletion layer capacitance
its value is a strong function of the drain source voltage vDS. For low values of vDS (vDS <
(vGS – vGS (th))) the value of CGD (CGD2) is considerably higher than its value for large vDS
as shown in Fig 6.7 (b). Although variation of CGD between CGD1 and CGD2 is continuous a
step change in the value of CGD at vDS = vGS – vGS(th) is assumed for simplicity. The lowest
value capacitance is formed between the drain and the source terminals due to the drain –
body depletion layer away form the gate metallization and below the source metallization.
Although this capacitance is important for some design considerations (such as snubber
design, zero voltage switching etc) it does not appreciably affect the “hard switching”
performance of a MOSFET. Consequently, it will be neglected in our discussion. From the
VD
DF IO
if
+
iD
CGD VDS
Rg
ig 
Vgg +

CGS
To turn the MOSFET on, the gate drive voltage changes from zero to Vgg. The gate
source voltage which was initially zero starts rising towards Vgg with a time constant τ1 =
Rg (CGS + CGD1) as shown in Fig 6.9.
I0 I0
if iD
∫∫ t
VDS
I0ros (ON)
∫∫ t
tdON tri tfv1 tfv2 td(off) trv2 trvi tfi
tON toff
Fig. 6.9: Switching waveforms of a clamped inductive switching circuit using MOSFET
Note that during this period the drain voltage vDS is clamped to the supply voltage VD
through the free wheeling diode DF. Therefore, CGS and CGD can be assumed to be
connected in parallel effectively. A part of the total gate current ig charges CGS while the
other part discharges CGD.
Till vGS reaches vGS (th) no drain current flows. This time period is called turn on delay
time (td(ON)). Note that td(ON) can be controlled by controlling Rg. Byond td(ON) iD
increases linearly with vGS and in a further time tri (current rise time) reaches Io. The
corresponding value of vGS and ig are marked as VGS Io and ig Io respectively in Fig 6.9.
At this point the complete load current has been transferred to the MOSFET from the free
wheeling diode DF. iD does not increase byond this point. Since in the active region iD and
vGS are linearly related, vGS also becomes clamped at the value vGSIo. The gate current ig
now discharges CGD and the drain voltage starts falling.
d d d ig V V I
v DS = ( vGS + vGD ) = v GD = = GG GS o ( 6.4 )
dt dt dt CGD CGD R g
To turn the MOSFET OFF, Vgg is reduced to zero triggering the exact reverse process of
turn on to take place. The corresponding waveforms and switching intervals are show in
Fig 6.9. The total turn off time toff = td(off) + trv1 + trv2 + tfi.
R1
Q1
Logic level RG
gate pulse RG
Q2 VGG
Q3
(b)
(a)
VD
D
DF
IL R
RG G
D R
S
B RB
G (d)
S
(c)
To turn the MOSFET on the logic level input to the inverting buffer is set to high state so
that transistor Q3 turns off and Q1 turns on. The top circuit of Fig 6.10 (b) shows the
equivalent circuit during turn on. Note that, during turn on Q1 remains in the active
region. The effective gate resistance is RG + R1 / (β1 + 1). Where, β1 is the dc current gain
of Q1.
The switching time of the MOSFET can be adjusted by choosing a proper value of RG.
Reducing RG will incase the switching speed of the MOSFET. However, caution should
be exercised while increasing the switching speed of the MOSFET in order not to turn on
the parasitic BJT in the MOSFET structure inadvertently. The drainsource capacitance
(CDS) is actually connected to the base of the parasitic BJT at the p type body region. The
body source short has some nonzero resistance. A very fast rising drainsource voltage
will send sufficient displacement current through CDS and RB as shown in Fig 6.10 (c).
The voltage drop across RB may become sufficient to turn on the parasitic BJT. This
problem is largely avoided in a modern MOSFET design by increasing the effectiveness
of the bodysource short. The devices are now capable of dvDS/dt in excess to 10,000
V/μs. Of course, this problem can also be avoided by slowing down the MOSFET
switching speed.
Since MOSFET on state resistance has positive temperature coefficient they can be
paralleled without taking any special precaution for equal current sharing. To parallel two
MOSFETs the drain and source terminals are connected together as shown in Fig 6.10
(d). However, small resistances (R) are connected to individual gates before joining them
together. This is because the gate inputs are highly capacitive with almost no losses.
Some stray inductance of wiring may however be present. This stray inductance and the
MOSFET capacitance can give rise to unwanted high frequency oscillation of the gate
voltage that can result in puncture of the gate qxide layer due to voltage increase during
oscillations. This is avoided by the damping resistance R.
Exercise 6.3
Answer: (i) largest; (ii) ohmic, active; (iii) threshold; (iv) inversely; (v) gate drive.
di D
since for vgs < vgs (th) iD = =0
dt
di D 4
12 (
∴ = 15  3) = 1.01×109 A sec
dt Max 50×950×10
dv DS Vgg  VGS , Io
=
dt CGD R g
VDSS: This is the drainsource break down voltage. Exceeding this limit will destroy the
device due to avalanche break down of the bodydrain pn junction.
Continuous and Pulsed power dissipation limits: They indicate the maximum
allowable value of the VDS, iD product for the pulse durations shown against each limit.
Exceeding these limits will cause the junction temperature to rise beyond the acceptable
limit.
All safe operating area limits are specified at a given case temperature.
Gate threshold voltage (VGS (th)): The MOSFET remains in the cut off region when vGS
in below this voltage. VGS (th) decreases with junction temperature.
Drain Source on state resistance (rDS (ON)): This is the slope of the iD – vDS
characteristics in the ohmic region. Its value decreases with increasing vGS and increases
with junction temperature. rDS (ON) determines the ON state power loss in the device.
GateSource breakdown voltage: Exceeding this limit will destroy the gate structure of
the MOSFET due to dielectric break down of the gate oxide layer. It should be noted that
this limit may by exceeded even by static charge deposition. Therefore, special
precaution should be taken while handing MOSFETs.
Input, output and reverse transfer capacitances (CGS, CDS & CGD): Value of these
capacitances are specified at a given drainsource and gatesource voltage. They are
useful for designing the gate drive circuit of a MOSFET.
In addition to the main MOSFET, specifications pertaining to the “body diode” are also
provided. Specifications given are
i. The maximum voltage a MOSFET can with stand is ________________ of drain current.
ii. The FBSOA and RBSOA of a MOSFET are ________________.
iii. The gate source threshold voltage of a MOSFET ________________ with junction
temperature while the on state resistance ________________ with junction temperature.
iv. The gate oxide of a MOSFET can be damaged by ________________ electricity.
v. The reverse break down voltage of the body diode of a MOSFET is equal to
________________ while its RMS forward current rating is equal to ________________.
Answer: (i) independent; (ii) identical; (iii) decreases, increases; (iv) static; (v) VDSS; IDM.
Reference
[1] “Evolution of MOSBipolar power semiconductor Technology”, B. Jayant Baliga,
Proceedings of the IEEE, VOL.76, No4, April 1988.
[2] “Power Electronics ,Converters Application and Design” Third Edition, Mohan,
Undeland, Robbins. John Wiley & Sons Publishers 2003.
[3] GE – Power MOSFET data sheet.
2. The gate oxide layer of a MOSFET is 1000 Angstrom thick Assuming a break down field
strength of 5 × 106 V/cm and a safely factor of 50%, find out the maximum allowable
gate source voltage.
3. Explain why in a high voltage MOSFET switching circuit the voltage rise and fall time is
always greater than current fall and rise times.
VGS(th) = 3V, gfs = 3, CGS = 800 PF, CGD = 250 PF. The MOSFET is used to switch an
inductive load of 15 Amps from 150V supply. The switching frequency is 50 kHz. The
gate drive circuit has a driving voltage of 15V and output resistance of 50Ω. Find out the
switching loss in the MOSFET.
2. From the given data the break down gate source voltage
v GS BD = E BD × t gs
where EBD = Break down field strength
tgs = thickness of the oxide layer.
∴
di D d
= g fs vGS = g fs
( Vgg  vGS )
dt dt R g CGS
During current rise Vgg >> vGS
di g fs
∴ D ≈ Vgg
dt R g CGS
Io
∴ t ri = t fi ≈ R g CGS where Io = load current.
g fs Vgg
d Vgg  Vg s , Io Vgg
v DS = ≈
dt R g CGD R g CGD
That is current rise and fall times are much shorter than voltage rise and fall times.
4. Referring to Fig 6.9 energy loss during switching occurs during intervals tri , tfv1, tfv2, trv2,trv1,
and tfi. For simplicity it will be assumed that tfv2 = trv2 = 0. Also the rise and fall of iD and vDS
will be assumed to be linear.
During tri
i D = g fs (vgs  vgs (th))
di D d Vgg  v gs
∴ = g fs v gs = g fs
dt dt (CGS + CGD )R g
di D g fs Vgg
∴ ≈ sinceVgg >> v gs during current rise
dt (CGS + CGD )R g
Io
∴ t ri = (CGS + CGD )R g
g fs Vgg
Energy loss during tri is
1 V I2
E ON1 = t ri VD Io = D o (CGS + CGD )R g
2 2g fs Vgg
During tfv
dVDS Vgg  Vgs, Io
=
dt CGD R g
I
But Vgs , Io = o + vgs (th)
g fs
I
Vgg  v gs (th)  o
dVDS g fs
∴ =
dt R g CGD
VD
∴ t fv = R g CGD
Io
Vgg  Vgs (th) 
g fs
E ON = EOFF
Instructional objects
On completion the student will be able to
With the discovery that power MOSFETs were not in a strong position to displace the BJT,
many researches began to look at the possibility of combining these technologies to achieve a
hybrid device which has a high input impedance and a low on state resistance. The obvious first
step was to drive an output npn BJT with an input MOSFET connected in the Darlington
configuration. However, this approach required the use of a high voltage power MOSFET with
considerable current carrying capacity (due to low current gain of the output transistor). Also,
since no path for negative base current exists for the output transistor, its turn off time also tends
to get somewhat larger. An alternative hybrid approach was investigated at GE Research center
where a MOS gate structures was used to trigger the latch up of a four layer thyristor. However,
this device was also not a true replacement of a BJT since gate control was lost once the thyristor
latched up.
After several such attempts it was concluded that for better results MOSFET and BJT
technologies are to be integrated at the cell level. This was achieved by the GE Research
Laboratory by the introduction of the device IGT and by the RCA research laboratory with the
device COMFET. The IGT device has undergone many improvement cycles to result in the
modern Insulated Gate Bipolar Transistor (IGBT). These devices have near ideal characteristics
for high voltage (> 100V) medium frequency (< 20 kHZ) applications. This device along with
the MOSFET (at low voltage high frequency applications) have the potential to replace the BJT
completely.
SiO2 SiO2
(Gate oxide) +  (Gate oxide)
n n
p Body region
J3
Drain drift
J2 n region
J1 n+ Buffer layer
p+ Injecting layer
Collector
Fig. 7.1: Vertical cross section of an IGBT cell.
The major difference with the corresponding MOSFET cell structure lies in the addition of a p+
injecting layer. This layer forms a pn junction with the drain layer and injects minority carriers
into it. The n type drain layer itself may have two different doping levels. The lightly doped n
region is called the drain drift region. Doping level and width of this layer sets the forward
blocking voltage (determined by the reverse break down voltage of J2) of the device. However, it
does not affect the on state voltage drop of the device due to conductivity modulation as
discussed in connection with the power diode. This construction of the device is called “Punch
Trough” (PT) design. The NonPunch Through (NPT) construction does not have this added n+
buffer layer. The PT construction does offer lower on state voltage drop compared to the NPT
construction particularly for lower voltage rated devices. However, it does so at the cost of lower
reverse break down voltage for the device, since the reverse break down voltage of the junction
J1 is small. The rest of the construction of the device is very similar to that of a vertical
MOSFET (Link to 6.2) including the insulated gate structure and the shorted body (p type) –
emitter (n+ type) structure. The doping level and physical geometry of the p type body region
however, is considerably different from that of a MOSFET in order to defeat the latch up action
of a parasitic thyristor embedded in the IGBT structure. A large number of basic cells as shown
in Fig 7.1 are grown on a single silicon wafer and connected in parallel to form a complete IGBT
device.
The IGBT cell has a parasitic pnpn thyristor structure embedded into it as shown in Fig 7.2(a).
The constituent pnp transistor, npn transistor and the driver MOSFET are shown by dotted
lines in this figure. Important resistances in the current flow path are also indicated.
MOSFET n+
J3
npn p
Body spreading resistance
Drift J2
resistance pnp n
n+
J1
p+
Collector
(a)
Drift
region Collector Drift
resistance region Collector
resistance
Gate Body
spreading
resistance
Emitter
Gate
(c)
Emitter
(b)
Fig. 7.2: Parasitic thyristor in an IGBT cell.
(a) Schematic structure
(b) Exact equivalent circuit.
(c) Approximate equivalent circuit
Fig 7.2(b) shows the exact static equivalent circuit of the IGBT cell structure. The top pnp
transistor is formed by the p+ injecting layer as the emitter, the n type drain layer as the base and
the p type body layer as the collector. The lower npn transistor has the n+ type source, the p
type body and the n type drain as the emitter, base and collector respectively. The base of the
lower npn transistor is shorted to the emitter by the emitter metallization. However, due to
imperfect shorting, the exact equivalent circuit of the IGBT includes the body spreading
resistance between the base and the emitter of the lower npn transistor. If the output current is
large enough, the voltage drop across this resistance may forward bias the lower npn transistor
and initiate the latch up process of the pnpn thyristor structure. Once this structure latches up
the gate control of IGBT is lost and the device is destroyed due to excessive power loss.
A major effort in the development of IGBT has been towards prevention of latch up of the
parasitic thyristor. This has been achieved by modifying the doping level and physical geometry
of the body region. The modern IGBT is latchup proof for all practical purpose. Fig 7.3(a) and
(b) shows the circuit symbol and photograph of an IGBT.
E
(a) (b)
Exercise 7.1
Fill in the blank(s) with the appropriate word(s).
Answers:
i) hybrid, MOSFET, BJT ; ii) high, medium ; iii) p+ ; iv) thickness, doping level ; v) low,
symmetrical ; vi) thyristor; vii) thryistor, latch up ; viii) body, latch up.
When the gate emitter voltage exceeds the threshold, an inversion layer forms in the p type body
region under the gate. This inversion layer (channel) shorts the emitter and the drain drift layer
and an electron current flows from the emitter through this channel to the drain drift region. This
in turn causes substantial hole injection from the p+ type collector to the drain drift region. A
portion of these holes recombine with the electrons arriving at the drain drift region through the
channel. The rest of the holes cross the drift region to reach the p type body where they are
collected by the source metallization.
From the above discussion it is clear that the n type drain drift region acts as the base of the
output pnp transistor. The doping level and the thickness of this layer determines the current
gain “∝” of the pnp transistor. This is intentionally kept low so that most of the device current
flows through the MOSFET and not the output pnp transistor collector. This helps to reduced
the voltage drop across the “body” spreading resistance shown in Fig 7.2 (b) and eliminate the
possibility of static latch up of the IGBT.
The total on state voltage drop across a conducting IGBT has three components. The
voltage drop across J1 follows the usual exponential law of a pn junction. The next component of
the voltage drop is due to the drain drift region resistance. This component in an IGBT is
considerably lower compared to a MOSFET due to strong conductivity modulation by the
injected minority carriers from the collector. This is the main reason for reduced voltage drop
across an IGBT compared to an equivalent MOSFET. The last component of the voltage drop
across an IGBT is due to the channel resistance and its magnitude is equal to that of a
comparable MOSFET.
(a) (b)
As the gate emitter voltage increases beyond the threshold voltage the IGBT enters into the
active region of operation. In this mode, the collector current ic is determined by the transfer
characteristics of the device as shown in Fig 7.4(b). This characteristic is qualitatively similar to
that of a power MOSFET and is reasonably linear over most of the collector current range. The
ratio of ic to (VgE – vgE(th)) is called the forward transconductance (gfs) of the device and is an
important parameter in the gate drive circuit design. The collector emitter voltage, on the other
hand, is determined by the external load line ABC as shown in Fig 7.4(a).
As the gate emitter voltage is increased further ic also increases and for a given load resistance
(RL) vCE decreases. At one point vCE becomes less than vgE – vgE(th). Under this condition the
driving MOSFET part of the IGBT (Fig 7.2(c)) enters into the ohmic region and drives the
output pnp transistor to saturation. Under this condition the device is said to be in the
saturation mode. In the saturation mode the voltage drop across the IGBT remains almost
constant reducing only slightly with increasing vgE.
In power electronic applications an IGBT is operated either in the cut off or in the saturation
region of the output characteristics. Since vCE decreases with increasing vgE, it is desirable to use
the maximum permissible value of vgE in the ON state of the device. vgE(Max) is limited by the
maximum collector current that should be permitted to flow in the IGBT as dictated by the
“latchup” condition discussed earlier. Limiting VgE also helps to limit the fault current through
It is interesting to note that an IGBT does not exibit a BJTlike second break down failure. Since,
in an IGBT most of the collector current flows through the drive MOSFET with positive
temperature coefficient the effective temperature coefficient of vCE in an IGBT is slightly
positive. This helps to prevent second break down failure of the device and also facilitates
paralleling of IGBTs.
Exercise 7.2
Fill in the blank(s) with the appropriate word(s).
Answers:
i) MOSFET; ii) threshold, inversion; iii) hole, collector; iv) MOSFET, BJT; v) cutoff; vi)
transfer, linear; vii)saturation; viii) constant; ix) positive; x) second break down.
VCE
VCE(sat)
VCC VCC
∫∫ t
iC ∫∫
iD IL IL IL IL
∫∫ t
tdON tri tfv1 tfv2 trv1 trv2 tfi2
tfi1
The turn off process of an IGBT follows the inverse sequence of turn ON with one major
difference. Once vgE goes below vgE(th) the drive MOSFET of the IGBT equivalent circuit turns
off. During this period (tfi1) the device current falls rapidly. However, when the drive MOSFET
turns off, some amount of current continues of flow through the output pnp transistor due to
stored charge in its base. Since there is no reverse voltage applied to the IGBT terminals that
could generate a negative drain current, there is no possibility for removing the stored charge by
carrier sweepout. The only way these excess carriers can be removed is by recombination within
the IGBT. During this recombination period (tfi2) the remaining current in the IGBT decays
relatively slowly forming a current fail. A long tfi2 is undesirable, because the power dissipation
The gate drive circuit of an IGBT should ensure fast and reliable switching of the device. In
particular, it should.
Ri
Q1
 RB R G IGBT
Vi
+ Q2
(Logic level)
E
Opto isolator
Level Totem pole
Shifting Vgg Vcc gate drive
Comparator amplifier
(a)
RB RB
R β1 +1 R β2 +1
G G
Vgg To IGBT To IGBT
Gate Vgg Gate
E E
Turn on equivalent circuit Turn off equivalent circuit
(b)
Fig. 7.7: IGBT gate drive circuit
(a) Gate drive
(b) Equivalent circuit of the gate drive during turn on and turn off.
Version 2 EE IIT, Kharagpur 13
The logic level gate drive signal is first optoisolated and fed to a level shifting comparator. This
stage converts the unipolar (usually positive) out put voltage of the optoisolator to a bipolar
(±Vgg) signal compatible to the IGBT gate drive levels. The output of the comparator feeds a
totem pole output amplifier stage which drives the IGBT. The equivalent circuit of the gate drive
during turn on and off are shown in Fig 7.7(b). If VCC > Vgg then both Q1 and Q2 will operate
in the active region and reasonably constant value of β1 & β2 of these two transistors can be used
for analysis purpose. These equivalent circuits along with the model of the IGBT input MOSFET
can be used to analyze the switching performance of the device. Conversely, for a desired
switching performance a suitable gate drive circuit can be designed.
Maximum continuous collector current (IC): This is the maximum current the IGBT can
handle on a continuous basis during ON condition. It is specified at a given case temperature
with derating curves provided for other case temperatures.
Maximum pulsed collector current (ICM): This is the maximum collector current that can flow
for a specified pulse duration. This current is limited by specifying a maximum gateemitter
voltage.
Maximum gateemitter voltage (VgES): This is the maximum allowable magnitude of the gate
emitter voltage (of both positive and negative polarity) in order to
• Prevent break down of the gate oxide insulation.
• Restrict collector current to ICM.
Collector leakage current (ICES): This is the leakage collector current during off state of the
device at a given junction temperature. This is usually specified at VgE = 0V and vCE = VCES.
Gateemitter leakage current (IGES): Usually specified at vCE = 0V & vgE = vgES.
Gateemitter threshold voltage (vgE(th)): It is specified at a low collector emitter voltage and
collector current.
Forward Transconductance (gfs): This is again specified at a low value of vCE. For more
detailed data the transfer characteristics of the device (ic vs vgE) is also provided.
Switching times (td(ON) tri, tfv, trv, tfi): These times are specified for inductive load switching as
functions of gate charging resistance and collector current. In addition turn on and turn off
energy losses per switching operation are also specified.
Maximum total power dissipation (Ptmax): This is the maximum allowable power lass in the
device (both switching and conduction) on a continuous basis at a given case temperature.
Derating curve at other temperatures are also specified.
The IGBT has robust SOA both during turn on and turn off. Fig 7.8 (a) shows the FBSOA. On
the left side it is restricted by the forward voltage drop characteristics. Up to maximum
continuous collector current this voltage remains reasonably constant at a low value. However, at
ICM this voltage starts increasing as the IGBT starts entering active region. On the top the
FBSOA is restricted by ICM.
iC iC
ICM ICM 1000V/μS
IC 105sec
104sec
2000V/μS
103sec
102sec 3000V/μS
DC
The RBSOA for low values of dvCE dt is rectangular. However, for increased dvCE dt the upperright
hand corner is progressively cut out. The reason for this restriction on the RBSOA is to avoid
dynamic latch up. The device user can easily control dvCE dt by proper choice of Vgg and the gate
drive resistance.
Exercise 7.3
Fill in the blank(s) with the appropriate word(s).
i. In a modern IGBT most of the collector current flows through the _________________
and not the _________________.
iii. During turn on of an IGBT the rate of fall of voltage slows down towords the end since
the output pnp transistor traverses its _________________ region more
_________________ compared to the drive MOSFET.
iv. During turn off of an IGBT a _________________ is formed due to excess stored charge
in the _________________ region of the output pnp transistor.
dvCE
vi. dt of an IGBT during turn off should be controlled to prevent _________________ of
the device.
vii. A specified maximum gate emitter voltage of an IGBT helps to limit the collector current
during _________________ fault.
ix. The FBSOA of an IGBT is similar to that of a _________________ except that the on
state voltage drop is much _________________.
x. The upper right hand corner of the IGBT RBSOA is gradually cut out with increasing
_________________ to avoid _________________ of the device.
Answer: (i) MOSFET, BJT; (ii) latch up, negative; (iii) active, slowly; (iv) current tail, base; (v)
EMI; (vi) Latch up; (vii) short circuit; (viii) decreases; (ix) MOSFET, lower; (x) dvCE dt , latch up.
Reference
[1] B. Jayanta Baliga, “Evolution of MOS Bipolar Power Semiconductor Technology”,
Proceedings of the IEEE, vol. 76, No. 4, April 1988, pp 409418.
[2] “Power electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins;
John Wiley & Sons, 2003
[3] B. Jayanta Baliga et. al, “The Insulated Gate Transistor: A new ThreeTerminal MOS
Controlled Bipolar. Power Device”, IEEE transaction on Electron Devices, vol. ED31,
No. 6 June 1984 pp 421828.
[4] Allen R. Hefner, “An Investigation of the drive circuit requirements for the Power
Insulated Gate Bipolar Transistor”, IEEE Transactions on Power Electronics. Vol. 6 No.
2. April 1991.
Lesson Summary
• IGBT is a hybrid device which combines the advantages of MOSFET and BJT.
• An IGBT is formed by adding a p+ collector layer on the drain drift layer of a Power
MOSFET.
• Punch through IGBT has a thin n+ buffer layer between the p+ collector layer and n
drain drift layer. They have significantly lower conduction loss.
• The IGBT cell structure embeds a parasitic thyristor in it. Latching up of this thyristor is
prevented by special structuring of the body region and increasing the effectiveness of the
body shorting.
• From the operational point of view an IGBT is a voltage controlled bipolar device.
• The operational equivalent circuit of an IGBT has an n channel MOSFET driving a pnp
BJT.
• Like other semiconductor devices on IGBT can also operate in the cut off active and
saturation regions.
• When the gateemitter voltage of an IGBT is below threshold it operates in the cut off
region.
• For a given load resistance the operating point of an IGBT can be moved from cut off to
saturation through the active region by increasing the gateemitter voltage.
• In the active region, the collector current of an IGBT is determined by the gateemitter
voltage which can be limited to a given maximum value to limit the fault current through
the device in the event of a load short circuit.
• The IGBTs have a slightly positive temperature coefficient of the onstate voltage drop
which makes paralleling of these devices simpler.
• An IGBT does not exhibit second break down phenomena as in the case of a BJT.
• The switching characteristics of an IGBT is similar to that of a MOSFET.
• To avoid dynamic latch up of the parasitic thryrstor in an IGBT, the gate emitter voltage
of the device is maintained at a negative value during it’s off period.
• During turn off, the collector current of an IGBT can exhibit “current tailing” due to
stored base change in the base region of the output pnp transistor.
• The forward bias SOA of an IGBT is similar to that of a MOSFET except the on state
voltage drop being much lower.
• The maximum allowable collector current in an IGBT is restricted by the static latch up
consideration.
Q2. (a) In an IGBT a major portion of the collector current flow through the driver MOSFET
section which has a voltage rating almost same as the device. Then how does the on state
voltage drop of an IGBT remain low compared to an equivalent MOSFET?
(b) An IGBT is used to switch a resistive load of 5Ω from a DC supply of 350 volts as
shown in the inset of Fig 7.4 (a). The ON state gate voltage is vgE = 15v. For the IGBT,
vgE (th) = 4 volts and gts = 25. Find out the maximum current flowing through the IGBT
in the event of a short circuit fault across the load. Also find out the power dissipation
inside the device.
Q3. What do you under stand by “dynamic latch up” of an IGBT. How can it be prevented?
Q4. What steps are taken in the cell structure design of an IGBT to minimize the “tail current”
during turn off operation.
Q5. In the basic gate drive circuit of an IGBT shown in Fig 7.7 (a) following data are given
Vgg = 15 V, Vcc = 20 V, β1 for Q1 = 50, β2 for Q2 = 50.
RB = 2.2 KΩ, R = 30Ω, VgE (th) of IGBT = 4V, gfs = 40
CgE = 4nF, CgD = 500pF,
The IGBT is used to switch a clamed inductive load of 50 Amps from a 400 volts supply.
dvCE
Find out maximum values of dic
dt and dt during Turn on and Turn off of the IGBT.
2. (a) The total voltage drop across a conducting IGBT has three components. The voltage
drop across the emitterbase junction of the output pnp transistor follows the usual
exponential low of a pn junction. The next component of the voltage drop is due to the
drain drift region resistance. In a normal high voltage MOSFET this component of the
voltage drop is large due to lower doping level (necessary for blocking high voltage) of
this region. However, in a conducting IGBT electrons arriving at the drain drift region
through the MOSFET channel causes large minority carrier injection from the p+
collector. The consequent conductivity modulation reduces the resistance (and hence the
voltage drop) in this region. The third component of the IGBT voltage drop occurs across
the channel of the driving MOSFET and is same as that of an equivalent high voltage
MOSFET. Therefore, the reduced voltage drop across a conducting IGBT is due to
reduction of the drain drift region resistance by “conductivity modulation”.
(b) In the event of a short circuit across the load the voltage across the device will be 350
volts and the IGBT will operate in the active region. In this region
4. Punch Through and Nonpunch through IGBTs solve the problem of tail current by two
different approaches. Punch through IGBT s attempt to minimize the current tailing
problem by shortening the duration of the tailing time. This is done by reducing the
excess carrier life time in the n+ buffer layer compared to the n drain drift layer. This n+
buffer layer acts as a sink for excess holes and greatly enhances the removal rate of holes
from the drain drift layer. Thus the tail time is reduced.
Non punch through IGBTs attack the current tailing problem by minimizing the
magnitude of the current during the failing interval. This is done by designing the IGBT
so that the MOSFET section carries as much of the total current as possible. Newer NPT
IGBT designs have more than 90% of the total current carried by the MOSFET section of
the device.
5. During turn on and turn off the IGBT passes through the active region.
dic d
∴ = gfs vgE
dt dt
But from the equivalent circuit of the IGBT gate drive circuit during turn on
d Vgg  vgE
vgE =
dt (
( CgE + CgD ) R + βR1 +1B )
dic d gfs ( Vgg  vgE )
∴ = gfs vgE =
dt dt (
( CgE + CgD ) R + βR1 +1B )
In the active region Vgg >> vgE
Also since Vcc > Vgg, Q1 & Q2 operates in the active region.
dic
Since β1 = β2 , during turn off will also have the same value
dt
dic
So = 1.82 A/ns
dt
Since load current is 50 Amps and gfs = 40
IL
vge IL = vgE (th) + = 5.25 volts
gfs
dvCE V  v IL
Daring turn on CgD = ig IL = gg gERB
dt R + β+1
dvCE
∴ during turn ON is
dt
dvCE Vgg  vgE IL 15  5.25
= =
dt ( RB
CgD R + β +1
1
)500 × 1012 ( 30 + 2200
51 )
dvCE
during turn off will be same
dt
dvCE
So = 2.67 × 108 V/Sec or 267 V/μs.
dt
With SCRs’ 'forced commutation' and 'natural (line) commutation' usually described the type of
switching. Both refer to the turnoff mechanism of the SCR, the turnon dynamics being
inconsequential for most purposes. A protective inductive snubber to limit the turnon di/dt is
usually utilised. For the SCRs’ the turnoff data helps to dimension the 'commutation
components' or to set the 'margin angle'. Conduction losses account for the most significant part
of total losses.
Present day fast converters operate at much higher switching frequencies chiefly to reduce
weight and size of the filter components. As a consequence, switching losses now tend to
predominate, causing the junction temperatures to rise. Special techniques are employed to
obtain clean turnon and turnoff of the devices. This, along with optimal control strategies and
improved evacuation of the heat generated, permit utilisation of the devices with a minimum of
deration.
This chapter first examines the switching process, estimates the device dissipation and indicates
design procedures for the cooling system.
Turnoff Turnon
Turnoff Turnoff
Conduction Losses
Conduction losses are caused by the forward voltage drop when the power semiconductor is on
and can be described by (with reference to an IGBT)
WC = Vce (sat)(Ic).Ic
where Ic is the current carried by the device and Vce(sat)(Ic) is the current dependant forward
voltage drop. This drop may be expressed as
This relation defines the forward drop of an IGBT in a similar manner to a diode. A part of the
drop is constant while another part is collector current dependent.
The given data should be used as follows: Using the numerical value is the most simple way to
determine conduction losses. The numerical value can be applied if the current in the device is
equal or close to the specified current  data sheet numerical values are specified for typical
application currents.
The graph most accurately determines conduction losses. The conditions in which the data are
used should correspond to the application. To estimate if a power semiconductor rating is
appropriate, usually the values valid for elevated temperature, close to the maximum junction
temperature TJmax , should be used to calculate power losses because this is commonly the
operating point at nominal load.
WB = Vb(I).IL
Where IL is the leakage current and Vb(I) is the current dependemt blocking voltage. Data sheets
indicates leakage current at certain blocking voltage and temperature. The dependence between
leakage current and applied voltage typically is exponential; this means that using a data sheet
value given for a blocking voltage higher than applied overestimates blocking losses. However in
general, blocking losses are small and can often, but not always, be neglected.
Switching Losses
IGBTs are designed for use in switching converters and not for linear operation. This means
switching time intervals are short compared to the pulse duration at typical switching
frequencies, as can be seen from their switching times, such as rise time tr and fall time tf in the
data sheets. Switching losses occur during these switching intervals.
For IGBTs they are specified as an amount of energy, Eon/off for a certain switching operation.
Eon/off are the energy dissipated at turnon/turnoff respectively. Using the numerical value is
again the most simple way to determine switching losses. The numerical value can be applied if
the switching operations are carried out at the same or similar conditions as indicated in the data
sheet. Graphs for Eon(IC)/(RG ), Eoff (IC)/(RG) with collector current IC and gate resistance RG are
provided.
The graphs permit the most accurate determination of switching losses, given the parameters of
the converter: RG and converter current IC.
The offstate losses of the main device and the turnon dissipation may be neglected for most
cases. With an IGBT driven DCDC chopper as an example, the dissipation can be estimated as:
The values of Eon , Eoff , Err are at the rated values only and have to be adjusted to the working
values of voltage (DC bus), VCE (working) and load current, Ic.
Eon / Eoff / Err ( working ) = Eon / Eoff / Err ( working ) • ⎡⎣VCE ( working ) / VCE ( rated ) ⎤⎦
a/b/c
Eon / Eoff / Err ( working ) = Eon / Eoff / Err ⎡⎣ I C / I C ( rated ) ⎤⎦
Where, a, b and c are constants.
The power device in a converter mostly sees an inductive load. A simple circuit illustrating such
a situation is shown in Fig. 3.3. Corresponding ideal waveforms are also indicated. The free
wheeling diode FWD, across the load is essential for clamping the induced voltages across the
inductance when the device switches off. However, its presence causes the supply voltage, Vs to
appear across the transistor whenever it carries part of the inductor current in overlap mode with
the FWD during both turnon and turnoff modes. This causes the transistor switching dissipation
to increase.
An RCD Switchingaidnetwork connected across the device reduces turnoff dissipation, Fig.
3.2. The controlled rise of the collector voltage of the transistor aids this process. However, turn
off energy is accumulated in the SAN, which is ultimately dissipated in the resistor. The RCD
does not also help reduce turnon dissipation when the reverse recovery current of the diode and
the SAN current add up with the load current with Vs again appearing across the device.
Example 3.1
Derive the expression for the power dissipation during turnon and turnoff of a transistor
unassisted by a SAN. The supply voltage is Vm, peak load current Im, and tr, toff being the turn on
and turnoff times. Assume idealised waveforms.
Solution
The transition of the swichings in the VC  IC plane is rectangular. The energy dissipated in each
turnoff switching cycle is
t off 1
W = ∫ VT . I T dt = .V .I .t
T 0 2 M M f
If actual waveforms are considered the dissipation is close to about double the above figure.
Example 3.2
For a transistor carrying a collector current IM and having a turnoff time tf, find the details of a
RCD SAN to restrict the voltage rise at the end of tf to half the supply voltage. Calculate the
corresponding losses in the transistor and in the SAN.
Solution
The action of the SAN in restricting the rise of transistor voltage till the current in it is
extinguished is illustrated in Fig. 3.4.
Since the current is assumed to fall linearly during the period tf, the collector voltage rises as:
2 2
⎛ t ⎞ I .t ⎛ t ⎞
V = V0 ⎜ ⎟ = M f ⎜ ⎟
⎜t ⎟
⎝ f ⎠ 2C ⎜⎝ t f ⎟⎠
Where V0 is the voltage at the capacitor at the end of turnoff time tf.
Thus,
IM t f
V0 =
2C
⎛ t ⎞
i = I M ⎜1 − ⎟
⎜ t ⎟
⎝ f ⎠
The Transistor current can be written as:
The dissipation in the transistor is
2
tf tf I M2 .t f ⎛ t ⎞⎛ t ⎞ I M2 .t 2f 1
WT = ∫ v.idt = ∫ ⎜⎜1 − ⎟⎟ ⎜⎜ ⎟⎟ dt = . Watts
0 0 2C ⎝ t f ⎠⎝ tf ⎠ 2C 12
When the transistor switches off, the nearly constant load current linearly charges up the
capacitor till it reaches the supply voltage. Subsequently, The FWD is positively biased and there
t2 1
CV0 = ∫ i.dt = IMt f
t1 2
IM t f
C≥
Vs
The energy dissipated in the SAN resistor which is also the energy shifted to the SAN from the
transistor during turnoff is
1
PR =
CVM2 F
2
Where F is the switching frequency. The resistance should be able to limit the transistor current
to its peak rating. Thus,
Vs
R≥
I CM − I M − I rr
I M .t f
C≥
Vs − R.I M
In a SinePWM controlled converter with a peak value of the fundamental current equal to Icp,
the conduction losses in the IGBT would be
π ⎡2 2 ⎤
Wc = δ .T ∫ I cVce ( sat ) dθ = 12 δ .T ⎢ I cpVo + I cp2 .R ⎥
⎣ π
0
⎦
Where Vo and R are as shown in Fig 3.1. For the diode the dissipation is
WF =
1
[1 − δ ]. 2 2 I cpVod + I cp2 Rd
2 π
Hard switching and its consequences have been discussed above. Reduction of size and weight
of converter systems require higher operating frequencies, which would reduce sizes of inductors
and capacitors. However, stresses on devices are heavily influenced by the switching frequencies
accompanied by their switching losses. It is obvious that switchingaidnetworks do not mitigate
the dissipation issues to a great extent. Turnon snubbers though not discussed, are rarely used.
Even if used, it would not be able to prevent the energy stored in the junction capacitance to
discharge into the transistor at each turnon. Soft switching techniques use resonant techniques to
switch ON at zero voltage and to switch OFF at zero current. There are negligible switching
losses in the devices, though there is a significant rise in conduction losses. There is no transfer
of dissipation to the resonant network which is nondissipative. The two basic configurations are
as shown in Fig. 3.5.
A Zero Current Switch based converter is provided as illustration to the soft switching
mechanism. It is equivalent to the topology shown above. The input capacitor and the one across
the diode may be combined to arrive at this topology.
The ZCS converter is considered to be in stable operation with Load current Itrans flowing through
the diode and the inductor Lf. The Capacitor Cr is charged to Vs. On switching the transistor ON
the current in it ramps up from zero but the diode continues conduction till this current reaches
the load current Iout level. Subsequently, the load current and the resonating current flows
through the transistor. This current reaches a natural zero when the negative magnitude of the
resonating current equals the load current. The transistor thus switches in the Zero Current mode
for both turn on and turn off. The diode, on the other hand switches in the Zero Voltage mode
under both situations. It must be noted that the peak current stress on the transistor is high . The
peak voltage stress on the diode is also about twice the supply voltage. Both these stresses are
significantly higher than that in a comparable Hard switched buck converter. Consequently,
Qs#3 Are resonant converters superior to the hard switched converter on all counts?
Ans: No. The resonant converter reduces switching losses at the cost of higher voltage/current
stresses on the devices.
Instructional Objectives
On completion the student will be able to
• Classify the rectifiers based on their number of phases and the type of devices used.
• Define and calculate the characteristic parameters of the voltage and current waveforms.
• Analyze the operation of single phase uncontrolled half wave and full wave rectifiers
supplying resistive, inductive, capacitive and back emf type loads.
• Calculate the characteristic parameters of the input/output voltage/current waveforms
associated with single phase uncontrolled rectifiers.
• Waveforms and characteristic values (average, RMS etc) of the rectified voltage and
current.
• Influence of the load type on the rectified voltage and current.
• Harmonic content in the output.
• Voltage and current ratings of the power electronic devices used in the rectifier circuit.
• Reaction of the rectifier circuit upon the ac network, reactive power requirement, power
factor, harmonics etc.
• Rectifier control aspects (for controlled rectifiers only)
The first assumption will be relaxed in a latter module. However, unless specified otherwise, the
second assumption will remain in force.
Rectifiers are used in a large variety of configurations and a method of classifying them
into certain categories (based on common characteristics) will certainly help one to gain
significant insight into their operation. Unfortunately, no consensus exists among experts
regarding the criteria to be used for such classification. For the purpose of this lesson (and
subsequent lessons) the classification shown in Fig 9.1 will be followed.
9.2 Terminologies
Certain terms will be frequently used in this lesson and subsequent lessons while characterizing
different types of rectifiers. Such commonly used terms are defined in this section.
Let “f” be the instantaneous value of any voltage or current associated with a rectifier
circuit, then the following terms, characterizing the properties of “f”, can be defined.
Peak value of f ( f̂ ) : As the name suggests f̂ = f max over all time.
Average (DC) value of f(Fav) : Assuming f to be periodic over the time period T
1 T
Fav = ∫ f(t)dt ……………………………….(9.1)
T 0
RMS (effective) value of f(FRMS) : For f , periodic over the time period T,
1 T 2
T ∫0
FRMS = f (t)dt …………………………..(9.2)
( )
Peak to peak ripple of f f̂ pp : By definition
f̂ pp = f max  f min Over period T……………… …(9.5)
Fundamental component of f(F1): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency 1/T.
∴ F1 =
1 2
2
( 2
)
f A1 + f B1 ………………………....(9.6)
2 T
where f A1 = ∫ f ( t ) cos 2π t dt ……………………(9.7)
T 0 T
2 T
f B1 = ∫ f ( t ) sin 2π t dt …………………….(9.8)
T 0 T
Kth harmonic component of f(FK): It is the RMS value of the sinusoidal component in the
Fourier series expression of f with frequency K/T.
∴ FK =
2
(
1 2 2
)
f AK + f BK …………………………(9.9)
2 T
where f AK = ∫ f(t) cos2πK t T dt ………………...(9.10)
T 0
2 T
f BK = ∫ f(t) sin2πK t T dt …………………(9.11)
T 0
Power factor of a rectifier (PF): As for any other equipment, the definition of the power factor
of a rectifier is
Actual power input to the Rectifier
PF = ….(9.17)
Apparent power input to the Rectifier
if the per phase input voltage and current of a rectifier are vi and ii respectively then
V I cosφi
PF = i1 i1 ………………………………(9.18)
ViRMS IiRMS
Pulse number of a rectifier (p): Refers to the number of output voltage/current pulses in a
single time period of the input ac supply voltage. Mathematically, pulse number of a rectifier is
given by
Time period of the input supply voltage
p= .
Time period of the minium order harmonic in the output voltage/current.
Classification of rectifiers can also be done in terms of their pulse numbers. Pulse number of a
rectifier is always an integral multiple of the number of input supply phases.
Commutation in a rectifier: Refers to the process of transfer of current from one device (diode
or thyristor) to the other in a rectifier. The device from which the current is transferred is called
the “out going device” and the device to which the current is transferred is called the “incoming
device”. The incoming device turns on at the beginning of commutation while the out going
device turns off at the end of commutation.
Commutation failure: Refers to the situation where the out going device fails to turn off at the
end of commutation and continues to conduct current.
Firing angle of a rectifier (α): Used in connection with a controlled rectifier using thyristors. It
refers to the time interval from the instant a thyristor is forward biased to the instant when a gate
pulse is actually applied to it. This time interval is expressed in radians by multiplying it with
Extinction angle of a rectifier (γ): Also used in connection with a controlled rectifier. It refers
to the time interval from the instant when the current through an outgoing thyristor becomes zero
(and a negative voltage applied across it) to the instant when a positive voltage is reapplied. It is
expressed in radians by multiplying the time interval with the input supply frequency (ω) in
rad/sec. The extinction time (γ/ω) should be larger than the turn off time of the thyristor to avoid
commutation failure.
Overlap angle of a rectifier (μ): The commutation process in a practical rectifier is not
instantaneous. During the period of commutation, both the incoming and the outgoing devices
conduct current simultaneously. This period, expressed in radians, is called the overlap angle
“μ” of a rectifier. It is easily verified that α + μ + γ = π radian.
Exercise 9.1
i) In a rectifier, electrical power flows from the _________ side to the ________ side.
ii) Uncontrolled rectifiers employ _________ where as controlled rectifiers employ
________ in their circuits.
iii) For any waveform “Form factor” is always _______ than or equal to unity.
iv) The minimum frequency of the harmonic content in the Fourier series expression of
the output voltage of a rectifier is equal to its _________.
v) “THD” is the specification used to describe the quality of ___________ waveforms
where as “Ripple factor” serves the same purpose for _________ for waveforms.
vi) Input “power factor” of a rectifier is given by the product of the _________ factor
and the ________ factor.
vii) The sum of “firing angle”, “Extinction angle” and “overlap angle” of a controlled
rectifier is always equal to _________.
Answers: (i) ac, dc; (ii) diodes, thyristors; (iii) greater; (iv) pulse number; (v) ac, dc; (vi)
displacement, distortion; (vii) π
1 π 2 2 V
VDRMS =
2π 0∫ 2Vi sin ωtdωt = i ……………………...(9.25)
2
Because of such high ripple content in the output voltage and current this rectifier is
seldom used with a pure resistive load.
The ripple factor of output current can be reduced to same extent by connecting an
inductor in series with the load resistance as shown in Fig 9.3 (a). As in the previous case, the
diode D is forward biased when the switch S is turned on. at ωt = 0. However, due to the load
inductance i0 increases more slowly. Eventually at ωt = π, v0 becomes zero again. However, i0
is still positive at this point. Therefore, D continues to conduct beyond ωt = π while the negative
supply voltage is supported by the inductor till its current becomes zero at ωt = β. Beyond this
point, D becomes reverse biased. Both v0 and i0 remains zero till the beginning of the next cycle
where upon the same process repeats.
or V0AV =
2Vi 1 cosβ
π 2 (
………………………………………... (9.29))
1 β 2 2
2π ∫0 i
V0RMS = 2V sin ωtdωt
( )
2
Vi 1 V 2β  sin2β
= β  sin2β = i ……………………..(9.30)
2π 2 2 2π
ωL
where tanφ =
R
2 2 2
and Z = R + ω L ……………………………………………..(9.35)
The problem of poor form factor (ripple factor) of the output voltage can be solved to
some extent by connecting a capacitor across the load resistance of Fig 9.2 (a). This single phase
half wave rectifier supplying a capacitive load is shown in Fig 9.5 (a). Corresponding
waveforms are shown in Fig 9.5 (b).
If the capacitor was initially discharged the diode “D” is forward biased when the switch
S is turned on at ωt = 0. The output voltage follows the input voltage. The diode D carries both
the capacitor charging current and the load current. At ωt = β the sum of these two currents
becomes zero and tends to grow in the negative direction. At this point the diode becomes
2Vi
or ii = [ ωRCcosωt + sinωt ]
R
1
2Vi ( 2 2 2 2
)
= 1+ ω R C cos(ωt  θ) ……………………..(9.39)
R
1 1
where θ = tan
ωRC
Again for β ≤ ωt ≤ 2π + φ
dv v
ii = 0, C 0 + 0 = 0, v 0 ( ωt = β ) = 2Vi cosθ .
dt R
(ωtβ) tanθ
∴ v 0 = 2Vi cosθ e …………………………………..(9.41)
at ωt = 2π + φ, v0 = 2Vsinφ
i
π
(2π+φ θ) tanθ
2Vi sinϕ = 2Vi cosθ e 2
3π
( +φθ) tanθ
2
or sinφ = cosθ e
⎡ ( θ) tanθ ⎤ φ tanθ
3π
Exercise 9.2
i) The ripple factor of the output voltage and current waveforms of a single phase
uncontrolled half wave rectifier is ____________ than unity.
ii) With an inductive load, the ripple factor of the output __________ of the half wave
rectifier improves but that of the output __________ becomes poorer.
iii) In both single phase half wave and full wave rectifiers the form factor of the output
voltage approaches _________ with capacitive loads provided the capacitance is
________ enough.
iv) The PIV rating of the rectifier diode used in a single phase half wave rectifier
supplying a capacitive load is approximately ________ the __________ input supply
voltage.
v) The % THD of the input current of the rectifiers supplying capacitive loads is
__________.
Answers: (i) greater; (ii) current, voltage; (iii) unity, large; (iv) double, peak; (v) high.
ii dωt = i 2 (1+ ω R C )
1 β 2 V 1 92.035 2
∫ 2π ∫54.9o
2 2 2
RMS. Diode current = cos (ωt  θ)dωt
2π ϕ R
1 ⎡β ϕ 1 1 ⎤
= 7.432 ⎢ + sin2(β  θ)  sin2(ϕ  θ) ⎥ = 0.8564 Amps.
2π ⎣ 2 4 4 ⎦
dv v
ii2 = i c + i 0 = C 0 + 0 ………………………………………………(9.51)
dt R
2Vi
or ii2 =  [ ωRCcosωt + sinωt ]
R
1
2Vi ( ) 1
1+ ω R C cos ( π + θ  ωt ) where θ = tan
2 2 2 2 1
= ….(9.52)
R ωRC
π π π 1 1
at ωt = π + β, ii1 = 0 so β  θ = or β = θ + or β = + tan …………(9.53)
2 2 2 ωRC
Again for β ≤ ωt ≤ π + φ
dv v
ii1 = 0 ∴ C 0 + 0 = 0 v0 ( ωt = β ) = 2Vsinβ
i = 2Vi cosθ ……….(9.54)
dt R
( ωtβ ) tanθ
∴ v 0 = 2Vi cosθ e …………………………………………….(9.55)
at ωt = π + φ, v0 = 2sinφ
( π2 +θπφ)tanθ
2Vsinφ
i = 2Vi cosθ e
 ( π2 +φθ )tanθ
or sinφ = cosθ e
⎡ ( θ ) tanθ ⎤ φtanθ
π
It can be shown that for the same R and C, v̂0pp given by Equation (9.57) is smaller than that
given by Equation (9.43) for the half wave rectifier. The diode PIV ratings remain equal to
2 2Vi however.
i) The output voltage form factor of a single phase full wave rectifier is ___________.
ii) The output voltage of a single phase full wave rectifier supplying an inductive load is
___________ of the load parameters.
iii) The peak to peak output voltage ripple of a single phase split supply full wave
rectifier supplying a capacitive load is ___________ compared to an equivalent half
wave rectifier.
2. An unregulated dc power supply is built around a single phase split supply full wave rectifier
using the same input voltage and output capacitor found in the problem 2 of Exercise 9.2.
The load resistance is 50 Ω. Find out the average output voltage, the peak to peak ripple in
the output voltage and the RMS current ratings of the diodes.
These problems can be mitigated by using a single phase full bridge rectifier as shown in Fig 9.8
(a). This is one of the most popular rectifier configuration and are used widely for applications
requiring dc. power output from a few hundred watts to several kilo watts. Fig 9.8 (a) shows the
rectifier supplying an RLE type load which may represent a dc. motor or a storage battery.
These rectifiers are also very widely used with capacitive loads particularly as the front end of a
variable frequency voltage source inverter. However, in this section analysis of this rectifier
supplying an RLE load will be presented. Its operation with a capacitive load is very similar to
that of a split supply rectifier and is left as an exercise.
When the switch S is turned on at the positive going zero crossing of vi no current flows in the
circuit till vi crosses E at point A. Beyond this point, D1 & D2 are forward biased by vi and
current starts increasing through them till the point B. After point B, vi falls below E and io starts
decreasing. Now depending on the values of R, L & E one of the following situations may arise.
• io may become zero before the negative going zero crossing of vi at point C.
• io may continue to flow beyond C and become zero before the point D.
• io may still be non zero at point D.
It should be noted that if io >0 either D1D2 or D3D4 must conduct. Fig 9.4 (b) shows the
waveforms for the third situation.
If io >0 at point C the negative going input voltage reverse biases D1 & D2. Current io
commutates to D3 and D4 as shown in the associated “conduction Diagram” in Fig 9.8 (b). It
shows pictorially the conduction interval of different devices. The current io continues to
decrease up to the point D beyond which it again increases. It should be noted that in this mode
of conduction io always remain greater than zero. Consequently, this is called the continuous
conduction mode of operation of the rectifier. In the other two situations the mode of operation
will be discontinuous.
The steady state waveforms of the rectifier under continuous conduction mode is shown to the
right of the point ωt = 0 in Fig 9.4 (b).
1 π 2 2
∴ VoAV = ∫
π o
2Vi 2sin ωt d ωt =
π
Vi (9.60)
1 π
π ∫o i
VoRMS = 2V 2 sin 2 ωt d ωt = Vi (9.61)
Finding out the characterizing quantities for ii will be difficult owing to its complicated
waveform. Considerable, simplification is achieved (without significant loss of accuracy) by
replacing the actual io waveform by its average value IoAV = VoAV / R.
Fig 9.9 shows the approximate input current wave form and its fundamental component.
for 0 < ωt ≤ π
Ldi o
vi = 2Vi sin ωt = Ri o + +E (9.67)
dt
io ωt=0 = io ωt=π (steady state periodic boundary cond.)
If the parameters of the load (i.e, R, L &E) are such that the left hand side of equation 9.71 is less
than the right hand side conduction of the rectifier becomes discontinuous i.e, the load current
becomes zero for a part of the input cycle. Discontinuous conduction mode of operation of this
rectifier is discussed next.
1 1 ⎡ β
2Vi sin ωt + ∫ E d ωt ⎤
π+θ π+θ
VoAV =
π ∫
θ
vo d ωt = ∫
π ⎣ θ β ⎦
2Vi
OR VoAV = [ cos θ  cos β + ( π + θ  β ) sin θ ] (9.75)
π
∴ io =
2Vi
Z
⎡sin ϕ  θ e tanωtθϕ  sinθ 1 e ωtθ
⎢⎣ ( )
cosϕ
tanϕ
( )
+ sin ( ωt  ϕ ) ⎤⎥
⎦
(9.79)
sin ( β  ϕ ) = tanϕ
(9.80)
cosϕ ⎣⎢ ⎦⎥
Form which β can be solved.
Exercise 9.4
i) The average output voltage of a full wave bridge rectifier and a split supply full wave
rectifier are __________ provided the input voltages are ___________.
Answers: (i) equal, equal; (ii) double, half; (iii) inductive; (iv) continuous, independent.
2. A battery is to be charged using a full bridge single phase uncontrolled rectifier. On full
discharge the battery voltage is 10.2 V. and on full charge it is 12.7 volts. The battery
internal resistance is 0.1Ω. Find out the input voltage to the rectifier so that the battery
charging current under full charge condition is 10% of the charging current under fully
discharged condition. Assume continuous conduction under all charging condition and find
out the inductance to be connected in series with the battery for this condition.
Answer: Let the rectifier input voltage be Vi and the charging current under fully discharged
condition be I.
Then assuming continuous conduction
2 2Vi 2 2
 0.1I = 10.2 and V  0.01I = 12.7
π π i
∴ 0.09I = 2.5 V ∴ I = 27.78 Amps and Vi = 14.415 volts.
If conduction is continuous at full charge condition it will be continuous for all other
charging conditions.
For continuous conduction
2sinϕ θ tanϕ sinθ
e = sin(ϕ  θ) +
1 e
π tanϕ
cosϕ
E
From given data sinθ = = 0.623, θ = 38.535°
2Vi
From which φ = 86.5°
∴ tan ϕ = ωL = 16.35 or ωL = 1.635 ohms
R
∴ L = 5.2 mH.
References
[1] P.C. Sen, “Power Electronics”, Tata McGraw –Hill Publishing Company Limited. 1995
[2] Muhammad H. Rashid, “Power Electronics, circuits, Devices and applications” Prentice –
Hall of India Private Limited, Second Edition, 1994
Q2. The split supply of a single phase full wave rectifier is obtained from a single phase
transformer with a single primary and a center tapped secondary. The rectifier supplies a
purely resistive load. Assuming the transformer to be ideal find out the, displacement
factor, distortion factor and the power factor at the primary side of the transformer.
Q3. A single phase split supply full wave rectifier is designed to supply an inductive load.
The average load current is 20 A, and the ripple current is negligible. Can the same
rectifier be used with a capacitive load drawing the same 20 Amps average current?
Justify your answer.
Q4. A 200V, 15 Amps, 1500 rpm separately excited dc motor has an armature resistance of 1
Ω and inductance of 50 mH. The motor is supplied from a single phase full wave bridge
rectifier with input voltage of 230 V, 50 HZ. Neglecting all no load losses, find out the
no load speed of the machine. Also find out the torque and speed at the boundary
between continuous and discontinuous conduction.
Then for 0 ≤ ωt ≤ β
2Vi
` i0 = (1 cosωt)
ωL
i0 2Vi
= (1 cosβ) for π ≤ β ≤ 2π the only solution is β = 2π
ωt = β ωL
Answer 2
Figure shows the secondary voltage and current waveforms of the rectifier.
⎜N ⎟ R
⎝ S⎠
∴ At the input
Displacement factor = Distortion factor = Power factor = 1.0
However E will not exceed 2Vi , since once ia becomes zero when E = 2Vi there will be no
developed torque to accelerate the motor. Hence the motor speed and E will not increase any
further.
Thus at no load E = 2Vi = 325.27 volts .
Under the rated condition at 1500 rpm
Erated = 200 – 15 × 1.0 = 185 volts.
E N
Now =
E rated N rated
E 325.27
∴ N = N rated × = 1500× = 2637 rpm .
E rated 185
At the boundary between the continuous and discontinuous mode of conduction.
2sinφ θ tanφ sinθ
e = sin(φ  θ) +
1 e
π tanφ
cosφ
2sinφ
= [ cosϕ sin(φ  θ) + sinθ ] e
θ tanφ
or π tanφ
1 e
3
ωL 100π ×50×10
where tanφ = = = 15.708
R 1
cosφ = 0.0635 φ = 1.507 rad. and sin2φ = 0.1268
1 E o
from which θ = sin = 38.5 ∴ E = 202.48 V
2Vi
but E at 1500 RPM = 185 volts.
∴ Speed at the junction of continuous and discontinuous condition is
202.48
1500 × = 1642 RPM.
185
Instructional Objectives
On completion the student will be able to
Fig.10. 1(a) shows the circuit diagram of a single phase fully controlled halfwave rectifier
supplying a purely resistive load. At ωt = 0 when the input supply voltage becomes positive the
thyristor T becomes forward biased. However, unlike a diode, it does not turn ON till a gate
pulse is applied at ωt = α. During the period 0 < ωt ≤ α, the thyristor blocks the supply voltage
and the load voltage remains zero as shown in fig 10.1(b). Consequently, no load current flows
during this interval. As soon as a gate pulse is applied to the thyristor at ωt = α it turns ON. The
voltage across the thyristor collapses to almost zero and the full supply voltage appears across
the load. From this point onwards the load voltage follows the supply voltage. The load being
purely resistive the load current io is proportional to the load voltage. At ωt = π as the supply
voltage passes through the negative going zero crossing the load voltage and hence the load
current becomes zero and tries to reverse direction. In the process the thyristor undergoes reverse
recovery and starts blocking the negative supply voltage. Therefore, the load voltage and the load
current remains clamped at zero till the thyristor is fired again at ωt = 2π + α. The same process
repeats there after.
From the discussion above and Fig 10.1 (b) one can write
For α < ωt ≤ π
v 0 = vi = 2 Vi sinωt (10.1)
v0 V
i0 = = 2 i sinωt (10.2)
R R
1 2π 1 π
2π ∫0 2π ∫α
Therefore VOAV = v 0 dωt = 2 Vi sinωt dωt (10.3)
V
Or VOAV = i (1+ cosα) (10.4)
2π
1 2π 2
2π ∫0
VORMS = v0 dωt (10.5)
1 π 2 2
2π ∫α
= 2vi sin ωtdωt
Vi2 π
=
2π ∫α
(1 cos2ωt)dωt
Vi2 ⎡ sin2α ⎤
= ⎢⎣ π  α + 2 ⎥⎦
2π
1
V
= i ⎛⎜ 1 +
α sin2α ⎞ 2
⎟
2⎝ π 2π ⎠
1
π ⎛⎜ 1 +
α sin2α ⎞ 2
VORMS ⎟
= ⎝ π
∴ 2π ⎠ (10.6)
FFVO =
VOAV (1+ cosα)
Similar calculation can be done for i0. In particulars for pure resistive loads FFio = FFvo.
1 2π
2π ∫0
Therefore VOAV = v0 dωt (10.8)
1 β
2π ∫α
= 2 Vi sinωt dωt
1 β 2 2
2π ∫α
= 2vi sin ωt dωt
1
V β  α sin2α  sin2β ⎞ 2
= i ⎛⎜ + ⎟
2⎝ π 2π ⎠
V Vi
I OAV = OAV = (cosα  cosβ) (10.10)
R 2πR
Since the average voltage drop across the inductor is zero.
However, IORMS can not be obtained from VORMS directly. For that a closed from expression for i0
will be required. The value of β in terms of the circuit parameters can also be found from the
expression of i0.
For α ≤ ωt ≤ β
di
Rio + L o = v0 = 2Vi sinωt (10.11)
dt
The general solution of which is given by
(ωtα)
 2Vi
i 0 = I0 e tanϕ + sin(ωt  ϕ) (10.12)
Z
ωL
Where tanφ = and Z = R 2 + ω2 L2
R
i0 ωt =α
=0
2Vi
∴ 0 = I0 + sin(α  φ)
Z
2Vi ⎡ ( ωtα )
⎤
∴ i0 = 
(10.13)
Z ⎢
⎣ sin(φ  α)e tanφ
+ sin(ωt  φ) ⎥⎦
i0 = 0 otherwise.
Equation (10.13) can be used to find out IORMS. To find out β it is noted that
i0 ωt=β = 0
αβ
Exercise 10.1
Answers: (i) diodes, thyristors; (ii) firing angle; (iii) discontinuous (iv) poorer; (v) better.
Answer: Referring to Fig 10.2(b), the free wheeling diode will remain off till ωt = π since the
positive load voltage across the load will reverse bias the diode. However, beyond this point as
the load voltage tends to become negative the free wheeling diode comes into conduction. The
load voltage is clamped to zero there after. As a result
i) Average load voltage increases
ii) RMS load voltage reduces and hence the load voltage form factor reduces.
iii) Conduction angle of load current increases as does its average value. The load
current ripple factor reduces.
Fig 10.3 (a) shows the circuit diagram of a single phase fully controlled bridge converter. It is
one of the most popular converter circuits and is widely used in the speed control of separately
excited dc machines. Indeed, the R–L–E load shown in this figure may represent the electrical
equivalent circuit of a separately excited dc motor.
The single phase fully controlled bridge converter is obtained by replacing all the diode
of the corresponding uncontrolled converter by thyristors. Thyristors T1 and T2 are fired together
while T3 and T4 are fired 180º after T1 and T2. From the circuit diagram of Fig 10.3(a) it is clear
that for any load current to flow at least one thyristor from the top group (T1, T3) and one
thyristor from the bottom group (T2, T4) must conduct. It can also be argued that neither T1T3
nor T2T4 can conduct simultaneously. For example whenever T3 and T4 are in the forward
blocking state and a gate pulse is applied to them, they turn ON and at the same time a negative
voltage is applied across T1 and T2 commutating them immediately. Similar argument holds for
T1 and T2.
For the same reason T1T4 or T2T3 can not conduct simultaneously. Therefore, the only
possible conduction modes when the current i0 can flow are T1T2 and T3T4. Of coarse it is
possible that at a given moment none of the thyristors conduct. This situation will typically
occur when the load current becomes zero in between the firings of T1T2 and T3T4. Once the
load current becomes zero all thyristors remain off. In this mode the load current remains zero.
Consequently the converter is said to be operating in the discontinuous conduction mode.
Fig 10.3(b) shows the voltage across different devices and the dc output voltage during
each of these conduction modes. It is to be noted that whenever T1 and T2 conducts, the voltage
across T3 and T4 becomes –vi. Therefore T3 and T4 can be fired only when vi is negative i.e, over
the negative half cycle of the input supply voltage. Similarly T1 and T2 can be fired only over
the positive half cycle of the input supply. The voltage across the devices when none of the
thyristors conduct depends on the off state impedance of each device. The values listed in Fig
10.3 (b) assume identical devices.
Under normal operating condition of the converter the load current may or may not
remain zero over some interval of the input voltage cycle. If i0 is always greater than zero then
the converter is said to be operating in the continuous conduction mode. In this mode of
operation of the converter T1T2 and T3T4 conducts for alternate half cycle of the input supply.
Version 2 EE IIT, Kharagpur 10
However, in the discontinuous conduction mode none of the thyristors conduct over some
portion of the input cycle. The load current remains zero during that period.
It is assumed that at t = 0 T3T4 was conducting. As T1T2 are fired at ωt = α they turn on
commutating T3T4 immediately. T3T4 are again fired at ωt = π + α. Till this point T1T2
conducts. The period of conduction of different thyristors are pictorially depicted in the second
waveform (also called the conduction diagram) of Fig 10.4.
1 π+α 2 2
Where VOAV =
π ∫α
v 0 dωt =
π
Vi cosα (10.17)
In this interval
di0
L + Ri 0 + E = 2Vi sinωt (10.24)
dt
The general solution of which is given by
( )
 ωtα ⎡ 2Vi sinθ ⎤
tanφ
i 0 = Ie ⎢sin(ωt  φ)  cosφ ⎥
+
Z
(10.25)
⎣ ⎦
ωL
Where, Z = R 2 + ω2 L2 ; tanφ = ; E = 2Vi sinθ; R = Zcosφ
R
Now at steady state i 0 ωt=α = i0 ωt =π+α since i0 is periodic over the chosen interval. Using this
boundary condition we obtain
2Vi ⎡ 2sin(φ  α) e tanφ + sin(ωt  φ)  sinθ ⎤
( ωtα )
i0 = ⎢ π ⎥ (10.26)
Z ⎢  cosφ ⎥
⎣ 1 e tanφ ⎦
Therefore, the rectifier appears as a lagging power factor load to the input ac system. Larger the
‘α’ poorer is the power factor.
The input current ii also contain significant amount of harmonic current (3rd, 5th, etc) and
therefore appears as a harmonic source to the utility. Exact composition of the harmonic currents
can be obtained by Fourier series analysis of ii and is left as an exercise.
Exercise 10.2
i) A single phase fully controlled bridge converter can operate either in the _________ or
________ conduction mode.
ii) In the continuous conduction mode at least _________ thyristors conduct at all times.
iii) In the continuous conduction mode the output voltage waveform does not depend on the
________ parameters.
iv) The minimum frequency of the output voltage harmonic in a single phase fully controlled
bridge converter is _________ the input supply frequency.
v) The input displacement factor of a single phase fully controlled bridge converter in the
continuous conduction mode is equal to the cosine of the ________ angle.
Answer: (i) continuous, discontinuous; (ii) two; (iii) load; (iv) twice; (v) firing.
2. A single phase fully controlled bridge converter operates in the continuous conduction
mode from a 230V, 50HZ single phase supply with a firing angle α = 30°. The load
resistance and inductances are 10Ω and 50mH respectively. Find out the 6th harmonic
load current as a percentage of the average load current.
2sin(φ  α) sinθ
π
 sin(φ  α)  ≥0 (10.32)

tanφ
cosφ
1 e
π ∫α π ⎢⎣ ∫α
VOAV = v 0 dωt = 2Vi sinωt dωt +
2Vi
Or VOAV = [cosα  cosβ + sinθ(π + α  β)] (10.34)
π
V  E VOAV  2Vi sinθ
IOAV = OAV = (10.35)
R Zcosφ
2Vi
Or IOAV = [cosα  cosβ + sinθ(α  β)] (10.36)
π Zcosφ
It is observed that the performance of the converter is strongly affected by the value of β. The
value of β in terms of the load parameters (i.e, θ, φ and Z) and α can be found as follows.
In the interval α ≤ ωt ≤ β
di
L o + Rio + E = 2Vi sinωt (10.37)
dt
i 0 ωt =α = 0
From which the solution of i0 can be written as
2Vi ⎡ ( )
⎤
{ }
 ωtα sinθ ( )
i0 = tanφ  ωtα (10.38)
⎢ sin(φ  α)e  tanφ + sin(ωt  φ) ⎥
Z ⎣ cosφ 1 e ⎦
Now i0 ωt=β
=0
αβ
sinθ ⎡ αβ
⎤
∴ sin(φ  α)e tanφ
 tanφ + sin(β  φ) = 0 (10.39)
cosφ ⎣1 e ⎦
Given φ, α and θ, the value of β can be found by solving equation 10.39.
2 2
V0 = Vi cosα (10.40)
π
For α < π/2, Vd > 0. Since the thyristors conducts current only in one direction I0 > 0 always.
Therefore power flowing to the dc side P = V0I0 > 0 for α < π/2. However for α > π/2, V0 < 0.
Hence P < 0. This may be interpreted as the load side giving power back to the ac side and the
converter in this case operate as a line commutated current source inverter. So it may be
tempting to conclude that the same converter circuit may be operated as an inverter by just
increasing α beyond π/2. This might have been true had it been possible to maintain continuous
conduction for α < π/2 without making any modification to the converter or load connection. To
supply power, the load EMF source can be utilized. However the connection of this source in
Fig 10.3 is such that it can only absorb power but can not supply it. In fact, if an attempt is made
to supply power to the ac side (by making α > π/2) the energy stored in the load inductor will be
exhausted and the current will become discontinuous as shown in Fig 10.7 (a).
Fig 10.8 (a) and (b) below shows the waveforms of the inverter operating in continuous
conduction mode and discontinuous conduction mode respectively. Analysis of the converter
remains unaltered from the rectifier mode of operation provided θ is defined as shown.
i) In the discontinuous conduction mode the load current remains __________ for a
part of the input cycle.
ii) For the same firing angle the load voltage in the discontinuous conduction mode
is __________ compared to the continuous conduction mode of operation.
iii) The load current ripple factor in the continuous conduction mode is _______
compared to the discontinuous conduction mode.
Answers: (i) zero; (ii) higher; (iii) lower; (iv) dc, ac; (v) 90, inverter.
2. A 220 V, 20A, 1500 RPM separately excited dc motor has an armature resistance of
0.75Ω and inductance of 50mH. The motor is supplied from a 230V, 50Hz, single phase
supply through a fully controlled bridge converter. Find the no load speed of the motor
and the speed of the motor at the boundary between continuous and discontinuous modes
when α = 25°.
Answer: At no load the average motor torque and hence the average motor armature current is
zero. However, since a converter carries only unidirectional current, zero average armature
current implies that the armature current is zero at all time. From Fig 10.6(b) this situation can
occur only when θ = π/2, i.e the back emf is equal to the peak of the supply voltage. Therefore,
E b no load = 2 × 230 V = 325.27 V, Under rated condition E b 1500 = 205 V
325.27
∴ N no load = ×1500 = 2380 RPM
205
At the boundary between continuous and discontinuous conduction modes from equation 10.32
1+ e π/tanφ
sinθ = cosφsin(φ  α)
1 eπ/tanφ
From the given data φ = 87.27°, α = 25°
∴ sinθ = 0.5632
∴ E b = 2Vi sinθ = 183.18 Volts
183.18
∴ Motor speed N = ×1500 = 1340 RPM .
205
Summary
• Single phase fully controlled converters are obtained by replacing the diodes of an
uncontrolled converter with thyristors.
• In a fully controlled converter the output voltage can be controlled by controlling the
firing delay angle (α) of the thyristors.
• Single phase fully controlled half wave converters always operate in the discontinuous
conduction mode.
• Half wave controlled converters usually have poorer output voltage form factor compared
to uncontrolled converter.
• Single phase fully controlled bridge converters are extensively used for small dc motor
drives.
References
1) “Power Electronics” P.C.Sen; Tata McGrawHill 1995
Q2. A 220V, 20A 1500 RPM separately excited dc motor has an armature resistance of 0.75Ω
and inductance of 50 mH. The motor is supplied from a single phase fully controlled
converter operating from a 230 V, 50 Hz, single phase supply with a firing angle of α =
30°. At what speed the motor will supply full load torque. Will the conduction be
continuous under this condition?
Q3. The speed of the dc motor in question Q2 is controlled by varying the firing angle of the
converter while the load torque is maintained constant at the rated value. Find the
“power factor” of the converter as a function of the motor speed. Assume continuous
conduction and ripple free armature current.
Q4. Find the load torque at which the dc motor of Q2 will operate at 2000 RPM with the field
current and α remaining same.
Q5. A separately excited dc motor is being braked by a single phase fully controlled bridge
converter operating in the inverter mode as shown in Fig 10.7 (b). Explain what will
happen if a commutation failure occurs in any one of the thyristors.
Figure shows that it is indeed possible for the half wave converter to operate in the inverting
mode for some values of the firing angle. However, care should be taken such that i0 becomes
zero before vi exceeds E in the negative half cycle. Otherwise i0 will start increasing again and
the thyristor T will fail to commutate.
2. For the machine to deliver full load torque with rated field the armature current should be
20 Amps.
2 2 × 230
Assuming continuous conduction v 0 = cos30o = 179.33 volts.
π
For 20 Amps armature current to flow the back emf will be
Eb = Va – IaRa = 179.33 – 20 × 0.75 = 164.33 volts
E
∴ sinθ = b = 0.505 .
2Vi
3. To maintain constant load torque equal to the rated value the armature voltage should be
N
Va = ra I a rated + E b rated
N rated
N
= 0.75 × 20 + 205 × = 0.137 N + 15 V
1500
2000
4. At 2000 RPM, E b = × 205 = 273.33 volts
1500
Eb
∴ sinθ = = 0.84, φ = 87.266o , α = 30o
2Vi
From equation 10.32 it can be shown that the conduction will be discontinuous.
⎣ ⎦
or e.0477(α  β)
[17.61+ .8412]  sin ⎡⎣57.266 + ( α  β ) ⎤⎦ = 17.61
o
5. Referring to Fig 10.8 (a) let there be a commutation failure of T1 at ωt = α. In that case
the conduction mode will be T3 T2 instead of T1 T2 and v0 will be zero during that period.
As a result average value of V0 will be less negative and the average armature current
will increase. However the converter will continue to operate in the inverter mode and
the motor will be braked.
Instructional Objectives
On completion the student will be able to
Exercise 11.1
Answer: (i) thyristors, diodes; (ii) diodes, two; (iii) same, different; (iv) form factor; (v) power
factor.
Answer
In the first conduction diagram the diodes and the thyristors conduct for equal periods, since the
load current is constant. The ration of the thyristors to the diode RMS current ratings will be
unity for the circuit of Fig 11.1 (b).
From the second conduction diagram the thyristors conduct for π  α radians while the diodes
conduct for π + α radians. Since the load current is constant.
Thyristor RMS current rating 1− α / π
=
Diode RMS current rating 1+ α / π
in this case
From the discussion in the previous paragraph it can be concluded that the output voltage (hence
the output current) is periodic over half the input cycle. Hence
1 π 1 π 2Vi
Voav =
π ∫o
vo dωt = ∫ 2Vi sin ωt dωt =
π α π
(1+ cosα) (11.1)
V E 2Vi
Iov = oav = (1+ cosα  π sinθ) (11.2)
R πR
The Fourier series representation of the load current can be obtained from the load voltage by
applying superposition principle in the same way as in the case of a fully controlled converter.
In the period α ≤ ωt ≤ π
dio
L + Rio + E = 2Vi sin ωt (11.3)
dt
(ωtα)
 2Vi ⎡ sinθ ⎤
io = I1e tanφ + ⎢ sin(ωt  φ)  (11.4)
Z ⎣ cosφ ⎥⎦
E ωL
Where sinθ = ; Z = R2 + ω2 L2 ; tanφ =
2Vi R
2Vi ⎡ sinθ ⎤
io α = I1 + ⎢sin(α  φ)  cosφ ⎥ (11.5)
Z ⎣ ⎦
(π  α) 2Vi ⎡ sinθ ⎤
io = I1  + ⎢ sinφ  (11.6)
π
tanφ Z ⎣ cosφ ⎥⎦
In the period π ≤ ωt ≤ π + α
dio
L + Rio + E = 0 (11.7)
dt
Version 2 EE IIT, Kharagpur 9
2Vi sinθ ⎡  tanφ ⎤
(ωtπ) (ωtπ)

tanφ
io = io π e  ⎢1 e ⎥ (11.8)
Z cosφ ⎢⎣ ⎥⎦
2Vi ⎡ sinθ ⎤
(ωtα) (ωtπ)
 
∴ io = I1 e tanφ
+ ⎢sinφ e
tanφ
 ⎥ (11.9)
Z ⎣⎢ cosφ ⎦⎥

π
2Vi ⎡ 
α
sinθ ⎤
∴ io π+α
= I1e tanφ
+ ⎢sinφ e
tanφ
 ⎥ (11.10)
Z ⎣⎢ cosφ ⎦⎥
⎧ 
(ωtα)
⎫
2Vi ⎪ ⎡ 
α
tanφ
⎤ e tanφ sinθ ⎪
io = ⎨ ⎢sin(φ  α) + sinφe ⎥ π
+ sin(ωt  φ)  ⎬ (11.12)
Z ⎪ ⎣⎢ ⎦⎥ 1 e tanφ
 cosφ ⎪
⎩ ⎭
For π ≤ ωt ≤ π + α
⎧ 
(ωtα)
⎫
2Vi ⎪ ⎡ 
α
tanφ
⎤ e tanφ 
(ωtπ)
tanφ sinθ ⎪
io = ⎨ ⎢sin(φ  α) + sinφe ⎥ π
+ sinφ e  ⎬ (11.13)
Z ⎪ ⎣⎢ ⎦⎥ 1 e tanφ
 cosφ ⎪
⎩ ⎭
ii = i0 for α ≤ ωt ≤ π
ii =  i0 for π + α ≤ ωt ≤ 2π
ii = 0 otherwise (11.14)
However, it will be very difficult to find out the characteristic parameters of ii using equation
11.14 since the expression of i0 is considerably complex. Considerable simplification can
however be obtained if the actual ii waveform is replaced by a quasisquare wave current
waveform with an amplitude of Ioav as shown in Fig 11.5.
2Vi
∴ Vi Ii1 cos α = Vo I oav = (1+ cosα)I OAV (11.17)
2 π
2 2
∴ Ii1 = IOAV cos α (11.18)
π 2
Ii1 2
∴ Distortion factor = =2 cos α (11.19)
IiRMS π(π  α) 2
Exercise 11.2
i. In a half controlled converter the output voltage can not become ___________________
and hence it can not operate in the ___________________ mode.
ii. For the same firing angle and input voltage the half controlled converter gives
___________________ output voltage form factor compared to a fully controlled
converter.
iii. For ripplefree continuous output current the input current displacement factor of a half
controlled converter is given by ___________________.
iv. For the same supply and load parameters the output current form factor of a half
controlled converter is ___________________ compared to a fully controlled converter.
Answer:
1
N NO load α 1 or φf α
φf N NO load
In order to increase Nno load by 30% φf should be reduced by 23%. Therefore the applied field
voltage must by 23%.
Now by (11.1)
1 + cos α
Vf ( α ) = Vf ( α = 0 )
2
1 + cos α 1 − cos α
∴ 1− = = 0.23
2 2
∴ α = 57.4o
io ωt
=α≥0 (11.21)
α

tanφ
sin(φ  α) + sinφ e sinθ
π
 sin(φ  α) ≥

tanφ
cosφ
1 e
If the condition in Eq. 11.22 is violated the conduction will become discontinuous. Clearly, two
possibilities exist. In the first case the load current becomes zero before ωt = π. In the second
case io continuous beyond ωt = π but becomes zero before ωt = π + α. In both cases however, io
starts from zero at ωt = α.
Fig. 11.6 shows the wave forms in these two cases.
Of these two cases the second one will be analyzed in detail here. The analysis of the first case
is left as an exercise.
π ⎢
⎣ α β ⎦⎥
2Vi
= [1+ cosα + (π + α  β)sinθ ] (11.24)
π
VOAV  E 2Vi
IOAV = = [1+ cosα + (α  β)sinθ] (11.25)
R π Z cosφ
1 π+α 2
π ∫α
VORMS = vo dωt
1
1 π
= ⎡ ∫ 2vi2 sin 2 ωt dωt + ∫ 2vi2 sin 2θ dωt ⎤
π+α 2
π ⎢
⎣ α β ⎥
⎦
1
2Vi ⎡ π  α 1 ⎤2
= ⎢ + (π + α  β) sin 2θ + sin 2α ⎥ (11.26)
π ⎣ 2 4 ⎦
However IORMS cannot be computed directly from VORMS. For this the closed form expression for
io has to be obtained. This will also help to find out an expression for the conduction angle β.
For α ≤ ωt ≤ π
di o
2Vi sin ωt = Ri o + L +E (11.27)
dt
(ωtα)
 2Vi
tanφ 2Vi sinθ
io = Io e +
sin(ωt  φ)  (11.28)
Z Z cosφ
Where Z = R 2 + ω2 L2 ; tanφ = ωL ; E = 2Vi sinθ
R
At ωt = α, io = 0
2Vi ⎡ sinθ ⎤
∴ Io = ⎢ + sin(φ  α) ⎥ (11.29)
Z ⎣ cosφ ⎦
2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪
ωtα
⎤  tanφ
∴ io = ⎨ + sin(φ  α) e + sin(ωt  φ)  ⎬ (11.30)
Z ⎪⎩ ⎢⎣ cosφ ⎥
⎦ cosφ ⎪⎭
For π ≤ ωt ≤ β
di o
O = Ri o + L +E (11.32)
dt
2Vi ⎧⎪ ⎡ sinθ ⎪⎫
απ
⎤ tanφ
∴ I1 = ⎨ + sin(φ  α) e + sinφ ⎬ (11.35)
Z ⎪⎩ ⎢⎣ cosφ ⎥
⎦ ⎪⎭
2Vi ⎧⎪ ⎡ sinθ sinθ ⎫⎪
ωtα ωtπ
⎤  tanφ 
∴ io = ⎨⎢ + sin(φ  α) ⎥ e + sinφe tanφ  ⎬ (11.36)
Z ⎩⎪ ⎣ cosφ ⎦ cosφ ⎭⎪
Equations (11.30) and (11.36) gives closed from expression of io in this conduction mode. To
find out β we note that at ωt = β, io = 0. So from equation (11.36)
αβ πβ
⎡ sinθ ⎤ tanφ sinθ
⎢ cosφ + sin(φ  α) ⎥ e + sinφ e tanφ  =0 (11.37)
⎣ ⎦ cosφ
β π α α
sinθ tanφ sinθ tanφ
or e = sinφ e tanφ + sin(φ  α) e tanφ + e (11.38)
cosφ cosφ
Given the values of ϕ, θ and α the value of β can be obtained from equation 11.38.
i. At the boundary between continuous and discontinuous conduction the value of the
output current at ωt = α is ___________________.
ii. The output voltage and current waveform of a single phase fully controlled and half
controlled converter will be same provided the extinction angle β is less than
___________________.
iii. For the same value of the firing angle the average output voltage of a single phase half
controlled converter is ___________________ in the discontinuous conduction mode
compared to the continuous conduction mode.
iv. Single phase half controlled converters are most suitable for loads requiring
___________________ voltage and current.
2. A single phase half controlled converter charges a 48v 50Ah battery from a 50v, 50Hz single
phase supply through a 50mH line inductor. The battery has on interval resistance of 0.1Ω. The
Version 2 EE IIT, Kharagpur 15
firing angle of the converter is adjusted such that the battery is charged at C/5 rate when it is
fully discharged at 42 volts. Find out whether the conduction will be continuous or discontinuous
at this condition. Up to what battery voltage will the conduction remain continuous? If the
charging current of the battery is to become zero when it is fully charged at 52 volts what should
be the value of the firing angle.
Answer: From the given data assuming continuous conduction the output voltage of the
converter to charge the battery at C/5 (10 Amps) rate will be
Vo = E + Ib rb = 42 + 0.1×10 = 43volts
∴ α = 24.43o
ωL
φ = tan −1 = 89.63o , tan φ = 157.08, sin φ = 0.99998 cos φ = 6.3 × 10−3
R
Putting these values in equation (11.22) one finds that the conduction will be continuous.
1 −α
cos φ sin ( φ − α ) e
− π tan φ tan φ
+ sin 2φ e
E 2
sin θ = = −π
2vi 1− e
tan φ
E = 2 × 50 × 0.606 = 42.8V
2Vi sin α = E = 52
sin 52
∴ α = 180o − = 132.66o
2 × 50
References
[1] “Power Electronics”; P.C. Sen; Tata McGraw Hill Publishing Company Limited 1995.
[2] “Power Electronics, circuits, devices and applications”; Second Edition; Muhammad H.
Rashid; Prentice – Hall of India; 1994.
[3] “Power Electronics, converters, applications and design”; Third Edition; Mohan,
Undeland, Robbins; John Wiley and Sons Inc., 2003.
Q2. A single phase half controlled converter is used to boost the no load speed of a
separately excited dc machine by weakening its field supply. At α = 0° the half
controlled converter produces the rated field voltage. If the field inductance is large enough
to make the field current almost ripple face what will be the input power factor when the dc
motor no load speed is bossed to 150%?
Q3. A single phase half controlled converter supplies a 220V, 1500rpm, 20A dc motor from a
230V 50HZ single phase supply. The motor has a armature resistance of 1.0Ω and
inductance of 50mH. What will be the operating modes and torques for α = 30°; and
speed of 1400 RPM.
Figure above explains the operation of the circuit following the fault. T1 is tired at ωt = α and the
load current commutates from T3 to T1. The conduction periods T1 D2 & T1 D4 commences as
usual. However at ωt = π + α when T3 is fired it fails to turn ON and as a consequences T1 does
not commutate. Now if the load is highly inductive T1 D4 will continue to conduct till ωt = 2π
and the load voltage will be clamped to zero during this period.
However, since T1 does not stop conduction fining angle control on it is lost after words. Hence
T1 D2 conduction period starts right after ωt = 2π instead of at ωt = 2π + α. Thus the full positive
half cycle of supply voltage is applied across the load followed by a entire half cycle of zero
voltage. Thus the load voltage becomes a half wave rectified sine wave and voltage control
through fining angle is last. This is the effect of the fault.
[Note: This phenomenon is known as “half cycle brusting”. It can be easily verified that this
possibility does not existion the circuit shown in Fig 11.1 (c)]
1 1
ωNO load α α
φf Vf
Vf rated
∴ Vf = for boosting no load speed by 150%
1.5
Vf 1 + cos α 1
but = =
Vf rated 2 1.5
∴ α = 70.53o
∴ Va = 193.2V, E = 186.7V
V −E
∴ Ia = a = 6.53A
ra
6.53
∴ Motor torque will be ×100 = 32.67% of full load torque.
20
Instructional Objectives
On completion the student will be able to
• Draw the conduction table and waveforms of a three phase half wave uncontrolled
converter supplying resistive and resistive inductive loads.
• Calculate the average and RMS values of the input / output current and voltage
waveforms of a three phase uncontrolled half wave converter.
• Analyze the operation of a three phase full wave uncontrolled converter to find out the
input / output current and voltage waveforms along with their RMS and Average values.
• Find out the harmonic components in the input / output voltage and current waveforms of
a three phase uncontrolled full wave converter.
• Analyze the operation of a three phase full wave uncontrolled converter supplying a
Capacitive – Resistive load.
Many of these disadvantages are mitigated to a large extent by using three phase ac – dc
converters. In a way it is also natural that bulk loads are supplied by three phase converters since
bulk electrical power is always transmitted and distributed in three phases and high power should
load three phases symmetrically. Polyphase rectifiers produce less ripple output voltage and
current compared to single phase rectifiers. The efficiency of polyphase rectifier is also higher
while the associated equipments are smaller.
A three phase supply gives the choice of a number of circuits. These can be placed in one of two
groups according to whether three or six diodes are used. These topologies will be analyzed in
detail in this section.
Fig. 12.1 (b) shows the conduction table of the converter. It should be noted that for the
type of load chosen the converter always operates in the continuous conduction mode. The
conduction diagram for the diodes (as shown in Fig. 12.1 (c) second waveform) can be drawn
easily from the conduction diagram. Since the diodes can block only negative voltage it follows
from the conduction table that a phase diode conducts only when that phase voltage is maximum
The phase current waveforms of Fig. 12.1 (c) deserve special mention. All of them have a
dc component which flows through the ac source. This may cause “dc saturation” in the ac side
transformer. This is one reason for which the converter configuration is not preferred very much
in practice.
3 5π/6
2π ∫π/6
VOAV = 2Vi sin ωt d(ωt)
3 6
= Vi (12.1)
2π
1
⎡ 3 5π/6 ⎤2
VORMS = ⎢ ∫ 2Vi2 sin 2 ωt d(ωt) ⎥
⎣ 2π π/6 ⎦
1
⎡ 3 3 ⎤2
= ⎢1 + ⎥ Vi (12.2)
⎣ 4π ⎦
VORMS
∴ The output voltage form factor = = 1.01 (12.3)
VOAV
VOAV
IO av = ,
R
IO
Ii RMS = I a RMS = I b RMS = I c RMS = (12.4)
3
3 6
VO av IO Vi IO
3
∴ Input power factor = AV
= 2π = (12.5)
3Vi Ii RMS IO 2π
3Vi
3
The harmonics present in vo and ii can be found by Fourier series analysis of the
corresponding waveforms of Fig. 12.1 (c) and is left as an exercise.
Exercise 12.1
Fill in the blank(s) with the appropriate word(s).
Answers: (i) three; (ii) three, four; (iii) 2π/3; (iv) three; (v) dc.
2. Assuming ripple free output current, find out the, displacement factor, distortion factor
and power factor of a three phase half wave rectifier supplying an R – L load.
With reference to Fig 12.1 the expression for phase current ia can be written as
π 5π
i a = Id ≤ ωt ≤
6 6
ia = 0 otherwise.
i a1 = 2 Ia1 sin(ωt + φ)
A1
where 2 Ia1 = A12 + B12 and φ = tan 1
B1
1 2π
π ∫0
A1 = i a cosωt dωt
1 2π
B1 = ∫ i a sinωt dωt
π 0
5π
1
∴ A1 = ∫π6 Id cosωt dωt = 0
π 6
5π
1 6 3
B1 = ∫
π 6
π I d sinωt dωt =
π
Id
3 3 Id
∴ 2I a1 = B1 = Id ∴ Ia1 =
π 2 π
φ = 0 ∴ Displacement factor = cosφ = 1.
Id
R.M.S value of ia = Ia =
3
Ia1 3
∴ Distortion factor = =
Ia 2π
3
Power Factor = Disp. Factor × Dist. Factor =
2π
It will also be assumed in the following analysis that the load side inductance is large enough to
keep the load current continuous. The relevant condition for continuous conduction will be
derived but analysis of discontinuous conduction mode will not be attempted. Compared to
single phase converters the cases of discontinuous conduction in 3 phase bridge converter are
negligible.
Fig. 12.2 (b) shows voltages across different diodes and the output voltage in each of
these conduction modes. The time interval during which a particular conduction mode will be
effective can be ascertained from this table. For example the D1D2 conduction mode will occur
when the voltage across all other diodes (i.e. vba, vca and vcb) are negative. This implies that
D1D2 conducts in the interval 0 ≤ ωt ≤ π/3 as shown in Fig. 12.2 (c). The diodes have been
numbered such that the conduction sequence is D1 → D2 → D3 → D4 → D5 → D6 → D1.
When a diode stops conduction its current is commutated to another diode in the same group (top
or bottom). This way the sequence of conduction modes become, D1D2 → D2D3 → D3D4 →
D4D5 → D5D6 → D6D1 → D1D2 . The conduction diagram in Fig. 12.2 (c) is constructed
accordingly.
The output dc voltage can be constructed from this conduction diagram using appropriate
line voltage segments as specified in the conduction table.
The input ac line currents can be constructed from the conduction diagram and the output
current. For example
ia = io for 0 ≤ ωt ≤ π/3 and 5π/3 ≤ ωt ≤ 2π
ia =  io for 2π/3 ≤ ωt ≤ 4π/3
ia = 0 otherwise. (12.6)
The line current wave forms and their fundamental components are shown in Fig. 12.2 (c).
It is clear from Fig 12.2 (c) that the dc voltage output is periodic over one sixth of the input ac
cycle.
3 2π/3 3 2
VOAV =
π ∫π/3
2VL sin ωt dωt =
π
VL (12.8)
3 2π/3 2
VORMS =
π ∫π/3
2VL sin 2 ωt dωt
⎛ 3 3⎞
= ⎜⎜ 1 + ⎟VL (12.9)
⎝ 2π ⎟⎠
2 VOAV − E
Ii RMS = IOAV ; IOAV = (12.10)
3 R
VOAV 6
∴ Ii1 = IOAV = IOAV (12.12)
3VL π
3 Ii1
∴ Power factor = distortion factor = = (12.13)
Ii RMS π
A closed form expression for io can be found as follows
ωt  π/3

tanφ 2VL ⎡ sinθ ⎤
io = I1e + ⎢ sin(ωt  φ)  (12.15)
Z ⎣ cosφ ⎥⎦
ωL E
Where tanφ = ; sinθ = ; Z = R 2 + ω2 L2
R 2VL
Now since the current waveform is periodic over one sixth of the input ac cycle
⎛ π⎞ ⎛ 2π ⎞
i o ⎜ ωt = ⎟ = i o ⎜ ωt = ⎟ (12.16)
⎝ 3⎠ ⎝ 3 ⎠
π
2VL ⎡ ⎛ π ⎞ sinθ ⎤  2VL ⎡ ⎛ 2π ⎞ sinθ ⎤
∴ I1 + sin  φ  =
⎢ ⎜ 3 ⎟ cosφ ⎥ 1 I e 3tanφ
+ sin ⎜  φ ⎟  (12.17)
Z ⎣ ⎝ ⎠ ⎦ Z ⎢⎣ ⎝ 3 ⎥
⎠ cosφ ⎦
2VL sinφ
∴ I1 = π
(12.18)
Z 
3tanφ
1 e
⎡ ωt  π/3 ⎤
2VL ⎢ sinφ  3tanφ sinθ ⎥
∴ io = e + sin ( ωt  φ )  (12.19)
Z ⎢  3tanφ
π
cosφ ⎥
⎣1 e ⎦
Exercise 12.2
Answers: (i) six; (ii) neutral; (iii) 2π/3; (iv) six; (v) odd, tripler, dc; (vi) continuous.
2. A 220 V, 1500 rpm 20 A separately excited dc motor has armature resistance of 1Ω and
negligible armature inductance. The motor is supplied from a three phase full wave
uncontrolled rectifier connected to a 220 V, 3 phase, 50 Hz supply through a Δ/Y
transformer. Find out the transformer turns ratio so that the converter applies rated
voltage to the motor. What is the maximum torque as a percentage of the rated torque the
motor will be able to supply without over heating. Assume ideal transformer and
continuous conduction.
3 2
V0 = VL = 220V
π
∴ VL = 163 Volts. This is the line voltage of the secondary side of the transformer.
The secondary is star connected. So
163
Secondary phase voltage = = 94 volts .
3
Primary side is delta connected. So
Primary phase voltage = 220 V.
220
∴ The required turns ratio = = 2.34 :1
94
V0  E α v hn
∴ i0 = +∑
r n =1 r
2 V2 2
V0RMS
= I 0AV  0AV +
r2 r2
17.743
∴ Maximum allowable torque = ×100 = 88.715 % of full load torque.
20
dvo
∴ ic = c = 2VL ωc cos ωt (12.21)
dt
v V
i o = o = 2 L sin ωt (12.22)
R R
VL
∴ ii = i o + i c = 2 [ ωRC cos ωt + sin ωt ]
R
V
= 2 L 1+ ω2 R 2 C2 cos (ωt  φ) (12.23)
R
1
Where tanφ =
ωRC
At ωt = β, ii = 0
π
∴ cos (β  φ) = 0 or β = +φ (12.24)
2
in the interval
β ≤ ωt ≤ α + π/3
dvo v o
c + =0
dt R
ωRC
v o β = 2VL sinβ = 2VL cosφ = 2VL (12.25)
1+ ω 2 R 2 C 2
(ωt  β) (ωt  β)
 ωRC 
∴ vo = vo β e ωRC
= 2VL e ωRC
(12.26)
1+ ω2 R 2 C 2
at ωt = α + π/3
π/6  α + φ
ωRC
v o = 2VL e ωRC
(12.27)
1+ ω2 R 2 C 2
Also at ωt = α + π/3
⎛ π⎞
v o = 2VL sin ⎜ ωt  ⎟
⎝ 3 ⎠ ωt = α + π
3
= 2VL sin α
From which the value of α can be found. Equation 12.23 gives the expression of the
output current ii of the rectifier.
Exercise 12.3
i) A three phase full wave uncontrolled rectifier supplying a capacitive load can operate in
the _________ conduction mode.
ii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very low.
iii) The output _________ ripple factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very high.
iv) The input current displacement factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is ___________.
v) The input current distortion factor of a three phase full wave uncontrolled rectifier
supplying a capacitive load is very ________.
Answers: (i) discontinuous; (ii) voltage; (iii) current; (iv) unity; (v) high.
2. A three phase full wave rectifier operates from 220 volts, three phase 50 Hz supply and
supplies a capacitive resistive load of 20 Amps. An inductor of negligible resistance is
inserted between the rectifier and the capacitor. Assuming the capacitor to be large
enough so that the output voltage is almost ripple free. Calculate the value of the
inductor so that the rectifier output current is continuous.
Answers: The following figure shows the circuit arrangement and the corresponding waveforms.
π 2π
In the interval ≤ ωt ≤
3 3
di
v0 + L L = 2VL sinωt
dt
3 2
Since v0 is almost ripple free v0 = V0 = VL
π
3 2 di
∴ VL + ωL L = 2VL sinωt
π dωt
2VL 3 2
i L = I0  cosωt  VL ωt
ωL πωL
Now i L av = 20A
References
[1] “Power Electronics”, P.C. Sen; Tata MC Grawhill publishing company limited; 1995.
[2] “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robbins;
John Willey and Sons Ine, Third Edition, 2003.
Lesson Summary
• Three phase uncontrolled rectifiers are available in half wave and full wave
configuration.
• Three phase uncontrolled half wave rectifier require three phase four wire power supply.
• The input ac line current in a three phase uncontrolled half wave rectifier contain dc
component which may cause “dc saturation” of input transformer.
• Three phase full wave uncontrolled rectifier is most widely used in the medium power
applications particularly as the input stage of the dc link inverter.
• Three phase full wave uncontrolled rectifier uses six diodes instead of three of the half
wave rectifier.
• Full bridge rectifier does not require neutral connection.
• The output voltage of a three phase full bridge rectifier contains multiplies of 6th
harmonic of input cycle.
• The input ac current of a three phase full bridge rectifier contain only odd harmonics but
no dc component or triplen harmonics.
• The input displacement factor of the three phase bridge rectifier is always unity.
• Three phase full bridge converter supplying an R – L – E load usually operate in the
continuous conduction mode.
• Compared to single phase rectifiers, three phase bridge converter require smaller inductor
to obtain the same output current ripple factor.
Q2. A three phase full wave rectifier operates from a three phase 220 V 50 Hz supply through
a three phase Δ/Y transformer and supplies a 200 V 1500 R.P.M, 50 Amps separately
excited dc motor. Find out the turns ratio of the transformer so that the motor operates at
rated speed at full load. If the motor armature resistance is 0.5 Ω find out the inductance
to be connected in series with the motor such that the rectifier operates in the continuous
conduction mode at 50 % of the full load torque.
Q3. A three phase full wave rectifier supplies a resistive capacitive load of 50 Amps from a
220 V. 3 phase 50 Hz supply. Find out the value of the load capacitance such that the
load voltage ripple is less than 5 %.
2
2 V0AV
PL = I 0AV R LOAD =
R LOAD
3 2VL 3 2 × 220
Now V0AV = = = 148.55 volts
2π 2π
2 2
V0AV ⎛ 148.55 ⎞
∴ PL = =⎜ ⎟ ×1 KW = 551.7 watts
R LOAD ⎝ 200 ⎠
1 3
Now from Equ. (12.2) V0RMS = + VL = 151.01 volts
3 4π
2. To run at rated speed at full load the motor terminal voltage must be 200 volts.
3 2
∴ V0AL = VL = 200 volts, ∴ VL = 148.1 volts
π
Where VL is the secondary line voltage. Secondary is star connected. So secondary
phase voltage
VL
V2 = = 85.5 volts
3
At 50% of full load torque the motor operates in the continuous conduction mode,
with reference to Fig. 12.2 and equation 12.19.
⎡ ωtπ/3 ⎤
2VL ⎢ sinφ  tanφ sinθ ⎥
i0 = e + sin(ωt  φ) 
z ⎢ 
π
cosφ ⎥
⎣1 e 3tanφ
⎦
E 187.5
Where sinθ = = = 0.9375
2VL 200
θ = 69.64º = 1.2154 rad.
i 0 Min = i 0 ωt = θ = 0
( θπ/3)
sinφ  sinθ
∴ π
e tanφ
+ sin(θ  φ)  =0

3tanφ
cosφ
1 e
( π/3  θ )
1 sin2φe tanφ 1 1
OR π
+ sinθ  sin(θ  2φ) = sinθ
2  2 2
1 e 3tanφ
V0Max + V0Min
V0AV =
2
V̂0pp = V0Max  V0Min
2 ( V0Max + V0Min ) V̂0pp
∴ = = 0.05
V0Max + V0Min V0AV
1 V0Min /V0Max
∴ = 0.025
1+ V0Min /V0Max
∴ V0Min /V0Max = 0.9512 .
1
where tanφ =
ωRC
from which φ = 3.5º ∴ tanφ = 0.06116
1
∴ ωRC = = 16.35 , R = 6.0694 Ω
tanφ
∴ ωC = 2.6938, ∴ C = 8575 μF.
• Draw the circuit diagram and waveforms associated with a three phase fully controlled
bridge converter.
• Find out the average, RMS valves and the harmonic spectrum of the output voltage /
current waveforms of the converter.
• Find out the closed form expression of the output current and hence the condition for
continuous conduction.
• Find out the displacement factor, distortion factor and the power factor of the input
current as well as its harmonic spectrum.
• Analyze the operation of higher pulse number converters and dual converter.
• Design the triggering circuit of the three phase fully controlled bridge converter.
i) The three phase fully controlled bridge converter is obtained by replacing six
_________ of an uncontrolled converter by six __________.
iii) In a three phase fully controlled converter each device conducts for an interval of
__________ degrees.
iv) In a three phase fully controlled converter operating in continuous conduction there
are ________ different conduction modes.
v) The output voltage of a three phase fully controlled converter operating in the
continuous conduction mode consists of segments of the input ac ________ voltage.
vi) The peak voltage appearing across any device of a three phase fully controlled
converter is equal to the ________ input ac ________ voltage.
vii) The input ac current of a three phase fully controlled converter has a ________ step
waveform.
viii) The input ac current of a three phase fully controlled converter contains only
_________ harmonics but no _________ harmonic.
ix) A three phase fully controlled converter can also operate in the _________ mode.
Answers: (i) diodes, thyristors; (ii) six; (iii) 120; (iv) six; (v) line; (vi) peak, line; (vii) six; (viii)
odd, tripler; (ix) inverting; (x) rare.
α α
v0 = V0 + ∑V
K=1,2
AK cos 6 Kωt + ∑V
K=1,2
BK sin 6 Kωt (13.1)
3 α+ π3 3 2 α+
π
⎛ π⎞
V0 = ∫
π α
v 0 dωt =
π
VL ∫α
3
sin ⎜ ωt + ⎟ dωt
⎝ 3⎠
3 2
= VL cosα (13.2)
π
6 α+ π3
VAK = ∫ v0 cos6 Kωt dωt
π α
6 α+ π ⎛ π⎞
= ∫ 3 2 VLsin ⎜ ωt + ⎟ cos6 ωt dωt
π α ⎝ 3⎠
3 2 ⎡ cos(6K +1)α cos(6K 1)α ⎤
= VL ⎢  (13.3)
π ⎣ 6K +1 6K 1 ⎥⎦
6 α+ π3 ⎛ π⎞
= ∫ 2 VLsin ⎜ ωt + ⎟ sin6 ωt dωt
π α
⎝ 3⎠
3 2 ⎡ sin(6K +1)α sin(6K 1)α ⎤
= VL ⎢  (13.4)
π ⎣ 6K +1 6K 1 ⎥⎦
1
3 α+
π
⎡ 3 3 ⎤2
π ∫α
V0RMS = 3
v02 dωt = VL ⎢1+ cos2α ⎥
⎣ 4π ⎦
π
ia = i0 α ≤ ωt ≤ α +
3
2π 4π
ia =  i0 α+ ≤ ωt ≤ α +
3 3
5π
ia = i0 α+ ≤ ωt ≤ α + 2π
3
ia = 0 otherwise
From Fig. 13.2 it can be observed that i0 itself has a ripple at a frequency six times the input
frequency. The closed from expression of i0, as will be seen later is some what complicated.
However, considerable simplification in the expression of ia can be obtained if i0 is replaced by
its average value I0. This approximation will be valid provided the ripple on i0 is small, i.e, the
load is highly inductive. The modified input current waveform will then be ia which can be
expressed in terms of a fourier series as
I A0 α α
ˆ
i a ≈ ia = + ∑ I An cos nωt + ∑ I Bn sin nωt (13.5)
2 n=1 n=1
Where
1 α+2π
2π ∫α
I A0 = i a dωt = 0 (13.6)
1 α+2π
I An = ∫ i a cos nωt n≠0
π α
4I nπ nπ
= 0 cos sin cos nα (13.7)
nπ 6 2
2 3I 0 ⎛ π⎞
I An = ( 1) sin ⎜ Kπ ± ⎟ cos ( 6K ±1) α
K
∴
( 6K ±1) π ⎝ 2⎠ (13.8)
for n = 6K ±1, K = 0, 1, 2, 3 ....
IAn = 0 otherwise.
2 3I 0 ⎛ π⎞
I Bn = ( 1) sin ⎜ Kπ ± ⎟ sin ( 6K ±1) α
K
∴
( 6K ±1) π ⎝ 2⎠ (13.10)
for n = 6K ±1, K = 0, 1, 2, ....
IBn = 0 otherwise.
2 3
= I0 cos ( ωt  α ) (13.12)
π
2VL
From Fig. 13.2 v an = cos ωt (13.13)
3
I0
I ⎛ 6⎞ 2 3
distortion factor = a1 = ⎜ ⎟ I0 = (13.15)
Ia ⎝ π ⎠ 3 π
3
∴ Power factor = Displacement factor × Distortion factor = cosα (13.16)
π
π
The closed form expression for i0 in the interval α ≤ ωt ≤ α + can be found as follows
3
in this interval
di ⎛ π⎞
Ri 0 + L 0 + E = v0 = 2VLsin ⎜ ωt + ⎟ (13.17)
dt ⎝ 3⎠
( ωt  α )
 2VLtanφ ⎛ π ⎞ E
i 0 = I1e +
sin ⎜ ωt +  φ ⎟  (13.18)
Z ⎝ 3 ⎠ R
ωL
Where Z = R 2 + ω2 L2 , tanφ =
R
∴ R = Zcosφ, E = 2VLsinθ (from Fig. 13.2) (13.19)
2VL ⎡ ⎛ π ⎞ sinθ ⎤
∴ I1 + ⎢sin ⎜ α + 3  φ ⎟  cosφ ⎥
Z ⎣ ⎝ ⎠ ⎦
π

3tanφ 2VL ⎡ ⎛ 2π ⎞ sinθ ⎤
= I1e + ⎢sin ⎜ α + 3  φ ⎟  cosφ ⎥
Z ⎣ ⎝ ⎠ ⎦
2VL sin ( φ  α )
OR I1 = π
(13.22)
Z 
1 e 3tanφ
⎡ (ω t  α ) ⎤
2VL ⎢ sin ( φ  α )  tanφ ⎛ π ⎞ sinθ ⎥
∴ i0 = e + sin ⎜ ω t +  φ ⎟  (13.23)
Z ⎢ 
π
⎝ 3 ⎠ cosφ ⎥
⎣ 1 e 3tanφ
⎦
To find out the condition for continuous conduction it is noted that in the limiting case of
continuous conduction.
π
i 0 min=0 , Now if θ ≤ α + then i0 is minimum at ωt = α. ∴ Condition
3
for continuous conduction is i0 ωt=α ≥ 0 . However discontinuous conduction is rare in these
conversions and will not be discussed any further.
3 2
V0 = VL cosα (13.24)
π
2 3
i a1 = I0 cos(ωt  α) (13.25)
π
Which imposes an upper limit on the value of α. In practice this upper value of α is further
reduced due to commutation overlap.
Exercise 13.2
1. A three phase fully controlled bridge converter operating from a 3 phase 220 V, 50 Hz
supply is used to charge a battery bank with nominal voltage of 240 V. The battery bank
has an internal resistance of 0.01 Ω and the battery bank voltage varies by ± 10% around
its nominal value between fully charged and uncharged condition. Assuming continuous
conduction find out.
When the battery bank is charged with a constant average charging current of 100 Amps through
a 250 mH lossless inductor.
Answer: The maximum and minimum battery voltages are, VB Min = 0.9 × VB Nom = 216 volts
and VB Max = 1.1 × VB Nom = 264 volts respectively.
2
(iii) Power loss during charging = I0RMs RB
2 2
VK VAK + VBK
But I 2
0RMs = I + I + I + ........ and I K ≈
2
0
2
1
2
2 =
6KωL 6 2KωL
For α = α Min
∴ 2
J 0RMs ≈ 1002 + (0.073) 2 + (0.017) 2 = 10000.00562
∴ Ploss = 100 watts.
2. A three phase fully controlled converter operates from a 3 phase 230 V, 50 Hz supply
through a Y/Δ transformer to supply a 220 V, 600 rpm, 500 A separately excited dc
motor. The motor has an armature resistance of 0.02 Ω. What should be the transformer
turns ratio such that the converter produces rated motor terminal voltage at 0º firing
angle. Assume continuous conduction. The same converter is now used to brake the
motor regeneratively in the reverse direction. If the thyristors are to be provided with a
minimum turn off time of 100 μs, what is the maximum reverse speed at which rated
braking torque can be produced.
∴ Eb = Va – Iara =  229.89 V.
6 2
v 0 = v01 + v02 = VL cosα +
π
α
(13.28)
2∑ cos3Kφ ⎡⎣ VAK cos3K ( 2ωt  φ ) + VBK sin3K ( 2ωt  φ ) ⎤⎦
K=1
Now if cos 3Kφ = 0 for some K then the corresponding harmonic disappear from the fourier
series expression of v0.
Then
α
6 2
v0 = VL cosα + 2∑ [ VAm cos 12mωt + VBm sin 12mωt ] (13.29)
π m=1
It can be seen that the frequency of the harmonics present in the output voltage has the form
12ω, 24ω, 36ω ………..
Similarly it can be shown that the input side line current iABC have harmonic frequency of the
form
11ω, 13ω, 23ω, 25ω, 35ω, 37ω, ………….
In a similar manner more number of 3 phase 6 pulse converters can be connected in series /
parallel and the φ angle can be adjusted to obtain 18 and 24 pulse converters.
One of the shortcomings of a three phase fully controlled converter is that although it can
produce both positive and negative voltage it can not supply current in both directions.
However, some applications such as a four quadrant dc motor drive require this capability from
the dc source. This problem is easily mitigated by connecting another three phase fully
controlled converter in anti parallel as shown in Fig. 13.5 (a). In this figure converterI supplies
positive load current while converterII supplies negative load current. In other words converter
I operates in the first and fourth quadrant of the output v – i plane whereas converterII operates
in the third and fourth quadrant. Thus the two converters taken together can operate in all four
quadrants and is capable of supplying a four quadrant dc motor drive. The combined converter is
called the Dual converter.
α2 = π – α 1 (13.30)
13.4 Gate Drive circuit for three phase fully controlled converter
Several schemes exist to generate gate drive pulses for single phase or three phase converters. In
many application it is required that the output of the converter be proportional to a control
voltage. This can be achieved as follows.
The following circuit can be used to generate “α” according to equation 13.32.
Therefore this method of generation of converter firing pulses is called “inverse cosine” control.
The output of the phase shift network is called carrier waveform.
Similar technique can be used for three phase converters. However the phase shift network here
consists of a three phase signal transformer with special connections as shown in Fig. 13.7.
ii) Constituent six pulse converters of a 12 pulse converter have _________ firing
angles.
iii) The input supply voltages to the converters of a 12 pulse converter have ________
magnitudes and are phase shifted from one another by _________ degrees.
iv) The input supply to a 12 pulse converter can be obtained through a _________
connected transformer.
v) Dual converters are used for supplying ________ quadrant dc motor drives.
vi) In a dual converter if one converter is fired at an angle ‘α’ the other has to be fired
at _________.
vii) In ___________ current dual converter only one converter conducts at any time.
viii) In a circulating current type dual converter an __________ is used between the
converters to limit the circulating current.
ix) To obtain a linear control relation between the control voltage and the output dc
voltage of a converter ___________ control logic is used.
x) In a three phase fully controlled converter the carrier waves for firing pulse
generation are obtained using three ___________ connected single phase
transformers.
Answers: (i) Series, parallel; (ii) same, (iii) equal, 30, (iv) star – star – delta; (v) four; (vi) π  α,
(vii) noncirculating ; (viii) inductor, (ix) inversecosine; (x) deltazigzag.
2. A 220V, 750 RPM, 200A separately excited dc motor has an armature resistance of 0.05
Ω. The armature is fed from a three phase non circulating current dual converter. If the
forward converter operates at a firing angle of 70º
Answer:
i) The output voltage = 3 2 × 400 cos 70o = 184.7 V
π
3. What will happen if the signal transformers generating the carrier wave have delta –
double star connection instead of deltazigzag connection.
Answer: With deltadouble star connection of the signal transformers the carrier wave forms
will be in phase with the line voltage waveforms. Therefore, without a phase shift
network it will not be possible to generate carrier waveforms which are in quadrature
with the line voltages. Hence inverse casine control law cannot be implemented.
References
1. “Power Electronics”; P.C. Sen; TataMcGrawhill publishing company limited; 1995.
2. “Power Electronics, Converters, Applications and Design”, Mohan, Undeland, Robbins;
John Willey and Sons Inc; Third Edition, 2003.
Answers
1.
The figure above shows the output voltage with α = 90º and a resistive load. Since the load is
resistive the load current becomes zero when the voltage becomes zero. Both the voltage and
amount remains zero thereafter till the next thyristor is fired.
Therefore for 5π ≤ ωt ≤ π
6
Version 2 EE IIT, Kharagpur 27
v0 = Vbc = 2VL sinωt
π ≤ ωt ≤ 7π
6
v0 = 0
∴ V0 RMS = 3 ∫5π 2VL2 sin 2 ωt dωt
π
π 6
π 6
2
V0
= VL 1 − 3 ∫5π cos2ωt dωt
RMS π
∴ P0 =
R 2 π 6
= 183 Watts
= VL 1 − 3 3
2 4π
= 67.65 V
2. To hold the overhauling load the motor must operate in the regenerative braking mode.
At 1000 RPM Eb = 220  50× 0.2 ×1000 = 140 volts
1500
3. With reference to the conduction diagram of problem – 1 it can be seen that the load
current becomes zero 30º after a new thyristor is fired (for example, T2). Therefore, both
the conducting thyristor (T1 and T2 in this case) turns off. However, when T3 is fired the
converter will be unable to resume operation from T2T3 mode unless T2 is fired
simultaneously. Similar explanation holds for all other thyristor firing. Therefore, to
ensure that the converter operates properly even under discontinuous load current
condition the final gate pulse for a particular thyristors must be generated by logically
“ANDing” the outputs of its own firing circuit with the output of the firing circuit of the
thyristor in the commutation sequence as shown in the table next below
To generate the
gate pulse of : T1 T2 T3 T4 T5 T6
• Draw the circuit diagram and waveforms of different variables associated with a three
phase half controlled converter.
• Identify the constructional and operational difference between a three phase fully
controlled and half controlled converter.
• Calculate the average and RMS value of the output dc voltage.
• Calculate the displacement factor, distortion factor and power factor of the input ac line
current.
• Calculate the Fourier series components of the output voltage and input current
waveforms.
• Derive the closed form expression for output dc current and hence identify continuous or
discontinuous conduction mode of the converter.
The three phase half controlled converter has several other advantages over a three phase
fully controlled converter. For the same firing angle it has lower input side displacement factor
compared to a fully controlled converter. It also extends the range of continuous conduction of
the converter. It has one serious disadvantage however. The output voltage is periodic over one
third of the input cycle rather than one sixth as is the case with fully controlled converters. This
implies both input and output harmonics are of lower frequency and require heavier filtering.
For this reason half controlled three phase converters are not as popular as their fully controlled
counterpart.
Although, from the point of view of construction and circuit complexity the half controlled
converter is simpler compared to the fully controlled converter, its analysis is considerably more
difficult. In this lesson the operating principle and analysis of a three phase half controlled
converter operating in the continuous conduction mode will be presented.
Next consider conduction of T1. The firing sequence of the thyristor is T1 → T3 → T5.
Therefore before T1 comes into conduction T5 conducts and voltage across T1 is
v ac = 2VL sin (ωt + π/3) . If the firing angle of T1 is α then T1 starts conduction at
ωt = α  π/3 and conducts upto α + π/3 . Similarly T3 and T5 conducts during α + π/3 ≤ ωt ≤ α + π
and α + π ≤ ωt ≤ 2π + α  π/3 . From this discussion the following conduction diagrams can be
drawn for continuous conduction mode.
Answer: (i) three, three; (ii) nine, six; (iii) inverter; (iv) same, free wheeling; (v) six; (vi) free
wheeling, 60; (vii) uncontrolled, controlled; (viii) quarter.
With T1 conducting there can be three conduction modes namely, T1D6, T1D2 and T1D4.
(
v0 = vab = 2VL sin ωt + 2π
3 ) (14.1)
0 ≤ ωt ≤ α + π
3
(
v0 = vac = 2VL sin ωt + π
3) (14.2)
3 2VL ⎡ 0 ⎛ π⎞ α+
π
⎛ π⎞ ⎤
V0 = ⎢ ∫α  π ⎜
sin ωt + 2 dωt+ ∫0 sin ωt + dωt
3
⎟ ⎜ ⎟ ⎥
2π ⎣ 3 ⎝ 3⎠ ⎝ 3⎠ ⎦
3 2
or, V0 = VL (1 + cosα) (14.4)
2π
For α> π, In the interval α  π ≤ ωt ≤ 2π
3 3 3
(
v0 = vac = 2VL sin ωt + π
3 ) (14.5)
for 2π ≤ ωt ≤ α + π
3 3
v0 = 0 (14.6)
3 2VL ⎡ 2π ⎛ π⎞ ⎤
∴ V0 = ⎢ ∫ π sin ⎜ ωt +
2π ⎣ α  3 ⎝
⎟
3⎠
dωt ⎥
⎦
3 2
= VL (1 + cosα)
2π
From the waveforms of Fig. 14.2, v0 is periodic over one third of the input cycle. Therefore one
can write
α
v 0 = V0 + ∑ [ VAn cos 3nωt + VBn sin 3nωt ] (14.8)
n=1
π
3α+
π∫
VAn = π
3
v0 cos 3nωt dωt (14.9)
α
3
π
3α+
π∫
VBn = 3
π v0 sin 3nωt dωt (14.10)
α
3
⎢+ + ⎥
⎢⎣ 3n + 1 α+
π 3n  1 0 ⎥⎦
3
Therefore
⎡1 + cos [ (3n + 1)(α  π/3) + 2π/3]  cos [ (3n + 1)(α + π/3) + π/3] ⎤
3 2VL ⎢ 3n + 1
⎥
VAn = ⎢ ⎥
2π ⎢ cos [ (3n  1)(α + π/3)  π/3]  cos [ (3n  1)(α  π/3)  2π/3] 1 ⎥
⎢+ ⎥
⎣ 3n  1 ⎦
⎡1  2sin [ (3n + 1)α + π/2] sin [ π/6  (3n + 1) π/3] ⎤
3 2VL ⎢ 3n + 1
⎥
= ⎢ ⎥
2π ⎢ 1 + 2sin [ (3n  1)α  π/2] sin [ π/6 + (3n  1) π/3] ⎥
⎢ ⎥
⎣ 3n  1 ⎦
3 2VL ⎡1+ 2sin(6n + 1)π/6 cos(3n + 1)α 1 2sin(6n  1)π/6 cos(3n  1)α ⎤
= 
2π ⎢⎣ 3n + 1 3n  1 ⎥⎦
3 2VL ⎡1+ (1) n cos(3n + 1)α 1+ (1) n cos(3n  1)α ⎤
=  (14.12)
2π ⎢⎣ 3n + 1 3n  1 ⎥
⎦
Similarly,
3 2VL ⎡ 0 ⎛ π⎞ α+
π
⎛ π⎞ ⎤
VBn = ⎢ ∫α  π ⎜
sin ωt + 2 sin3nωtdωt + ∫ sin ⎜ ωt + ⎟ sin3nωtdωt ⎥ (14.13)
3
⎟
π ⎣ 3 ⎝ 3⎠ 0
⎝ 3⎠ ⎦
⎡ 0 ⎧ ⎡ π⎤ ⎡ π ⎤⎫ ⎤
⎢ ∫α  π ⎨cos ⎢ (3n  1)ωt  2 ⎥  cos ⎢ (3n + 1)ωt + 2 ⎥ ⎬ dωt ⎥
3 2VL ⎢ 3 ⎩ ⎣ 3⎦ ⎣ 3 ⎦⎭ ⎥
or, VBn =
2π ⎢ α + 3 ⎧ ⎡π
π⎤ ⎡ π ⎤⎫ ⎥
⎢+ ∫ ⎨ cos ⎢ (3n  1)ωt  ⎥  cos ⎢ (3n + 1)ωt + ⎥ ⎬ dωt ⎥
⎣⎢ ⎩ ⎣ 3⎦ ⎣ 3 ⎦⎭ ⎦⎥
0
⎢ 3n  1 3n + 1 ⎥
⎣ 0 0 ⎦
∴ α  π ≤ ωt ≤ 2π ia = I0
3 3
α + π ≤ ωt ≤ 4π ia =  I0
3 3
otherwise ia = 0
π 0
⎡ 2π 4π ⎤
= 1 ⎢ ∫ 3 π I 0 cos nωt dωt  ∫
I0 cos nωt dωt ⎥
3
π ⎣ α 3 α+ π
3 ⎦
I0 ⎡ sin nωt 2 3 ⎤
π 4π
= ⎢  sin nωt 3
⎥
π ⎢ n α π n α+ π ⎥
⎣ 3 3 ⎦
=
I0 ⎡ 2nπ
nπ ⎢⎣
sin
3 3 ( ) 3 (
 sin n α  π + sin n α + π  sin 4nπ ⎤
3 ⎥⎦ )
2I
= 0 ⎡sin 2nπ + cos nα sin nπ ⎤
nπ ⎢⎣ 3 3 ⎥⎦
2I0
or, Ian = ⎡⎣cos nα  ( 1) n ⎤⎦ sin nπ (14.16)
nπ 3
π 0
⎡ 2π 4π ⎤
= 1 ⎢ ∫ 3 π I 0 sin nωt dωt  ∫
I0 sin nωt dωt ⎥
3
π ⎣ α 3 α+ π
3 ⎦
I ⎡ α π 4π ⎤
= 0 ⎢ cos nωt π 3 + cos nωt 3 π ⎥
nπ ⎣ 2
3
α +
3⎦
I
nπ ⎣ 3 3 3 ( )
= 0 ⎡⎢sin 4nπ  cos 2nπ + cos n α  π  cos n α + π ⎤⎥
3 ⎦ ( )
2I
= 0 sin nα sin nπ (14.17)
nπ 3
3I 0
i a1 =
π
[ cosωt + cosα cosωt + sinα sinωt ]
3I0
=
π
[cosωt + cos(ωt  α)]
=
2 3I0
π
cos α cos ωt  α
2 2 ( ) (14.18)
6 3
cos 2 α = (1 + cosα) (14.21)
π (π  α) 2 2(π  α) π
( )
ωt
2VL ⎡ ⎤
sin ωt + π  φ  sinθ ⎥

∴ i 0 = Ie tanφ + ⎢ (14.23)
Z ⎣ 3 cosφ ⎦
Where tanφ = ωL , Z = R 2 + ω 2 L2 and E = 2VL sinθ (14.24)
R
At ωt = α + π
3
( )
( α + π/3)
2VL ⎡ ⎤
sin α  φ + 2π  sinθ ⎥

i 0 = I1 = Ie tanφ + ⎢ (14.25)
Z ⎣ 3 cosφ ⎦
di 0
∴ L + Ri 0 + E = v bc = 2VL sinωt (14.26)
dt
( ωt  α  π/3)
2VL ⎡ ⎤
sin ( ωt  φ )  sinθ ⎥

∴ i 0 = I 2 e tanφ + (14.27)
Z ⎢⎣ cosφ ⎦
At ωt = α + π
3
i0 = I2 +
2VL ⎡
Z ⎣ ⎢ 3 (⎤
sin α + π  φ  sinθ ⎥ = I1
cosφ ⎦ ) (14.28)
( α + π/3)
 2VL
∴ I2 = Ie tanφ
sin ( α  φ )
 (14.29)
Z
( ωt ) ( ωt  α  π/3)
 2VL ⎡ 
sinθ ⎤
∴ i 0 = Ie tanφ
+ ⎢sin ( φ  α ) e tanφ + sin ( ωt  φ )  ⎥ (14.30)
Z ⎢ cosφ ⎥
⎣ ⎦
( )
2π ⎡ ( α  π/3) ⎤
2VL
) tanφ  sin φ  2π  sinθ ⎥

i0 ωt = 2π
= Ie 3tanφ
+ ⎢ (sin φ  α e (14.31)
Z ⎢⎣ 3 cosφ ⎥
3
⎦
i0 ωt =
2π
3
= i0 ωt = 0
= I+
2VL ⎡
Z ⎢⎣ (
sin π  φ  sinθ ⎥
3 ) ⎤
cosφ ⎦
(14.32)
for α + π ≤ ωt ≤ 2π
3 3
⎡ ⎧  ( ωt  α  π/3) α  π/3  ωt
⎫  ωt ⎤
2VL ⎢ ⎪ e tanφ ⎪ sinφ e tanφ s inθ ⎥
i0 = sin ( φ  α ) ⎨e tanφ
+ ⎬+ + sin ( ωt  φ ) 
Z ⎢ ⎪  2π
⎪⎭  2π cos φ ⎥
⎣⎢ ⎩ 1 e 3tanφ 1 e 3tanφ ⎦⎥
(14.34)
Exercise 14.2
i. In a three phase half controlled converter each thyristor and diode conduct for
________________ degrees.
ii. The output voltage waveform of a three phase half controlled converter is periodic over
________________ of the input voltage cycle.
iii. The output voltage waveform of a three phase half controlled converter operating with α >
π/3 and α ≤ π/3 are ________________ and have ________________ formula for the
average voltage.
iv. The output voltage and current of a three phase half controlled converter contain
________________ harmonics of the input ac frequency.
v. The ac input current of a half controlled three phase converter can be zero for larger than
________________ of the input ac cycle provided the value of α is ________________
than 60°.
vi. The input ac current of a three phase half controlled converter contain ________________
harmonics but no ________________ harmonics.
vii. For the same output load current and firing angle the three phase half controlled converter
has better ________________ factor but poorer ________________ factor compared to a
fully controlled converter.
Answer: (i) 120°; (ii) one third; (iii) different, same; (iv) triplen; (v) one third, greater; (vi) even,
triplen; (vii) displacement, distortion.
Answer:
(i) Under rated operating condition the motor must be supplied with rated voltage.
3 2
Therefore Vo = VL (1+ cosα ) = 200V
2π
Where VL = 230V
∴ α ≈ 70o
(ii) Io = 100A
From equation (14.18)
6
Ii1 = I o cos α = 63.87 amps
π 2
References
1. “Power Electronics”’ P.C. Sen, Tata McGrawhill publishing company limited, 1995.
2. “Power Electronics, Converters, Applications and Design”; Mohan, Undeland, Robins;
John Willey and Sons Inc, Third Edition, 2003.
2. A 220V, 1500 rpm, 50A, separately excited dc motor with armature resistance of 0.5Ω if
fed from a 3 phase half controlled rectifier. The available ac source is 440V, 50Hz. A star
delta connected transformer is used to feed the armature so that the motor terminal
voltage equals rated voltage when converter firing angle is zero.
(i) Calculate the transformer turns ratio
(ii) Firing angle when (a) motor is running at 1200 rpm and rated torque; (b) 1500 rpm
and half the rated torque.
3. A battery with a nominal voltage of 200V and internal resistance of 10mΩ has to be
charged at a constant current of 20 amps from a 3 phase 220V 50 Hz power supply.
Which of the following converters will give better performance with respect to input
current displacement factor, distortion factor and power factor?
(i) 3 phase fully controlled converter; (ii) 3 phase half controlled converter.
i) When α ≤ π/3 the free wheeling diode will not come into conduction and therefore,
the converter will continue to perform like a fully controlled converter which is very
different from that of a half controlled converter for this range of α.
ii) For α > π/3 the output voltage will be clamped to zero for certain part of the input
cycle. However, the output voltage will still have “six pulse” characteristics unlike a
half controlled converter. Similarly the input current waveform will retain its quarter
cycle symmetry which is not the case with a half controlled converter.
3 2
i) V0 = VL (1 + cosα)
2π
at α = 0, V0 = 220 V, ∴ VL = 163 V,
∴ E b 1200 = 195 ×
12 = 156 V
15
Torque is rated, ∴ Ia = 50 A, V1200 = 156 + 0.5 × 50 = 181 volts
∴ 181 = 3 2 × 163(1 + cosα) ∴ α = 49.87º
2π
∴ Displacement factor and power factor of a half controlled converter are better
compared to a fully controlled converter while the distortion factor is poorer.
• Draw the voltage and current waveforms associated with a converter taking into account
the effect of source inductance.
• Find the average output voltage of the converter as a function of the firing angle and
overlap angle.
• Estimate overlap angles under a given operating condition and hence determine the turn
off time available for the thyristors.
• Draw the dc equivalent circuit of a converter and parameterize it.
• Find out the voltage stress on the thyristors due to commutation overlap.
dii
L = vi for α ≤ ωt ≤ α + μ (15.1)
dt
ii(ωt = α) =  I0 (15.2)
2Vi
∴ ii = I  cosωt (15.3)
ωL
2Vi
ii =I cosα =  I0 (15.4)
ωt = α ωL
2Vi
∴ I= cosα  I0 (15.5)
ωL
2Vi
∴ ii = (cosα  cosωt)  I0 (15.6)
ωL
at ωt = α + μ ii = I0
2Vi
∴ I0 = (cosα  cos(α + μ))  I0 (15.7)
ωL
V0 = I
α+π
π ∫ α
vi dωt (15.9)
V0 = I
α+π
or
π ∫α+μ
2vi sinωt dωt
2vi
=
π
[cos(α + μ) − cos(π + α)]
2vi
=
π
[cosα + cos(α + μ)] (15.10)
vi 2vi
∴ V0 = 2 2
π
cosα 
π
[ cosα − cos(α + μ)]
= 2 2 vi cosα  2 ωL I0 (15.11)
π π
The simple equivalent circuit of Fig. 15.3 represents the single phase fully controlled converter
with source inductance as a practical dc source as far as its average behaviour is concerned. The
open circuit voltage of this practical source equals the average dc output voltage of an ideal
converter (without source inductance) operating at a firing angle of α. The voltage drop across
the internal resistance “RC” represents the voltage lost due to overlap shown in Fig. 15.1(b) by
the hatched portion of the v0 waveform. Therefore, this is called the “Commutation resistance”.
Although this resistance accounts for the voltage drop correctly there is no power loss associated
with this resistance since the physical process of overlap does not involve any power loss.
Therefore this resistance should be used carefully where power calculation is involved.
In the time interval α < ωt ≤ α + μ, T6 and T2 from the bottom group and T1 from the top group
conducts. The equivalent circuit of the converter during this period is given by the circuit
diagram of Fig. 15.5.
di b di
vb = L  L c + vc (15.12)
dt dt
or, d
v bc = L (i b  ic ) (15.13)
dt
di b di
but ib + ic + Io = 0 ∴ = c (15.14)
dt dt
∴ 2L d i b = vbc = 2VL sinωt (15.15)
dt
2VL
∴ ib = C  cosωt (15.16)
2ωL
2VL
at ωt = α, ib =  I0 ∴ C= cosα  I0 (15.17)
2ωL
2VL
∴ ib = (cosα  cosωt)  I0 (15.18)
2ωL
at ωt = α + μ, ib = 0
2VL
∴ (cosα  cos(α + μ)) = I0 (15.19)
2ωL
Or, cosα  cos(α + μ) = 2ωL I (15.20)
VL 0
Equation 15.20 holds for μ ≤ 60º. It can be shown that for this condition to be satisfied
I0 ≤
VL
2ωL
(
cos α  π
3 ) (15.21)
for α + μ ≤ ωt ≤ α + π v0 = vac
3
⎡ α+μ π
⎤
V0 = 3 ⎢ ∫ 3 va dωt +
α+
∴
π⎣ α 2 ∫
α+μ
3
vac dωt ⎥
⎦
π⎣ α 2 α+μ
⎦
⎡ α+ π
α+μ ⎛ v ⎞ ⎤
= 3 ⎢ ∫ 3 vac dωt + ∫ ⎜ a + vc ⎟ dωt ⎥
π⎣ α α
⎝ 2 ⎠ ⎦
= 3 2 VL cosα  3 ∫ v bc dωt
α+μ
(15.23)
π 2π α
3 2VL
V0 = 3 2 VL cosα 
α+μ
or
π 2π ∫α sinωt dωt
3 2VL
= 3 2 VL cosα  [cosα  cos(α + μ)] (15.24)
π 2π
V0 = 3 2 VL cosα  3 ωL I0 (15.25)
π π
Equation 15.25 suggests the same dc equivalent circuit for the three phase converter with source
inductance as shown in Fig. 15.3 with
Exercise 15.1
Answer: (i) inductive; (ii) inductance, instantaneous; (iii) overlap; (iv) current ; (v) four; (vi)
three, sixty; (vii) decreases; (viii) commutation; (ix) inverter, (x) notches.
2. A 220V, 1450 RPM, 100A separately excited dc motor has an armature resistance to
0.1Ω. It is supplied from a 3 phase fully controlled converter connected to a 3 phase 50
Hz ac source. The ac source has an inductive reactance of 0.5Ω at 50 Hz. The line voltage
is adjusted such that at α = 0; the motor operates at rated speed and torque. The motor is
to be braked regeneratively in the reverse direction at rated speed using the converter.
What is the maximum braking torque the motor will be able to produce under this
condition without causing commutation failure?
Answer: Under rated operating condition, the motor terminal voltage is 220V and it draws 100
Amps current. Therefore from eqn. 15.25.
3 2 3
220 = VL  × .5×100
π π
or VL = 198 volts Eb rated speed = 220 − 100 × 0.1 = 210V
Io
∴ cos α = −1
198 2
3 3 2 ⎛3 ⎞
∴ Io − × 198 − ⎜ × 0.5 + 0.1⎟ I o = −210
π π ⎝π ⎠
∴ Maximum braking torque will be approximately 150% of the rated motor torque.
Lesson Summary
• Ac power sources supplying an acdc converter have internal impedances which are not
always negligible.
• The internal impedance of an ac source is predominantly inductive with negligible
resistive component.
• Due to the presence of the source inductance in the ac line the thyristors in a acdc
converter can not commutate instantaneously.
• The period over which the commutation process continuous is called the overlap period.
• The length of the overlap period increases with increasing source inductance and load
current.
• In a single phase converter all four thyristors conduct during the overlap period.
• In a three phase converter, three thyristors conduct during the overlap period provided it
is less than 60º.
• The average output voltage of a converter decreases as a result of commutation overlap.
• The voltage drop due to commutation overlap can be represented as a drop across a
commutation resistance the value of which is proportional to the ac line reactance per
phase.
• The commutation resistance is “loss less” since the actual process of overlap does not
involve any real power loss.
• Commutation overlap reduces the margin angle (γ) of a converter and may cause
commutation failure.
• Commutation overlap introduces “notches” in the ac supply voltage waveform which
may affect other equipment connect to the same power source.
2.8.1 Introduction
After the discussion of various types of ac to dc converters (rectifiers), both single and three
phase, in the lessons (#2.12.6) of this module (# 2), the drop in the output voltage due to the
commutation overlap in the converter, was presented, the inductance on the source (ac) side
being taken into account, in the previous lesson (#2.7).
In this (last) lesson (#2.8), three important points – power factor improvement, harmonic
reduction, and filters, as applicable to converters, are described. The three schemes for power
factor improvement are discussed. Then, the use of various filters to reduce the harmonics in the
output voltage and current waveforms, are presented. Lastly, the harmonic reduction techniques
are taken up, in brief. In all these cases, the circuit of a single phase full wave half (semi)
controlled bridge converter (acdc) is used mostly as an example.
Power Factor Improvement
For phasecontrolled operation in both single phase full wave half and full controlled bridge
converters as discussed in this module (#2), the displacement factor (or power factor, which is
lagging) decreases, as the average value of output voltage (Vdc) decreases, with the increase in
firing angle delay, α. This is also applicable for both three phase half wave and full wave
(bridge) converters. The three schemes used for power factor (pf) improvement are:
iT1
+
S1 S2 i 0 = Ia
v0
+ is iT2
DF L
vs O
 A
D
D2 D1
iDF

(a) Circuit
v0
β
0 ωt
πβ π 2π  β 2π
iT1
Ia
0 ωt
πβ π 2π 3π  β
Ia iT2
0 ωt
π 2π  β
iDF Ia
ωt
0 πβ π 2π  β 2π
is
is1
Ia
2π  β
0 ωt
πβ π 2π 3π  β
 Ia
io
Ia Load current
ωt
0
(b) Waveforms for extinction angle control
Fig. 16.1 Singlephase forcedcommutated semiconverter.
⎡ 2 πβ ⎤ ⎡1 ⎛ 1 ⎞⎤
2 2
Vo = ⎢ ∫ 2V 2 sin 2 ωt d ( ωt ) ⎥ = V ⎢ ⎜ ( π − β ) + sin 2β ⎟ ⎥
⎣ 2π 0 ⎦ ⎣π ⎝ 2 ⎠⎦
Here also, Vo varies from V to 0.
This scheme of extinction angle control can also be used for single phase full wave full
controlled bridge converter with four switches, instead of two needed in the earlier case. The
students are requestedto study this matter form text books, but details are not included here.
Vm vs = Vmsinωt
π
0
ωt
v0
Vm
β
0
is1 π 2π 3π ωt
Ia
0
is2 π /2 π 2π 5π /2 ωt
Ia
0 ωt
is π 3π /2 2π
Ia is1
π
0
πβ π+β 2π ωt
 Ia 2 2
i0
Ia
Load current
0
ωt
(a)
v
vr
vc
Ar
Ar
0 π 2π 3π ωt
S1 S2 S1
vg
β
0 π 2π 3π ωt
(b)
Fig. 16.2 Symmetrical angle control.
Vo = ⎢ ∫ 2V sin ( ωt ) d ( ωt ) ⎥ = V ⎢ ( β + sin β ) ⎥
⎣ 2π ( πβ ) / 2
⎦ ⎣π ⎦
0
π 2π 3π ωt
v0
δm
0
αm π 2π 3π ωt
is1
Ia
δm
δm
0
is3 π 2π 3π ωt
Ia
0
π π + αm 2π 3π ωt
is
Ia
δm
π + αm
0
αm π 2π 3π ωt
i0
 Ia
Ia
Load current
0
ωt
(a)
v
vr
Ar
vc
Ac
0 π
vg2 S1 S1 S1
δm δm
α1 αm ωt π
(b)
π ωt
vg2
S1 S1 S1
δm
0 αm π ωt
(c)
The details of output voltage and current waveforms of the converter are given. The output
voltage (i.e., performance parameters) can be obtained in two steps: (i) by considering only one
pair of pulses such that, if one pulse starts at ωt = α1 , and ends at ωt = α1 + δ1 , the other pulse
starts at ωt = π + α1 , and ends at ωt = ( π + α1 + δ1 ) , and (2) then by combining the effects of all
pairs of pulse.
If mth pulse starts at ωt = α m and its width is δm , the average output voltage due to p number
of pulses is found as
p
⎡ 2 α m +δm ⎤ 2V p
Vdc = ∑ ⎢ ∫
m =1 ⎣ π
αm
2V sin ωt d ( ωt ) ⎥ =
⎦
∑ ⎡cos α m − cos ( α m + δm )⎤⎦
π m =1 ⎣
If the load current with an average value of Ia is continuous and has negligible ripple, the
instantaneous input current is expressed in a Fourier series as
α
is ( t ) = Idc + ∑ (a
n =1,3,5,...
n cos nωt + b n sin nωt )
Due to symmetry of the input current waveform, even harmonics are absent, and Idc is zero. The
Fourier coefficients are obtained as
1 2π
a n = ∫ is ( t ) cos nωt d ( ωt )
π 0
p
⎡ 1 α m +δm 1 π+αm +δm ⎤
= ∑⎢ ∫ I a cos nωt d ( ωt ) − ∫ I a cos nωt d ( ωt ) ⎥ = 0
m =1 ⎣ π π ⎦
α m π+α m
1 2π
is ( t ) sin nωt d ( ωt )
π ∫0
bn =
p
⎡ 1 α m +δm 1 π+α m +δm ⎤
= ∑⎢ ∫ Ia sin nωt d ( ωt ) − ∫ I a sin nωt d ( ωt ) ⎥
m =1 ⎣ π π ⎦
α m π+α m
p
2I
= a ∑ ⎡⎣ cos nα m − cos n ( α m + δ m ) ⎤⎦
nπ m =1
2 = bn
2
2
0 ωt
iT1
+Ia
0 ωt
αm π 2π 3π
δm
iT2
+Ia
0 ωt
π π + αm 2π 3π
is δm
+Ia π + αm
π + αm + δ m
0 ωt
αm π 2π 3π
 Ia
io
Ia
Load current
0 ωt
Fig. 16.4 Sinusoidal pulsewidth modulation control.
Filters
It is known that the output voltage waveform of a single phase full wave diode (uncontrolled)
bridge converter (rectifier) fed from f = 50 Hz (fundamental) supply, contains harmonics of 2f =
100 Hz. So, it is necessary to filter out this and other harmonics from the output voltage to obtain
dc component only. The harmonic frequency present in the output voltage waveforms of three
phase halfwave and full wave (bridge) diode converters, are 150 Hz (3f) and 300 Hz (6f)
respectively. The higher the harmonic frequency, it is easier to filter it. For phasecontrolled
thyristor converters, the harmonic frequency remains same, but magnitudes vary, as the firing
angle delay, α is changed. It may also be noted that the harmonics present in the output current
waveforms of the converters with resistive (R) load, remain same. .
For simple filter, a capacitor (C) is connected in parallel across the output of the diode
converters with resistive (R) load. The reactance of the capacitor should be low, such that
harmonics currents pass through it. So, the harmonics in the output voltage decrease. The value
of the capacitor chosen varies with the predominant harmonic frequency present. Thus, the
capacitor of higher value is needed to filter lower harmonic frequency, say 100 Hz, whereas a
lower value of C could be chosen for say, three phase converters. The function of the capacitor
n ωC
The condition to be satisfied is
10
ZL = or ZL 10 = 1 ( n ω C )
n ωC
and the effect of load is negligible. As shown, the capacitive reactance chosen is total load
impedance divided by a factor of 10
The advantages are small ripple factor with just a single stage (LC) used, with higher dc
output voltage. The main advantage is poor voltage regulation, also resulting in higher peak
anode current and peak inverse voltage rating.
D1 D2
1φ +
Supply L
G O
(50Hz) A RL
 C
is D
H
D4 D3
 B
(a)
A E
+
R RL, L
L
O
C1 C2 A
D

B
(b)
Fig. 16.5 (a) Low pass (LC) filter, (b) Twostage filter
iL
Ia
is
Ia
0
π(T/2) 2π(T) ωt
Ia
+ G
C H

B

Fig. 16.6 (b) Low pass (LC) filter on source (AC) side
+ Ld +
ic
+
vs │vs│ vd (Vd > Vˆ s )
Cd

 
(a)
vs
is
0 ωt
(b)
│vs│
iL
0 ωt
(c)
Fig. 16.7 Active harmonic filtering: (a) stepup converter for current
shaping; (b) line waveforms; (c) │vs│ and iL.
The control used is constant toleranceband one. Here, the current. iL, is controlled, such that
peaktopeak ripple Irip in iL remains constant. The reference input, i*L , is made sinusoidal having
same (line) frequency. With a preselected value of Irip, iL is forced to be in tolerance band (iL +
Irip/2) and (iL – Irip/2) by controlling the status of the switch, S. So, the input current, iL, follows
the reference input, i*L , which is sinusoidal. As described later (module #3), the switch, S may be
a selfcommutated switching device, power transistor or MOSFET. For detail, any text book may
be used by the student, as only a brief discussion is presented here.
In this lesson, last one in this module, three important points – power factor (pf)
improvement, harmonic reduction and filters, are presented. Firstly, three methods, viz extinction
angle control, symmetrical angle control and pulse width modulation (PWM) control, are
described in detail with relevant waveforms. Then, various types of filters (C, LC & RC) used
for the reduction in harmonic content of output voltage and current waveforms of the acdc
Introduction
In the last module (#2) consisting of eight lessons, the various types of circuits used in both
singlephase and threephase acdc converters, were discussed in detail. This includes halfwave
and fullwave, and also halfcontrolled and fullcontrolled ones.
In this lesson − the first one in this module (#3), firstly, three basic types of dcdc converter
circuits − buck, boost and buckboost, are presented. Then, the expressions for the output voltage
in the above circuits, with inductive (RL) and battery (or back emf = E), i.e., RLE, load, are
derived, assuming continuous conduction. The different control strategies employed are briefly
described.
Keywords: DCDC converter circuits, Thyristor choppers, Buck, boost and buckboost
converters (dcdc), Stepdown (buck) and stepup (boost) choppers, Output voltage and current.
DCDC Converters
There are three basic types of dcdc converter circuits, termed as buck, boost and buckboost.
In all of these circuits, a power device is used as a switch. This device earlier used was a
thyristor, which is turned on by a pulse fed at its gate. In all these circuits, the thyristor is
connected in series with load to a dc supply, or a positive (forward) voltage is applied between
anode and cathode terminals. The thyristor turns off, when the current decreases below the
holding current, or a reverse (negative) voltage is applied between anode and cathode terminals.
So, a thyristor is to be forcecommutated, for which additional circuit is to be used, where
another thyristor is often used. Later, GTO’s came into the market, which can also be turned off
by a negative current fed at its gate, unlike thyristors, requiring proper control circuit. The turn
on and turnoff times of GTOs are lower than those of thyristors. So, the frequency used in GTO
based choppers can be increased, thus reducing the size of filters. Earlier, dcdc converters were
called ‘choppers’, where thyristors or GTOs are used. It may be noted here that buck converter
(dcdc) is called as ‘stepdown chopper’, whereas boost converter (dcdc) is a ‘stepup chopper’.
In the case of chopper, no buckboost type was used.
With the advent of bipolar junction transistor (BJT), which is termed as selfcommutated
device, it is used as a switch, instead of thyristor, in dcdc converters. This device (NPN
transistor) is switched on by a positive current through the base and emitter, and then switched
off by withdrawing the above signal. The collector is connected to a positive voltage. Nowa
days, MOSFETs are used as a switching device in low voltage and high current applications. It
may be noted that, as the turnon and turnoff time of MOSFETs are lower as compared to other
switching devices, the frequency used for the dcdc converters using it (MOSFET) is high, thus,
reducing the size of filters as stated earlier. These converters are now being used for applications,
one of the most important being Switched Mode Power Supply (SMPS). Similarly, when
application requires high voltage, Insulated Gate Bipolar Transistors (IGBT) are preferred over
S Switch L
+
+ I0
L
Vs V0 O
DF A
D


Fig. 17.1(a): Buck converter (dcdc)
v0 Vs
V0
TON
t
T TOFF
i0
t
Fig. 17.1(b): Output voltage and current waveforms
The output voltage and current waveforms of the circuit (Fig. 17.1a) are shown in Fig. 17.1b.
The output voltage is same as the input voltage, i.e., v0 = Vs , when the switch is ON, during the
period, TON ≥ t ≥ 0 . The switch is turned on at t = 0 , and then turned off at t = TON . This is
Is L D I0
+ +
L
S
Vs V0 O
A
D
Switch
 
Fig. 17.2(a): Boost converter (dcdc)
I2
I1
0 TON T 2T
TOFF
Is Switch I0
+ S 
L
Vs L O V0
IL A C
D
 +
Fig. 17.3(a): Buckboost converter (dcdc)
IL2
IL1
TON T 2T
TOFF
Fig. 17.3(b): Inductor current (iL) waveform
Then, the switch, S is put OFF. The inductor current tends to decrease, with the polarity of
the induced emf reversing. ( d i L d t ) is negative now, the polarity of the output voltage, V0
being opposite to that of the input voltage, Vs . The path of the current is through L, parallel
combination of load & C, and diode D, during the time interval, TOFF . The output voltage
remains nearly constant, as the capacitor is connected across the load.
Control Strategies
In all cases, it is shown that the average value of the output voltage can be varied. The two
types of control strategies (schemes) are employed in all cases. These are:
(a) Timeratio control, and (b) Current limit control.
Timeratio Control
In the time ratio control the value of the duty ratio, k = TON / T is varied. There are two ways,
which are constant frequency operation, and variable frequency operation.
Constant Frequency Operation
In this control strategy, the ON time, TON is varied, keeping the frequency ( f = 1 / T ), or
time period T constant. This is also called as pulse width modulation control (PWM). Two cases
with duty ratios, k as (a) 0.25 (25%), and (b) 0.75 (75%) are shown in Fig. 17.4. Hence, the
output voltage can be varied by varying ON time, TON .
T t
V0
v0
k = 0.75
TON TOFF
T t
TON k = 0.25
t
v0
k = 0.75
TON TOFF
T t
(a) Constant TON
v0
T t
v0 Load voltage
TOFF
TON k = 0.75
T t
I max
i0 I min
v0
TON TOFF
t
T
In this lesson, first one in this module (#3), the three basic circuits − buck, boost and buck
boost, of dcdc converters (choppers) are presented, along with the operation and the derivation
of the expressions for the output voltage in each case, assuming continuous conduction. The
different strategies employed for their control are discussed. In the next lesson − second one, the
expression for the maximum and currents for continuous conduction in buck dcdc converter will
be derived.
Introduction
In the last lesson − first one in the module (#3), firstly the circuits of the various types of dc
dc converters (choppers), such as buck, boost and buckboost, were presented. Then, the
operation and the derivation of the expressions for the output voltage for the above dcdc
converters, including current waveforms, were described in detail. Lastly, the different control
strategies used were briefly discussed.
In this lesson − the second one in this module, the analysis of the buck converter (dcdc) or
stepdown chopper circuit, using thyristor as a switching device, with inductive (RL) and
battery (or back emf = E) load, is presented in detail. Starting with the derivation of the
expressions for the maximum and minimum load currents, assuming continuous conduction, the
procedure for the calculation of following expressions ─ the duty ratio for the limit of continuous
conduction, the average value and the ripple factor, of the output (load) current, and the
harmonic components of the output voltage waveform, are described in detail.
Keywords: Buck converter (dcdc), Stepdown chopper, Output (load) current – maximum and
minimum values, average value, ripple factor, harmonic analysis.
A K Switch R
+
+
G
L
Vs V0 +
DF E



Fig. 18.1: Stepdown chopper circuit using thyristor.
Version 2 EE IIT, Kharagpur 3
Ig
0
t
io
0
v0 t
VS
E
0
TON TOFF t
T
(a) Discontinuous load current
Ig
0
t
io
Imax
Imin
0
iT iD t
v0
VS
V0
0
TON TOFF t
∞
⎛ 2V ⎞ ∞
⎛ 2V ⎞
= V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos [ nθ − (n π k ) ]) = V0 + ∑ ⎜ s ⎟ (sin π n k ) ( cos[n (θ − π k )]) The
n =1 ⎝ n π ⎠ n =1 ⎝ n π ⎠
In this lesson ─ the second one in this module, the analysis of the analysis of the buck
converter (dcdc) or stepdown chopper circuit, using thyristor as a switching device, with
inductive (RL) and battery (or back emf = E) load, is presented in detail The procedure for the
derivation of following expressions ─ the maximum and minimum output (load) currents,
assuming continuous conduction, the duty ratio for the limit of continuous conduction, the
average value and the ripple factor, of the output current, and the harmonic components of the
output voltage waveform, are described in detail. Starting with the next lesson ─ the third one in
this module, the operation of the additional circuits needed for commutation in thyristorbased
choppers, with relevant waveforms, will be taken up in detail.
In all practical cases, a negative current flows through the device. This current returns to zero
only after the reverse recovery time trr, when the SCR is said to have regained its reverse
blocking capability. The device can block a forward voltage only after a further tfr, the forward
recovery time has elapsed. Consequently, the SCR must continue to be reversebiased for a
minimum of tfr + trr = tq, the rated turnoff time of the device. The external circuit must therefore
reverse bias the SCR for a time toff > tq. Subsequently, the reapplied forward biasing voltage must
rise at a dv/dt < dv/dt (reapplied) rated. This dv/dt is less than the static counterpart. General
Electric has suggested six classification methods for the turnoff techniques generally adopted
for the SCR. Others have chosen different classification rules.
SCRs have turnoff times rated between 8  50 μsecs. The faster ones are popularly
known as 'Inverter grade' and the slower ones as 'Converter grade' SCRs. The latter are available
at higher current levels while the faster ones are expectedly costlier.
Fig. 3.2 A resonant load commutated SCR and the corresponding waveforms
When the SCR is triggered, anode current flows and charges up C with the dot as positive. The
LCR form a second order underdamped circuit. The current through the SCR builds up and
completes a half cycle. The inductor current will then attempt to flow through the SCR in the
reverse direction and the SCR will be turned off.
Soln # 1
The commutating capacitor is charged to the supply voltage = 100 V
The peak resonant current is,
i peak = V C
L
If the SCR is to commutate at twice this load current, for a rated "Inverter grade' SCR turn
off time of 20 μsecs,
20.20 μF
C=
75
= 15.33 ≈ 15 μF
C
L= = 667 ≈ 700
0.0225 μH
20
The reapplied forward voltage has a dV = = 1.33 volts/sec rise.
dt 15
It can be observed that if the peak of the commutating current is just equal to the load
current, the turnoff time would be zero as the capacitor would not be able to impress any
negative voltage on the SCR.
Fig. 3.4 Class C turnoff, SCR switched off by another loadcarring SCR
The circuit shown in Figure 3.3 (Class C) can be converted to Class D if the load current is
carried by only one of the SCR’s, the other acting as an auxiliary turnoff SCR. The auxiliary
SCR would have a resistor in its anode lead of say ten times the load resistance.
Example 2
SCRA must be triggered first in order to charge the upper terminal of the capacitor as
positive. As soon as C is charged to the supply voltage, SCRA will turn off. If there is substantial
inductance in the input lines, the capacitor may charge to voltages in excess of the supply
voltage. This extra voltage would discharge through the diodeinductorload circuit.
When SCRM is triggered the current flows in two paths: Load current flows through the
load and the commutating current flows through C SCRM LD network. The charge on C is
reversed and held at that level by the diode D. When SCRA is retriggered, the voltage across C
appears across SCRM via SCRA and SCRM is turned off. If the load carries a constant current as
in Fig. 3.4, the capacitor again charges linearly to the dot as positive.
Problem # 2
A Class D turnoff circuit has a commutating capacitor of 10 μF. The load consists of a clamped
inductive load such that the load current is reasonably constant at 25 amperes. The 'Inverter
grade' SCR has a turnoff time of 12 μsecs. Determine whether the SCR will be satisfactorily
commutated. Also dimension the commutating inductor. The supply voltage is 220 VDC.
Assuming that the capacitor charges to 70% of its original charge because of losses in the
C SCRM LD network, and it charges linearly when SCRA is again triggered,
LOAD
energy trapped in the load inductance is dissipated. During the negative half cycle, therefore, the
SCR will turn off when the load current becomes zero 'naturally'. The negative polarity of the
voltage appearing across the outgoing SCR turns it off if the voltage persists for the rated turn
off period of the device. The duration of the half cycle must be definitely longer than the turn
off time of the SCR.
The rectifier in Fig.3.6 is supplied from an single phase AC supply. The commutation
process involved here is representative of that in a three phase converter. The converter has an
input inductance Ls arising manly out of the leakage reactance of the supply transformer.
Initially, SCRs Th1 and Th1' are considered to be conducting. The triggering angle for the
converter is around 600. The converter is operating in the continuous conduction mode aided by
the highlyinductive load.
When the incoming SCRs, Th2 and Th2' are triggered, the current through the incoming
devices cannot rise instantaneously to the load current level. A circulating current Isc builds up in
the shortcircuited path including the supply voltage, VsLsTh1' Th2 and Vs LsTh2'Th1 paths.
This current can be described by:
Vs sin(ωt − 90 0 ) Vs V cos(ωt ) Vs
I sc = + cos α = s + cos α
ωL s ωLs ωLs ωL s
where α the triggering angle and Isc and Vs as shown in Fig. 3.6.
This expression is obtained with the simplifying assumption that the input inductance
contains no resistances. When the current rises in the incoming SCRs, which in the outgoing
Version 2 EE IIT, Kharagpur 10
ones fall such that the total current remains constant at the load current level. When the current in
the incoming ones reach load current level, the turnoff process of the outgoing ones is initiated.
The reverse biasing voltage of these SCRs must continue till they reach their forward blocking
state. As is evident from the above expression, the overlap period is a function of the triggering
angle. It is lowest when α ~ 900. These SCRs being 'Converter grade', they have a larger turnoff
time requirement of about 3050 μsecs.
The period when both the devices conduct is known as the 'overlap period'. Since all
SCRs are in conduction, the output voltage for this period is zero. If the 'fullycontrolled'
converter in Fig. 3.7 is used as an inverter with triggering angles > 900, the converter triggering
can be delayed till the 'margin angle' which includes the overlap angle and the turnoff time of
the SCR  both dependent on the supply voltages.
The majority of inverter applications, however, would result in circuit malfunction due to
dv/dt turnon. One solution to this problem is to reduce the dv/dt imposed by the circuit to a
value less than the critical dv/dt of the SCR being used. This is accomplished by the use of a
circuit similar to those in Figure 3.8 to suppress excessive rate of rise of anode voltage. Z
represents load impedance and circuit impedance. Variations of the basic circuit is also shown
where the section of the network shown replaces the SCR and the RC basic snubber.
Since circuit impedances are not usually well defined for a particular application, the values
of R and C are often determined by experimental optimization. A technique can be used to
simplify snubber circuit design by the use of nomographs which enable the circuit designer to
select an optimized RC snubber for a particular set of circuit operating conditions.
Another solution to the dv/dt turnon problem is to use an SCR with higher dv/dt turnon
problem is to use an SCR with higher dv/dt capability. This can be done by selecting an SCR
designed specially for high dv/dt applications, as indicated by the specification sheet. Emitter
shorting is a manufacturing technique used to accomplish high dv/dt capability.
Ans: (Hints): The capacitor would now charge in an exponential manner. The time it takes to
discharge from its reverse charged state once SCRA is triggered is the circuit turnoff time which
must be in excess of the rated 12 μsecs.
#2 For a Class F converter, will the overlap period rise with the leakage inductance of the
converter? What happens to the output voltage?
Ans: Yes. The overlap time is directly related to the commutating inductance. The output
voltage decreases. In fact, this inductor limits the maximum output current of the converter. The
input current maximum would be as for a shorted network with the leakage inductance only
present.
Ans: Yes. Most of the above circuits are also called 'forced commutated' DCDC chopper
circuits.
20.1 Introduction
The commutation process plays an important role in the operation and control of both
naturally commutated (or line commutated) and forced commutated SCR based converters.
These converters may be either ACDC, DCDC or DCAC converters. The ACDC Phase
Fig. 20.1 Top: A threephase Phase Angle Converter; bottom: The input
threephase voltage waveforms
Angle Converter, (PAC) continues to be used in much high power and very high power
converters where the application is noncritical or the nonstateoftheart is preferred for
operational advantages. The following section discusses commutation with respect to this
application.
Fig. 20.2 Significant voltage and current waveforms of a single phase converter
highlighting the overlap instants and the corresponding converter terminal and
output voltages
Subsequently, at the crossover point, VY becomes most negative and SCR2 is more forward
biased with respect to SCR6. The incoming SCR does not take the full load current IL, nor does
the outgoing SCR turnoff immediately. There ensues an ‘overlap’ period when three SCRs
conduct for a transient period. It is evident that with the simultaneous conduction of SCR2 and
SCR6 there is a short circuit at the converter terminals with the short circuit current ISC being
limited by the perphase series inductances LS. Line voltage VYB drives this current. With no
delay in triggering (as if the SCRs are all replaced by diodes) the SCRs, they would be triggered
600 after the zero crossing of the corresponding line voltage. The triggering on this line voltage is
delayed by the trigger angle αfrom this 600 point.
There are a few significant effects of the commutation process when three devices
conduct. The voltage waveforms at the output and at the converter input terminals reflect the
commutation process. AllSCR (fullycontrolled) converters, which are capable of operating with
trigger angles α between 00 to 1800 ideally, are restricted in the inverter mode to operate within
the ‘marginangle’. This angle is of the order of 1600 and the output voltage is limited.
Fig. 20.3 Short circuit currents between incoming and out going
SCRs for various trigger angles
Example 20.1
A singlephase converter, Fig. 20.2 operates with an input inductance LS = 0.04 mH. Indicate the
current waveforms of the outgoing and incoming phase for trigger angles
α = 450, 900, 1600.Calculate the overlap times for each case and sketch the current waveform in
the incoming SCR pair. The input voltage is 230 V, 50 Hz and the level load current is 15 Amps.
Solution 20.1
The commutating voltage for a single phase converter is the supply voltage itself, 230 V.
When the incoming SCRs (say 2 and 2’) are triggered, the SCR pairs 1, 1’ and 2, 2’ are all
conducting. A short circuit of the supply voltage takes place via the SCRs. A shortcircuiting
current, ISC flows through the SCRs, in the forward mode in 2, 2’ and reverse mode, opposing
the load current, IL in 1, 1’. Current, ISC is initially zero and rises ultimately to load current level
when SCRs 1, 1’ turn off and the overlap time is complete.
VS = 230∠0 0 Volts
Forα = 45 , 90 and 160 0
0 0
Forα = 45 0 ,
Transient component = 73.21sin(90 0 − 45 0 ) = 51.77 Amps
Forα = 90 0 ,
Transient component = 73.21sin(90 0 − 90 0 ) = 0.00 Amps
Forα = 160 0 ,
Transient component = 73.21sin(90 0 − 160 0 ) = −68.80 Amps
In each case the transient current adds up with the steadystate component to give the net
current. Since the transients are all level currents, the steady state component can be considered
to just being shifted up or down by an amount equal to the transient component. Thus for
α = 450, the shift is by +51.77, there is no transient for α = 900, and forα = 1600 the shift is by –
68.80. Note the shape of the relevant portions of the current waveform lying between 0 to IL in
each case. The expressions for each delay angle α is:
= 37.33 0
The two angles are numerically equal as is evident from Fig. Example 20.1.
The threephase converter, Fig. 20.1, has three inductances LS, each in series with each of
the three phases. They are the leakage inductances of the transformer, which may supply other
equipment of the plant too.
Fig. 20.4
The overlap time is dependent on the load current existing during the commutation period and
also the voltage behind the short circuit current. This commutating voltage magnitude is dictated
by the trig