FIGURES FOR APPENDICES

y
r
v

|w|
w
0

Figure C-1 Circle representation in the complex z-plane.

np0

pn (dn)

np( dp)

(dp + Wp)

dp

pn0
dn

dn + Wn

Figure F-1 pn-junction under forward bias.

/4

Port 2

Z0

2Z 0
Port 1

Z0

2Z 0

2Z

Port 3

Z0

/4
(a) Transmission line model
/4
2Z0
Port 1

Z0

Z0

Port 2

Z0

Port 3

2Z0
2Z0
/4

(b) Microstrip line realization

Figure G-1 3 dB Wilkinson power divider.

3.0

10
15

RL1 and IL23, dB

CP12 , dB

IL23
3.1

RL 1

20

3.2

25

3.3

0.5

1.25
0.75
1.0
Normalized frequency, f /f0

1.5

30

0.5

1.25
0.75
1.0
Normalized frequency, f /f0

Figure G-2 Frequency response of Wilkinson power divider.

1.5

VS /2

port 2 Z0

2Z 0
2Z0

port 1

2Z0

port 1

VS /2
+

Z0

Z0

VS /2

2Z

VS /2

port 3

Z0

even mode

odd mode
port 2 Z0

port 2 Z0

2Z 0

2Z0

Z0
o.c.

+
VS /2

2Z 0
2Z0

Z0

+
VS/2

o.c.

(a) Even mode

(b) Odd mode
Figure G-3 Even and odd mode representation of Wilkinson divider (o.c. = open circuit).

Z0 / 2
Port 1

Z0
Z0

Port 4

Z0
/4
/4

Z0

Port 2

Z0
Z0

Port 3

Z0 / 2
Figure G-4 Microstrip line realization of quadrature hybrid.

VS /2

VS /2
+

Port 1

VS /2

Z0

VS /2

/8

Z0

/8 Z0

/8

Z0

/8 Z0

Port 1

Z0 / 2

Z0

Z0

Z0 / 2
Z0

/4

Port 4

Even mode
Z0

Port 2

Z0 / 2

Port 3

Odd mode
Z0

Port 2

Port 1

Z0 / 2

Port 2

+
VS /2

/8

Z0

/8 Z0

Z0

VS /2

/8

Z0

(a) even mode

(b) odd mode
Figure G-5 Building blocks of a branch line coupler.

/8 Z0

Z0

Port 1

Z0

Port 2
/4

/4

/4
Port 3

Z0

Z0

Z0
2Z0
3/4
Figure G-6 A 180 ring coupler.

Port 4

Port 1

Z0

Z0

Port 2

/4

Port 4

Z0

Z0
Figure G-7 A 3 dB Lange coupler.

Port 3

RS
RL = RS
Vn

Figure H-1 Noise voltage of a circuit.

R
(noise free)
R
(noisy)

In

R
(noise free)

Vn
Figure H-2 Equivalent voltage and current models for noisy resistor.

I1

V1

I1

I2
Noisy
network

V2

V1

In1

I2
Noise free
network

Figure H-3 Noisy two-port network and its equivalent representation.

In 2 V2

I1

V1

Vn

I2

In

Noise free
network

V2

Noisy network
Figure H-4 Transformed network model with noise sources at the input.

VnS
RS
VS

V2

RS

Vn

I2
Rin
In

Vin

VS
Figure H-5 Amplifier model and network representation with noise sources.

gVVin V2

P1
ZS

VnS

P2
Vn

VS

In

Pn1

Noise free
network

ZL

Pn2

Figure H-6 Generic noise model for noise figure computation.

Vn

InS

YS

Inc

Inu

Figure H-7 Noise sources modeled at network input.

1
P1

GA1

P2

Pni1
Pn1

2
GA2

Pk

GAk
Pnik

Pni2
Pn2

Pnk

Figure H-8 Cascaded network representation.