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Classifying memory
SRAM Static RAM. A more complex memory cell design with bit
storage implemented using a latch-type mechanism. The stored
data does not have to be refreshed. I/O is asynchronous with
respect to any external system clocks.
Memory = Array
All of the different memory types require both address and data
signals. They differ in the number and the nature of the necessary
control signals.
Memories: terminology
Memories: terminology
Memory architecture
Independent of
memory type, the
typical memory chip
appears as:
The vertical and
horizontal dimensions
are usually very
similar, for an aspect
ratio of unity.
Multiple words are
stored in each row
and selected
simultaneously
A column decoder is
added to select the
desired word from a
row.
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Memory architecture
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Larger memories start to suffer excess delay along bit and word
lines. A third dimension is added to the address space to solve this
problem:
ROM overview
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SRAM - Overview
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Write Timing:
CS_
D
Data In
Write Address
Read Timing:
High Z
Data Out
Read Address
Read Address
OE_
RW_
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Write
Hold Time
Write Setup Time
Read Access
Time
Read Access
Time
DRAM - Overview
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CAS or Column
Address Strobe is a
clock used in
dynamic memories
to control the input
of column
addresses to the
memory.
RAS or Row
Address Strobe is a
clock used in
dynamic memories
to control the input
of row addresses to
the memory
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0x0000-0x0FFF
0x1000-0x1FFF
0x2000-0x2FFF
0x3000-0xFFFF
4K RAM0
4K RAM1
4K RAM2
Vacant
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Full I/O decoding involves checking every single line (ie. all bits) of
the address bus (and the I/O R/W signal eventually) to determine if a
device is selected or not. With Full I/O decoding, each hardware
register is mapped to an unique I/O port address.
Full address decoding is very efficient in the use of the available I/O
address space (one I/O address for one hardware register), but is
often impracticable to use because of the excessive hardware
needed to implement it.
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Partial I/O decoding only checks for a few lines (ie. bits) of the
address bus (and the I/O R/W signal eventually) to determine if a
device is selected or not.
There are caveats to such simple decoding:
Ghost addresses
Since not all the address bus lines are decoded, a device can respond
to several differents I/O address but, more importantly, several devices
can respond to the same ghost address (which may lead to bus conflict,
see below).
Bus conflict
This is a short circuit between two,
or more, devices trying to drive the
DATA bus at the same time.
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GPIOs
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Since the uP only supports eight address lines, the full address is
built up in two transfers on the address bus.
Each address and data byte is stored in a register.
Each address/data transfer is accompanied by a strobe signal. After
the data has been stored in the data latches, the write command is
issued.
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A multiplexed
implementation is the
more common
architecture: sharing
one set of bus lines
between the two
functions (address
and data).
Under such
circumstances, the
addressand data
registers are
necessary for
temporary storage.
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I/O Interface
Control
Register
Data and
Status Registers
Input/Output Device
FFFF
Control Lines
I/O
Memory
Address
Decoder
Control
Circuits
Data and
Status Registers
I/O Interface
0000
Peripheral
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Input/Output Device
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Memory
0000
I/O
0000
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Caching
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Locality
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Cache systems
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The main memory page size is set equal to the cache size;
therefore, each page will contain a corresponding number of blocks.
Block address 0
Block address 1
Block address 0
Block address 1
Block address 0
Block address 1
Block address 0
Block address 1
Block address 0
Block address 1
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The tag table contains one record for each block in the cache (i.e.
for the current design128 entries). Typical information contained in
each record includes:
TAG: A subset of bits from the main memory address identifying the
page (in main memory) where the block originated.
VALID BIT: A flag indicating whether the corresponding block contains
valid data (i.e. just memorized). If the valid bit is TRUE, the block must
be checked for changes before overwriting it.
DIRTY BIT: A flag indicating whether the corresponding block contains
data that has been modified. Cache and main memory must be
coherent. The write through approach propagates any data change
immediately to main memory; the delayed write approach assumes that
if a piece of data changed once, it may change again in the near future.
Thus, time can be saved by not performing (potentially) multiple write
operations to the same data.
TIME: when the block was brought into the cache or when it was last
accessed
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Block address 0
Block address 1
Block address ?
Block address ?
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Process vs Programming
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The ROM stores a particular set of data. If the data are incorrect, the
device is considered to have a failure. Thus, the testing strategy
must address the stuck-at and bridging faults as well as ensuring
that the correct data has been stored.
An effective method for testing ROM memories that can address all
of these issues is based on the CRC or cyclic redundancy check
and is known as signature analysis.