Compal La-9535p r1.0 Schematics

A
Compal Confidential
Model Name : EA/EG50_CX (Z5WE1)
File Name : LA-9535P
1
Compal Confidential
2
EA/EG50_CX (Z5WE1) M/B Schematics Document

Intel Ivy Bridge ULV Processor + Panther Point PCH
Nvidia N14M-GE & N14P-GV2
2013-06-07
REV:1.0
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2013/02/04
EOP
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Rev
1.0
LA-9535P M/B Schematics
Date:
A
Cover Page
Size
Document Number
Custom
Friday, June 07, 2013
Sheet
E
of
55
Fan Control
page 40
204pin DDR3-SO-DIMM X1
1
Nvidia N14P series

with DDR3 x 4
Intel
Ivy Bridge
page 22~28
page 29
CRT Conn.
HDMI Conn.
page 31
Dual Channel
page 4~10
FDI x8
page 30
DMI x4
CLK=100MHz
CLK=100MHz
2.7GT/s
2.97GT/s
2.5GB/s x4
Intel
Panther Point-M
PCIE
PCIe 2.0
5GT/s
port 1
port 2
PCH
989pin BGA
SATA
page 13~21
LAN(GbE)
MINI Card
Boardcom
57786Xpage
WLAN
32~33
SATA3.0
SATA3.0
6.0 Gb/s
6.0 Gb/s
port 0
Touch
Screen
USB 3.0
conn x1
USB 2.0
conn x2
CMOS
Camera
USB port 3
page 29
USB port 0
page 36
USB/B (port 1,2)

page 36
USB port 10
USBx8
48MHz
HD Audio
3.3V 24MHz
page 29
SPI
HDA Codec
ALC3225
page 39
port 2
USB port 8 page 34
SATA HDD
Conn.
SATA CDROM
Conn.
page 35
LPC BUS
page 35
2 in 1
(SD/MMC)
ENE
KB9012
page
page 32~33
SPI ROM x1
CLK=24MHz
Card Reader
RTC CKT.
page 12
BANK 4, 5, 6, 7
LVDS
HDMI x 4 lanes
PCIe 2.0
5GT/s
204pin DDR3-SO-DIMM X1
1.5V DDR3 1333/1600
ULV Processor
BGA1023
eDP
eDP Conn.
page 11
BANK 0, 1, 2, 3
Memory BUS
Int. Speaker
page 13
Int. MIC
page 39
Combo Jack
page 39
page 39
37
Sub Board
page 13
Touch Pad
LS-9531P
Power On/Off CKT.
Int.KBD
page 38
page 38
PWR/B
page 36
page 38
LS-9532P
4
DC/DC Interface CKT.

page 41
USB/B
(port 1,2)
page 36
Power Circuit DC/DC
Deciphered Date
EOP
page 42~52
A
Compal Secret Data

2013/02/04
Issued Date
Title
Block Diagrams
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
of
55
SIGNAL
STATE
Voltage Rails
Power Plane
VIN
Adapter power supply (19V)
S1
S3
S5
N/A
N/A
N/A
BATT+
Battery power supply (12.6V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VGA_CORE
Core voltage for GPU
ON
OFF
OFF
+0.75VS
+0.675VSP to +0.675VS switched power rail for DDR terminator
ON
OFF
OFF
+1.05VSDGPU
+1.0VSDGPU switched power rail for GPU
ON
OFF
OFF
+0.95VSDGPU
+0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU
ON
OFF
OFF
Vcc
Ra/Rc/Re
OFF
Board ID
OFF
+1.5VSDGPU
+1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU
ON
OFF
OFF
+1.8VS
+3VS to 1.8V switched power rail to CPU
ON
OFF
OFF
+1.8VSDGPU
+1.8VS to +1.8VSDGPU switched power rail for GPU
ON
OFF
OFF
+3VALW
+3VALW always on power rail
ON
ON
ON*
+3VLP
B+ to +3VLP power rail for suspend power
ON
ON
ON
0
1
2
3
4
5
6
7
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
+VSB
+VSBP to +VSB always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
Address
Smart Battery
0001 011X
EC SM Bus2 address
Device
HIGH
HIGH
ON
ON
ON
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Address
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
BTO Option Table
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
0.2
0.3
1.0
USB 2.0
Port
PCH SM Bus address
0
1
2
3
4
5
6
7
Address
ChannelA
DIMM0
1001 000x
JDIMM1
DIMM1
1001 010x
JDIMM2
EHCI1
USB 2.0
EHCI2
BOM Config
UMAO: EDP@/IOAC@/BL@/EMC@/UMAO@/
DIS GV2: EDP@/IOAC@/BL@/EMC@/VGA@/
DIS GE: EDP@/IOAC@/BL@/EMC@/VGA@/
CPU config
GC6@/N14PGV2@/GV2GT@/8X@/ CPU config + X76
GC6@/N14MGE@/8X@/
CPU config + X76
USB 3.0 Port

0
1
XHCI
2
3
3 External
USB Port
USB Port(Left 3.0)
USB Port(Right 2.0)
USB Port(Right 2.0)
Touch Screen
Mini Card (WLAN+BT)

Camera
VRAM@
Back light
IOAC
BL@
IOAC@
Celeron 847
847@
Celeron 1007
1007@
I3-3227M
I33227@
I5-3337M
I53337@
I7-3537M
I73537@
UMA ONLY GPIO

EDP
LVDS
UMAO@
EDP@
LVDS@
EMC POP
EMC NON POP
EMC@
XEMC@
Compal Secret Data

2013/02/04
EOP
Deciphered Date
Title
Notes List
Size
Document Number
Custom
Rev
1.0
Date:
A
N14MGE@
N14PGT@
N14PGV2@
GV2GT@
VGA@
128@
16X@
8X@
GC6@
NGC6@
USB Port(Left 3.0)
Issued Date
Unpop VRAM
N14M-GE option
N14P-GT option
N14P-GV2 option
N14P-GT/GV2 Strap
VGA SKU
VRAM x 8pcs
PEG 16X
PEG 8X
GC6
NON GC6
Port
8
9
10
11
12
13
BOM Structure
@
CONN@
SP@
TP@
SPI2@
CPU@
GPU@
USB Port Table
ChannelB
BTO Item
Unpop
Connector
PCH RTC CMOS
TEST PAD
Unpop SPI2
Unpop CPU
Unpop GPU
VGA Internal Thermal Senser 1001 111x (0x9E)
Device
Board ID / SKU ID Table for AD channel
ON
OFF
HIGH
S5 (Soft OFF)
OFF
OFF
ON
S4 (Suspend to Disk)
ON
ON
ON
LOW
ON
ON
Clock
ON
LOW
+1.5V to +1.5VS switched power rail
+3VALW to +3VS power rail
+VS
ON
S3 (Suspend to RAM)
+1.35VP to +1.35V power rail for DDRIIIL
+3VS to +3VSDGPU switched power rail for GPU
+V
HIGH
S1(Power On Suspend)
+1.5V
+3VSDGPU
+VALW
HIGH
HIGH
+1.5VS
+3VS
SLP_S1# SLP_S3# SLP_S4# SLP_S5#

HIGH
Full ON
Description
Sheet
E
of
55
ZZZ
Part Number
DAZ10O00100
LA9535_PCB
Description
PCB Z5WE1 LA-9535P LS-9531P/LS-9532P
REV0 DA6000ZK000
REV1 DA6000ZK010
UCPU1
S IC AV8063801119500 SR0XF L1 1.9G ABO!

I33227@
SA00006D990
1. PEG_RCOMPO and PEG_ICOMPI should be connected together with 4-mil width first. Then be connected to R1 from ball of PEG_ICOMPI.
2. PEG_ICOMPO should be connected to R1 with width 12-mil.
3. No longer than 500-mil to above two.
AV8063801119500 SR0XF L1 1.9G ABO!

1
UCPU1
S IC AV8063801129900 SR0XL L1 1.8G ABO!

I53337@
SA00006D860
+1.05VS_VTT
PEG_GTX_HRX_P[0..15]
1
AV8063801129900 SR0XL L1 1.8G ABO!

UCPU1
R1
SA00006DB90
24.9_0402_1%
PEG_HTX_C_GRX_P[0..15]
UCPU1A
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
AV8063801119700 SR0XG L1 2G ABO!

UCPU1
S IC AV8062700852800 SR08N Q0 1.1G ABO!

SA00005VK20
UCPU1
S IC AV8063801118700 SR109 P0 1.5G ABO!

1007@
SA00006EW30
AV8063801118700 SR109 P0 1.5G ABO!
IVY BRIDGE
UCPU1
S IC AV8063801130300 SR10A P0 1.6G ABO!

1017@
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
15
15
15
15
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
15
15
15
15
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
N3
P7
P3
P11
K1
M8
N4
R2
K3
M7
P4
T3
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
UCPU1
S IC AV8063801058800 SR0VQ P0 1.8G ABO!
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
SA000061240
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
15
15
15
15
15
15
15
15
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
U7
W11
W1
AA6
W6
V4
Y2
AC9
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
UCPU1
S IC AV8063801119100 SR105 P0 1.9G ABO!

SA00006UG30
AV8063801119100 SR105 P0 1.9G ABO!

UCPU1
S IC AV8063801058401 SR0N9 L1 1.8G ABO!
+1.05VS_VTT
AV8063801058401 SR0N9 L1 1.8G ABO!

R66
1K_0402_5%
EDP@
HM77@
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
15
15
FDI_LSYNC0
FDI_LSYNC1
AA11
AC12
U11
AA10
AG8
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
FDI0_LSYNC
FDI1_LSYNC
24.9_0402_1%
CPU_EDP_HPD#
AF3
AD2
AG11
EDP_AUXN
EDP_AUXP
AG4
AF4
EDP_TXN0
EDP_TXN1
AC3
AC4
AE11
AE7
EDP_TXP0
EDP_TXP1
AC1
AA4
AE10
AE6
EDP_COMP
SA00005AGI0
29
15
15
15
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
R2
2
S IC BD82HM77 SLJ8C C1 BGA 989P PCH ABO!
U1010
3
SA00005L5C0
1
I33217@
U6
W10
W3
AA7
W7
T4
AA3
AC8
Intel(R) FDI
15
15
15
15
15
15
15
15
AV8063801058800 SR0VQ P0 1.8G ABO!
2127@
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
SA00006UH50
AV8063801130300 SR10A P0 1.6G ABO!
2117@
15
15
15
15
M2
P6
P1
P10
DMI
AV8062700852800 SR08N Q0 1.1G ABO!
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
CPU_EDP_HPD#
PCI EXPRESS -- GRAPHICS
847@
15
15
15
15
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
BD82HM77 SLJ8C C1 BGA 989P PCH ABO!

29
29
U1010
HM70@
SA00005MQ60
EDP_AUXN
EDP_AUXP
29
29
EDP_TXN0
EDP_TXN1
29
29
EDP_TXP0
EDP_TXP1
BD82HM70 SJTNV C1 BGA 989P PCH ABO !

U1010
S IC BD82NM70 SLJTA C1 BGA 989P PCH ABO!

NM70@
SA00005WU20
BD82NM70 SLJTA C1 BGA 989P PCH ABO!
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP
S IC BD82HM70 SJTNV C1 BGA 989P PCH ABO !
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
G3
G1
G4
PEG_COMP
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0
PEG_HTX_C_GRX_N[0..15]
I73537@
PEG_GTX_HRX_N[0..15]
S IC AV8063801119700 SR0XG L1 2G ABO!
C1
C2
C3
C4
C5
C6
C7
C8
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
8X@
8X@
8X@
8X@
8X@
8X@
8X@
8X@
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PEG_GTX_HRX_N7
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
PEG_GTX_HRX_N4
PEG_GTX_HRX_N3
PEG_GTX_HRX_N2
PEG_GTX_HRX_N1
PEG_GTX_HRX_N0
PEG_GTX_HRX_P[0..15]
22
PEG_GTX_HRX_N[0..15]
22
PEG_HTX_C_GRX_P[0..15]
22
PEG_HTX_C_GRX_N[0..15]
22
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0
C9
C10
C11
C12
C13
C14
C15
C16
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
8X@
8X@
8X@
8X@
8X@
8X@
8X@
8X@
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PEG_GTX_HRX_P7
PEG_GTX_HRX_P6
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
PEG_GTX_HRX_P3
PEG_GTX_HRX_P2
PEG_GTX_HRX_P1
PEG_GTX_HRX_P0
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0
C17
C18
C19
C20
C21
C22
C23
C24
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
8X@
8X@
8X@
8X@
8X@
8X@
8X@
8X@
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0
C25
C31
C27
C28
C29
C30
C33
C32
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
8X@
8X@
8X@
8X@
8X@
8X@
8X@
8X@
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0
IVY-BRIDGE_BGA1023
CPU@
PCH
eDP_COMPIO and eDP_ICOMPO should be connected to R247 respectively.
eDP_COMPIO
Trace Width to R2= 4-mil
Trace Spacing to Other Signals= 15-mil
Max. Routing Length= 500-mil
eDP_ICOMPO
Trace Width to R2= 12-mil
Trace Spacing to Other Signals= 15-mil
Routing Length= 500-mil
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(1/7) DMI,FDI,PEG
Sheet
E
of
55
UCPU1B
C57
37,49
R5
H_CATERR#
C49
H_PECI
A48
H_PECI
1 62_0402_5%
R7
56_0402_5%
1
2
H_PROCHOT#
H_PROCHOT#
PAD
18
H_PROCHOT#_R
C45
D45
H_THRMTRIP#
PECI
PROCHOT#
H_PM_SYNC
C48
PM_SYNC
10K_0402_5%
H_CPUPWRGD
H_CPUPWRGD
B46
UNCOREPWRGOOD
Daisy chain
PM_DRAM_PWRGD_R
BUF_CPU_RST#
RESERVED for ESD

H_CPUPWRGD
H_PROCHOT#
BE45
D44
SM_DRAMPWROK
RESET#
H_PECI
1
C34 XEMC@
0.1U_0402_16V7K
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PRDY#
PREQ#
TCK
TMS
TRST#
JTAG & BPM
R11
18
15
AG3 DPLL_REF_CLK
AG1 DPLL_REF_CLK#
For LVDS
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_CLK 14
DPLL_REF_CLK#
14
R517
R518
2 LVDS@ 1 1K_0402_5%
2 LVDS@ 1 1K_0402_5%
+1.05VS_VTT
AT30
SM_DRAMRST#
BF44
BE43
BG43
SM_RCOMP0 R6
SM_RCOMP1 R8
SM_RCOMP2 R9
SM_DRAMRST#
2
2
2
Width
Spacing
Length
SM_RCOMP0
20-mil
20-mil
< 500-mil
SM_RCOMP1
20-mil
20-mil
< 500-mil
SM_RCOMP2
15-mil
20-mil
< 500-mil
1 140_0402_1%
1 25.5_0402_1%
1 200_0402_1%
THERMTRIP#
PWR MANAGEMENT
C state information
care should be taken to no stub caused by R11 by this resistor
14
14
If use External Graphic or

use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
SM_DRAMRST#
THERMALTRIP# will be asserted when CPU junction

temperature exceeds approximately 130 C
2
CLK_CPU_DMI
CLK_CPU_DMI#
CATERR#
THERMAL
37
+1.05VS_VTT
T2
PROC_DETECT#
DPLL_REF_CLK
DPLL_REF_CLK#
J3
H2
TDI
TDO
N53
N55
+3VS
L56
L55
J58
XDP_TCK
XDP_TMS
XDP_TRST#
PAD
PAD
PAD
T7
T3
T4
TP@
TP@
TP@
M60
L59
XDP_TDI
XDP_TDO
PAD
PAD
T5
T6
TP@
TP@
K58
XDP_DBRESET#
R10
1K_0402_5%
2
TP@
PROC_SELECT#
BCLK
BCLK#
F49
H_SNB_IVB#
MISC
17
CLOCKS
For 2nd Generation IntelR Core processor family mobile, the output will be high.
For Mobile 3rd Generation IntelR Core processor family, the output will be low.
DDR3
MISC
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
XDP_DBRESET#
G58
E55
E59
G55
G59
H60
J59
J61
15
C37 XEMC@
0.1U_0402_16V7K
Reserved for ESD
1
C65 XEMC@
0.1U_0402_16V7K
C68 XEMC@
0.1U_0402_16V7K
IVY-BRIDGE_BGA1023
CPU@
+3VALW
SM_DRAMPWROK
Buffered Reset to CPU
+3VS
+1.5VS
1
+1.05VS_VTT
PM_SYS_PWRGD_BUF
1
R15
2
PM_DRAM_PWRGD_R
130_0402_5%
17,37
PLT_RST#
PLT_RST#
Y
A
MC74VHC1G09DFT2G_SC70-5
NC
R14
75_0402_5%
U4
SYS_PWROK
PM_DRAM_PWRGD
U1
BUFO_CPU_RST#
R17
43_0402_1%
1
2
BUF_CPU_RST#
15
15
G VCC
R13
200_0402_5%
SN74LVC1G07DCKR_SC70-5
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(2/7) PWR MANAGMENT

Sheet
E
of
55
UCPU1C
UCPU1D
12
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
11
11
11
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
BD37
BF36
BA28
BE39
BD39
AT41
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
11
11
11
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
AU36
AV36
AY26
AT40
AU40
BB26
BB40
BC41
AY40
BA41
SA_CLK_DDR0 11
SA_CLK_DDR#0 11
DDRA_CKE0_DIMMA
11
SA_CLK_DDR1 11
SA_CLK_DDR#1 11
DDRA_CKE1_DIMMA
11
DDRA_CS0_DIMMA#
DDRA_CS1_DIMMA#
11
11
SA_ODT0
SA_ODT1
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_B_D[0..63]
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
11
11
DDR_A_DQS#[0..7]
11
DDR_A_DQS[0..7]
DDR_A_MA[0..15]
11
11
12
12
12
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
12
12
12
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
BG39
BD42
AT22
AV43
BF40
BD45
IVY-BRIDGE_BGA1023
CPU@
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
SB_ODT[0]
SB_ODT[1]
DDR SYSTEM MEMORY B
DDR_A_D[0..63]
DDR SYSTEM MEMORY A
11
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
BA34
AY34
AR22
BA36
BB36
BF27
BE41
BE47
AT43
BG47
SB_CLK_DDR0 12
SB_CLK_DDR#0 12
DDRB_CKE0_DIMMB
12
SB_CLK_DDR1 12
SB_CLK_DDR#1 12
DDRB_CKE1_DIMMB
12
DDRB_CS0_DIMMB#
DDRB_CS1_DIMMB#
12
12
SB_ODT0
SB_ODT1
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
12
12
DDR_B_DQS#[0..7]
12
DDR_B_DQS[0..7]
12
DDR_B_MA[0..15]
12
IVY-BRIDGE_BGA1023
CPU@
+1.5V
R19
1K_0402_5%
SM_DRAMRST#
R21
4.99K_0402_1%
DIMM_DRAMRST#_R
Q1
LBSS138LT1G_SOT-23-3
RST_GATE_R
14
RST_GATE
2
R176
100K_0402_5%
C38
0.047U_0402_16V7K
1
R20
2
1K_0402_5%
S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
DRAM not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# Low,DDR3 DRAMRST# HIGH
DRAM not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
DRAM reset
DIMM_DRAMRST#
1
11,12
C2066
0.1U_0402_16V4Z
SM_DRAMRST#
XEMC@
RESERVED for ESD
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(3/7) DDRIII
Sheet
E
of
55
CFG Straps for Processor

current placement need to support
PEG bus lan reversal
1
CFG2
R23
1K_0402_1%
VGA@
UCPU1E
PCIe Static x16 Lane Numbering Reversal
PAD
TP@
TP@
T49
T50
PAD
PAD
VCC_VAL_SENSE
VSS_VAL_SENSE
H43
K43
TP@
TP@
T51
T52
PAD
PAD
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
H45
K45
TP@
F48
T9
PAD
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
CFG2
N42
L42
L45
L47
RSVD30
RSVD31
RSVD32
RSVD33
M13
M14
U14
W14
P13
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
CFG4
AT49
K24
RSVD39
RSVD40
R550 EDP@
1K_0402_1%
AH2
AG13
AM14
AM15
RSVD41
RSVD42
RSVD43
RSVD44
check VGA 8lane or 16lane?

CFG5
N50
RSVD45
These pins are for solder joint

reliability and non-critical to
function. For BGA only.
VCC_DIE_SENSE
H48
K48
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
1: (Default)Normal Operation
Lane # definition matches socket pin map definition
0: Lane Reversed
T53
BCLK_ITP
BCLK_ITP#
TP@
CFG4
CFG5
CFG6
CFG7
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
CFG6
By 3/12
1
CFG2
N59
N58
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
CFG0
R544
1K_0402_1%
@
DC_TEST_C4_D3
R541
1K_0402_1%
VGA@
2
PAD
T8
RESERVED
TP@
DC_TEST_A59_C59
DC_TEST_A61_C61
eDP Enable Strap

DC_TEST_BE59_BE61
DC_TEST_BG59_BG61
CFG4
1: (Default)Disable
*0: Enable
DC_TEST_BE3_BG3
PCIE Port Bifurcation Straps
DC_TEST_BE1_BG1
CFG[6:5]
IVY-BRIDGE_BGA1023
CPU@
11:
10:
01:
00:
(Default) 1x16 PCI Express

2x8 PCI Express
Reserved
1x8,2x4 PCI Express
PEG DEFER TRAINING

CFG7
4
1: (Default) PEG Trains immediately and follows

xxRESETB de-assertion
0: PEG Wait for BIOS for training
2013/02/04
EOP
Deciphered Date
Title
PROCESSOR(4/7) RSVD,CFG
Size
Document Number
Custom
Rev
1.0
Date:
A
Compal Secret Data
Issued Date
Tacoma_Fall2 1.0 P.12
Sheet
E
of
55
UCPU1F
POWER
+1.05VS_VTT
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
+1.05VS_VTT
VCCIO50
VCCIO51
W16
W17
reserve via
VCCIO_SEL
BC22
VCCIO_SEL
PAD
TP@
T41
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
C39
1U_0402_6.3V6K
R34
130_0402_5%
CPU Power Rail Table
R35
75_0402_5%
2
AM25
AN22
VCCPQE[1]
VCCPQE[2]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
PEG IO AND DDR IO
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
QUIET
RAILS
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
CORE SUPPLY
+CPU_CORE
VIDALERT#
VIDSCLK
VIDSOUT
A44
B43
C44
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DAT
R36
2 43_0402_1%
VR_SVID_ALRT#
49
VR_SVID_CLK
49
VR_SVID_DAT 49
Voltage Rail
Voltage
VCC
S0 Iccmax
Current(A)
0.65~1.2
33
Processor Core Voltage
VCCIO
1.05
8.5
Processor Uncore Voltage
VDDQ
1.5
Memory Controller Voltage
VCCSA
0.675~0.9
System Agent Voltage
VCCPLL
1.8
1.2
Processor PLL Voltage
0.65~1.25
29
Processor Graphics Voltage
+CPU_CORE
1
SVID
Place the PU resistors close to CPU
R39
100_0402_1%
VCCSENSE
VSSSENSE
R42
AN16
AN17
VCCSENSE
VSSSENSE
2 10_0402_5%
+1.05VS_VTT
VCCIO_SENSE
VSSIO_SENSE
1
VCCIO_SENSE
VSS_SENSE_VCCIO
F43
G43
49
49
VAXG
VCC_SENSE
VSS_SENSE
R43
100_0402_1%
48
Refer to Mobile 3rd Generation IntelR Core Processor Family External Design
Specification (EDS) Volume 1 of 2 Revision 2.2
SENSE LINES
Place the PU resistors close to VR
R44
10_0402_5%
IVY-BRIDGE_BGA1023
CPU@
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(5/7) PWR,BYPASS
Sheet
E
of
55
+1.5VS
1
POWER
R45
1K_0402_5%
BE7
BG7
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREF
1
C44
0.1U_0402_16V7K
C53
C48
C49
1
2
1
2
1
2
1
2
1
2
C46
1
+
C50
330U_2.5V_M
Place BOT OUT BGA

@
1
C58
1
2
1
2
1
2
C57
10U_0603_6.3V6M
C60
10U_0603_6.3V6M
C55
10U_0603_6.3V6M
C54
10U_0603_6.3V6M
C56
1
- 1.5V RAILS
C45
1U_0402_6.3V6K
C47 @
1U_0402_6.3V6K
DDR3
Place TOP IN BGA

@
Follow VDDQ 1.5V-Rail Decoupling Recommendation from Intel PDDG Rev 1.0,
1. 1x 330uF
2. 8x 10uF (0603)
+1.5VS
3. 10x 1uF (0402)
1U_0402_6.3V6K
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
1U_0402_6.3V6K
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
R46
1K_0402_5%
PAD
PAD
T47
T48
TP@
TP@
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
10U_0603_6.3V6M
+V_SM_VREF
10U_0603_6.3V6M
+VGFX_CORE
+V_SM_VREF should be 20-mil trace width and 20-mil spacing
AY43
1U_0402_6.3V6K
SM_VREF
5A
GRAPHICS
VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]
1U_0402_6.3V6K
AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61
DC 29A
UCPU1G
+VGFX_CORE
Part Number
SF000002Z00
Description
ESR
S_A-P_CAP 330U 2.5V M 6.3X4.2 R17M VLPS
17m
2
R54
+1.5VS
BB3
BC1
BC4
1
1
2
+VCCSA
Place TOP IN BGA

+VCCSA
@
1
2
1
2
1
2
C78
1U_0402_6.3V6K
C84
1U_0402_6.3V6K
C67
1U_0402_6.3V6K
100U_1206_6.3V6M
C66
1U_0402_6.3V6K
C423
@
1
2
1
2
1
2
1
2
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]
1
2
QUIET RAILS
C59
1U_0402_6.3V6K
*For ULV Only

VID[0] ball D48
BC43
BA43
VDDQ_SENSE
VSS_SENSE_VDDQ
VID[1] ball D49
VCCSA Output
0.9V
0.85V
0.775V
0.75V
U10
VCCSA_SENSE
D48
D49
VCCSA_VID[0]
VCCSA_VID[1]
H_VCCSA_VID0
H_VCCSA_VID1
H_VCCSA_VID0
H_VCCSA_VID1
47
47
Follow VCCSA Plane Decoupling Recommendations from Intel PDDG Rev 1.0,
1. 1x 330uF
2. 5x 10uF (0603)
3. 5x 1uF (0402)
C81
10U_0603_6.3V6M
C82
10U_0603_6.3V6M
C80
10U_0603_6.3V6M
10U_0603_6.3V6M
C83
6A
VCCPLL[1]
VCCPLL[2]
VCCPLL[3]
AM28
AN26
VCCDQ[1]
VCCDQ[2]
IVY-BRIDGE_BGA1023
CPU@
Place BOT OUT BGA

<BOM Structure>
C79
1U_0402_6.3V6K
C61
1U_0402_6.3V6K
C85
@
100U_1206_6.3V6M
1.2A
SA RAIL
100_0402_5%
1.8V RAIL
R52
VCCPLL Plane Decoupling Recommendation from Intel PDDG Rev 1.0,

1. 1x 330uF
+1.8VS
2. 2x 1uF (0402)
SENSE LINES
VAXG_SENSE
VSSAXG_SENSE
VCCSA VID
lines
F45
G45
49 VCC_AXG_SENSE
49 VSS_AXG_SENSE
SENSE
LINES
100_0402_5%
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(6/7) PWR
Sheet
E
of
55
UCPU1H
UCPU1I
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13
BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS
NCTF
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
IVY-BRIDGE_BGA1023
CPU@
IVY-BRIDGE_BGA1023
CPU@
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PROCESSOR(7/7) VSS
Sheet
E
10
of
55
+V_DDR_REFA
+1.5V
+1.5V
JDIMM1
+V_DDR_REFA
DDR_A_D0
DDR_A_D1
DDR_A0_DM0
2
1
DDR_A_DQS#[0..7]
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D16
DDR_A_D17
6
6
DDR_A_MA[0..15]
DDR_A_D2
DDR_A_D3
DDR_A_D10
DDR_A_D11
DDR_A_DQS[0..7]
DDR_A_D[0..63]
C105
0.1U_0402_16V7K
C86
2.2U_0402_6.3V6M
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
+1.5V
DDR_A0_DM3
DDR_A_D26
DDR_A_D27
@
1
C103
1U_0402_6.3V6K
C106
1U_0402_6.3V6K
C100
1U_0402_6.3V6K
C91
1U_0402_6.3V6K
DDRA_CKE0_DIMMA
DDRA_CKE0_DIMMA
DDR_A_BS2
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
2
Should be as close as possible to sink of JDIMM1
+1.5V
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
C98
10U_0603_6.3V6M
C93
10U_0603_6.3V6M
C109
10U_0603_6.3V6M
C87
10U_0603_6.3V6M
6
6
+1.5V
SA_CLK_DDR0
SA_CLK_DDR#0
SA_CLK_DDR0
SA_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_BS0
6
6
DDR_A_WE#
DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
DDR_A_MA13
DDRA_CS1_DIMMA#
DDRA_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
1
+
C101
330U_2.5V_M
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
Part Number
SF000002Z00
+0.75VS
17m
DDR_A0_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
C94
1U_0402_6.3V6K
ESR
Should be as close as possible to sink of JDIMM1.203 and JDIMM1.204
C104
1U_0402_6.3V6K
Description
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A0_DM7
DDR_A_D58
DDR_A_D59
+3VS
+0.75VS
205
1
C102
0.1U_0402_16V7K
DDR_A0_DM0
DDR_A0_DM1
DDR_A0_DM2
DDR_A0_DM3
DDR_A0_DM4
DDR_A0_DM5
DDR_A0_DM6
DDR_A0_DM7
G1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
+1.5V
All VREF_DQ and VREFCA should be rounted with width

at least 20-mil and with spacing at-least 20-mil.
+VREF_CA
+VREF_CA
1. +V_DDR_REFA
2. +VREF_CA
+V_DDR_REFA
8
7
6
5
1K_0804_8P4R_1%
DDR_A0_DM1
DIMM_DRAMRST#
DIMM_DRAMRST#
12,6
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A0_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDRA_CKE1_DIMMA
DDRA_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
2
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
SA_CLK_DDR1
SA_CLK_DDR#1
SA_CLK_DDR1 6
SA_CLK_DDR#1 6
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1 6
DDR_A_RAS#
6
DDRA_CS0_DIMMA#
SA_ODT0
DDRA_CS0_DIMMA#
SA_ODT0 6
SA_ODT1
SA_ODT1
+VREF_CA
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A0_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
@
1
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A0_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA 12,14
D_CK_SCLK 12,14
+0.75VS
JDIMMA (Channel A) H4 Slot RVS TYPE
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
DDRIII DIMMA
Size
Document Number
Custom
Rev
1.0
Date:
A
RP33
1
2
3
4
+V_DDR_REFA
FOX_AS0A626-U4RN-7F
CONN@
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C90
2.2U_0402_6.3V6M
C107
10U_0603_6.3V6M
C96
10U_0603_6.3V6M
C88
10U_0603_6.3V6M
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
C92
0.1U_0402_16V7K
@
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Sheet
E
11
of
55
RP 1% P/N SD300002V00
+1.5V
+V_DDR_REFB
+1.5V
+1.5V
JDIMM2
+V_DDR_REFB
DDR_B_D0
DDR_B_D1
DDR_B0_DM0
1
DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
DDR_B_D[0..63]
C127
0.1U_0402_16V7K
C110
2.2U_0402_6.3V6M
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_MA[0..15]
DDR_B_D2
DDR_B_D3
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
+1.5V
@
1
DDR_B_D26
DDR_B_D27
C125
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
C122
1U_0402_6.3V6K
2
2
C115
1U_0402_6.3V6K
DDR_B0_DM3
DDRB_CKE0_DIMMB
DDRB_CKE0_DIMMB
DDR_B_BS2
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
Should be as close as possible to sink of JDIMM2
+1.5V
DDR_B_MA3
DDR_B_MA1
C121
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C131
10U_0603_6.3V6M
C112
10U_0603_6.3V6M
DDR_B_MA8
DDR_B_MA5
6
6
6
6
6
+1.5V
DDR_B_WE#
DDR_B_CAS#
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDRB_CS1_DIMMB#
DDRB_CS1_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B0_DM5
DDR_B_D42
DDR_B_D43
+0.75VS
DDR_B_D48
DDR_B_D49
Should be as close as possible to sink of JDIMM2.203 and JDIMM2.204

1
C113
1U_0402_6.3V6K
C130
1U_0402_6.3V6K
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B0_DM7
DDR_B_D58
DDR_B_D59
+3VS
205
1
C124
0.1U_0402_16V7K
DDR_B0_DM0
DDR_B0_DM1
DDR_B0_DM2
DDR_B0_DM3
DDR_B0_DM4
DDR_B0_DM5
DDR_B0_DM6
DDR_B0_DM7
+0.75VS
G1
CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
+VREF_CB
DDR_B_D4
DDR_B_D5
+V_DDR_REFB
All VREF_DQ and VREFCA should be rounted with width

at least 20-mil and with spacing at-least 20-mil.
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
RP32
+V_DDR_REFB
DDR_B0_DM1
DIMM_DRAMRST#
DIMM_DRAMRST#
11,6
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B0_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31
DDRB_CKE1_DIMMB
DDRB_CKE1_DIMMB
6
2
DDR_B_MA15
DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
SB_CLK_DDR1
SB_CLK_DDR#1
SB_CLK_DDR1 6
SB_CLK_DDR#1 6
DDR_B_BS1
DDR_B_RAS#
DDR_B_BS1 6
DDR_B_RAS#
6
DDRB_CS0_DIMMB#
SB_ODT0
DDRB_CS0_DIMMB#
SB_ODT0 6
SB_ODT1
SB_ODT1
+VREF_CB
+VREF_CB
DDR_B_D36
DDR_B_D37
@
1
DDR_B0_DM4
DDR_B_D38
DDR_B_D39
DDR_B_D44
DDR_B_D45
DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B0_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
D_CK_SDATA
D_CK_SCLK
D_CK_SDATA 11,14
D_CK_SCLK 11,14
+0.75VS
JDIMMB (Channel B) H4 RVS TYPE Slot
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
DDRIII DIMMB
Size
Document Number
Custom
Rev
1.0
Date:
A
8
7
6
5
1K_0804_8P4R_1%
1. +V_DDR_REFB
2. +VREF_CB
DDR_B_D12
DDR_B_D13
1
2
3
4
+VREF_CB
FOX_AS0A626-U4RN-7F
CONN@
CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1
VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26
C116
0.1U_0402_16V7K
DDR_B_BS0
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C111
2.2U_0402_6.3V6M
DDR_B_MA10
DDR_B_BS0
C128
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
2
3
C114
10U_0603_6.3V6M
SB_CLK_DDR0
SB_CLK_DDR#0
SB_CLK_DDR0
SB_CLK_DDR#0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Sheet
E
12
of
55
+RTCBATT
D3
BAS40-04_SOT23-3
2 1M_0402_5%
SM_INTRUDER#
2 330K_0402_5%
PCH_INTVRMEN
* H: Integrated VRM enable
R78
for DcpSus well
+CHGRTC
R77
INTVRMEN(Internal Voltage Regulator Enable)
+RTCVCC
+RTCVCC
20mil
20mil
+3VS
L: Integrated VRM disable
C136
20mil
0.1U_0402_16V4Z
RP23
1
2
3
4
SERIRQ
PCH_SATALED#
JME2 should
be placed close to JDIMM1
14
PCH_GPIO20
PCH_GPIO20
8
7
6
5
10K_0804_8P4R_5%
2 20K_0402_5%
PCH_RTCRST#
D20
R83
2 20K_0402_5%
PCH_SRTCRST#
G22
SM_INTRUDER#
K22
PCH_INTVRMEN
C17
RTCX2
RTCRST#
FWH4 / LFRAME#
SRTCRST#
PCH_RTCX1
PCH_RTCX2
C138
1U_0603_10V6K
Y1
1
2
10M_0402_5%
1
R84
JME1
SHORT PADS
SP@
HDA_BITCLK_PCH
N34
HDA_SYNC_PCH
L34
PCH_SPKR
T10
HDA_RST_PCH#
K34
HDA_SDIN0
E34
INTRUDER#
C139
18P_0402_50V8J
HDA_BCLK
39
C142
15P_0402_50V8J
PCH_SPKR
HDA_SYNC
SPKR
HDA_RST#
2
HDA_SDIN0
G34
HDA_SDIN1
C34
+3VALW_PCH
R88
A34
1 1K_0402_5%
HDA_SYNC_PCH
On-Die PLL Voltage Regulator Voltage Select
R90
51_0402_5%
2
1
PCH_JTAG_TCK
J3
PAD
T10 TP@
PCH_JTAG_TMS
H7
PAD
T11 TP@
PCH_JTAG_TDI
K5
PAD
T12 TP@
PCH_JTAG_TDO
H1
for HDA_SYNC Potential Leakage Concern
Q4
1
2
3
4
R95
1M_0402_5%
2 1K_0402_5%
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TCK
JTAG_TMS
JTAG_TDI
SATAICOMPO
SATAICOMPI
JTAG_TDO
SATA3RCOMPO
33_0804_8P4R_5%
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_DOCK_RST# / GPIO13
HDA_SYNC_PCH
+3VS
R101 1
HDA_DOCK_EN# / GPIO33
N32
+5VS
HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
HDA_SDOUT_AUDIO
HDA_SDO
C36
for VccVRM
RP26 EMC@
8
HDA_BITCLK_PCH
7
HDA_SYNC_PCH_R
6
HDA_RST_PCH#
5
HDA_SDOUT_PCH
HDA_SDIN3
A36
HDA_SDOUT_PCH
* H: 1.5V for VccVRM (for Mobile platform)

L: 1.8V for VccVRM (for Desktop platform), weak internal pull low
39
39
39
39
HDA_SDIN2
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA
HDA_SDIN0
IHDA
39
JTAG
SERIRQ
PCH_SPKR
PCH_SPI_CLK_2
R97
2 XEMC@ 1
PCH_SPI_CLK_1
R99
2 EMC@ 1
SATA3COMPI
33_0402_5%
PCH_SPI_CLK
T3
PCH_SPI_CS0#
Y14
PCH_SPI_CS1#
T1
PCH_SPI_MOSI
V4
PCH_SPI_MISO
U3
SPI_CLK
33_0402_5%
follow design guide 2.0 to cancel series resistor
PCH_SPI_MOSI_2
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_SPI_MISO_2
R151
R159
R160
R184
2 SPI2@
2
2
2 SPI2@
1
1
1
1
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
D36
LPC_FRAME#
E36
K36
PCH_GPIO23
V5
SERIRQ
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
37
37
37
37
LPC_FRAME#
1
R87
SERIRQ
AM3
AM1
AP7
AP5
37
2 10K_0402_5%
37
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
35
35
35
35
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
35
35
35
35
HDD Connector (JHDD1)
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
ODD Connector (JODD1)
As Intel's definition, SATA Port 1 and Port 3 is diabled by

HM70 NM70
SATAICOMPO and SATACOMPI should be connected together then to R121.

SATA3ICOMPO and SATA3COMPI should be connected together then to R440.
Trace Impedance= 50-ohm
Keep-out to other Signals, especially to CLK= 15-mil
+1.05VS_VTT
Y11
Y10
SATA_COMP
+3VS
2
37.4_0402_1%
R92
R259
10K_0402_5%
+1.05VS_VTT
AB12
AB13
SATA3_COMP
R98
2
49.9_0402_1%
AH1
1
RBIAS_SATA3
R100
2
750_0402_1%
SGEN#
R258
10K_0402_5%
@
SPI_CS0#
SPI_CS1#
No Reboot
H: enable "No Reboot" mode
L: disable "No Reboot" mode (default by weak internal PD)
SATA3RBIAS
SPI
LDRQ0#
LDRQ1# / GPIO23
INTVRMEN
32.768K 12.5PF 1TJF125DP1A000D
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
R85
RTCX1
C20
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
PCH_RTCX2
C38
A38
B37
C37
SPI_MOSI
SATALED#
SATA0GP / GPIO21
SPI_MISO
SATA1GP / GPIO19
P3
PCH_SATALED#
V14
SGEN#
P1
PCH_GPIO19
PCH_SATALED#
38
GPIO21
SGEN#
COUGARPOINT_FCBGA989
PCH@
Switchable GPU
* Non-Switchable
HDA_SDOUT_PCH
HDA_SDOUT_PCH
+3VALW_PCH
+3VALW_PCH
Flash Descriptor Security Override /Intel ME Debug Mode
1
2
3
4
8MB SPI ROM
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DI
8
7
6
5
+3VS
SPI_HOLD1#
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
2
R105
1
3.3K_0402_5%
R106
4.7K_0402_5%
EN25QH64-104HIP_SO8
SA00006MK00
+3VALW_PCH
PCH_GPIO19
U15
+3VALW_PCH
C141
10P_0402_50V8J
1
2
2
R109
XEMC@
Reserve for EMI

1 PCH_SPI_CLK
XEMC@ 33_0402_5%
R107 1 SPI2@
R108 1 SPI2@
2 3.3K_0402_5%
2 3.3K_0402_5%
PCH_SPI_CS1#
SPI_WP2#
SPI_HOLD2#
1MB SPI ROM for Win8 supported

still use PCB footprint of 4GB ROM (is the same,
after check spec), but change the part number
for load BOM
1
3
7
4
CS#
WP#
HOLD#
GND
VCC
SCLK
SI
SO
8
6
5
2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
BIOS request stuff 1023
S IC FL 8M W25Q80BVSSIG SOIC 8P
SPI2@
Issued Date
In accordance with design guide 2.0 page 274, if default

boot destination is SPI, no external pull-up/-down resistors
on the board are necessary.
Routing
GTN1#/GPIO51 (BBS1)
2013/02/04
Reserved
LPC
* SPI
Title
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Size
Document Number
Custom
Rev
1.0
Date:
B

EOP
Deciphered Date
A
SATA1GP/GPIO19 (BBS0)
Reserved
Compal Secret Data
0
1
Boot BIOS Destination Selection

@
R104 1
H: enable "ME Debugt" mode

L: disable "ME Debug" mode (default by weak internal PD)
+3VALW_PCH
U16
PCH_SPI_CS0#
PCH_SPI_MISO_1
2 3.3K_0402_5% SPI_WP1#
37
A20
LPC
PCH_RTCX1
SATA 6G
32.768 for Real Time Clock
JME2
SHORT PADS
SP@
RTC
C137
1U_0603_10V6K
+RTCVCC
U1010A
Sheet
E
13
of
55
U1010B
BG36
BJ36
AV34
AU34
PCIe Port[8:5] is not supported by HM70 NM70
BF36
BE36
AY34
BB34
+3VS
R113
1 10K_0402_5%
MINI1_CLKREQ#
+3VALW_PCH
BG37
BH37
AY36
BB36
Can depop by bios set to GPO
RP9
@
8
7
6
5
1
2
3
4
USB_OC4#
PCH_GPIO44
PCH_GPIO46
PCH_GPIO47
USB_OC4#
BJ38
BG38
AU36
AV36
17
BG40
BJ40
AY40
BB40
10K_0804_8P4R_5%
1
2
3
4
RP10 @
8
7
6
5
PCH_GPIO45
PCH_GPIO73
PCH_GPIO29
PCH_GPIO29
BE38
BC38
AW38
AY38
15
PERN2
PERP2
PETN2
PETP2
SMBDATA
PERN3
PERP3
PETN3
PETP3
PERN5
PERP5
PETN5
PETP5
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
for WLAN(JMIN1)
34
34
CLK_PCIE_MINI1#
CLK_PCIE_MINI1
34
MINI1_CLKREQ#
AB49
AB47
MINI1_CLKREQ#
M1
AA48
AA47
No use, pull-up with 10K to +3VS
for 10/100 LAN
32
32
18,32
13
PCH_GPIO20
V10
PCH_GPIO20
Y37
Y36
CLK_PCIE_LAN#
CLK_PCIE_LAN
LAN_CLKREQ#
LAN_CLKREQ#
A8
Y43
Y45
No use, pull-up with 10K to +3VALW_PCH

18
PCH_GPIO26
L12
PCH_GPIO26
V45
V46
22
22
CLK_PEG_VGA#
CLK_PEG_VGA
22
VGA_CLKREQ#
L14
PCH_GPIO44
AB42
AB40
VGA_CLKREQ#
E6
V40
V42
T13
PCH_GPIO45
V38
V37
K12
PCH_GPIO46
AK14
AK13
RST_GATE
RST_GATE
34
1
2
3
4
PCH_SMBCLK
PCH_SMBDATA
PCH_SML1CLK
PCH_SML1DATA
for S3 Power Reduction
C13
PCH_GPIO74
E14
PCH_SML1CLK
M16
PCH_SML1DATA
PCH_GPIO74
15
R111
P10
CL_RST1#
DRAM on Slot
+3VS
D_CK_SDATA
R116
4.7K_0402_5%
1
2
PCH_SMBCLK
D_CK_SDATA
11,12
D_CK_SCLK
11,12
+3VS
Q5B
DMN66D0LDW-7_SOT363-6
M10
PCH_GPIO47
+3VS
AB37
AB38
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
1. Thermal Sensor for VGA

2. EC
PCH_SML1DATA 6
AV22
AU22
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
CLKIN_DMI2_N
CLKIN_DMI2_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
CLKIN_PCILOOPBACK
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_CPU_DMI
AM12 DPLL_REF_CLK#
AM13 DPLL_REF_CLK
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
for CPU eDP
BF18
BE18
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
R114
R123
2
2
1 10K_0402_5%
1 10K_0402_5%
BJ30
BG30
CLKIN_GND1#
CLKIN_GND1
R127
R130
2
2
1 10K_0402_5%
1 10K_0402_5%
G24
E24
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
R132
R133
2
2
1 10K_0402_5%
1 10K_0402_5%
AK7
AK5
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
R134
R139
2
2
1 10K_0402_5%
1 10K_0402_5%
K45
CLK_BUF_ICH_14M
R117 1
2 10K_0402_5%
H45
CLK_PCI_LPBACK
V47
V49
XTAL25_IN
XTAL25_OUT
Y47
XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCH_SML1CLK
CLKOUTFLEX1 / GPIO65
K43
CLK_FLEX0
CLK_PCI_LPBACK
F47
CLK_FLEX1
TP@
H47
CLK_FLEX2
TP@
K49
DGPU_PRSNT#
T14
PAD
T15
PAD
EC_SMB_CK2
22,37
17
XTAL25_OUT
+1.05VS_VTT
2
1M_0402_5%
R119
25MHZ_10PF_7V25000014
1
C147
10P_0402_50V8J
PAD
T13
EC_SMB_CK2
XTAL25_IN
Reserved for EMI, need to place as close as possible to PCH ball.
TP@
22,37
CLKIN_GND1_P (BG30) and CLKIN_GND1_N (BJ30) can

share the same PD resistor. <Design Guide 2.0 Page 395>
EC_SMB_DA2
NOT used in Full Clock Integration mode
Need to inform BIOS team to configure it,

follow ME FW Bring Up Guide.
EC_SMB_DA2
Q1006B
2 XEMC@ 1
1
2
R118
33_0402_5% C146
22P_0402_50V8J
XEMC@
R120
90.9_0402_1%
1
2
Q1006A
DPLL_REF_CLK# 5
DPLL_REF_CLK 5
PEG_B_CLKRQ# / GPIO56
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
T11
CL_DATA1
CLKOUT_PCIE2N
CLKOUT_PCIE2P
2.2K_0804_8P4R_5%
2
1K_0402_5%
R115
4.7K_0402_5%
1
2
Q5A
CLKOUT_PCIE7N
CLKOUT_PCIE7P
8
7
6
5
function field : MEMORY (2.3)
1
GND
4
GND
Y2
C148
10P_0402_50V8J
+3VS
2
PCH@
R122
10K_0402_5%
UMAO@
DGPU_PRSNT#
2 1
+3VALW_PCH
R124
10K_0402_5%
VGA@
1
R126
10K_0402_5%
VGA_CLKREQ#
RP8
PCH_SMBDATA
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCH_SMBDATA
+3VALW_PCH
Directly to WLAN on JMINI1
M7
CL_CLK1
CLKOUT_PCIE0N
CLKOUT_PCIE0P
18
34
+3VS
SML1DATA / GPIO75
PERN6
PERP6
PETN6
PETP6
SMB_ALERT#
PCH_SMBCLK
RST_GATE
SML1CLK / GPIO58
FLEX CLOCKS
J2
PCH_GPIO73
PCH_SMBDATA
G12
SML1ALERT# / PCHHOT# / GPIO74
CLOCKS
PCH_SMBCLK
C9
C8
SML0CLK
10K_0804_8P4R_5%
Y40
Y39
SMB_ALERT#
A12
SML0ALERT# / GPIO60
SML0DATA
PERN4
PERP4
PETN4
PETP4
E12
H14
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
SMBCLK
1
1
BE34
BF34
BB32
AY32
SMBALERT# / GPIO11
C143
C149
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PERN1
PERP1
PETN1
PETP1
34 PCIE_PRX_DTX_N2
34 PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
SMBUS
34
34
1
1
BG34
BJ34
AV32
AU32
Link
WLAN
C145
C144
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
Controller
PCIE LAN
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1
PCI-E*
32
32
32
32
R125
10K_0402_5%
@
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (2/9) PCIE, SMBUS, CLK

Sheet
E
14
of
55
U1010C
R128 2
R131
1 200K_0402_5%
PCH_ACIN
1 200_0402_5%
PM_DRAM_PWRGD
RP24
1
2
3
4
8
7
6
5
PCH_GPIO74
RI#
PCH_PCIE_WAKE#
PCH_RSMRST#
PCH_GPIO74
14
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
4
4
4
4
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
4
4
4
4
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
4
4
4
4
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
BC24
BE20
BG18
BG20
4
4
4
4
DMI
+3VALW_PCH
FDI_INT
10K_0804_8P4R_5%
BJ24
1
R135
1
R136
+1.05VS_VTT
Ball BJ24 and Ball BG25 should be short together then

be connected R134, no longer then 500-mil.
BG25
2
DMI_IRCOMP
49.9_0402_1%
2
DMI2RBIAS
750_0402_1%
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
FDI_LSYNC1
T23
PAD
SUSACK#
C12
SUSACK#
K3
XDP_DBRESET#
XDP_DBRESET#
P12
SYS_PWROK
L22
L10
PCH_PWROK
PM_DRAM_PWRGD
37
PCH_RSMRST#
17
37
SUSWARN#
PBTN_OUT#
37,44
D4
1
ACIN
17
PM_DRAM_PWRGD
B13
PCH_RSMRST#
C21
SUSWARN#
K16
PBTN_OUT#
E20
PCH_ACIN
H20
RB751V-40_SOD323-2
PCH_GPIO72
PCH_GPIO72
RI#
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
System Power Management
DSWVRMEN
TP@
DPWROK
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A10
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
RI#
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
4
4
4
4
4
4
4
4
A18
DSWODVREN
E22
PCH_RSMRST#
B9
PCH_PCIE_WAKE#
N3
PCH_GPIO32
G8
SUS_STAT#
+RTCVCC
1
DSWODVREN
R129
1 330K_0402_5%
DSWODVREN - On Die DSW VR Enable

* H: Enable On Die DSW VR
L: Disable On Die DSW VR
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
Let DPWROK connect to RSMRST# since DS3 is not supported
N14
SLP_S5# / GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN# / GPIO29
PAD
T16 TP@
PAD
T29 TP@
+3VS

PAD
PWRBTN#
BATLOW# / GPIO72
4
4
4
4
4
4
4
4
FDI_INT
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
G10
SLP_A#
G16
SLP_SUS#
AP14
H_PM_SYNC
K14
PCH_GPIO29
T17 TP@
PAD
T18 TP@
PAD
T19 TP@
PAD
E10
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
WAKE#
SUSWARN# / SUS_PWR_DN_ACK / GPIO30
ACPRESENT / GPIO31
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
PAD
T20 TP@
PAD
T21 TP@
PM_SLP_S5#
37
PM_SLP_S4#
37
PM_SLP_S3#
37
PCH_GPIO32
R137
2 8.2K_0402_5%
T22 TP@
H_PM_SYNC
PCH_GPIO29
14
PU resistor is reserved but no stuff first
PCH@
B
A
Y
3
SYS_PWROK
SYS_PWROK
R143
10K_0402_5%
R142
@
10K_0402_5%
U17
VGATE
37,49
PCH_PWROK
37
+3VS
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (3/9) DMI,FDI,PM

Sheet
E
15
of
55
1
2
3
4
1
R179
1
R172
RP12
8
7
6
5
CTRL_CLK
PCH_LCD_CLK
CTRL_DATA
PCH_LCD_DATA
37 ENBKL
PCH_ENVDD
DPST_PWM
29 PCH_LCD_CLK
29 PCH_LCD_DATA
2
100K_0402_5%
2
100K_0402_5%
ENBKL
PCH_ENVDD
J47
M45
DPST_PWM
P45
PCH_LCD_CLK
PCH_LCD_DATA
T40
K47
T45
P39
CTRL_CLK
CTRL_DATA
R138
2.37K_0402_1%
2
1
AF37
AF36
LVDS_IBG
should be placed as close as possible to PCH.
29
29
PCH_TXCLKPCH_TXCLK+
29
29
29
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
29
29
29
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
AE48
AE47
PCH_TXCLKPCH_TXCLK+
AK39
AK40
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
AN48
AM47
AK47
AJ48
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
If the LVDS interface is not implemented,

all signals associated with the interface can
be left as No Connects.
The supply pins VCCTX_LVDS and VCCA_LVD can be connected to
ground.
DG 471984 P.193
AH43
AH49
AF47
AF43
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
1
2
3
4
31
31
31
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
31 PCH_CRT_CLK
31 PCH_CRT_DATA
150_0804_8P4R_1%
31
31
should be placed as close

as possible to PCH.
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
N48
P49
T49
PCH_CRT_CLK
PCH_CRT_DATA
T39
M40
M47
M49
PCH_CRT_HSYNC
PCH_CRT_VSYNC
T43
T42
CRT_DDC_CLK
CRT_DDC_DATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
CRT_IREF
CRT_BLUE
CRT_GREEN
CRT_RED
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
CRT
RP13
AP39
AP40
P38
M39
SDVO_SCLK
SDVO_SDATA
AT49
AT47
AT40
PCH_DPB_HPD
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
SDVO_SCLK 30
SDVO_SDATA 30
PCH_DPB_HPD
PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
30
30
30
30
30
30
30
30
30
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PCH@
R152
1K_0402_0.5%
AP43
AP45
AM42
AM40
L_CTRL_CLK
L_CTRL_DATA
By 3/11
8
7
6
5
U1010D
29
29
2.2K_0804_8P4R_5%
Digital Display Interface
+3VS
LVDS
should be placed as close as possible to PCH T43,

and keep the trace is at least 30-mil away from other
siganls (especially clocks).
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (4/9) LVDS,CRT,DP,HDMI

Sheet
E
16
of
55
+3VS
U1010E
10K_0804_8P4R_5%
RP16
8
7
6
5
1
2
3
4
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
10K_0804_8P4R_5%
1
R158
1
R155
1
R153
2
PCH_GPIO4
10K_0402_5%
2
PCH_GPIO54
10K_0402_5%
2
PCH_GPIO50
10K_0402_5%
B21
M20
AY16
BG46
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
NV_DQS0
NV_DQS1
TP21
TP22
TP23
TP24
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_ALE
NV_CLE
NV_RCOMP
NV_RB#
36
36
Boot BIOS Destination Selection

Routing
GTN1#/GPIO51 (BBS1)
PCH_USB3_RX0_P
PCH_USB3_RX0_P
PCH_USB3_TX0_N
PCH_USB3_TX0_N
SATA1GP/GPIO19 (BBS0)
Reserved
Reserved
LPC
* SPI
36
PCH_USB3_TX0_P
PCH_USB3_TX0_P
PAD
37,5
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
K40
K38
H38
G38
PCH_GPIO50
PCH_GPIO52
PCH_GPIO54
C46
C44
E40
PCH_GPIO51
PCH_GPIO55
D47
E42
F46
PCH_GPIO4
PCH_GPIO5
G42
G40
C42
D44
K10
T25 TP@
PLT_RST#
PLT_RST#
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
C6
TP25
TP26
TP27
TP28
TP29
TP30
TP31
TP32
TP33
TP34
TP35
TP36
TP37
TP38
TP39
TP40
PIRQA#
PIRQB#
PIRQC#
PIRQD#
NV_RE#_WRB0
NV_RE#_WRB1
NV_WE#_CK0
NV_WE#_CK1
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
CLK_PCI_LPBACK
CLK_PCI_LPC
CLK_PCI_LPBACK
37 CLK_PCI_LPC
R164
R162
2 EMC@ 1 22_0402_5%
1 EMC@ 2 22_0402_5%
PAD
PAD
PAD
T24 TP@
T26 TP@
T27 TP@
CLK_PCI0
CLK_PCI1
CLK_PCI2
CLK_PCI3
CLK_PCI4
H49
H43
J48
K42
H40
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AT10
BC8
EDS
Processor Select: This pin is an output that indicates if the
processor used is Sandy Bridge or Ivy Bridge.
For Sandy Bridge the output will be high, and for Ivy Bridge the
output will be low
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AY1
DF_TVS
PU, Set to 1
HR CPU NC
PD, Set to 0
CR CPU PD
PLTRST#
+1.8VS
R154
2.2K_0402_5%
DF_TVS
R156 2
1 1K_0402_5%
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
H_SNB_IVB#
AV10
AT8
AY5
BA2
AT12
BF3
Port 0 to Port 7 resides EHCI1

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
C33
USBRBIAS
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
36
36
36
36
36
36
29
29
MB USB 3.0 Connector (JUSB1)

USB2.0 Sub/B
2
USB2.0 Sub/B
+3VALW_PCH
Touch Screen
Port 4, Port 5, Port 6, Port 7, Port 12 and Port 13 is not

supported by HM70 NM70
Port 8 to Port 13 resides EHCI2

USB20_N8
USB20_P8
USB20_N10
USB20_P10
USB20_N8
USB20_P8
34
34
USB20_N10
USB20_P10
18
18
18
15
Mini Card (WLAN)

CMOS Camera (LVDS)
RP19
15
1
2
3
4
USB_OC6#
USB_OC7#
SUSWARN#
SUSWARN#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
USB_OC0#
18,36
USB_OC4#
14
8
7
6
5
10K_0804_8P4R_5%
2
22.6_0402_1%
1
2
3
4
USB_OC1#
USB_OC3#
USB_OC5#
USB_OC2#
B33
A14
K20
B17
C16
L16
A16
D14
C14
RP21 @
8
7
6
5
10K_0804_8P4R_5%
29
29
Connect USBRBIAS and USBRBIAS# (impedance= 50-ohm

single-end) together first, then connect to R158 from USBRBIAS#
(no longer than 500-mil). Keep-out 15-mil to other signals.
1
R161
1
2
3
4
PCH_GPIO12
PCH_GPIO24
PCH_GPIO57
PCH_GPIO72
PCH_GPIO12
PCH_GPIO24
PCH_GPIO57
PCH_GPIO72

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
DG
Sandy Bridge + Ivy Bridge Compatible:
Connect DF_TVS signal of the PCH to PROC_SELECT# of the
processor through a 1K5% series resistor. PROC_SELECT#
also needs a 2.2K5% pull up resistor to PCH VccDFTERM rail.
DMI,FDI Termination Voltage
PME#
14
USB
In accordance with design guide 2.0 page 274, if default

boot destination is SPI, no external pull-up/-down resistors
on the board are necessary.
PCH_USB3_RX0_N
PCH_USB3_RX0_N
PCI
36
AY7
AV7
AU3
BG4
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
PCH_GPIO5
PCH_GPIO51
PCH_GPIO52
PCH_GPIO55
NVRAM
RP20 @
1
2
3
4
RSVD
8
7
6
5
RP36 @
8
7
6
5
10K_0804_8P4R_5%
3
PCH@
PLT_RST_BUF#
32,34
R163
100K_0402_5%
NM70
HM70/NM70 USB port 4, 5, 6,7,12 and 13 are disabled on 8 port SKUs.
USB3.0
USB 3.0 port 3 and 4 are disabled on HM70

USB 3.0 are all disabled on NM70
PCIE
HM70/NM70 PCIe port 58 are disabled on this SKU.
SATA
HM70/NM70 SATA port 1 and 3 are disabled on 4 port SKUs.

HM70/NM70 SATA 6 Gb/s support on port 0 only. SATA port 0 also supports 3 Gb/s & 1.5 Gb/s
HM77 SATA 6 Gb/s support on port 0 & port 1. SATA port 0 and 1 also support 3 Gb/s & 1.5 Gb/s.
22
PLTRST_VGA#
VGA@
R165
100K_0402_5%
VGA@
2
Y
G
DGPU_HOLD_RST#
U19
2
B
1
A
37
DGPU_HOLD_RST#
HM70
14
+3VS
Note
HM77
USB2.0
PLT_RST#
U18
2
B
1
A
+3VS
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (5/9) PCI, USB, NVRAM

Sheet
E
17
of
55
For common BIOS code

+3VS
R169
10K_0402_5%
R170
10K_0402_5%
GPIO69
GPIO70
Q7YE0
Q5Wxx-QC
V5VT1
*Z5WE1_CR
PCH_GPIO70
R178
10K_0402_5%
PCH_GPIO28
PCH_GPIO69
PCH_GPIO68
R167
10K_0402_5% @
R166
10K_0402_5% @
* H: enable On-Die PLL Voltage Regulator

L: disable On-Die PLL Voltage Regulator
R168
4.7K_0402_5%
R174
10K_0402_5% @
GPIO68
Q5WE0
Project ID
+3VS
On-Die PLL Voltage Regulator
for VccVRM
+3VS
+3VALW_PCH
U1010F
2 10K_0402_5%
2 10K_0402_5%
@
@
PCH_GPIO27
T7
PCH_GPIO1
A42
PCH_GPIO6
H36
EC_SCI#
E38
EC_SMI#
C10
17
37
+3VS
1
1
1
1
R175
R180
R182
R183
2
2
2
2
EC_SCI#
37
EC_SMI#
PCH_GPIO12
PCH_GPIO12
EC_LID_OUT#
EC_LID_OUT#
PCH_GPIO16
EC_KBRST#
PCH_GPIO1
EC_SCI#
PCH_GPIO16
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
37
37,50
R110 1
VGA_PWROK
On Board DRAM Flag

17
PCH_GPIO24
2 0_0402_5%
C4
G2
U2
D40
PCH_GPIO22
T5
PCH_GPIO24
E8
PCH_GPIO27
E16
PCH_GPIO28
P8
PAD
K1
T40 TP@
T30 TP@
PAD
K4
T43 TP@
PAD
V8
T44 TP@
PAD
M5
OPTIMUS_EN#
N2
On Board DRAM Flag
PCH_GPIO39
M3
On Board DRAM Flag
PCH_GPIO48
V13
T45 TP@
+3VALW_PCH
17
PCH_GPIO57
PAD
V3
PCH_GPIO57
D6
BMBUSY# / GPIO0
TACH4 / GPIO68
TACH1 / GPIO1
TACH5 / GPIO69
TACH2 / GPIO6
TACH6 / GPIO70
TACH3 / GPIO7
TACH7 / GPIO71
R186
EC_SMI#
A44
use pull up to +3V_LAN

2 10K_0402_5%
R188 1
@
R187
2 1K_0402_5%
A45
LAN_CLKREQ#
LAN_CLKREQ#
14,32
A46
A5
EC_LID_OUT#
A6
RP29
1
2
3
4
8
7
6
5
PCH_GPIO26
USB_OC0#
SMB_ALERT#
PCH_GPIO26
14
USB_OC0# 17,36
SMB_ALERT# 14
B3
B47
BD1
10K_0804_8P4R_5%
in accordance with Chief River check list 1.7,

when Unused as GPIO or SATA*GP Use
8.2K-10K pull-down to ground
BD49
BE1
BE49
+3VS
BF1
BF49
R623
R639
1 VGA@
2 10K_0402_5%
OPTIMUS_EN#
PCH_GPIO69
C41
PCH_GPIO70
A40
PCH_GPIO71
PCH_GPIO71
R177 2
GPIO15
A20GATE
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24 / MEM_LED
PECI
RCIN#
PROCPWRGD
THRMTRIP#
INIT3_3V#
For eDP/LVDS detect
29
1 10K_0402_5%
P4
AU16
P5
T42
37
PAD
EC_KBRST#
EC_KBRST#
AY11
AY10
+3VS
GATEA20
TP@
1
PCH_THRMTRIP#_R
R181
Ctrl+Alt+Del
37
H_CPUPWRGD
2
H_THRMTRIP#
390_0402_5%
5
H_THRMTRIP#
T14
GPIO27
GPIO28
NC_1
STP_PCI# / GPIO34
NC_2
GPIO35
NC_3
SATA2GP / GPIO36
NC_4
SATA3GP / GPIO37
NC_5
AH8
AK11
AH10
AK10
P37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
SDATAOUT1 / GPIO48
VSS_NCTF_15
SATA5GP / GPIO49
VSS_NCTF_16
GPIO57
VSS_NCTF_17
VSS_NCTF_1
VSS_NCTF_19
VSS_NCTF_2
VSS_NCTF_20
VSS_NCTF_3
VSS_NCTF_21
NCTF
A4
2 1K_0402_5%
PCH_GPIO68
B41
LAN_PHY_PWR_CTRL / GPIO12
VSS_NCTF_18
1
C40
GPIO8
CPU/MISC
1
1
R171
R173
PCH_GPIO0
GPIO
+3VALW_PCH
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_6
VSS_NCTF_24
VSS_NCTF_7
VSS_NCTF_25
VSS_NCTF_8
VSS_NCTF_26
VSS_NCTF_9
VSS_NCTF_27
VSS_NCTF_10
VSS_NCTF_28
VSS_NCTF_11
VSS_NCTF_29
VSS_NCTF_12
VSS_NCTF_30
VSS_NCTF_13
VSS_NCTF_31
VSS_NCTF_14
VSS_NCTF_32
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
+3VS
D49
E1
PCH_GPIO48
PCH_GPIO0
PCH_GPIO22
PCH_GPIO39
E49
1
2
3
4
RP35 @
8
7
6
5
F1
10K_0804_8P4R_5%
F49
PCH@
2 10K_0402_5%
+3VS
PCH_GPIO6
GPIO38
2
@
R189
10K_0402_5%
OPTIMUS_EN#
OPTIMUS
DIS Only
0
1
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (6/9) GPIO, CPU, MISC

Sheet
E
18
of
55
U1010G
CRT
VCCADAC
VCCALVDS
VSSALVDS
AP21
Be close to ball AN21, AN16 and AN33
AP23
2
AP26
AT24
AN33
AN34
+3VS
Be close to ball BH29

1
0.178A
C168
0.1U_0402_16V7K
AP16
PAD
HVCMOS
VCCIO[15]
VCCIO[16]
+1.05VS_VCCAPLL_FDI
BG6
T32
TP@
AP36
AP37
0.1uH inductor, 200mA

R365
0_0603_5%
EDP@
LVDS@ LVDS@ LVDS@

2
2
2
VCC3_3[6]
VccVRM voltage supplies for
1
VCC3_3[7]
1. VccACLK
2. VccAFDIPLL
3. VccAPLLEXP
4. VccaPLLDMI2
5. VccAPLLSATA
V33
Be close to ball V33
V34
C160
0.1U_0402_16V7K
AU20
1.05
0.002
Processor I/O
0.001
PCH Core Well Reference Voltage
0.001
Suspend Well Reference Voltag
Vcc3_3
3.3
0.178
I/O Buffer Voltage
VccADAC
3.3
0.063
Display DAC Analog Power. This power is

supplied by the core well.
VccADPLLA
1.05
0.075
Display PLL A power
VccADPLLB
1.05
0.075
Display PLL B power
VccCore
1.05
1.73
Internal Logic Voltage
VccDMI
1.05
0.047
DMI Voltage
VccIO
1.05
3.799
Core Well I/O buffers
VccASW
1.05
0.803
1.05 V Supply for Intel Management Engine

and Integrated LAN
VccSPI
3.3
0.01
3.3 V Supply for SPI Controller Logic
VccDSW3_3
3.3
0.001
3.3v supply for Deep Sx well
VccDFTERN
(VccPNAND)
1.8
0.002
1.8V power supply for DF_TVS
VccRTC
3.3
6 uA
RTC Battery Voltage
VCCIO[18]
VCCIO[19]
VCCVRM[3]
AT16
+1.05VS_VTT
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCDMI[1]
AT20
1
+1.05VS_VTT
VCCIO[1]
C166
1U_0402_6.3V6K
CAP shared with AU20,

but should be close to AT20
AB36
1
2
C167
1U_0402_6.3V6K
VCCIO[25]
VCCIO[26]
VCCPNAND[1]
VCC3_3[3]
VCCVRM[2]
VCCFDIPLL
VCCPNAND[2]
VCCPNAND[3]
AG16
+1.8VS
AG17
1
AJ16
Be close to AG16
C169
0.1U_0402_16V7K
VCCIO[27]
VCCDMI[2]
VCCPNAND[4]
VCCSPI
V1
1
Be close to V1
C170
1U_0402_6.3V6K
PCH@
VccSus3_3
3.3
0.065
Suspend Well I/O Buffer Voltage
VccSusHDA
3.3
0.01
High Definition Audio Controller Suspend

Voltage
VccVRM
1.5
0.147
1.5 V Internal PLL and VRMs
2
AJ17
+3VS
AP17
V_PROC_IO
V5REF_Sus
+1.5VS
+1.05VS_VTT
share CAP with AT20
AM38
Voltage
V5REF
LVDS@ L34
0.1UH_MLF1608DR10KT_10%_1608
2
1
Be close to ball AM37

+VCCTX_LVDS
S0 Iccmax
Current(A)
Voltage Rail
+1.8VS
AK37
AM37
Refer to IntelR 7 Series / C216 Chipset Family Platform Controller Hub (PCH) External Design Specification
(EDS) Revision 2.1
PCH Power Rail Table
R366 2 LVDS@ 1 0_0603_5%

R367 2 EDP@ 1 0_0603_5%
+VCCA_LVDS
VCCIO[17]
+1.5VS
+1.05VS_VTT
BH29
AK36
+3VS
FDI
C171
1U_0402_6.3V6K
C172
1U_0402_6.3V6K
C163
1U_0402_6.3V6K
C162
1U_0402_6.3V6K
C164
10U_0603_6.3V6M
AP24
0.01U_0402_16V7K 0.1U_0402_16V7K
2
2
+3VS
C156
10U_0603_6.3V6M
VCCAPLLEXP
DMI
AN27
VCCTX_LVDS[2]
VCCTX_LVDS[4]
NAND / SPI
AN26
C155
U47
VCCIO[28]
VCCIO
AN21
C340
AN17
C154
C341
AN16
22U_0805_6.3V6M
BJ22
+VCCADAC
0.01U_0402_16V7K
C328
+VCCAPLLEXP
3.8A
VCCTX_LVDS[1]
VCCTX_LVDS[3]
PAD TP@
T31
+1.05VS_VTT
VSSADAC
U48
L1
FBMA-L11-201209-221LMA30_2P
2
+3VS
+1.05VS_VTT
AN19
SM010014520 3000ma 220ohm@100mhz DCR 0.04
Be close to ball U48
0.01U_0402_16V7K
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
LVDS
C158
1U_0402_6.3V6K
C153
1U_0402_6.3V6K
C152
1U_0402_6.3V6K
C151
10U_0603_6.3V6M
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
VCC CORE
Be close to ball AA23

1
POWER
1.61A
+1.05VS_VTT
VccCLKDMI
1.05
0.075
DMI differential Clock Buffer Voltage
VccSSC
1.05
0.095
Spread Modulators Power Supply
VccDIFFCLKN
1.05
0.05
Differential Clock Buffers Power Supply
VccALVDS
3.3
0.001
Analog power supply for LVDS (Mobile Only)
VccTX_LVDS
1.8
0.04
I/O power supply for LVDS (Mobile Only)
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (7/9) PWR

Sheet
E
19
of
55
+3VS
+3VALW
for EMI
L3 EMC@
10UH_LB2012T100MR_20%
1
2
VCCIO[31]
T33 TP@
V12
+PCH_VCCDSW
DCPSUSBYP
VCCIO[32]
Be close to T16
PAD
1. VccACLK
2. VccAFDIPLL
3. VccAPLLEXP
4. VccaPLLDMI2
5. VccAPLLSATA
AL29 should be connected to shared with

C80, C86, C87, C88, C89 and 90.
T38 TP@
+VCCAPLL_CPY_PCH
AL29
+1.05VS_VTT
PAD
BH23
+VCCSUS1 AL24
T46 TP@
VCCIO[33]
VCCSUS3_3[7]
VCCAPLLDMI2
VCCSUS3_3[8]
VCCIO[14]
DCPSUS[3]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
AA24
C185
22U_0805_6.3V6M
C182
22U_0805_6.3V6M
2
2
C181
1U_0402_6.3V6K
2
2
C180
1U_0402_6.3V6K
C183
330U_2.5V_M
1
1
C184
1U_0402_6.3V6K
C187
1U_0402_6.3V6K
1
2 +1.05VS_VCCA_B_DPL
L5
10UH_LB2012T100MR_20%
C179
1U_0402_6.3V6K
L4
10UH_LB2012T100MR_20%
1
2
+1.05VS_VCCA_A_DPL
AA26
AA27
AA29
AA31
AC26
Be close to AA19
AC27
Be close to BD47
AC29
AC31
Be close to BF47
AD29
Part Number
SF000002Z00
Description
ESR
AD31
17m
W21
W23
W24
W26
W29
W31
W33
Be close to N16
VCCASW[1]
VCCIO[34]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
V5REF_SUS
VCCASW[15]
DCPSUS[4]
VCCSUS3_3[1]
1
0.1U_0402_16V7K
N16
+VCCRTCEXT
V5REF
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
VCCASW[16]
VCC3_3[4]
+1.05VS_VCCA_A_DPL
BD47
+1.05VS_VCCA_B_DPL
BF47
AF17
AF33
AF34
AG34
+1.05VS_VTT
VCCASW[19]
VCC3_3[2]
VCCASW[20]
Be close to AF17
+1.05VS_VTT
1 C196
1U_0402_6.3V6K
2
Be close to AF33
DCPRTC
VCCVRM[4]
VCCIO[13]
VCCIO[6]
VCCADPLLA
VCCADPLLB
VCCVRM[1]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[11]
VCCIO[2]
VCCIO[3]
Be close to AG33
AG33
2
C199
1 C198
1U_0402_6.3V6K
PAD
T37 TP@
1 +VCCSST
0.1U_0402_16V7K
V16
+1.05VM_VCCSUS
T17
V19
VCCIO[10]
VCCIO[4]
VCCASW[22]
V24
Be close to P24
C177
0.1U_0402_16V7K
+3VALW_PCH
Be close to T23
P24
+1.05VS_VTT
+5VALW_PCH
D6
RB751V-40_SOD323-2
T26
R195
100_0402_5%
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
AN24
TP@T35
TP@
T35
PAD
Be close to M26
2
+3VALW_PCH
+3VS
+5VS
C186
0.1U_0402_16V7K
D5
R198
100_0402_5%
P34
+PCH_V5REF_RUN
+3VALW_PCH
N20
1
N22
P20
C188
1U_0603_10V6K
C189
1U_0402_6.3V6K
Be close to P34
Be close to N20
P22
+3VS
AA16
@ 1
W16
T34
C190
0.1U_0402_16V7K
@ 1
C191
0.1U_0402_16V7K
C192
0.1U_0402_16V7K
Be close to AA16
Be close to T34
+1.05VS_VTT
AJ2
AF13
1
AH13
2
AH14
VCCASW[23]
VCCASW[21]
Be close to AH13
C194
1U_0402_6.3V6K
AF14
AK1 +VCCSATAPLL
TP@
T36
PAD
+1.5VS
AF11
+1.05VS_VTT
AC16
AC17
Be close to AC16
AD17
C197
1U_0402_6.3V6K
T21
V21
T19
+3VALW_PCH
A22
1
C205
0.1U_0402_16V7K
C203
1U_0402_6.3V6K
V23
+RTCVCC
Be close to BJ8
V_PROC_IO
VCCRTC
RTC
C202
0.1U_0402_16V7K
C200
4.7U_0603_6.3V6K
@
C176
0.1U_0402_16V7K
T24
+1.05VS_VTT
DCPSUS[1]
DCPSUS[2]
CPU
BJ8
+3VALW_PCH
T23
DCPSST
+1.05VS_VTT
VCCAPLLSATA
MISC
1 C195
1U_0402_6.3V6K
Be close to AJ2
SATA
+1.05VS_VTT
Be close to N26
T29
+5VALW_PCH
J17
JUMP_43X39
2
1
2
VCCASW[18]
PCH@
HDA
T27
VCCASW[17]
VCCIO[12]
Y49
+1.5VS
RB751V-40_SOD323-2
VCCIO[5]
2
C193
+3VALW_PCH
VCCASW[2]
PCI/GPIO/LPC
AA21
Clock and Miscellaneous
AA19
+1.05VS_VTT
+1.05VS_VTT
VCC3_3[5]
USB
T38
+3VS_VCC_CLKF33
VccVRM voltage supplies for
+5VALW
C175
1U_0402_6.3V6K
P28
C178
0.1U_0402_16V7K PAD
P26
Be close to T38
VCCIO[30]
VCCDSW3_3
N26
T16
1
+1.05VS_VTT
VCCIO[29]
+3VALW_PCH
POWER
VCCACLK
AD49
+VCCACLK
T34 TP@
U1010J
PAD
C174
1U_0402_6.3V6K
@ C173
10U_0603_6.3V6M
J16
JUMP_43X39
2
1
2
+3VS_VCC_CLKF33
1
+3VALW_PCH
VCCSUSHDA
P32
Be close to P32
1
C206
0.1U_0402_16V7K
2
4
Be close to A22
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (8/9) PWR

Sheet
E
20
of
55
U1010I
U1010H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
PCH@
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
PCH@
4
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Size
Document Number
Custom
Rev
1.0
Date:
A
PCH (9/9) VSS

Sheet
E
21
of
55
R1010
2
10K_0402_5%
VGA_CLKREQ#_R
14
14
17
PLTRST_VGA#
2 VGA@
R1011
PEX_TSTCLK_OUT+
1
PEX_TSTCLK_OUT200_0402_1%
2 VGA@
R1012
1
PEX_TREMP
2.49K_0402_1%
DACA_HSYNC
DACA_VSYNC
DACA_VDD
DACA_VREF
DACA_RSET
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
2
DGPU_VID
PSI
50
1
6
VGA@
Q1000A
GPIO8_OVERT
50
4
3
GPU_ALERT
VGA@
Q1000B
GPIO9_ALERT
2
D1001
ACIN_BUF
AG10
AP9
AP8
2
R1005
1
10K_0402_5%
GPU_ACIN
R4
R5
VGA_DDC_CLK
VGA_DDC_DATA
R7
R6
I2CB_SCL
I2CB_SDA
RB751V-40_SOD323-2
VGA@
R2
R3
VGA_LCD_CLK
VGA_LCD_DATA
T4
T3
VGA_LCD_CLK
VGA_LCD_DATA
I2CS_SDA
I2CS_SCL
I2CS_SCL
I2CS_SDA
RP1001 VGA@
2.2K_0804_8P4R_5%
1
8
2
7
3
6
4
5
SM010019400 3000ma 33ohm@100mhz DCR 0.05
78mA
VGA@
1
L1001
+PLLVDD
1
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N
PEX_RST_N
PEX_TERMP
VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
AD8
C1023
VGA@
22U_0603_6.3V6M
+PLLVDD
VGA@
1
+GPU_PLLVDD
AE8
L1000
AD7
+GPU_PLLVDD
H3
H2
XTALIN
XTALOUT
J4
H1
XTAL_OUTBUFF
XTAL_SSIN
C1024
VGA@
4.7U_0603_6.3V6K
VGA@
C1026
0.1U_0402_16V4Z
1
VGA@
C1027
0.1U_0402_16V4Z
1
NV DG PLL_VDD
0.1Ux1
22Ux1 33ohm(ESR0.05)x1
GC6 function
GPU_CLAMP_EN
GC6_TGL_REQ#
D1000
GC6_CLAMP
R1019
37,41,50
VGA_ON
1.5VS_DGPU_PWR_EN
1.5VS_DGPU_PWR_EN
3
BAV70W_SOT323-3
GC6@
By 3/12
R1021
1 NGC6@ 2
R1020
10K_0402_5%
GC6@
VGA@
C1028
10P_0402_50V8J
LCD_BLEN
GPIO5
Reserved
GPIO6
FB_CLAMP_TGL_REQ
GPIO7
3D Vision
GPIO8
I/O
OVERT
GPIO9
I/O
ALERT
GPIO10
MEM_VREF_CTL
GPIO11
PWM_VID
GPIO12
PWR_LEVEL
GPIO13
PSI
GPIO14
HPD_A
GPIO15
HPD_C
GPIO16
FRM_CLK
GPIO17
HPD_D
GPIO18
HPD_E
GPIO19
HPD_F or HPD_B
2
BLM18PG181SN1D_2P
Reserved
GPIO21
Reserved
GPIO22
Near GPU
GPIO24
VGA@
R1013
1M_0402_5%
2
1
XTAL_SSIN
R1014
10K_0402_5%
VGA_CLKREQ#_R
VGA@
R1015
10K_0402_5%
GND
GND
X1000
4
2
VGA@
XTAL_OUTBUFF
XTALIN
+3VSDGPU
VGA@
C1029
10P_0402_50V8J
I2CS_SCL
GPIO20
Pull high @ VGA side
1
6
VGA@
Q1004A
EC_SMB_CK2
14,37
EC_SMB_DA2
14,37
+3VSDGPU
VGA_CLKREQ#
L2N7002LT1G_SOT23-3
I2CS_SDA
47
4
3
VGA@
Q1004B
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
0_0402_5%
GPIO4
2
1
0_0402_5%
LCD_VCC
23
14
Q1001
VGA@
1
D
Add R(100K)C(0.047u)delay
on PWR side
LCD_BL_PWM
Crystals must have a max ESR of 80 ohm
GC6@
GPU_CLAMP_EN
GPIO3
VGA_ON From EC
37
USAGE
Title
N14P PEG 1/7
37
from EC
GPU_TGLREQ#
GPIO2
27MHZ_10PF_7V27000050
RB751V-40_SOD323-2
GC6@
MEM_VD_CTL
GPIO23
Q47
3
S
D7
VGA@
VGA_ON
+3VSDGPU
GPIO1
C1025
VGA@
22U_0603_6.3V6M
XTALOUT
NV DG SP_PLLVDD,VID_PLLVDD
0.1Ux2 Under GPU
4.7Ux1,22Ux1
180ohm(ESR0.2)x1
+3VSDGPU
GC6_CLAMP_MON
2
BLM18PG330SN1_2P
112mA
VGA@
1
2
C1000
0.1U_0402_16V4Z
FB_CLAMP_MON
+1.05VSDGPU
SM010028480 1500ma 180ohm@100mhz DCR 0.18
Place Under AD8
37
DG-06246 v04
N14x floating
N13x PD 10K to GND
RP1000 VGA@
2.2K_0804_8P4R_5%
1
8
I2CB_SCL
2
7
I2CB_SDA
6
VGA_DDC_DATA 3
5
VGA_DDC_CLK 4
I/O
Near GPU
PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N
R1017
10K_0402_5%
GC6@
37
AM9
AN9
Place Under AE8,AD7
GC6@
R360
1K_0402_5%
37
AK9
AL10
AL9
GPU@
N13P-GL-A1_FCBGA908
+3VSDGPU
GPU_OVERT
GPIO9_ALERT_GATE
PLLVDD
AJ12
AP29
DGPU_VID
ACIN_BUF
PSI
+3VSDGPU
SP_PLLVDD
AJ26
AK26
GPIO8_OVERT
GPIO9_ALERT
GPIO
DACs
DACA_RED
DACA_GREEN
DACA_BLUE
PEX_WAKE_N
AL13
AK13
AK12
CLK_PEG_VGA
CLK_PEG_VGA#
PLTRST_VGA#
GPIO
GPIO0
1 VGA@
+3VSDGPU
VGA@
GC6_TGL_REQ#
GPIO20,21
N14P-GV/-GV2/N14M-LP/GS = availble
N14M-GE/GL = NC
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
AJ11
GC6_CLAMP_MON
+3VSDGPU
RP46
10K_0804_8P4R_5%
8
1
7
2
6
3
5
4
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
PEG_GTX_HRX_P0
PEG_GTX_HRX_N0
PEG_GTX_HRX_P1
PEG_GTX_HRX_N1
PEG_GTX_HRX_P2
PEG_GTX_HRX_N2
PEG_GTX_HRX_P3
PEG_GTX_HRX_N3
PEG_GTX_HRX_P4
PEG_GTX_HRX_N4
PEG_GTX_HRX_P5
PEG_GTX_HRX_N5
PEG_GTX_HRX_P6
PEG_GTX_HRX_N6
PEG_GTX_HRX_P7
PEG_GTX_HRX_N7
P6
M3
L6
P5
P7
L7
M7
N8
M1
M2
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
I2C
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GPIO8_OVERT
GPIO9_ALERT
GPIO9_ALERT_GATE
ACIN_BUF
Part 1 of 7
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
CLK
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_N7
PCI EXPRESS
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
GPIO need confirm with nVidia
U51A
Size Document Number

Custom
Date:

Sheet
22
Rev
1.0
of
55
U51B
27
27
DQMA[3..0]
DQMA[7..4]
DQSA[3..0]
27
DQSA[7..4]
27
DQSA#[3..0]
27
DQSA#[7..4]
27
MDA[15..0]
27
MDA[31..16]
27
MDA[47..32]
27
MDA[63..48]
28
MDC[15..0]
28
MDC[31..16]
28
MDC[47..32]
28
MDC[63..48]
DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7
P30
F31
F34
M32
AD31
AL29
AM32
AF34
DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7
M31
G31
E33
M33
AE31
AK30
AN33
AF33
DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7
M30
H30
E34
M34
AF30
AK31
AM34
AF32
MDA[15..0]
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_CMD_RFU0
FBA_CMD_RFU1
R32
AC32
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
R28 FBA_DEBUG0
AC28 FBA_DEBUG1
2 VGA@
2 VGA@
R1022
R1024
R30
R31
AB31
AC31
1
1
60.4_0402_1%
60.4_0402_1%
CLKA0 27
CLKA0# 27
CLKA1 27
CLKA1# 27
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
NC
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
2 VGA@ 1
R1026
10K_0402_5%
FB_CLAMP
E1
GC6_CLAMP
28
DQMC[3..0]
28
DQMC[7..4]
28
DQSC[3..0]
22
62+35mA
FB_DLL_AVDD
FB_VREF
K27
28
+FB_PLLAVDD
U27
H26
C1031
VGA@
Place Under U27
DQSC[7..4]
C1033
VGA@
Place Under K27
CMDC[31..0]
Part 3 of 7
+1.5VSDGPU
FBA_DEBUG0
FBA_DEBUG1
FBA_PLL_AVDD
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
27
CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30
CMDA31
0.1U_0402_16V4Z
27
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
AA31
AA29
AA28
AC34
AC33
AA32
AA33
Y28
Y29
W31
Y30
AA34
Y31
Y34
Y33
V31
0.1U_0402_16V4Z
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
MEMORY INTERFACE
A
U51C
CMDA[31..0]
Part 2 of 7
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63
28
28
DQSC#[3..0]
DQSC#[7..4]
MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62
MDC63
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7
E11
E3
A3
C9
F23
F27
C30
A24
DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7
D10
D5
C3
B9
E23
E28
B30
A23
DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7
D9
E4
B2
A9
D22
D28
A30
B23
GPU@
N13P-GL-A1_FCBGA908
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
MEMORY INTERFACE B
VRAM Interface
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD_RFU0
FBB_CMD_RFU1
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10
CMDC11
CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30
CMDC31
28
DG-06246 v04:
Reserve footprint for debug only.
C12
C20
+1.5VSDGPU
FBB_DEBUG0
FBB_DEBUG1
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
G14
G20
FBB_DEBUG0
FBB_DEBUG1
R1023
R1025
D12
E12
E20
F20
2 VGA@
2 VGA@
1
1
60.4_0402_1%
60.4_0402_1%
CLKC0 28
CLKC0# 28
CLKC1 28
CLKC1# 28
F8
E8
A5
A6
D24
D25
B27
C27
NC
FBB_WCKB01
FBB_WCKB01_N
FBB_WCKB23
FBB_WCKB23_N
FBB_WCKB45
FBB_WCKB45_N
FBB_WCKB67
FBB_WCKB67_N
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
D6
D7
C6
B6
F26
E26
A26
A27
SM010019400 3000ma 33ohm@100mhz DCR 0.05
Place Near GPU

+1.05VSDGPU
+FB_PLLAVDD
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
L1002
62mA
FBB_PLL_AVDD
H17
+FB_PLLAVDD
2
2
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
VGA@
1
2
BLM18PG330SN1_2P
C1030
VGA@
22U_0603_6.3V6M
Place Near GPU

VGA@
C1032
0.1U_0402_16V4Z
Place Under H17
FBx_PLL_AVDD,FB_DLL_AVDD
0.1Ux1 1 Per pin Under GPU
22Ux1 Near GPU
30ohm@100Mhz(ESR0.01ohm) x1 Near GPU
GPU@
N13P-GL-A1_FCBGA908
MDA[31..16]
MDA[47..32]
MDA[63..48]
MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
A
Title
N14P VRAM 2/7

Custom
Rev
1.0
Date:
Sheet
23
of
55
MULTI LEVEL STRAPS
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N
IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N
IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N
IFPF_L0
IFPF_L0_N
IFPF_L1
IFPF_L1_N
IFPF_L2
IFPF_L2_N
IFPF_L3
IFPF_L3_N
GND_SENSE
AK3
AK2
AB3
AB4
AF3
AF2
R1033
4.99K_0402_1%
GV2GT@
R1034
N14PGV2@
4.99K_0402_1%
R1032
@
30K_0402_1%
X76M1G@
X76402BOL11|X76402BOL12
N14M-GE 1G VRAM X76
ZZZ
N14M-GE 2G MB X76
ROM_SI
ROM_SO
ROM_SCLK
X76M2G@
X76402BOL13
1
R1041
P1GDFR@
34.8K_0402_1%
R1042
10K_0402_1%
N14MGE@
ZZZ
R1043
N14PGT@
15K_0402_1%
N14P-GV2 2G MB X76
X76P2G@
X76402BOL14|X76402BOL15
R1040
GV2GT@
20K_0402_1%
R1039
GV2GT@
4.99K_0402_1%
R1035
N14PGV2@
15K_0402_1%
R1037
GV2GT@
34.8K_0402_1%
R1036
@
4.99K_0402_1%
N14M-GE 2G VRAM X76
R3
ZZZ
N14M-GE 1G MB X76
1
R1031
@
10K_0402_1%
R1030
@
4.99K_0402_1%
R1
R1029
@
20K_0402_1%
+3VSDGPU
strap3
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
R3
R1028
@
4.99K_0402_1%
1
N14M-GE-A2
N14MGE@
N14P-GT-A2
N14PGT@
SA00006B530 SA00005W200 SA000068A10
L4
VCCSENSE_VGA
L5
VSSSENSE_VGA
VCCSENSE_VGA
50
VSSSENSE_VGA
50
R1035
N14PGT@
24.9K_0402_1%
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
AK11
TESTMODE
AM10
AM11
AP12
AP11
AN11
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_RST
PAD TP@T155
TP@ T155
PAD TP@
TP@T156
T156
PAD TP@
TP@T157
T157
RP47
10K_0804_8P4R_5%
TESTMODE
JTAG_TCK
JTAG_RST
8
7
6
5
1
2
3
4
GPU
Freq.
N14P-GV2
VGA@
SERIAL
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
H6
H4
H5
H7
ROM_CS_N
ROM_SCLK
ROM_SI
ROM_SO
R1047
1 VGA@
N14P-GT
2 10K_0402_5%
Memory Size
BUFRST_N
CEC
IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N
IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N
THERMDP
THERMDN
IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
GPU@
N13P-GL-A1_FCBGA908
2 10K_0402_5%
L3
J1
J2
J7
J6
J5
J3
K3
K4
MULTI_STRAP_REF0_GND
R1049
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
1 N14PGV2@
2
40.2K_0402_1%
Binary
R1041
10K_0402_1%
P2GMCN@
Memory Config
strap0
128M* 16* 4 1GB

128M* 16* 4 1GB
0x4: HYNIX SA00006H430 R3 H5TC2G63FFR-11C

0x6: HYNIX SA00003YO90 R3 H5TQ2G63DFR-11C
900 MHZ
900 MHZ
256M* 16* 4 2GB

256M* 16* 4 2GB
0x1: MICRON SA000065D10 R3 MT41K256M16HA-107G:E

0x2: HYNIX SA00006E840 R3 H5TC4G63AFR-11C
900 MHZ
900 MHZ
128M* 16* 4 1GB

256M* 16* 4 2GB
strap1
R
PU 45.3K
strap2
strap3
Hynix SA00003YO90
Micron SA000065D10
ROM_SI
ROM_SO
ROM_SCLK
PD 34.8K
PD 24.9K
R
PD 15K
R
PD 34.8K
strap4
R
PD 4.99K
R
PD 20K
R
PD 24.9K
R
PU 4.99K
R
PU 4.99K
PD 10K
PD 15K
PD 34.8K
PH 30.1K
1000
R1049
Hexadecimal
N14PGT@
40.2K_0402_1%
0000
10K
1001
0001
15K
1010
0010
20K
1011
0011
24.9K
1100
0100
30.1K
1101
0101
34.8K
1110
0110
45.3K
1111
0111
Bit3
PCI_DEVID[5]
PEX_PLL_EN_TERM
ROM_SI
RAM_CFG[3]
RAM_CFG[2]
RAM_CFG[1]
RAM_CFG[0]
ROM_SO
FB[1]
FB[0]
SMB_ALT_ADDR
VGA_DEVICE
STRAP0
USER[3]
USER[2]
USER[1]
USER[0]
STRAP1
3GIO_PADCFG[3] 3GIO_PADCFG[2] 3GIO_PADCFG[1] 3GIO_PADCFG[0]
STRAP2
PCI_DEVID[3]
PCI_DEVID[2]
PCI_DEVID[1]
PCI_DEVID[0]
STRAP3
SOR3_EXPOSED
SOR2_EXPOSED
SOR1_EXPOSED
SOR0_EXPOSED
STRAP4
RESERVED
0:No Video BIOS ROM*

1:BIOS ROM is present
0:Disable*
1:Enable
0:Reserved
1:Reserved
2:256MB*
3:Reserved
0001
0x1
P2GAFR@
0010
0x2
0011
0x3
M2GMFR@
0100
0x4
P1GFFR@,M2GAFR@
0101
0x5
0110
0x6
0111
0x7
1000
0x8
1010
0xA
1011
0xB
1100
0xC
M1GFFR@
1101
0xD
M2GMCN@
1110
0xE
1111
0xF
PCIE_MAX_SPEED DP_PLL_VDD33V
DP_PLL_VDD33V
0:0x9E(Default)*
1:0x9C(Multi-GPU usage)
0:3D Device*
1:VGA Device
0:Reserved
1:Default*
SOR[3:0]_EXPOSED
Define audio on each 0:Disable PCIE Gen3 operation*

digital display port 0:Enable PCIE Gen3 operation
0000:Not in Use*
GPU
0x9
VGA_DEVICE
0110:GEN1/GEN2 support only*

0000:GEN3 support
PCIE_SPEED_CHANGE_GNE3
For N14M-GE Binary strap table
1001
PCIE_SPEED_
CHANGE_GNE3
SMB_ALT_ADDR
3GIO_PADCFG[3:0]
M1GDFR@,P1GDFR@
Freq.
N14M-GE
PCIE_MAX_SPEED
Memory Config
strap3
strap2
strap1
strap0
128Mx16x4
0x6: HYNIX SA00003YO90 R3 H5TQ2G63DFR-11C
PD10K
PH10K
PH10K
PD10K
900MHz
128Mx16x4
0xC: HYNIX SA00006H430 R3 H5TC2G63FFR-11C
PH10K
PH10K
PD10K
PD10K
900MHz
256Mx16x4
0xD: MICRON SA000065D10 R3 MT41K256M16HA-107G:E

0x3: HYNIX SA00006DG30 R3 H5TC4G63MFR-11C
0x4: HYNIX SA00006E840 R3 H5TC4G63AFR-11C
PH10K
PD10K
PD10K
PH10K
PD10K
PH10K
PD10K
PH10K
PD10K
PH10K
PH10K
PD10K
0X6
HYNIX 128 H5TQ2G63DFR-11C

strap2
strap1
strap0
R1029
10K_0402_1%
M1GDFR@
R1028
10K_0402_1%
M1GDFR@
strap2
R1030
10K_0402_1%
M1GFFR@
strap2
strap1
strap0
R1029
10K_0402_1%
M2GMCN@
ROM_SI
R
PD 10K
R
PD 10K
strap0
strap3
0X4
ROM_SO
R
PD 10K
HYNIX 256 H5TQ4G63AFR-11C

strap2
R1036
10K_0402_1%
M1GFFR@
strap2
strap1
strap0
R1037
10K_0402_1%
M2GAFR@
R1036
10K_0402_1%
M2GAFR@
strap0
1
R1028
10K_0402_1%
M2GMFR@
R1039
10K_0402_1%
M2GAFR@
1
R1027
10K_0402_1%
M2GMFR@
R1035
10K_0402_1%
M2GMFR@
Deciphered Date

EOP
Title
N14P LVDS 3/7
Date:
strap1
Size
Document Number
Custom
B
R1029
10K_0402_1%
M2GAFR@
Compal Secret Data

2013/02/04
ROM_SCLK
R
PD 10K
HYNIX 256 H5TQ4G63MFR-11C
R1039
10K_0402_1%
M2GMFR@
Issued Date
strap3
0X3
strap4
R1029
10K_0402_1%
M1GFFR@
R1027
10K_0402_1%
M2GMCN@
R1037
10K_0402_1%
M2GMCN@
strap1
R1037
10K_0402_1%
M1GFFR@
MICRON 256 MT41K256M16HA-107G:E
R1030
10K_0402_1%
M2GMCN@
HYNIX 128 H5TQ2G63FFR-11C
strap3
0XC
R1036
10K_0402_1%
M1GDFR@
strap3
0XD
0:Limit booting to PCIE Gen1

1:Allow booting to PCIE Gen2/3*
Decive ID : 0x1140
Memory Size
900MHz
N14M-GE
VRAM Strapstrap3
0
Bit0
SUB_VENDOR
FB[1:0]
P2GMCN@
Bit1
PCI_DEVID[4]
PEX_PLL_EN_TERM
0x0
Bit2
ROM_SCLK
SUB_VENDOR
0000
Strap Name
Bom structure
R1039
10K_0402_1%
M1GDFR@
R
PD 15K
+3VSDGPU
GENERAL
1 VGA@
R1041
15K_0402_1%
P2GAFR@
Decive ID : 0x1292
Decive ID : 0xFE4
Resistor Values Pull-up to +3V Pull-down to Gnd
R1048
N14P-GV2
VRAM Strap
R1043
10K_0402_1%
N14MGE@
900 MHZ
900 MHZ
4.99K
L2
R1041
10K_0402_1%
N14MGE@
For N14P-GV2 strap table

For N14P-GT strap table
TEST
MULTI_STRAP_REF0_GND
AG3
AG2
N14P-GV2-A1
N14PGV2@
strap2
R1040
10K_0402_1%
N14MGE@
LVDS/TMDS
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
R1027
GV2GT@
45.3K_0402_1%
strap1
N14P-GV2 VRAM X76
VDD_SENSE
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
strap0
IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N
U51
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
P8
AC6
AJ28
AJ4
AJ5
AL11
C15
D19
D20
D23
D26
H31
T8
V32
U51
IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N
NC
AM6
AN6
AP3
AN3
AN5
AM5
AL6
AK6
AJ6
AH6
U51
N14P-GV2/GT
VRAM Strap
+3VSDGPU
Straps
Part 4 of 7
U51D

Sheet
24
Rev
1.0
of
55
NV DG PEX_IOVVD/Q combined
1Ux4 Under GPU
4.7Ux2 Near GPU
10Ux4,22Ux4 Midway GPU & Power supply
Under GPU
Near GPU
VGA@ C1040
22U_0603_6.3V6M
VGA@ C1039
22U_0603_6.3V6M
VGA@ C1038
10U_0603_6.3V6M
VGA@ C1037
10U_0603_6.3V6M
VGA@ C1036
4.7U_0603_6.3V6K
NV 14x DG FBVDDQ(DDR3) GB4-128

0.1Ux4,1Ux4,4.7Ux4 Under GPU
10Ux2,22Ux2 Near GPU
+1.05VSDGPU
VGA@ C1035
1U_0402_6.3V6K
VGA@ C1034
1U_0402_6.3V6K
Midway GPU & Power supply
U51E
1
VGA@ C1069
22U_0603_6.3V6M
VGA@ C1068
22U_0603_6.3V6M
VGA@ C1067
10U_0603_6.3V6M
VGA@ C1066
10U_0603_6.3V6M
Under GPU
Near GPU
PEX_PLL_HVDD
2 0_0402_5%
FB_VDDQ_SENSE
F1
2 0_0402_5%
FB_GND_SENSE
F2
1 40.2_0402_1%
FB_CAL_PD_VDDQ
R1051
+1.5VSDGPU
R1052
PEX_PLLVDD
R1053
R1054
3
R1055
2 VGA@
2 VGA@
2 VGA@
1 42.2_0402_1%
1 51.1_0402_1%
FB_CAL_PU_GND
FB_CAL_TERM_GND
J27
H27
H25
VDD33_0
VDD33_1
VDD33_2
VDD33_3
150mA
PEX_SVDD/PLL_HVDD
connect to NV3V3
0.1Ux1,4.7Ux2 Near GPU
210mA
AH12
IFPC_IOVDD
N14PGV2@
R1050
0_0603_5%
N14MGE@
BLM18PG121SN1D_0603
R1050
150mA
AG26
+PEX_PLLVDD
C1063
VGA@
0.1U_0402_16V4Z
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD
C1064
VGA@
1U_0402_6.3V6K
C1065
VGA@
4.7U_0603_6.3V6K
if use N14M-GE/GL,use bead

120ohm@100MHz(ESR=0.18)
Near GPU
J8
K8
L8
M8
NV DG PEX_PLLVDD
0.1Ux1 Under GPU
1Ux1,4.7Ux1 Near GPU
NV DG VDD33/3VSMISC
0.1Ux3 Under GPU 1Per pin
1Ux1,4.7Ux1 Near GPU
+3VSDGPU
AH8
AJ8
IFPAB_PLLVDD
AG8
AG9
IFPAB_IOVDD
AF7
AF8
IFPC_PLLVDD
AF6
IFPC_IOVDD
AG7
AN2
IFPD_PLLVDD
AG6
IFPD_IOVDD
AB8
AD6
IFPEF_PLLVDD
AC7
AC8
IFPEF_IOVDD
Under GPU (one per pin)
Near GPU
VGA@
RP1002
IFPEF_PLLVDD
IFPEF_IOVDD
IFPC_PLLVDD
IFPD_PLLVDD
1
2
3
4
8
7
6
5
3
FB_CAL_TERM_GND
IFPEF_PLVDD
IFPEF_RSET
+1.05VSDGPU
AG12
FB_CAL_PD_VDDQ
IFPD_PLLVDD
IFPD_RSET
Midway GPU & Power supply
Near GPU
IFPC_PLLVDD
IFPC_RSET
VGA@ C1054
22U_0603_6.3V6M
VGA@ C1053
10U_0603_6.3V6M
VGA@ C1052
10U_0603_6.3V6M
VGA@ C1043
4.7U_0603_6.3V6K
VGA@ C1042
1U_0402_6.3V6K
VGA@ C1051
1U_0402_6.3V6K
+3VSDGPU
FB_VDDQ_SENSE
FB_CAL_PU_GND
Near GPU
Under GPU
IFPA_IOVDD
IFPB_IOVDD
FB_GND_SENSE
1
PEX_SVDD_3V3
IFPAB_PLLVDD
IFPAB_RSET
+1.5VSDGPU
Under GPU
VGA@ C1074
4.7U_0603_6.3V6K
VGA@ C1073
1U_0402_6.3V6K
VGA@ C1062
4.7U_0603_6.3V6K
VGA@ C1072
0.1U_0402_16V4Z
VGA@ C1061
4.7U_0603_6.3V6K
VGA@ C1060
4.7U_0603_6.3V6K
VGA@ C1059
4.7U_0603_6.3V6K
Under GPU
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
VGA@ C1058
4.7U_0603_6.3V6K
3300 mA
total 3300mA
Design guide page.76
VGA@ C1071
0.1U_0402_16V4Z
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
AG19
AG21
AG22
AG24
AH21
AH25
VGA@ C1057
4.7U_0603_6.3V6K
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
VGA@ C1070
0.1U_0402_16V4Z
VGA@ C1055
1U_0402_6.3V6K
VGA@ C1046
1U_0402_6.3V6K
VGA@ C1045
1U_0402_6.3V6K
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
VGA@ C1056
0.1U_0402_16V4Z
Under GPU
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
POWER
VGA@ C1050
0.1U_0402_16V4Z
VGA@ C1047
1U_0402_6.3V6K
VGA@ C1049
0.1U_0402_16V4Z
VGA@ C1048
0.1U_0402_16V4Z
VGA@ C1044
22U_0603_6.3V6M
+1.05VSDGPU
Part 5 of 7
VGA@ C1041
0.1U_0402_16V4Z
+1.5VSDGPU
IFPD_IOVDD
IFPAB_IOVDD
IFPC_IOVDD
IFPAB_PLLVDD
10K_0804_8P4R_5%
VGA@
RP1003
1
8
2
7
3
6
4
5
10K_0804_8P4R_5%
GPU@
N13P-GL-A1_FCBGA908
MULTI LEVEL STRAPS
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
A
Title
N14P POWER & GND 4/9

Custom
Date:

Sheet
25
Rev
1.0
of
55
U51F
U51G
+VGA_CORE
+VGA_CORE
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
Part 7 of 7
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
T12
T14
T16
T19
T21
T23
U13
U15
U17
U18
U20
U22
V13
V15
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
N14M-GE 35A
N14P-GV2 45A
N14P-GT 55A
1
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
2
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
3
GPU@
N13P-GL-A1_FCBGA908
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
GPU@
N13P-GL-A1_FCBGA908
VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
POWER
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
GND
Part 6 of 7
A2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB2
AB21
A33
AB23
AB28
AB30
AB32
AB5
AB7
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE2
AE28
AE30
AE32
AE33
AE5
AE7
AH10
AA15
AH13
AH16
AH19
AH2
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AH5
AH7
AJ7
AK10
AK7
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AL5
AM13
AM16
AM19
AM22
AM25
AN1
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AN4
AN7
AP2
AP33
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
Title
N14P POWER & GND 5/7

Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
26
of
55
VRAM DDR3 chips
23
23
128Mx16 DDR3 *8==>2GB

256Mx16 DDR3 *8==>4GB
DQSA[7..0]
Low 32
MDA[63..0]
MDA[63..0]
CMDA[30..0]
CMDA[30..0]
High 32
U1004 VRAM@
CMDA12
CMDA27
CMDA26
M2
N8
M3
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
DQSA1
DQSA2
F3
C7
DQMA1
DQMA2
E7
D3
DQSA#1
DQSA#2
G3
B7
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
RESET
L8
Group1
MDA17
MDA21
MDA18
MDA23
MDA19
MDA22
MDA16
MDA20
Group2
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDA12
CMDA27
CMDA26
M2
N8
M3
J7
K7
K9
CLKA0
CLKA0#
CMDA3
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA2
CMDA0
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
DQSA0
DQSA3
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA0
DQMA3
E7
D3
DQSA#0
DQSA#3
G3
B7
T2
CMDA5
L8
ZQ1
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDA3
MDA4
MDA2
MDA7
MDA0
MDA5
MDA1
MDA6
MDA27
MDA29
MDA25
MDA30
MDA24
MDA28
MDA26
MDA31
Group0
Group3
R1058
VGA@
243_0402_1%
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
R1059
VGA@
243_0402_1%
J1
L1
J9
L9
96-BALL
SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96
+MEM_VREF2
+MEM_VREF3
M8
H1
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VREFCA
VREFDQ
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
MDA39
MDA35
MDA37
MDA33
MDA38
MDA32
MDA36
MDA34
D7
C3
C8
C2
A7
A2
B8
A3
MDA61
MDA59
MDA60
MDA57
MDA63
MDA56
MDA62
MDA58
+MEM_VREF3
+MEM_VREF2
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
Group4
Group7
+1.5VSDGPU
M8
H1
VREFCA
VREFDQ
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
B2
D9
G7
K2
K8
N1
N9
R1
R9
CMDA12 M2
CMDA27 N8
CMDA26 M3
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CLKA1
CLKA1#
CMDA19
J7
K7
K9
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
A1
A8
C1
C9
D2
E9
F1
H2
H9
DQSA4
DQSA7
F3
C7
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSA#4
DQSA#7
G3
B7
CMDA5
T2
ZQ2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
E7
D3
DQMA4
DQMA7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
L8
ZQ/ZQ0
J1
L1
J9
L9
VGA@
R1060
243_0402_1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
CMDA12
CMDA27
CMDA26
M2
N8
M3
CLKA1
CLKA1#
CMDA19
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDA18
CMDA16
CMDA30
CMDA15
CMDA13
K1
L2
J3
K3
L3
DQSA5
DQSA6
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMA5
DQMA6
G3
B7
CMDA5
T2
ZQ3
L8
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VGA@
R1061
243_0402_1%
B1
B9
D1
D8
E2
E8
F9
G1
G9
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ
DML
DMU
DQSL
DQSU
RESET
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
A14
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
2
23
CMD18
ODT_H
CMD19
CKE_H
CMD20
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
A13
U1002
U1002
U1002
U1002
SA00003YO90
H5TQ2G63DFR-11C
SA00006H430
H5TC2G63FFR-11C
SA000065D10
MT41K256M16HA
SA00006E840
H5TC4G63AFR-11C
CLKA1#
HYDFR@
HYFFR@
MTHA@
HYAFR@
U1003
U1003
U1003
U1003
CLKA1#
SA00003YO90
H5TQ2G63DFR-11C
No Termination
R1072 1 VGA@
R1076 1 VGA@
SA00006H430
H5TC2G63FFR-11C
SA000065D10
MT41K256M16HA
SA00006E840
H5TC4G63AFR-11C
HYDFR@
HYFFR@
MTHA@
HYAFR@
U1004
U1004
U1004
U1004
2 10K_0402_5%
2 10K_0402_5%
SA00003YO90
H5TQ2G63DFR-11C
SA00006H430
H5TC2G63FFR-11C
SA000065D10
MT41K256M16HA
SA00006E840
H5TC4G63AFR-11C
HYDFR@
HYFFR@
MTHA@
HYAFR@
U1005
U1005
U1005
U1005
SA00003YO90
H5TQ2G63DFR-11C
HYDFR@
SA00006H430
H5TC2G63FFR-11C
HYFFR@
SA000065D10
MT41K256M16HA
MTHA@
SA00006E840
H5TC4G63AFR-11C
HYAFR@
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
A
CAS*
CS0_H#
Not Available
VGA@ C1090
0.1U_0402_16V4Z
10k
VGA@ C1102
0.1U_0402_16V4Z
VGA@ C1101
0.1U_0402_16V4Z
VGA@ C1100
0.1U_0402_16V4Z
VGA@ C1099
0.1U_0402_16V4Z
VGA@ C1098
1U_0402_6.3V6K
VGA@ C1097
1U_0402_6.3V6K
VGA@ C1096
1U_0402_6.3V6K
VGA@ C1095
1U_0402_6.3V6K
VGA@ C1094
1U_0402_6.3V6K
VGA@ C1093
1U_0402_6.3V6K
VGA@ C1092
1U_0402_6.3V6K
VGA@ C1091
1U_0402_6.3V6K
A14
CMD5
+1.5VSDGPU
CMD4
CMD17
C1076
VGA@
0.1U_0402_16V4Z
VGA@ C1089
0.1U_0402_16V4Z
RST
CS*
VGA@ C1088
0.1U_0402_16V4Z
10k
VGA@ C1087
0.1U_0402_16V4Z
10k
CKEx
+1.5VSDGPU
R1069
VGA@
1.33K_0402_1%
VGA@ C1086
1U_0402_6.3V6K
Default Pull-down
ODTx
VGA@ C1085
1U_0402_6.3V6K
Command Bit
CKE_L
CMD16
R1064
VGA@
160_0402_1%
CMDA18
CMDA19
DDR3
ODT_L
CMD3
+MEM_VREF3
C1075
VGA@
0.1U_0402_16V4Z
VGA@ C1084
1U_0402_6.3V6K
C1078
VGA@
0.1U_0402_16V4Z
VGA@ C1083
1U_0402_6.3V6K
R1074
VGA@
1.33K_0402_1%
VGA@ C1082
1U_0402_6.3V6K
C1077
VGA@
0.1U_0402_16V4Z
R1068
VGA@
1.33K_0402_1%
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
VGA@ C1081
1U_0402_6.3V6K
R1073
VGA@
1.33K_0402_1%
R1070 1 VGA@
R1071 1 VGA@
R1075 1 VGA@
VGA@ C1080
1U_0402_6.3V6K
CMD2
CLKA1
CLKA1
R1063
VGA@
1.33K_0402_1%
+MEM_VREF2
+MEM_VREF1
CMDA2
CMDA3
CMDA5
CLKA0#
VGA@ C1079
1U_0402_6.3V6K
+MEM_VREF0
CLKA0#
+1.5VSDGPU
1
23
Group6
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
32..63
CS0_L#
CMD1
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
0..31
+1.5VSDGPU
R1062
VGA@
1.33K_0402_1%
VGA@
R1065
160_0402_1%
R1067
VGA@
1.33K_0402_1%
CMD0
Group5
A1
A8
C1
C9
D2
E9
F1
H2
H9
ODT/ODT0
CS/CS0
RAS
CAS
WE
CLKA0
R1066
VGA@
1.33K_0402_1%
MDA53
MDA49
MDA55
MDA50
MDA52
MDA48
MDA54
MDA51
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
23
+1.5VSDGPU
D7
C3
C8
C2
A7
A2
B8
A3
Mode D
Address
96-BALL
SDRAM DDR3
+1.5VSDGPU
CLKA0
MDA45
MDA40
MDA46
MDA41
MDA47
MDA43
MDA44
MDA42
+1.5VSDGPU
BA0
BA1
BA2
E7
D3
DQSA#5
DQSA#6
96-BALL
SDRAM DDR3
+1.5VSDGPU
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VSDGPU
96-BALL
SDRAM DDR3
23
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
+1.5VSDGPU
BA0
BA1
BA2
DQSL
DQSU
E3
F7
F2
F8
H3
H8
G2
H7
ZQ/ZQ0
B2
D9
G7
K2
K8
N1
N9
R1
R9
ZQ0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
T2
CMDA5
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
D7
C3
C8
C2
A7
A2
B8
A3
M8
H1
+MEM_VREF1
+MEM_VREF0
+1.5VSDGPU
BA0
BA1
BA2
J7
K7
K9
CLKA0
CLKA0#
CMDA3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
MDA12
MDA13
MDA8
MDA15
MDA9
MDA11
MDA10
MDA14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
E3
F7
F2
F8
H3
H8
G2
H7
CMDA9
CMDA11
CMDA8
CMDA25
CMDA10
CMDA24
CMDA22
CMDA7
CMDA21
CMDA6
CMDA29
CMDA23
CMDA28
CMDA20
CMDA4
CMDA14
U1005 VRAM@
U1003 VRAM@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
VREFCA
VREFDQ
U1002 VRAM@
M8
H1
+MEM_VREF0
+MEM_VREF1
DQMA[7..0]
DQMA[7..0]
23
23
DQSA#[7..0]
DQSA#[7..0]
23
DQSA[7..0]
Title
N14P DDR3 6/7

Size
Document Number
Custom
Rev
1.0
Date:
Sheet

E
27
of
55
23
DQSC#[7..0]
DQMC[7..0]
DQMC[7..0]
23
MDC[63..0]
MDC[63..0]
23
Low 32
CMDC[30..0]
CMDC[30..0]
U1006 VRAM@
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDC12
CMDC27
CMDC26
M2
N8
M3
J7
K7
K9
CLKC0
CLKC0#
CMDC3
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC1
DQSC2
F3
C7
DQMC1
DQMC2
E7
D3
DQSC#1
DQSC#2
G3
B7
J1
L1
J9
L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
D7
C3
C8
C2
A7
A2
B8
A3
MDC18
MDC20
MDC17
MDC22
MDC16
MDC23
MDC19
MDC21
+MEM_VREF5
+MEM_VREF4
M8
H1
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDC12
CMDC27
CMDC26
M2
N8
M3
Group1
Group2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
CMDC2
CMDC0
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC0
DQSC3
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMC0
DQMC3
E7
D3
DQSC#0
DQSC#3
G3
B7
CMDC5
T2
ZQ5
L8
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
R1078
128@
D7
C3
C8
C2
A7
A2
B8
A3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
MDC26
MDC31
MDC25
MDC30
MDC27
MDC28
MDC24
MDC29
+MEM_VREF6
+MEM_VREF7
Group0
Group3
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
M8
H1
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
CMDC12
CMDC27
CMDC26
M2
N8
M3
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
CLKC1
CLKC1#
CMDC19
+1.5VSDGPU
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
MDC3
MDC7
MDC1
MDC4
MDC2
MDC6
MDC0
MDC5
VREFCA
VREFDQ
A1
A8
C1
C9
D2
E9
F1
H2
H9
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC4
DQSC5
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMC4
DQMC5
E7
D3
DQSC#4
DQSC#5
G3
B7
CMDC5
T2
ZQ6
L8
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
E3
F7
F2
F8
H3
H8
G2
H7
MDC39
MDC33
MDC37
MDC32
MDC36
MDC34
MDC38
MDC35
D7
C3
C8
C2
A7
A2
B8
A3
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
J1
L1
J9
L9
R1079
128@
243_0402_1%
96-BALL
SDRAM DDR3
MDC44
MDC43
MDC47
MDC40
MDC45
MDC42
MDC46
MDC41
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CLKC1
CLKC1#
CMDC19
+1.5VSDGPU
CMDC18
CMDC16
CMDC30
CMDC15
CMDC13
K1
L2
J3
K3
L3
DQSC7
DQSC6
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
DQMC7
DQMC6
E7
D3
DQSC#7
DQSC#6
G3
B7
B1
B9
D1
D8
E2
E8
F9
G1
G9
CLKC0#
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
R1088
128@
1.33K_0402_1%
10k
No Termination
Group7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ/ZQ0
J1
L1
J9
L9
NC/ODT1
NC/CS1
NC/CE1
NCZQ1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
CMD2
Group6
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5VSDGPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
CKE
CMD4
A14
A14
CMD5
RST
RST
CMD6
A9
A9
CMD7
A7
A7
CMD8
A2
A2
CMD9
A0
A0
CMD10
A4
A4
CMD11
A1
A1
CMD12
BA0
BA0
CMD13
WE*
WE*
CMD14
A15
A15
CMD15
CAS*
CS0_H#
CMD18
ODT_H
CMD19
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
CKE_H
CMD20
A13
A13
CMD21
A8
A8
CMD22
A6
A6
CMD23
A11
A11
CMD24
A5
A5
CMD25
A3
A3
CMD26
BA2
BA2
CMD27
BA1
BA1
CMD28
A12
A12
CMD29
A10
A10
CMD30
RAS*
RAS*
LOW
HIGH
Not Available
U1006
U1006
SA00003YO90
H5TQ2G63DFR-11C
SA000065D10
MT41K256M16HA
U1007
U1007
SA00003YO90
H5TQ2G63DFR-11C
SA000065D10
MT41K256M16HA
U1008
U1008
SA00003YO90
H5TQ2G63DFR-11C
SA000065D10
MT41K256M16HA
U1009
U1009
CLKC1
GTHYDFR@
GTMTHA@
CLKC1#
CLKC1#
R1091 1 128@
R1093 1 128@
CMDC18
CMDC19
2 10K_0402_5%
2 10K_0402_5%
C1104
128@
0.1U_0402_16V4Z
GTHYDFR@
SA00003YO90
H5TQ2G63DFR-11C
GTMTHA@
SA000065D10
MT41K256M16HA
GTMTHA@
Compal Secret Data

2013/02/04
GTMTHA@
EOP
Deciphered Date
B
CMD17
Issued Date
CAS*
CMD16
Title
N14P DDR3 7/7

Size
Document Number
Custom
Rev
1.0
Date:
A
ODT_L
CMD3
GTHYDFR@
CS0_L#
CMD1
+1.5VSDGPU
32..63
0..31
CMD0
GTHYDFR@
128@ C1130
0.1U_0402_16V4Z
128@ C1129
0.1U_0402_16V4Z
128@ C1128
0.1U_0402_16V4Z
128@ C1127
0.1U_0402_16V4Z
128@ C1126
1U_0402_6.3V6K
128@ C1125
1U_0402_6.3V6K
128@ C1124
1U_0402_6.3V6K
128@ C1123
1U_0402_6.3V6K
128@ C1122
1U_0402_6.3V6K
128@ C1121
1U_0402_6.3V6K
128@ C1120
1U_0402_6.3V6K
128@ C1119
1U_0402_6.3V6K
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
VDDQ
VDDQ
DML
DMU
CLKC1
128@ C1116
0.1U_0402_16V4Z
RST
R1090
128@
1.33K_0402_1%
128@ C1115
0.1U_0402_16V4Z
10k
C1103
128@
0.1U_0402_16V4Z
128@ C1114
1U_0402_6.3V6K
10k
CKEx
+1.5VSDGPU
MDC54
MDC48
MDC52
MDC50
MDC53
MDC51
MDC55
MDC49
Mode D
Address
+MEM_VREF7
128@ C1113
1U_0402_6.3V6K
Default Pull-down
ODTx
CS*
C1106
128@
0.1U_0402_16V4Z
23
+MEM_VREF6
R1087 1 128@
R1089 1 128@
R1092 1 128@
CMDC2
CMDC3
CMDC5
DDR3
D7
C3
C8
C2
A7
A2
B8
A3
MDC63
MDC58
MDC62
MDC59
MDC60
MDC61
MDC57
MDC56
96-BALL
SDRAM DDR3
128@ C1112
1U_0402_6.3V6K
CLKC0#
Command Bit
L8
+1.5VSDGPU
128@ C1111
1U_0402_6.3V6K
ZQ7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
E3
F7
F2
F8
H3
H8
G2
H7
+1.5VSDGPU
CK
CK
CKE/CKE0
R1095
128@
1.33K_0402_1%
T2
R1080
128@
243_0402_1%
R1084
128@
1.33K_0402_1%
128@ C1109
1U_0402_6.3V6K
23
+MEM_VREF5
C1105
128@
0.1U_0402_16V4Z
CMDC5
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
R1083
128@
1.33K_0402_1%
128@ C1108
1U_0402_6.3V6K
R1094
128@
1.33K_0402_1%
M2
N8
M3
B2
D9
G7
K2
K8
N1
N9
R1
R9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
CLKC0
CLKC0
128@ C1107
1U_0402_6.3V6K
+MEM_VREF4
CMDC12
CMDC27
CMDC26
VREFCA
VREFDQ
R1081
128@
160_0402_1%
R1082
128@
160_0402_1%
R1086
128@
1.33K_0402_1%
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
96-BALL
SDRAM DDR3
128@ C1110
1U_0402_6.3V6K
23
R1085
128@
1.33K_0402_1%
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
Group5
23
+1.5VSDGPU
M8
H1
Group4
+1.5VSDGPU
+1.5VSDGPU
+MEM_VREF7
+MEM_VREF6
+1.5VSDGPU
BA0
BA1
BA2
J7
K7
K9
U1009 VRAM@
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
+1.5VSDGPU
CK
CK
CKE/CKE0
A1
A8
C1
C9
D2
E9
F1
H2
H9
U1008 VRAM@
E3
F7
F2
F8
H3
H8
G2
H7
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
J7
K7
K9
CLKC0
CLKC0#
CMDC3
96-BALL
SDRAM DDR3
VREFCA
VREFDQ
+1.5VSDGPU
BA0
BA1
BA2
DQSL
DQSU
MDC8
MDC12
MDC11
MDC13
MDC9
MDC14
MDC10
MDC15
1
2
L8
243_0402_1%
R1077
128@
ZQ4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3
E3
F7
F2
F8
H3
H8
G2
H7
243_0402_1%
T2
CMDC5
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
CMDC9
CMDC11
CMDC8
CMDC25
CMDC10
CMDC24
CMDC22
CMDC7
CMDC21
CMDC6
CMDC29
CMDC23
CMDC28
CMDC20
CMDC4
CMDC14
U1007 VRAM@
VREFCA
VREFDQ
M8
H1
+MEM_VREF4
+MEM_VREF5
High 32
128@ C1118
0.1U_0402_16V4Z
128Mx16 DDR3 *8==>2GB

256Mx16 DDR3 *8==>4GB
DQSC[7..0]
DQSC[7..0]
DQSC#[7..0]
23
23
128@ C1117
0.1U_0402_16V4Z
VRAM DDR3 chips
Sheet
E
28
of
55
Place closed to JLVDS1

+3VS
LCD POWER CIRCUIT

+3VS
+LCDVDD
U8
W=60mils
IN
GND
IN
EN
2
C367 2
4.7U_0603_6.3V6K
L11
FBMA-L11-201209-221LMA30_2P
C419
@
0.1U_0402_16V4Z
XEMC@
G5243T11U_SOT23-5
2
16
PCH_ENVDD
B+
W=60mils
C364
1000P_0402_50V7K
C140
1U_0402_6.3V6K
OUT
+INVPWR_B+
W=60mils
C375
0.1U_0402_16V4Z
1
EMC@
1 XEMC@
C365
68P_0402_50V8J
2
SM010014520 3000ma
220ohm@100mhz
DCR 0.04
Touch Screen
Touch Module
17
17
1
2
3
4
5
6
USB20_N3
USB20_P3
USB20_N3
USB20_P3
TS_EN_1
TS_EN_2
+3VS
R556
10K_0402_5%
CPU_EDP_HPD#
LCD/ LED PANEL Conn.
2
G
L2N7002LT1G_SOT23-3
EDP_HPD 2
G
PCH_GPIO71
EDP_HPD
2
EDP@
PCH_GPIO71
Q8
R202
100K_0402_5%
EDP@
18
Q33
L2N7002LT1G_SOT23-3
EDP@
@
1 R959
2
100K_0402_5%
JLVDS1
W=60mils
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
+INVPWR_B+
W=60mils
GPIO71
+LCDVDD
PCH_GPIO71
eDP
LVDS
0
1
eDP
3
4 EDP_TXN0
4 EDP_TXP0
4 EDP_TXN1
4 EDP_TXP1
4
4
EDP_AUXN
EDP_AUXP
C372 1
C371 1
2 0.1U_0402_16V7K EDP@
2 0.1U_0402_16V7K EDP@
EDP_TXN0_C
EDP_TXP0_C
C374 1
C373 1
2 0.1U_0402_16V7K EDP@
2 0.1U_0402_16V7K EDP@
EDP_TXN1_C
EDP_TXP1_C
C369 1
C370 1
2 0.1U_0402_16V7K EDP@
2 0.1U_0402_16V7K EDP@
EDP_AUXN_C
EDP_AUXP_C
+5VS
+5VS_TS
16
16
+3VS
16 DPST_PWM
37 BKOFF#
PCH_LCD_CLK
PCH_LCD_DATA
16
16
PCH_TXOUT0PCH_TXOUT0+
16
16
16
16
R81
0_0603_5%
1
2
@
16
16
PCH_TXCLKPCH_TXCLK+
DPST_PWM
BKOFF#
PCH_LCD_CLK
PCH_LCD_DATA
PCH_TXCLKPCH_TXCLK+
EDP_TXN0_C
EDP_TXP0_C
EDP_TXN1_C
EDP_TXP1_C
37
TS_EN
7
8
Part Number = SP010013W00

PCB Footprint = ACES_88460-00601-P01_6P
1
2
3
4
5 G1
6 G2
ACES_88460-00601-P01
HPD
CONN@
JTS1
+5VS_TS
R414 1
R424 1
R425 1
R426 1
@
@
2 0_0402_5%
2 0_0402_5%
TS_EN_1
2 0_0402_5%
2 0_0402_5%
TS_EN_2
EDP_AUXN_C
EDP_AUXP_C
EDP_HPD
Touch Screen
TS_INT_1 for TS one chip solution

TS_INT_2 for TS two chip solution
17
17
Camera
+3VS
USB20_P10
USB20_N10
USB20_P10
USB20_N10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
G1
G2
G3
G4
G5
G6
41
42
43
44
45
46
ACES_50203-04001-001
SP010014B00
CONN@
4
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
Title
eDP Connector
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
29
of
55
+HDMI_5V_OUT
U3
OUT
IN
GND
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N0
PCH_DPB_P0
C381
C382
C379
C380
2
2
2
2
1
1
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
HDMI_TX1HDMI_TX1+
HDMI_TX2HDMI_TX2+
4
3
2
1
16
16
16
16
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3
C383
C384
C385
C386
2
2
2
2
1
1
1
1
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
HDMI_TX0HDMI_TX0+
HDMI_CLKHDMI_CLK+
4
3
2
1
5
6
7
8
C378
0.1U_0402_16V4Z
2 EMC@
RP18
680_0804_8P4R_5%
HDMI_CLK-
R368 1 XEMC@ 2 0_0402_5%
HDMI_R_CK-
HDMI_CLK+
R369 1 XEMC@ 2 0_0402_5%
HDMI_R_CK+
HDMI_TX0-
R370 1 XEMC@ 2 0_0402_5%
HDMI_R_D0-
HDMI_TX0+
R371 1 XEMC@ 2 0_0402_5%
HDMI_R_D0+
HDMI_TX1-
R372 1 XEMC@ 2 0_0402_5%
HDMI_R_D1-
HDMI_TX1+
R373 1 XEMC@ 2 0_0402_5%
HDMI_R_D1+
HDMI_TX2-
R374 1 XEMC@ 2 0_0402_5%
HDMI_R_D2-
AP2330W-7_SC59-3
C396
0.1U_0402_16V4Z
2 EMC@
C398
0.1U_0402_16V4Z
2 EMC@
5
+3VS
Q14B
1
1
W=40mils
16
16
16
16
HDMI_GND
+5VS
RP17
680_0804_8P4R_5%
5
6
7
8
For ESD at HDMI USB3 test
R375 1 XEMC@ 2 0_0402_5%
HDMI_TX2+
HDMI_R_D2+
+3VS
+3VS
2
PCH_DPB_HPD
Q14A
HDMI_HPD
16
R376
1M_0402_5%
R121
100K_0402_5%
+HDMI_5V_OUT
+3VS
1
2
3
4
C387
220P_0402_50V7K
XEMC@
RP15
2.2K_0804_8P4R_5%
8
HDMI_SCLK
7
HDMI_SDATA
6 SDVO_SCLK
5 SDVO_SDATA
HDMI connector
HDMI_HPD
+HDMI_5V_OUT
HDMI_SDATA
HDMI_SCLK
2
SDVO_SCLK
HDMI_R_CK+
HDMI_R_D0-
HDMI_SCLK
3
HDMI_SDATA
Q15B
HDMI_R_D0+
HDMI_R_D1-
D2
XEMC@
HDMI_R_D1+
HDMI_R_D2-
YSLC05CH_SOT23-3
SDVO_SDATA
HDMI_R_CK-
Q15A
16
16
+3VS
+3VS
JHDMI1
HDMI_R_D2+
Place closed to JHDMI1
Reserved for ESD
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
GND
D2GND
D2_shield GND
D2+
GND
20
21
22
23
ACON_HMR2U-AK120C
CONN@
DC232002700
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
Title
EOP
A
HDMI Conn
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
30
of
55
+HDMI_5V_OUT
CRB1.0 use 47ohm@100Mhz Bead
L42
EMC@
BLM18BA470SN1D_2P
PCH_CRT_G
CRT_R_1
PCH_CRT_B
CRT_G_1
EMC@
EMC@
CRT_G_2
CRT_B_2
C616
10P_0402_50V8J
JCRT1
CRT_11
C618
10P_0402_50V8J
EMC@
CRT_R_2
C647
10P_0402_50V8J
EMC@
C588
22P_0402_50V8J
EMC@
C601
22P_0402_50V8J
CRT_B_1
C622
22P_0402_50V8J
L28
BLM18BA470SN1D_2P
C611
10P_0402_50V8J
R538
150_0402_1%
C615
10P_0402_50V8J
R537
150_0402_1%
C648
10P_0402_50V8J
R536
150_0402_1%
L31
BLM18BA470SN1D_2P
L46
EMC@
BLM18BA470SN1D_2P
16
L45
EMC@
BLM18BA470SN1D_2P
16
PCH_CRT_R
16
CRT Connector
L35
BLM18BA470SN1D_2P
CRT_4
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
EMC@
C-H_13-12201560CP
CONN@
DC060006E00
R185
1 XEMC@ 2 0_0603_5%
+HDMI_5V_OUT
16
R439
0_0402_5%
1
@
PCH_CRT_HSYNC
CRT_HSYNC
CRT_DATA
OE
Vcc
R190
1 XEMC@ 2 0_0603_5%
IN A
CRT_HSYNC_2
U24
GND OUT Y
CRT_VSYNC_2
C448
10P_0402_50V8J
@
CRT_HSYNC_1
2@
C449
10P_0402_50V8J
CRT_CLK
M74VHC1GT125DF2G_SC70-5
+HDMI_5V_OUT
U23
16
2
@
R441
0_0402_5%
PCH_CRT_VSYNC
CRT_VSYNC
OE
Vcc
IN A
GND OUT Y
CRT_VSYNC_1
M74VHC1GT125DF2G_SC70-5
+3VS
3
2 C452
VCC_SYNC
VCC_VIDEO
VCC_DDC
10
11
C454
0.1U_0402_16V4Z
@
For contact
discharge ESD +/-8kV
DDC_IN1
DDC_IN2
3
S
PCH_CRT_CLK 4
DDC_OUT1
DDC_OUT2
BYP
3
4
5
CRT_R_2
CRT_G_2
CRT_B_2
14
16
CRT_HSYNC_1
CRT_VSYNC_1
9
12
CRT_CLK
CRT_DATA
DDC_CLK/DAT reserved PU Resistor
CM2009-00QR_QSOP16
@
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
+3VS
CRT_CLK
RP37
2.2K_0804_8P4R_5%
8
CRT_DATA
7
CRT_CLK
6 PCH_CRT_CLK
5 PCH_CRT_DATA
SYNC_OUT1
SYNC_OUT2
GND
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_CLK
1
2
3
4
Q1008A
VIDEO_1
VIDEO_2
VIDEO_3
SYNC_IN1
SYNC_IN2
13
15
+HDMI_5V_OUT
1
2
7
16
PCH_CRT_HSYNC
PCH_CRT_VSYNC
CRT_DATA
Q1008B
G
0.1U_0402_16V4Z
@
U10
6
D
PCH_CRT_DATA
PCH_CRT_DATA
16
+HDMI_5V_OUT
+3VS
Title
CRT Connector
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
31
of
55
+1.2V_LAN
+VDDO_CR
TRD2_N
TRD2_P
39
45
51
R02 modify
for ESD
+LAN_GPHYPLLVDDL
36
+LAN_PCIEPLLVDD
32
29
C786 1
EMC@
2 0.1U_0402_16V4Z PLT_RST_BUF#
AVDDL
AVDDL
AVDDL
TRD1_N
TRD1_P
TRD0_N
TRD0_P
GPHY_PLLVDDL
14
14
14
14
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
PCIE_PTX_C_DRX_P1
PCIE_PTX_C_DRX_N1
37
R763 1
EC_PME#
TRAFFICLED#_SERIALDI
GPIO1_LR_OUT
GPIO_0
LAN_PME#
R766 1
17,34 PLT_RST_BUF#
14 CLK_PCIE_LAN
14 CLK_PCIE_LAN#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
2 4.7K_0402_5%
2 0_0402_5%
11
31
30
33
33
33
33
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
1
1
1
1
EMC@
EMC@
EMC@
EMC@
2
2
2
2
CR_DATA0_R
CR_DATA1_R
CR_DATA2_R
CR_DATA3_R
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
25
24
23
22
52
53
54
55
SI_EEDATA
CS#_EECLK
SR_DISABLE/XD_DETECT#
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
CR_DATA4
CR_DATA5
CR_DATA6
CR_DATA7
MS_INS#/XD_CE#
GPIO2_MEDIA_SENSE/XD_RE#
CR_WP#/XD_WP#
CR_LED_CR_BUS_PWR/XD_ALE
+3VS
58
2 1K_0402_5%
R777 1
2 4.7K_0402_5% 6
LAN_MIDI2LAN_MIDI2+
43
44
LAN_MIDI1LAN_MIDI1+
41
40
LAN_MIDI0LAN_MIDI0+
LAN_MIDI3LAN_MIDI3+
33
33
LAN_MIDI2LAN_MIDI2+
33
33
LAN_MIDI1LAN_MIDI1+
33
33
LAN_MIDI0LAN_MIDI0+
33
33
0.1U_0402_16V7K
C792
65
LAN_LINK#
R12
10K_0402_5%
20mil
+LAN_XTALVDDH
C785
20mil
37
L56
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
2
1
33
66
0_0402_5%
+VDDO_CR_R
R761 1
2 0_0603_5%
5IN1_LED_R#
R762
64
63
SPROM_DOUT
SPROM_CLK
LAN_ACTIVITY#
+VDDO_CR
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z
L58
0_0402_5%
C789
@
0.1U_0402_16V4Z
33
+3V_LAN
20mil
L57
1
2
BLM18AG601SN1D_2P
+LAN_AVDDH
R760
0.1U_0402_16V7K
2
67
C784
0.1U_0402_16V4Z
C790
0.1U_0402_16V4Z
+VDDO_CR
5IN1_LED#
38
PREST#
PCIE_REFCLK_P
PCIE_REFCLK_N
CR_CLK/XD_RY_BY#
R776 1
47
46
Q6
WAKE#
SD_DETECT/XD_WE#
CR_DATA0 R768
CR_DATA1 R769
CR_DATA2 R770
CR_DATA3 R771
C787
2 0_0402_5%
R764 1
+3V_LAN
PCIE_PRX_C_DTX_P1 28
PCIE_PRX_C_DTX_N1 27
33
34
LAN_MIDI3LAN_MIDI3+
60mil
1
+LAN_BIASVDDH
SCLK_SPD1000LED#
2 C788
2 C791
49
50
LAN_PWR_EN#
PCIE_PLLVDDL
SPD100LED#_SERIALDO
1
1
C820
EMC@
1U_0402_6.3V6K
PCIE_PLLVDDL
SO_LINKLED#
0.1U_0402_16V7K
0.1U_0402_16V7K
DMG2301U-7_SOT23-3
C815
TRD3_N
TRD3_P
+LAN_AVDDL
+LAN_AVDDH
VDDO
VDDO
VDDO
48
42
7
56
62
AVDDH
AVDDH
+3V_LAN
+3V_LAN
C783
4.7U_0603_6.3V6K
XTALVDDH
+LAN_XTALVDDH
C780
0.1U_0402_16V4Z
VDDC
VDDC
17
+3V_LAN
+3V_LAN_R
C779
4.7U_0603_6.3V6K
L74
BLM31PG601SN1L_2P
EMC@
2
+3VALW
+LAN_BIASVDDH
35
61
37
1
2
+1.2V_LAN
1 EMC@
BIASVDDH
VDDO_CR
20
0.1U_0402_16V4Z
C803
1
C777
4.7U_0603_6.3V6K
C774
0.1U_0402_16V4Z
C773
0.1U_0402_16V4Z
C772
0.1U_0402_16V4Z
C771
4.7U_0603_6.3V6K
U48
1
CR_CMD_XD_CLE
CR_XD_WE#_SD_DETECT_R
R767
0_0402_5%
CR_XD_WE#_SD_DETECT
57
CR_WP#_XD_WP#_R
R772
0_0402_5%
CR_WP#_XD_WP#
60
CR_PWR_EN_R
R773
0_0402_5%
CR_PWR_EN
21
CR_CLK_XD_RY_BY#_R
R774
CR_XD_WE#_SD_DETECT
33
68
59
9
CR_WP#_XD_WP#
CR_PWR_EN
2 56_0402_5%
CR_CMD_XD_CLE_R
R775
For EMI request
CR_CLK_XD_RY_BY#
EMC@
26
33
33
2 22_0402_5%
CR_CMD_XD_CLE
33
33
VMAIN_PRSNT
+3V_LAN
10
R778
4.7K_0402_5%
40mil
TEST2
SR_LX
19
18
LAN_XTALO_R
LAN_XTALI
TEST1
LOW_PWR
SR_VFB
L59
2
+1.2V_LAN_OUT 1
4.7UH_PG031B-4R7MS_1.1A_20%
16
13
C793
0.1U_0402_16V4Z
XTALO
XTALI
14,18
LAN_CLKREQ#
12
R896
0_0402_5%
RDAC
CLK_REQ#
BCM57786XA1KMLG_QFN68_8X8
+3V_LAN
GND PLANE
15mil 38
SR_VDDP
SR_VDD
EMI Request...2010/07/27
C794
10U_0603_6.3V6M
SM010005500 500ma 600ohm@100mhz DCR 0.38
R794
10K_0402_5%
20mil
40mil
15
14
1 0.1U_0402_16V4Z
C795
L60
1
2
BLM18AG601SN1D_2P
+LAN_PCIEPLLVDD
+3V_LAN
69
Reserved for leakage current

2 LAN_RDAC
1.24K_0402_1%
+1.2V_LAN
1
R02 Modify
1
R780
40mil
1
4.7U_0603_6.3V6K
C796
C797
0.1U_0402_16V4Z
20mil
SPROM_CLK
SPROM_DOUT
R779
200_0402_1%
1
2
R783
1K_0402_5%
LAN_XTALI
LAN_XTALO_R
GND
3
1
15P_0402_50V8J
SPROM_CLK
(EECLK)
SPROM_DOUT
(EEDATA)
On chip
AT24C02
LAN_XTALO
C799
3
GND
20mil
C804
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
+1.2V_LAN
C805
4.7U_0603_6.3V6K
C800
15P_0402_50V8J
4
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
Broadcom BCM57786X
Size
Document Number
Custom
Rev
1.0
Date:
A
+1.2V_LAN
C802
L62
1
2
BLM18AG601SN1D_2P
+LAN_AVDDL
2
4
0.1U_0402_16V4Z
R784
1K_0402_5%
C801
4.7U_0603_6.3V6K
L61
1
2
BLM18AG601SN1D_2P
+LAN_GPHYPLLVDDL
C798
PLACE NEXT P14
+3V_LAN
Y6
25MHZ_10PF_7V25000014
+1.2V_LAN
Sheet
E
32
of
55
LAN_MIDI1+
LAN_MIDI1-
LAN_MIDI1+
LAN_MIDI1-
7
8
9
LAN_MIDI0LAN_MIDI0+
LAN_MIDI0LAN_MIDI0+
10
11
12
MCT2
MX2+
MX2-
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
RJ45_MIDI3+
RJ45_MIDI3-
21
20
19
RJ45_MIDI2RJ45_MIDI2+
18
17
16
RJ45_MIDI1+
RJ45_MIDI1-
15
14
13
RJ45_MIDI0RJ45_MIDI0+
R786
1K_0402_5%
LAN Connector
R787
1K_0402_5%
1
C806 1
XEMC@
C807 1
XEMC@
JRJ45
GST5009-E
SP050006B10
RJ45_MIDI0+
C810
0.1U_0402_16V4Z
32
32
TCT2
TD2+
TD2-
24
23
22
32
32
MCT1
MX1+
MX1-
LAN_MIDI2LAN_MIDI2+
4
5
6
TCT1
TD1+
TD1-
1
R788
75_0402_1%
2
1
R789
75_0402_1%
2
1
R790
75_0402_1%
2
1
R791
75_0402_1%
32
32
LAN_MIDI2LAN_MIDI2+
C813
0.1U_0402_16V4Z
LAN_MIDI3+
LAN_MIDI3-
C812
0.1U_0402_16V4Z
LAN_MIDI3+
LAN_MIDI3-
32
32
C811
0.1U_0402_16V4Z
T1
1
2
3
+3V_LAN
RJ45_MIDI0-
RJ45_MIDI1+
RJ45_MIDI2+
RJ45_MIDI2-
RJ45_MIDI1-
RJ45_MIDI3+
RJ45_MIDI3-
PR1+
LED_YELLOW_A1
PR1LED_YELLOW_A2
LED_GREEN_B1
PR3LED_GREEN_B2
C808 1
XEMC@
11
LAN_LINK#
12
C809 1
XEMC@
PR2PR4+
GND
GND
2 220P_0402_50V7K
LAN_ACTIVITY#
10
PR2+
PR3+
2 220P_0402_50V7K
LAN_ACTIVITY#
32
2 68P_0402_50V8J
LAN_LINK#
32
2 68P_0402_50V8J
13
14
40mil
PR4SANTA_130451-F
CONN@
CARD READER_2in1 SP07000TF00
DC234005300
RJ45_GND
Place close to TCT pin
BOTHHAND: S X'FORM_ GST5009-E LF LAN, SP050006B10

TIMAG:S X'FORM_ IH-160 LAN , SP050006F00
FCE:S X'FORM_ NS892407 1G , SP050006800
JP1
XEMC@
B88069X9231T203_4P5X3P2-2
2
C814 1
EMC@
10P_0402_50V8J
+XDPWR_SDPWR_MSPWR
JREAD1
SM01000LU00 300ma 22ohm@100mhz DCR 0.3

32
CR_CMD_XD_CLE
3
4
5
6
7
CR_CMD_XD_CLE
R897 2 EMC@ 1 CR_CLK

BLM15BA220SN1D_0402
CR_CLK_XD_RY_BY#
32
32
32
32
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
8
9
1
2
CR_DATA0
CR_DATA1
CR_DATA2
CR_DATA3
32 CR_WP#_XD_WP#
CR_XD_WE#_SD_DETECT
CR_WP#_XD_WP#
CR_XD_WE#_SD_DETECT
10
11
12
13
DAT0
DAT1
DAT2
CD/DAT3
WP SW
CD SW
GND SW
GND SW
C823
1U_0402_6.3V6K
By 3/11
U13
SP07000TF00
OUT
L75
BLM31PG601SN1L_2P
EMC@
1
C821
EMC@
1U_0402_6.3V6K
IN
EN
+XDPWR_SDPWR_MSPWR_R
IN
GND
40mil
3
2
G5243T11U_SOT23-5
CR_PWR_EN
32
C230
0.22U_0402_6.3V6K
C26
R26
1 XEMC@ 2
+XDPWR_SDPWR_MSPWR
T-SOL_156-1000302601_NR
CONN@
CR_CLK
+3VALW
32
CMD
VSS
VDD
CLK
VSS
C819
0.1U_0402_16V4Z
32
C817
4.7U_0603_6.3V6K
For EMI change to 22 ohm Bead

3
2
2
Card Reader Connector
J15
JUMP_43X118
@
LANGND
RJ45_GND
40mil
JP2
XEMC@
B88069X9231T203_4P5X3P2-2
D39 EMC@
L30ESDL5V0C3-2_SOT23-3
2
XEMC@
22_0402_5%
6.8P_0402_50V8C
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
LAN Magnetic & RJ45

Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
33
of
55
For Wireless LAN

+1.5VS
60mil
+3VS
1
2
1
2
1
JUMP_43X118
C441
470P_0402_50V7K
EMC@
C458
4.7U_0603_6.3V6K
C459
+1.5VS_WLAN
J13
JUMP_43X39
+3VS_WLAN
@ J3
C460
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C463
0.1U_0402_16V4Z
+3VS_WLAN
Mini Card Power Rating
Add 3/12
+3VS_WLAN
+1.5VS_WLAN
R429 1
2 4.7K_0402_5%
JMINI1
37
14
+3VS_WLAN
+3VALW
U9
5
IOAC@
C165
1U_0402_6.3V6K
4
1
OUT
MINI1_CLKREQ#
14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1
W=60mils
IN
GND
2
14
14
IN
EN
G5243T11U_SOT23-5
IOAC@
WLAN_PME#
WLAN_PME#
37
14
14
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
WLAN_ON
+3VS_WLAN
R435
0_0402_5%
1
2
@
1
2
@
37 E51TXD_P80DATA
37 E51RXD_P80CLK
E51TXD_P80DATA_R
E51RXD_P80CLK_R
R436
0_0402_5%
R437
100K_0402_5%
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GNDGND
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
WL_OFF#
PLT_RST_BUF#
MINI1_SMBCLK
MINI1_SMBDATA
WL_OFF#
37
PLT_RST_BUF#
R432 1
R434 1
@
@
USB20_N8
USB20_P8
17
17
R443 1
17,32
2 0_0402_5%
2 0_0402_5%
2 100K_0402_5%
+3VS_WLAN
MINI1_LED#
PCH_SMBCLK
14
PCH_SMBDATA
14
37
54
BELLW_80053-1021
CONN@
DC040009P00
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
MINI CARD (WLAN)

Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
34
of
55
SATA HDD Conn.

JHDD1
13
13
C391 1
C394 1
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0
SATA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
+3VS
+5VS
+3VS
+5VS_HDD
0_0805_5%
+5VS
C397
0.1U_0402_16V4Z
C420
10U_0603_6.3V6M
C390
0.1U_0402_16V4Z
100mils
13
13
SATA_PTX_DRX_P2
SATA_PTX_DRX_N2
13
13
SATA_PRX_DTX_N2
SATA_PRX_DTX_P2
C401 1
C402 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PTX_C_DRX_P2
SATA_PTX_C_DRX_N2
C403 1
C405 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_PRX_C_DTX_N2
SATA_PRX_C_DTX_P2
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
+5VS
1
R593
80mils
2
0_0805_5%
GND
GND
GND
GND
23
24
25
26
8
9
10
11
12
13
+5VS_ODD
C407
0.1U_0402_16V4Z
R49
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12
JODD1
C404
10U_0603_6.3V6M
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SATA ODD Conn.
GND
A+
AGND
BB+
GND
C392 1
C393 1
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
13
13
1
2
3
4
5
6
7
T28 PAD
TP@
DP
+5V
+5V
MD
GND
GND
GND
GND
14
15
SANTA_201902-1_13P-T
CONN@
LTCX004HZ00
CCM_C127043HR022M27FZR_22P-T
CONN@
DC231211190
2
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
HDD/ODD
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
35
of
55
D15
L24
17
PCH_USB3_TX0_P
PCH_USB3_TX0_P_C
0.1U_0402_16V7K
C484
U3TXDP0
U3RXDN0
U3RXDP0
17
PCH_USB3_TX0_N
PCH_USB3_TX0_N_C
0.1U_0402_16V7K
C482
1 1
10 9
U3RXDN0
2 2
9 8
U3RXDP0
U3TXDN0
4 4
7 7
U3TXDN0
U3TXDP0
5 5
6 6
U3TXDP0
+USB3_VCCA
U25
C483
0.01U_0402_16V7K
1
2
3
4
U3TXDN0
DLW21SN670HQ2L_4P
EMC@
+5VALW
For ESD request
37
USB_EN#
GND
IN
IN
EN/ENB
8
7
6
5
OUT
OUT
OUT
OCB
W=60mils
1
R454
0_0402_5%
2
@
USB_OC0#
17,18
SY6288D10CAC_MSOP8
3 3
L25
1 17
17
PCH_USB3_RX0_P
PCH_USB3_RX0_P
PCH_USB3_RX0_N
PCH_USB3_RX0_N
U3RXDP0
U3RXDN0
L05ESDL5V0NA-4 SLP2510P8
XEMC@
+USB3_VCCA
DLW21SN670HQ2L_4P
EMC@
By 3/18
W=100mils
1
@
@
2 0_0402_5%
2 0_0402_5%
220U_6.3V_M
C487
2
2
L26
17
USB20_P0
17
USB20_N0
USB20_P0
USB20_N0
U2DP0_L
U2DN0_L
0.1U_0402_16V4Z
C486
R458 1
R461 1
1 EMC@
U2DN0_L
U2DP0_L
WCM2012F2SF-670T04-0805_4P
XEMC@
U3RXDN0
U3RXDP0
U3TXDN0
U3TXDP0
SF000002Y00
220U 6.3V OSCON
ESR 17mohm@100Khz
USB3.0 Conn.
JUSB1
1
2
3
4
5
6
7
8
9
VBUS
DD+
GND
StdA-SSRXStdA-SSRX+
GND-DRAIN
StdA-SSTXStdA-SSTX+
GND
GND
GND
GND
10
11
12
13
OCTEK_USB-09EAAB
CONN@
2
DC233008O20
USB/B
(USB Port 1, Port2)
+5VALW
PWR/B
JUSB2
JPWR1
1
2
3
4
5
6
GND
GND
1
2
3
4
5
6
LID_SW#
PWR_LED#
ON/OFFBTN#
+3VALW
+3VLP
LID_SW#
37
PWR_LED#
38
ON/OFFBTN#
38
USB_EN#
7
8
17
17
USB20_N1
USB20_P1
17
17
USB20_N2
USB20_P2
USB20_N1
USB20_P1
USB20_N2
USB20_P2
ACES_88514-00601-071
CONN@
SP010014M00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
ACES_88514-01201-071
CONN@
SP01001BF00
4
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
USB3.0 Conn/USB_B/PWR_B
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
36
of
55
+EC_VCCA
+3VALW_EC
+3VS
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
TS_EN
MINI1_LED#
GPU_TGLREQ#
WL_OFF#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
2.2K_0804_8P4R_5%
38
Reserve for ESD

1
C339
38
2 0.01U_0402_16V7K
KSI[0..7]
KSI[0..7]
KSO[0..17]
KSO[0..17]
PLT_RST#
XEMC@
34
22
43,44
43,44
14,22
14,22
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
15
15
PM_SLP_S3#
PM_SLP_S5#
18 EC_SMI#
29 TS_EN
MINI1_LED#
GPU_TGLREQ#
34
40
32
FAN_SPEED1
EC_PME#
E51TXD_P80DATA
E51RXD_P80CLK
PCH_PWROK
PWR_SUSP_LED#
EC_WLAN_LED#
FAN_SPEED1
EC_PME#
E51RXD_P80CLK use for BT_ON

38
WL_OFF#
34
34
E51TXD_P80DATA
E51RXD_P80CLK
15 PCH_PWROK
38 PWR_SUSP_LED#
EC_WLAN_LED#
PAD
TP@
ECAGND
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
4.7K_0402_5%
TP_DATA
R292
4.7K_0402_5%
EC_VDD/AVCC
21
23
26
27
EC_SPOK
BEEP#
EC_SPOK 43
BEEP# 39
USB_EN# 36
GPU_OVERT
+3VS
GPU_OVERT
63
64
65
66
75
76
BATT_TEMP
68
70
71
72
GPU_ALERT
EN_DFAN1
83
84
85
86
87
88
EC_MUTE#
97
98
99
109
VGATE
VGA_ON
HDA_SDOUT_PCH
VCIN0_PH_R
RP11
22
BATT_TEMP
ADP_I
VGA_PWROK
VGA_PWROK
43
43,44
10K_0804_8P4R_5%
H_PROCHOT#
EC_MUTE#
49,5
22
40
2
G
H_PROCHOT#_EC
Q16
39
LAN_PWR_EN#
WLAN_PME#
DGPU_HOLD_RST#
TP_CLK
TP_DATA
8
7
6
5
18,50
GPU_ALERT
EN_DFAN1
1
2
3
4
GPU_OVERT
GPU_ALERT
GPU_TGLREQ#
100P_0402_50V8J ECAGND
EMC@
ADP_I
AD_BID0
WLAN_PME# 34
DGPU_HOLD_RST#
TP_CLK 38
TP_DATA 38
VGATE 15,49
VGA_ON 22,41,50
HDA_SDOUT_PCH
32
17
13
SPI Device Interface
SPI Flash ROM
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
119
120
126
128
R302 1
GPIO
Bus
GPIO
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
GPI
11
24
35
94
113
T39
122
123
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00
Int. K/B
Matrix
+5VS
C338 2
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
R293
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
TP_CLK
43
73
74
89
90
91
92
93
95
121
127
ENBKL
100
101
102
103
104
105
106
107
108
PCH_RSMRST#
EC_LID_OUT#
VCIN1_PROCHOT_R
H_PROCHOT#_EC
MAINPWON
BKOFF#
PBTN_OUT#
110
112
114
115
116
117
118
ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
124
+V18R
2 100K_0402_5%
ENBKL
16
KBL_EN#
FSTCHG
BATT_BLUE_LED#
GPU_CLAMP_EN
PWR_LED
BATT_AMB_LED#
SYSON
VR_ON
38
FSTCHG 44
BATT_BLUE_LED# 38
GPU_CLAMP_EN 22
PWR_LED 38
BATT_AMB_LED# 38
SYSON
41,46
VR_ON 49
PM_SLP_S4#
15
PCH_RSMRST#
15
EC_LID_OUT#
18
H_PROCHOT#_EC
43
MAINPWON
43,45
BKOFF# 29
PBTN_OUT#
BKOFF#
15
SA_PGOOD
SA_PGOOD
2
@
R297
100K_0402_5%
ACIN
47
2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
GND/GND
GND/GND
GND/GND
GND/GND
GND0
8
7
6
5
67
9
22
33
96
111
125
AD Input
RP34
1
2
3
4
+3VS
ECAGND
18 EC_SCI#
34 WLAN_ON
2 10K_0402_5%
LID_SW#
PW M Output
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
ACIN 15,44
EC_ON 45
ON/OFF
38
LID_SW# 36
SUSP# 41,44,46,48
9012_PECI
KB9012QF-A3_LQFP128_14X14
R306 1
2 43_0402_1%
H_PECI
GPU_ACIN
GPU_ACIN
C342
100P_0402_50V8J
EMC@
22
+3VALW_EC
C344
4.7U_0603_6.3V6K
20mil
Connection for power OTP mechanism
EC_PME#
2 100K_0402_5%
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0LPC & MISC
43
R287
C335
0.1U_0402_16V4Z
AGND/AGND
2 100K_0402_5%
12
13
37
20
38
+EC_VCCA
EC_MUTE#
69
CLK_PCI_LPC
PLT_RST#
EC_RST#
EC_SCI#
WLAN_ON
1
2
3
4
5
7
8
10
SM010015410 300ma 80ohm@100mhz DCR 0.3
+3VLP
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
17 CLK_PCI_LPC
17,5 PLT_RST#
@
EMC@
U22
+3VALW_EC
R295 1
0.1U_0402_16V4Z
18 GATEA20
18 EC_KBRST#
13 SERIRQ
13 LPC_FRAME#
13 LPC_AD3
13 LPC_AD2
13 LPC_AD1
13 LPC_AD0
R294 1
1
@
C333
1000P_0402_50V7K
EC_RST#
1
@
C336
0.1U_0402_16V4Z
C332
0.1U_0402_16V4Z
C331
0.1U_0402_16V4Z
1 47K_0402_5%
C337 2
L29
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
+3VALW_EC
2 EMC@ 1
CLK_PCI_LPC
R285
33_0402_5%
R288 2
+3VALW_EC
1
2
@
0_0805_5%
C330
0.1U_0402_16V4Z
C329
10P_0402_50V8J
1
2
EMC@
1
R286
L30
1
ECAGND 2
FBMA-L11-160808-800LMT_0603
R309
10K_0402_5%
@
VCIN0_PH_R
SM010015410 300ma 80ohm@100mhz DCR 0.3
+3VLP
Reserve for EMI
VCIN1_PROCHOT_R
Board ID
comparator is incorporated by 9012
2
R442
2
R440
@
@
1
0_0402_5%
1
0_0402_5%
VCIN0_PH
43
VCIN1_PROCHOT
43
See definition no Notes page, NEED to check EVERY TIME before new gerber-out
+3VALW_EC
R314
100K_0402_5%
Phase
AD_BID0
Ra
Rb
R316
33K_0402_5%
C346
0.1U_0402_16V4Z
@
Revision
BID0
BID1
EVT
0.1
* PVT
0.2
PVT2
0.3
MP
1.0
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
EC ENE-KB9012
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
37
of
55
KSI[0..7]
KB Conn.
37
37
TP_CLK
TP_DATA
To TP/B Conn.
+5VS
JTP2
27
28
E-T_6905-E26N-01R
CONN@
SP01000IJ00
SW4
TJE-532QR5_6P
TP_DATA 37
TP_CLK 37
LEFT_BTN#
RIGHT_BTN#
LEFT_BTN#
CONN@
100g for Press
KB BackLight Conn.
+5VS
JBL1
4
3
2
1
+5VS_BL
BL@
R451
Q44
100K_0402_5% DMG2301U-7_SOT23-3
1
BL@ 2 KBL_EN_R
37
C524
0.1U_0603_25V7K
@
36
37
Q17
L2N7002LT1G_SOT23-3
R535
100K_0402_5%
avoid flash issue when
abnormall shutdown
PWR_LED#
37
LED6
BATT_BLUE_LED#
BATT_BLUE_LED#
BATT_AMB_LED#
BATT_AMB_LED#
R699
51_0402_5%
R698
680_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
LED7
G
Q26
L2N7002LT1G_SOT23-3
@
PWR_LED
+3VALW
LED
PWR_LED#
PWR_LED#
37
PWR_SUSP_LED#
PWR_SUSP_LED#
27
28
R700
51_0402_5%
R701
680_0402_5%
+3VS
HDD LED
SP01000IJ00
+3VS
2 2
+3VLP
MEDIA_LED#
B
A
2
1
LED8
5IN1_LED#
37
32
PCH_SATALED#
EC_WLAN_LED#
EC_WLAN_LED#
13
R702
680_0402_5%
LTST-C191KFKT-2CA_ORANGE
LTST-C191TBKT-CA_BLUE
+3VS
R632
10K_0402_5%
U39
Y
G
For BCM57786X
LED4
ON/OFF BTN
+3VS
R740
51_0402_5%
LTST-C295TBKF-CA_AMBER-BLUE
G1
G2
KBL_EN#
6
5
SP01000Z300
37
G2
G1
ACES_50504-0040N-001
CONN@
2
1
1
@
R592
0_0402_5%
4
3
2
1
3
+5VALW
E-T_6905-E26N-01R
CONN@
SW5
TJE-532QR5_6P
RIGHT_BTN#
100g for Press
SP010014M00
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
ACES_88514-00601-071
JKB2
7
8
GND
GND
KB Conn.
0.1U_0402_16V4Z
2
C663 1
1
2
3
4
5
6
1
2
3
4
5
6
5
6
G1
G2
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
XEMC@ C551
100P_0402_50V8J
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
KSO[0..17]
XEMC@ C553
100P_0402_50V8J
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSI[0..7]
KSO[0..17]
JKB1
ON/OFFBTN#
36
1
@
R594
0_0402_5%
R534
100K_0402_5%
ON/OFF
37
ON/OFFBTN#
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
KB & TP & LED

Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
38
of
55
Int. Speaker Conn.

+VDDA
40mil
JUMP_43X118
@
1
1
1
1
XEMC@
XEMC@
XEMC@
XEMC@
2
2
2
2
JSPK1
40mil
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
2
C554
EMC@
0.1U_0402_16V4Z
R527
R528
R532
R533
1
2
3
4
SPK_R+
SPK_RSPK_L+
SPK_L-
1
2
3
4
+VDDA
C444
XEMC@
330P_0402_50V7K
2
GNDA
0.1U_0402_16V4Z
1
C604
HD Audio Codec
R238 1
2 60.4_0603_1% HPOUT_L_1
HP_RIGHT R237 1
2 60.4_0603_1% HPOUT_R_1
17
18
21
19
20
35
37
29
10mil
30
10mil 31
+INTMIC_VREFO
C584 1
GNDA
C574 1
GND
C583 1
R546 2
LINE2_R
35mA
SPK_OUT_L+
MIC2_R
SPK_OUT_L-
LINE1_L
SPK_OUT_R+
LINE1_R
SPK_OUT_RMIC1_L
HPOUT_L
MIC1_R
HPOUT_R
CBN
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
2
10U_0603_6.3V6M
1 20K_0402_1%
10mil 27
39
7
15
CBP
SDATA_OUT
MIC2_VREFO
HP_PLUG#_1
R545
GND
39.2K_0402_1%
C575 1
2 2.2U_0402_6.3V6M
CPVEE
SENSE_A
34
10mil 13
SYNC
RESETB
MIC1_VREFO_R
42
SPKL+
43
SPKL-
MIC2JD
48
BCLK
45
SPKR+
44
SPKR-
32
HP_LEFT
33
8
5
10
11
LDO2_CAP
GPIO0/DMIC_DATA
LDO3_CAP
GPIO1/DMIC_CLK
JDREF
PCBEEP
MONO_OUT
AVSS2
VREF
13
3
13
+INTMIC_VREFO
GND
R417
EC_MUTE#
INT_MIC_R
37
12
J12
JUMP_43X39
1
2
2
@ 1
MONO_IN
16
38
28
GND
BEEP#_R
1
1
BEEP#
37
2
R529
47K_0402_5%
CODEC_VREF
10mil
25
1
C555
1U_0402_6.3V6K
GNDA Place next pin27
XEMC@
100P_0402_50V8J
C556
J11
JUMP_43X39
1
2
2
@ 1
For EMI
15mil
47
15mil
1 XEMC@ 2
L51
0_0603_5%
JMIC1
1
2
INT_MIC_R_1
C550
XEMC@
220P_0402_50V7K
3
4
1
2
G1
G2
ACES_88266-02001
CONN@
PCH_SPKR
GND
13
R530
47K_0402_5%
SP020008Y00
GNDA
GNDA
4
GNDA
GNDA
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
Title
HD Audio Codec ALC3225

Size
Document Number
Custom
Rev
1.0
Date:
A
Int. MIC
SM010030010 200ma 120ohm@100mhz DCR 0.2
10K_0402_5%
4.7K_0402_5%
R531
J14
JUMP_43X39
1
2
2
@ 1
13
XEMC@
2 C573
22P_0402_50V8J
C578
10U_0603_6.3V6M
AVSS1
GND
13
SPDIFO
GND
J7
JUMP_43X39
1
2
2
@ 1
GNDA
ALC3225-CG_MQFN48_6X6
GND
HDA_SDIN0
HDA_RST_AUDIO#
HDA_BITCLK_AUDIO
LDO1_CAP
DVSS
COM_MIC
13
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
C577
2.2U_0402_6.3V6M
49
GNDA
HDA_SDOUT_AUDIO
1 XEMC@ 2
1
R548 0_0402_5%
SENSE A
SENSE B
GNDA
HP_RIGHT
2
HDA_SDIN0_AUDIO 1 R547
33_0402_5%
C576
0.1U_0402_16V4Z
GND
GNDA
MIC1_VREFO_L
CPVEE
DC230009K00
D1
AZ5125-02S.R7G_SOT23-3
EMC@
R543
22K_0402_5%
14
1
DVDD
36
46
41
40
68mA 600mA
PD#
Place near
codec
C571
MIC2_L
SDATA_IN
C570
2.2U_0402_6.3V6M
+MIC2_VREFO
GNDA
LINE2_L
R542
22K_0402_5%
1
2
MIC2JD
10U_0603_6.3V6M
DVDD_IO
23
CPVDD
24
PVDD2
LINE2_C_L
4.7U_0603_6.3V6K
2
LINE2_C_R
4.7U_0603_6.3V6K
2
MIC2_C_L
4.7U_0603_6.3V6K
2
MIC2_C_R
4.7U_0603_6.3V6K
PVDD1
26
U34
22
R539
2.2K_0402_5%
10U_0603_6.3V6M
2
2
0.1U_0402_16V4Z
6
SINGA_2SJ3053-100111F
CONN@
HP_PLUG#
0_0603_5%
1
C564
GND Place near Pin1, 9
GNDA
1
INT_MIC
C770 1
1K_0402_5%
2
C769 1
1000P_0402_50V7K
C568 1
1
COM_MIC_R
1K_0402_5%
C569 1
GNDA
2
5
COM_MIC
2
R540
HPOUT_R_2
+MIC2_VREFO
+3VS
GNDA
COM_MIC
1
C636
Combo MIC
2
R726
C62 1
EMC@
HPOUT_L_2
2
0.1U_0402_16V4Z
AVDD2
INT_MIC_R
1 XEMC@ 2
L38
0_0603_5%
C562
L52
Place near Pin25, 38
Internal MIC
1
@ C582
AVDD1
1
2
0_0603_5%
JHP1
4
20mil
2
C567
10U_0603_6.3V6M
+VDDA
2
SM010030010 200ma 120ohm@100mhz DCR 0.2
20mil
+3VS_DVDD 0.1U_0402_16V4Z
+AVDD1_HDA
@
SM010030010 200ma 120ohm@100mhz DCR 0.2
Headphone Out
GNDA
HP_PLUG#
GNDA
Place near Pin40
L54
GND
GNDA
C445
XEMC@
COM_MIC
330P_0402_50V7K
1
2
+3VS_VDDA
C605
10U_0603_6.3V6M
0_0603_5%
L36
0_0603_5%
1 XEMC@ 2
Place near Pin46

HP_LEFT
L55
HP_PLUG#
C608
10U_0603_6.3V6M
2
G
Q31
L2N7002LT1G_SOT23-3
GND
Place near Pin41
+3VS
GND
0.1U_0402_16V4Z
C558
+PVDD_HDA
40mil
L33
FBMA-L11-201209-221LMA30_2P
2
1
SM010014520 3000ma 220ohm@100mhz DCR 0.04
GND
D37
AZ5125-02S.R7G_SOT23-3
XEMC@
R523
100K_0402_5%
HP_PLUG#_1
+VDDA
5
6
SP02000K200
D27
AZ5125-02S.R7G_SOT23-3
XEMC@
GND
G1
G2
ACES_88266-04001
CONN@
40mil
SPKR+
SPKRSPKL+
SPKL-
J6
+5VS
Sheet
E
39
of
55
FAN1 Conn
EN_DFAN1
+VCC_FAN1
2
@
R515
0_0402_5%
EN
GND
VIN
GND
VOUT
GND
VSET
GND
NCT3942S_SO8
FD2
@
FIDUCIAL_C40M80
FD3
FD4
@
H27
H_3P7
1
2
3
+VCC_FAN1
C630
1000P_0402_50V7K
XEMC@
1
2 GND
3 GND
4
5
H22
H_2P5N
ACES_88231-03041
CONN@
SP020020710
H21
H_3P0
JFAN1
FAN_SPEED1
40mil
37
FIDUCIAL_C40M80
H23
H_2P5X3P5N
@
R516
10K_0402_5%
+3VS
FIDUCIAL_C40M80
FIDUCIAL_C40M80
H13
H14
H15
H16
H20
H24
H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 H_4P0
C627
4.7U_0603_10V6K
1
2
@
C631
1000P_0402_50V7K
1
2
8
7
6
5
FD1
37
1
2
3
4
U31
H3
H4
H5
H6
H9
H10
H11
H12
H17
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
C632
4.7U_0603_10V6K
1
2
+5VS
Compal Secret Data
2013/02/04
Issued Date
Deciphered Date
EOP
Title
FAN & Screw Hole & G-Sensor
Custom
Rev
1.0
Date:
Sheet
40
E
of
55
+5VALW
+1.5V to +1.5VS
C468
1 4.7U_0603_6.3V6K
+1.5V
+1.5VS
U30
AO4478L_SO8
+VSB
Q1009A
1.5VS_GATE
1
2
SUSP
+5VALW
5VS_ON
6
7
+5VALW
2
0.1U_0402_16V4Z
VOUT1
VOUT1
ON1
CT1
VBIAS
GND
ON2
CT2
VIN2
VIN2
VOUT2
VOUT2
GPAD
C416
0.1U_0603_25V7K
14
13
+3VS_OUT
C976
12
+3VS
46
JUMP_43X118
Q29
L2N7002LT1G_SOT23-3
11
2
10
SUSP
SUSP
1 330P_0402_50V7K
1
330P_0402_50V7K
C967
+5VS_OUT
9
8
C469
4.7U_0603_6.3V6K
@ J37
15
37,44,46,48
SUSP#
R555
10K_0402_5%
+5VS
2
R926 1
0_0402_5%
C979
FF change to CPU
2
0.1U_0402_16V4Z
VIN1
VIN1
1
+1.5VS_R
3VS_ON
R378
330K_0402_5%
47K_0402_5%
2 R927
1
C980
JUMP_43X118
SUSP#
1
2
+3VALW
R377
470_0603_5%
@ J36
U11
R552
100K_0402_5%
1
2
3
C414
4.7U_0603_6.3V6K
C410
4.7U_0603_6.3V6K
8
7
6
5
TPS22966DPUR_SON14_2X3
2
5
4
+1.05VSDGPU_R
1 VGA@ 2
R1105
270K_0402_5%
EN
Q54A
VGA@
G5243T11U_SOT23-5
VGA@
+5VALW
R573
470_0603_5%
+1.5V
C621
VGA@
1 4.7U_0603_6.3V6K
R554
100K_0402_5%
@
Q54B
VGA@
C1451
0.1U_0603_25V7K
VGA@
1
3
SYSON#
+1.5V_R
1
VGA_ON#
1.05VSDGPU_GATE
+VSB
VGA_ON#
C620
VGA@
1U_0402_6.3V6K
GND
IN
OUT
IN
100mil(1.5A)
2
SUSP
G
Q38
L2N7002LT1G_SOT23-3
@
R1101
47_0603_5%
VGA@
2
SUSP
G
Q37
L2N7002LT1G_SOT23-3
@
VGA_ON From EC
22,37,50
VGA_ON
2
Q40A
@
5
SYSON
Q40B
@
SYSON#
+3VSDGPU
U12
+3VS
(By 3/12)
3 2
VGA@
C1449
@
1U_0402_6.3V6K
1
2
3
C1447
VGA@
10U_0603_6.3V6M
C1448
10U_0603_6.3V6M
VGA@
8
7
6
5
2
SUSP
G
Q36
L2N7002LT1G_SOT23-3
R568
470_0603_5%
+1.8VS_R
+1.05VSDGPU
+1.05VS_VTT_R
U40
AO4478L_SO8
R567
470_0603_5%
2
+0.75VS_R
+3VS to +3VSDGPU for GPU
+1.05VS_VTT
R566
470_0603_5%
+1.05VS_VTT to +1.05VSDGPU
+1.8VS
+1.05VS_VTT
+0.75VS
Q1009B
SUSP
SYSON
37,46
S3 reduce
+5VALW
+0.75V sequence
R560
100K_0402_5%
VGA@
Q34
L2N7002LT1G_SOT23-3
VGA_ON#
2
2
VGA_ON
R561
100K_0402_5%
VGA@
G
VGA@
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
A
Title
DC Interface
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
41
of
55
EMI@ PL102
HCB2012KF-121T50_0805
1
2
EMI@ PC101
1000P_0603_50V7K
EMI@ PC102
100P_0603_50V8
1
2
DC_IN_S1
1
2
3
4
GND
GND
VIN
EMI@ PL101
HCB2012KF-121T50_0805
1
2
EMI@ PC103
100P_0603_50V8
CONN@ PJP101
ACES_50305-00441-001_4P
EMI@ PC104
1000P_0603_50V7K
PBJ1 @
PR57
560_0603_5%
1
2
+RTCBATT_R1
+RTCBATT_R
PR102
560_0603_5%
1
2
+RTCBATT
ML1220T13RE
@ PR105
0_0402_5%
1
2
+3VLP
+CHGRTC
Compal Secret Data
2013/02/04
Issued Date
Deciphered Date
EOP
Title
DCIN
Custom
Rev
1.0
Date:
Sheet
42
E
of
55
+3VLP
EMI@ PL202
HCB2012KF-121T50_0805
1
2
37,44
37,45
MAINPWON
MAINPWON
@ PU204
1
@ PR231
100K_0402_1%
37,44
EC_SMB_DA1
1
2
37
@ PR230
10K_0402_1%
3
4
VCC TMSNS1
GND RHYST1
OT1
TMSNS2
OT2
RHYST2
8
2
7
6
EC_SMB_CK1
1
2
@ PR229
10K_0402_1%
2
BATT_TEMP
@ PC209
0.1U_0603_25V7K
EMI@ PC201
0.01U_0402_25V7K
EMI@ PC202
1000P_0402_50V7K
PR201
100_0402_1%
PR203
1K_0402_1%
PR208
1K_0402_1%
1
2
BATT+ <45,47>
PR202
100_0402_1%
+3VLP
2
1
PR206
6.49K_0402_1%
EMI@ PL201
HCB2012KF-121T50_0805
1
2
CONN@ PJP201
SUYIN_200275GR008G13GZR
10
GND 9
GND 8
BATT_S1
8 7
7 6
BI
6 5
TH
5 4
EC_SMCK
4 3
EC_SMDA
3 2
2 1
1
@ PR232
47K_0402_1%
@ PH202
100K_0402_1%_TSM0B104F4251RZ
G718TM1U_SOT23-8
For KB9012
OTP
For KB9012
sense 20m
Active
Recovery
92
1.2V, Active
65W
84W,1.2V
56W,0.793V
56
2.255V, Recovery
90W
117W,1.2V
77W,0.791V
PQ202
TP0610K-T1-E3_SOT23-3
120W
37 +EC_VCCA
ADP_I 37,44
PR228
12.4K_0402_1%
2
G
VCIN0_PH 37
PQ203
2N7002KW_SOT323-3
VCIN1_PROCHOT
1
PR207
10K_0402_1%
1
2
@
H_PROCHOT#_EC
PH201
100K_0402_1%_TSM0B104F4251RZ
@ PJ201
1
37
B value:4250K1%
+VSB
+VSBP
37
@ PC208
1U_0402_6.3V6K
90W@ PR218
10.5K_0402_1%
@ PR219
0_0402_5%
1
2
45 SPOK
@ PR213
100K_0402_1%
65W@ PR218
4.87K_0402_1%
1
2
PH201 under CPU botten side :

CPU thermal protection at 92 degree C ( shutdown )
Recovery at 56 degree C
+VSBP
PC206
0.1U_0603_25V7K
VL
PR212
22K_0402_1%
2
1
1
PR211
100K_0402_1%
37 EC_SPOK
PC205
0.22U_0603_25V7K
B+
JUMP_43X39
PR225
10K_0402_1%
For 65W adapter==>action 84W , Recovery 56W

For 90W adapter==>action 117W , Recovery 77W
PR226
0_0402_5%
37 ECAGND
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
A
Title
BATTERY CONN / OTP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
43
of
55
for reverse input protection
2
G
PR305
1_0402_1%
1
2
PC308
0.01U_0402_50V7K
PC318
10U_0805_25V6K
PC315
10U_0805_25V6K
1
2
1 CSON1
2
1 CSOP1
2
2
1
2
PC314
0.1U_0402_25V6
PR313
4.7_1206_5%
5
3
2
1
PC317
0.1U_0402_25V6
Typ
18.006V
17.593V
Max.
18.504V
18.237V
@ PR325
0_0402_5%
1
2
EC_SMB_CK1
37,43
EC_SMB_DA1
37,43
ILIM and external DPM

Min.
3.906A
Close EC
ADP_I
Typ
Max.
4.006A 4.108A
37,43
@ PC325
0.1U_0402_16V7K
Min.
17.520V
16.967V
2
G
SUSP#
2
2
PC324
100P_0402_50V8J
37,41,46,48
L-->H
H-->L
PC326
2200P_0402_50V7K
2
1
Vin Detector
PR324
64.9K_0402_1%
PQ308
+3VALW
ACDET
FSTCHG
1
2
1
1 2
37
PQ307
PDTC115EU_SOT323-3
PR326
100K_0402_1%
1
2
PR322
422K_0402_1%
PR321
2M_0402_1%
BATT+
@EMI@
PC322
0.01U_0402_25V7K
ACDET
VIN
2 CSON1
PR315
6.8_0603_5%
BQ24725_BATDRV
PR317
316K_0402_1%
2
1
PR320
100K_0402_1%
For 4S per cell 4.35V battery
PR319
2M_0402_1%
SRN 1
PR314
10_0603_5%
2 CSOP1
ILIM
15,37 ACIN
12
11
BATDRV
SCL
ACOK
SRP 1
@EMI@
PC316
680P_0402_50V7K
SRN
13
10
ACDRV
ACOK
SRP
SDA
2
PR316
100K_0402_1%
CMSRC
DL_CHG
14
GND
PL302
PR312
10UH_FDSD0630-H-100M-P3_3.8A_20%
0.01_1206_1%
2
4
BQ24725_LX 1
CHG 1
PQ306
SIS412DN-T1-GE3_POWERPAK8-5
15
ACP
IOUT
PC307
2200P_0402_50V7K
PC313
1U_0603_25V6K
16
BTST
3
2
1
LODRV
BQ24735_ACDRV
PQ305
4
DH_CHG-1
REGN
ACN
ACDET
+3VLP
PC305
0.1U_0402_25V6
2
1
PR310
2.2_0603_5%
1
PR311
2.2_0603_5%
1
2
EMI request 3/13
1
BQ24725_BST 2
BQ24725_LX
DH_CHG
BQ24725ARGRR_QFN20_3P5X3P5
BQ24735_CMSRC
EMI request not mount 3/12
PD303
RB751V-40_SOD323-2
17
PR309
10_1206_1%
20
PAD
PR306
4.12K_0603_1%
@EMI@ @EMI@
19
PHASE
1
2
3
1
21
EMI request 3/13
PC312
1U_0603_25V6K
PU301
BQ24725_BATDRV 1
PC310
0.047U_0402_25V7K
1
2
2
1
PC304
10U_0805_25V6K
2
1
PC303
10U_0805_25V6K
2
1
PC747 EMI@
470P_0402_50V7K
PC746 EMI@
PD302 470P_0402_50V7K
BAS40CW_SOT323-3
1
2
BQ24735_ACP
BQ24735_ACN
4x4x2
DH_CHG
18
EMI@ PL301
1.2UH_PNS40201R2YAF_3A_30%
1
2
HIDRV
EMI@ PC745
VIN
470P_0402_50V7K
PR308
4.12K_0603_1%
CHG_B+
add EMI request cap 3/12
PR303
0.02_1206_1%
PC306
0.1U_0402_25V6
1
2
PR307
4.12K_0603_1%
2
1
B+
PC321
0.1U_0603_25V7K
P2
1
2
PC302
0.1U_0402_25V6
PC301
2200P_0402_50V7K
2
1
PQ303
1
2
3
5
1
2
3
100ppm
P1
PQ302
AON6414AL_DFN8-5
PR304
1_0402_1%
VIN
PR301
3M_0402_5%
PC311
0.1U_0603_25V7K
PR302
1M_0402_5%
PQ304
1
2
5
3
VCC
PC309
0.1U_0402_25V6
PQ301
2N7002KW_SOT323-3
S 2N7002KW_SOT323-3
Issued Date
Compal Secret Data

2013/02/04
Deciphered Date
EOP
Title
CHARGER
Custom
Rev
1.0
Date:
Sheet
D
44
of
55
PR401
499K_0402_1%
1
2
PR405
150K_0402_1%
2
1
B+
EN1 and EN2 dont't floating
B+
new version SY8208C add rise time
@ PC405
10U_0805_25V6K
2
1
EN2
3V_VIN
IN
3V5V_EN
FB
BS
1
BST_3V
PR404
2
0_0603_5%
PC426
PR413
0.01UF_0402_25V7K 1K_0402_5%
1
2
1
2
PC401
1
2
0.1U_0603_25V7K
PL402
@EMI@ PC423
2
3.3V LDO 150mA~300mA
Vout is 3.234V~3.366V
TDC=8A
@
+3VALWP
PC413
22U_0805_6.3V6M
SY8208BQNC_QFN10_3X3
PR450
100K_0402_1%
2
PC414
22U_0805_6.3V6M
2
1
+3VLP
PC422
4.7U_0603_6.3V6K
PC416
22U_0805_6.3V6M
2
1
+3VALWP
1
LDO
PG
OUT
1UH_FDSD0630-H-1R0M-P3_11A_20%
680P_0603_50V7K 4.7_1206_5%
SPOK
SPOK
GND
LX_3V
PC411
22U_0805_6.3V6M
2
1
10
LX
9
43
EN1
@EMI@ PR409
13V_SN
2
1
PC408
10U_0805_25V6K
2
1
EMI@ PC410
2200P_0402_50V7K
2
1
PL401
HCB2012KF-121T50_0805
1
2
@EMI@ PC403
0.1U_0402_25V6
2
1
EMI@
PU401
PJ401
P
J401
+3VALWP
+3VALW
JUMP_43X118
new version SY8208C add rise time

PU402
BS
MAINPWON
PR403
0_0603_5%
1
2
1
PC404
0.1U_0603_25V7K
1
2
VL
SY8208CQNC_QFN10_3X3
PJ402
P
J402
+5VALWP
+5VALW
JUMP_43X118
Vout is 4.998V~5.202V
5V LDO 150mA~300mA
PR402
P
R402
2
+5VALWP
PC412
22U_0805_6.3V6M
LDO
1UH_FDSD0630-H-1R0M-P3_11A_20%
PC415
22U_0805_6.3V6M
2
1
PG
PC418
22U_0805_6.3V6M
2
1
OUT
LX_5V
VCC
10
LX
@EMI@ PC424 @EMI@ PR408

2
15V_SN
2
1
GND
PR407
2.2K_0402_5%
1
2
1
BST_5V
PC421
4.7U_0603_6.3V6K
PC420
4.7U_0603_6.3V6K
1
2
37,43
3
6
PC425
PR412
6800P_0402_25V7K1K_0402_5%
3V5V_EN
PL403
9
EC_ON
EN
FB
SPOK
37
IN
VCC_3.3V
@EMI@ PC402
0.1U_0402_25V6
2
1
EMI@ PC409
2200P_0402_50V7K
2
1
@ PC407
10U_0805_25V6K
2
1
PC406
10U_0805_25V6K
2
1
5V_VIN
PC417
22U_0805_6.3V6M
2
1
PL404
HCB2012KF-121T50_0805
1
2
680P_0603_50V7K 4.7_1206_5%
EMI@
B+
TDC=8A
0_0402_5%
4
1
2
PC419
4.7U_0603_6.3V6K
1
PR406
1M_0402_1%
3V5V_EN
change to common part 0603 size(0311)

EN1 and EN2 dont't floating
<BOM Structure>
Compal Secret Data

2013/02/04
Issued Date
EOP
Deciphered Date
Title
3VALW/5VALW
Custom
Date:

Sheet
45
Rev
1.0
of
55
PC521
0.1U_0402_25V6
PC503
2200P_0402_50V7K
1
PQ502
MDV1525URH_PDFN33-8-5
2
3
2
1
+1.5VP
12
DCR:8.5m
1
@EMI@ PC507
680P_0402_50V7K
@EMI@ PR503
4.7_1206_5%
PC506
330U_2.5V_M
PR504
8.45K_0402_1%
2
1
13
PQ503
S TR MDU1512RH 1N POWERDFN56-8
5
16
14
Rds=4.2m(Typ)
5.0m(Max)
11
2
PR505
5.1_0603_5%
+5VALW
@ PJ504
1
1
2
+1.5VP
PC509
1U_0603_10V6K
+3VALW
PR506
10K_0402_1%
@EMI@
PL501
S COIL 1.5UH 20% TMPB0604M-1R5MN-Z01 11A
1
2
LG_1.35V
TON
S5
VDD
EMI@
B+
6.6x7.3x3.8 TAI-TECH
15
PR509
10K_0402_1%
1
2
1
PR513
100K_0402_1%
PC511
0.1U_0402_16V7K
EMI@ PL507
HCB2012KF-121T50_0805
2
1
PR510
10K_0402_1%
PC510
1U_0603_10V6K
+1.5V
@ PJ505
1
PGOOD_1.35V
JUMP_43X118
@ PJ506
1
+0.75VSP
+0.75VS
JUMP_43X79
HW request 0308
FB=0.75V
To GND = 1.5V
To VDD = 1.8V
JUMP_43X118
PR508
887K_0402_1%
2
1 1.35V_B+
2
G
SUSP
41 SUSP
10
8
S5_1.35V
S3
VDDQ
PGOOD
VDDP
@ PR507
0_0402_5%
1
2
PQ501
2N7002KW_SOT323-3
PHASE
17
UGATE
BOOT
18
19
VLDOIN
VTTREF
PR511
470K_0402_1%
1
2
37,41 SYSON
CS
RT8207MZQW_WQFN20_3X3
PC502
10U_0805_25V6K
5
2
GND
PGND
FB
PC508
0.033U_0402_16V7K
LGATE
VTTSNS
+1.5VP
HW sequence 0222
VTTGND
+VTT_REFP
PAD
S3_1.35V
20
PU501
21
PC504
0.1U_0603_25V7K
1
BST_1.35V-1 2
LX_1.35V
VTT
1
2
PC505
10U_0805_25V6K
PC501
10U_0805_25V6K
Output Cap PAD
37,41,44,48 SUSP#
PR502
2.2_0603_5%
1
BST_1.35V 2
120%
+0.75VSP
UG_1.35V
3
2
1
PJ503
+1.5VP
115%
1.35V_B+
2012/9/6
OVP=110%
+1.35VP
Ipeak = max{ 0.7*Ibudget, 1st +2nd max loading}
Ipeak = max{ 12.34*0.7 ,
4.2+8.14
}
Ipeak=12.34A ; 1.2Ipeak=14.808A ;Imax=8.638A
1/2Delta I=0.7353A (F=300K Hz)
PR504=(1.2Ipeak-1/2Delta I) *Rds(on)(max)*1.2/9uA=8.45Kohm
choose PR504=8.45Kohm (for safety >1.2Ipeak)
Rds(on)=5.0m ohm(max) ; Rds(on)=4.2m ohm(typical)
Ilimit_min=(8.366K*9uA)/(5.0m*1.2)=15.058A
Ilimit_max=(8.535K*11uA)/(4.2m*1.2)=22.352A
Iocp=Ilimit+1/2Delta I=15.79A~23.09A
Iocp(min)>1.2Ipeak
JUMP_43X39
STATE
4
S3
S5
S0
Hi
Hi
On
On
S3
Lo
Hi
On
On
Lo
Lo
S4/S5
1.35VP
VTT_REFP
0.675VSP
On
Off
(Hi-Z)
Off
Off
Off
(Discharge) (Discharge) (Discharge)
Issued Date
2013/02/04
EOP
Deciphered Date
Note: S3 - sleep ; S5 - power off

A
Compal Secret Data
Title
1.5VP/0.75VSP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
46
of
55
VFB= 0.704V
Vo=VFB*(1+11.5K/10K)= 1.5V
Freq=290KHz(typ)
VGA@EMI@ PL504
HCB2012KF-121T50_0805
VGA@
VFB
V5IN
TST
DRVL
TP
3
2
1
+5VALW
DL_1.5VSG
11
TPS51212DSCR_SON10_3X3
VGA@ PC515
1U_0603_10V6K
Frequency(KHz)
290
340
380
430
VGA@ PR515
11.5K_0402_1%
FB=0.704V
JUMP_43X118
+1.5VSDGPU
@ PJ510
3
2
1
VID [0]
0
0
1
1
@ PJ509
+1.5VSDGPUP
1
2
PC519
0.1U_0402_25V6
PC518
10U_0805_25V6K
VGA@ PC523
330U_2.5V_M
2
@EMI@ PC522
680P_0402_50V7K
VGA@ PR516
10K_0402_1%
+1.5VSDGPUP
@EMI@ PR518
4.7_1206_5%
VGA@
Rds=13.5m(Typ)
16.5m(Max)
470
200
100
39
Resistance(K)
VGA@ PL502
4.7UH_PCMB063T-4R7MS_5.5A_20%
VGA@ PR514
470K_0402_1%
SW_1.5VSG
@EMI@
SW
DH_1.5VSG
VGA@ PC514
0.1U_0603_25V7K
FB_1.5VSG
RF_1.5VSG
EN
B+
DRVH
BST_1.5VSG
PQ505
SI7716ADN-T1-GE3_POWERPAK8-5
VGA@ PR512
56.2K_0402_1% EN_+1.5VSG
TRIP
10
VGA@EMI@ VGA@
VBST
PC1009
0.1U_0402_16V7K
VGA@
TRIP_1.5VSG
1.5VS_DGPU_PWR_EN
PGOOD
PR1003
VGA@
30K_0402_1%
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.85V
0.775V
0.75V
JUMP_43X118
JUMP_43X118
+1.05VS_VTT_VIN
+5VALW
SA_PGOOD
1
0_0402_5%
@ PR746
VIN
Vo
VPP
Vo
POK
D1
VEN/MODE
D0
+VCCSAP
4
3
@ PR743
0_0402_5%
H_VCCSA_VID1
H_VCCSA_VID1
H_VCCSA_VID0
H_VCCSA_VID0
0_0402_5%
@ PR744
G978F11U_SO8
PC742
1U_0603_6.3V6M
2
1
VCCPPWRGOOD
PC741
1U_0402_6.3V6K
2
1
48
GND
+VCCSAP
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
B
+VCCSA
PJ702
JUMP_43X118
Imax= 4.2A, Ipeak= 6A

FB=0.6V
0.9V
PC740
22U_0805_6.3V6M
2
1
PU702
PC737
22U_0805_6.3V6M
2
1
+1.05VS_VTT
PJ701
output voltage adjustable network
PC738
22U_0805_6.3V6M
2
1
PC743
22U_0805_6.3V6M
2
1
1
2
37
PR745
100K_0402_1%
+3VS
PC739
22U_0805_6.3V6M
2
1
PC744
22U_0805_6.3V6M
2
1
22
VGA@ PR517
2.2_0603_1%
VGA@ PU502
HW sequence (0311)
PC517
10U_0805_25V6K
Cesr= 15m ohm

Ipeak= 4.7A Imax= 3.29A Iocp=5.64A
Iocp= 5.72A~6.43A
PC516
2200P_0402_50V7K
1.5VSG_B+
PQ504
Title
+VCCSAP/+1.5VSDGPUP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
47
of
55
+1.05VSP Ipeak=5.36A ; Imax=3.752A ; 1.2Ipeak=6.432

Delta I=0.xxxxA=>1/2Delta I=0.xxxxA,F= 800K Hz(typ)
EMI@
PL601
HCB2012KF-121T50_0805
1
2
UG_+1.05VS_VTTP
SW_+1.05VS_VTTP
DRVL
TP
LG_+1.05VS_VTTP
11
TPS51212DSCR_SON10_3X3
PC606
1U_0603_6.3V6M
3
2
1
@ PC611
1000P_0402_50V7K
1
2
@ PR607
1.2K_0402_1%
1
2
+1.05VS_VTTP
PQ602
PR606
470K_0402_1%
+5VALW
1
2
PC609
@EMI@
680P_0402_50V7K
PR608
4.99K_0402_1%
1
2
+1.05VS_VTTP
<BOM Structure>
PR605
@EMI@
4.7_1206_5%
TST
7*7*3
PC610
0.1U_0402_16V7K
V5IN
VFB
SH00000KS00
PL602
1UH_VMPI0703AR-1R0M-Z01_11A_20%
1
2
SW
DRVH
EN
5
RF_+1.05VS_VTTP
HW sequence 0222
PC601
0.1U_0402_16V7K
4
FB_+1.05VS_VTTP
TRIP
EN_+1.05VS_VTTP3
PC605
0.1U_0603_25V7K
1
2
PC608
330U_2.5V_M
PR604
2.2_0603_5%
1
2
BST_+1.05VS_VTTP
2
TRIP_+1.05VS_VTTP
VBST
MDU1512RH_POWERDFN56-8-5
PR601
200K_0402_1%
1
2
SUSP#
PGOOD
37,41,44,46
3
2
1
10
PU601
PR603
105K_0402_1%
1
2
B+
PQ601
@ PR611
0_0402_5%
1
2
VCCPPWRGOOD
@EMI@
PC604
10U_0805_25V6K
PR602
100K_0402_1%
47
PC603
2200P_0402_50V7K
+3VS
PC602
0.1U_0402_25V6
+1.05VS_VTTP_B+
1
+
ESR=17m ohm
2
2
PR609
100_0402_5%
1
2
VCCIO_SENSE
The RC value (PC611 and PR607) need fine-tune if need
PR610
10K_0402_1%
@ PJ601
2
2
+1.05VS_VTTP
+1.05VS_VTT
JUMP_43X118
@ PJ602
1
2
1
2
JUMP_43X118
+3VS
@ PC5002
1U_0402_6.3V6K
+1.8VSP
1
<BOM Structure>
PR5003
15.8K_0402_1%
PJ603
2
+1.8VS
JUMP_43X118
<BOM Structure>
<BOM Structure>
@ PR5001
22K_0402_5%
+1.8VS_ON
+1.8VSP
PC5005
22U_0805_6.3V6M
1
2
@
PC5004
22U_0805_6.3V6M
FB_1.8VS
PC5003
0.022U_0402_16V7K
<BOM Structure>
<BOM Structure>
PC5001
0.1U_0402_16V7K
FB=0.8V
PR5000
200K_0402_1%
1
2
SUSP#
<BOM Structure>
PR5002
20K_0402_1%
GND
1
2
PC5000
4.7U_0603_6.3V6K
Note:Iload(max)=3A
PU5000
APL5930KAI-TRG_SO8
6
5 VCNTL
3
VOUT 4
9 VIN
VIN
VOUT
8
7 EN
2
POK
FB
<BOM Structure>
<BOM Structure>
Issued Date
Compal Secret Data
Ien=10uA, Vth=0.3V, notice

the res. and pull high
voltage from HW
2013/02/04
EOP
Deciphered Date
Title
+1.05VS_VTTP/+1.8VSP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
48
of
55
2
VCC_AXG_SENSE
VSS_AXG_SENSE
VSSSENSE
1
2
PC709
10U_0805_25V6K
PC708
10U_0805_25V6K
1
2
PC707
2200P_0402_50V7K
1 VSUMG-_1
1 VSUMG+_1
B+
VSUMG+
VSUMG-
+
2
PC719
33U_25V_M
1
PC718
33U_25V_M
PC722
0.1U_0402_25V6
PC721
10U_0805_25V6K
PC720
10U_0805_25V6K
1
2
+
2
Height 8 mm
1 VSUM-_1
1 VSUM+_1
1_0402_5%
PR736
3.65K_0402_1%
PR735
@EMI@
VSUM+
Close CPU choke
10K_0402_1%_ERTJ0EG103FA
VSUM-
PC735
0.1U_0402_16V7K
VSUM-
PL701
Issued Date
<BOM Structure>
2013/02/04
PL702 FootprintSH00000HQ00,SH00000NM00_R222PIN
2012/07/05
Compal Secret Data

EOP
Deciphered Date
Title
CPU_CORE/VGFX_CORE
Size
Document Number
Custom
Rev
1.0
Date:
B
3
2
1
3
2
1
PR734
2.61K_0402_1%
CM@
@EMI@
+CPU_CORE
11K_0402_1%
1
2
PH704
PR740
1
2
PC731
0.1U_0603_25V7K
1
2
PC730
0.047U_0402_25V7K
1
2
PR739
422_0402_1%
1
1
PC736
0.01UF_0402_25V7K
PQ704
VSUM_NTC
1
PR742
137K_0402_1%
PC732
150P_0402_50V8J
2
1
2
PC729
68P_0402_50V8J
1
2
PC727
PR731
680P_0402_50V7K 4.7_1206_5%
1
4
VSUM+
LGATE1
PC725
2
0.1U_0603_25V7K
4
PR733
42.2K_0402_1%
1
2
2 1
PHASE1
2.2_0603_5%
PR730
BOOT1 1
OCP setting=39.9~44.99A
PL704
0.22UH_FDUE0640J-H-R22M-P3_25A_20%
PQ703
PQ705
PR727
0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A
+3VS
3
2
1
UGATE1
A
5
@ PR728
0_0603_5%
1
2UGATE1-1 4
15,37
2
8
1
2
PC717
1U_0603_10V6K
PHASE1
1.91K_0402_1%
@ PC734
330P_0402_50V7K
1
2
VCCSENSE
1
LGATE1
18
1 2
1
PR718
0_0603_5%
1
2
PC716
1U_0603_10V6K
19
PR741
1.91K_0402_1%
1
2
EMI@ PL703
HCB2012KF-121T50_0805
1
2
UGATE1
PR738
649 +-1% 0402
PC728
470P_0402_50V7K
1
2
1
2
PR737
499_0402_1%
3
2
1
25
UGATEG
BOOT1
1.91K_0402_1%
1
2
16
PGOOD
20
VGATE
PC733
6800P_0402_25V7K
PR732
2K_0402_1%
1
2
@EMI@ PC715
680P_0402_50V7K
EMI@ PL702
HCB2012KF-121T50_0805
1
2
17
UGATE1
1_0402_5%
PR715
Close CPU L/S MOS
PC726
470P_0402_50V7K
1
2
3
2
1
1
2
PR711
27
28
29
30
31
26
BOOTG
PGOODG
COMPG
FBG
RTNG
32
ISUMPG
PHASE1
ISEN2
+5VS
NTC
transient request 0218
+CPU_B+
@ PR721
LGATE1
15
PR722
0_0402_5%
VR_HOT#
PR719
1_0603_5%
3.65K_0402_1%
PR714
MDU1511 Vds=30V
Rds(on)=2.7~3.3m ohm@Vgs=4.5V
21
PWM2
COMP
PQ702
22
VDD
SDA
PR724
61.9K_0402_1%
1
2
PH703
470K +-5% ERTJ0EV474J 0402
1
2
PR716 and PR724

27.4K ohm for 100 degree
61.9K ohm for 110 degree
@ PC724
0.1U_0402_16V7K
23
@EMI@ PR713
4.7_1206_5%
4
PL701
0.36UH_FDUM0640J-H-R36M-P3_22A_20%
3
BOOT1
+1.05VS_VTT
3
PR729
3.83K_0402_1%
NTC_1
PR723
54.9_0402_1%
1
2
PR726
130_0402_1%
PR725
499_0402_1%
@ PC723
47P_0402_50V8J
_HOT#, already
igh at power side.
ALERT#
14
24
VCCP
ISL95833HRTZ-T_TQFN32_4X4
FB
6
NTC
SCLK
13
ISUMNG
PAD
VR_SVID_DAT
LGATEG
RTN
H_PROCHOT#
+VGFX_CORE
1
+5VS
LGATEG
PHASEG
12
37,5
VR_SVID_ALRT#
0.22uH DCR= 0.97+-5% m ohm, Idc~Isat= 25~34A
PC714
0.1U_0603_25V7K
1
2 1
2
BOOTG
PR712
2.2_0603_5%
4
LGATEG
BOOTG
VR_ON
ISUMN
VR_SVID_DAT
VR_SVID_CLK
@EMI@
4
PQ701
UGATEG1
NTCG
11
VR_SVID_ALRT#
8
ISUMP
0_0402_5%
VR_SVID_CLK
NTCG
ISEN1
VR_ON
10
37
33
PU701
@ PR706
0_0603_5%
2 UGATEG1-1
PC710
330P_0402_50V7K
PHASEG
PR716
61.9K_0402_1%
1
2
UGATEG1
PHASEG
1.91K_0402_1%
1
2
PC713
0.047U_0402_25V7K
PC712
0.1U_0603_25V7K
1
2
1 2
PR709
11K_0402_1%
1
2
PR710
2.61K_0402_1%
0.1U_0402_16V7K
PC711
+3VS
Close GFX L/S MOS
PH702
PR717
470K +-5% ERTJ0EV474J 0402
3.83K_0402_1%
1
2
1
2
NTCG_1
@ PR720
1
2
MDV1525 Vds=30V
Rds(on)=11.5~14m ohm@Vgs=4.5V
1 2
PR707
1
576 +-1% 0402
VSUMG+
GFX_OCP 0314
VSUMG_NTC
PC704
470P_0402_50V7K
1
2
1
2
PR701
PC706
499_0402_1%
150P_0402_50V8J
1
2 1
2
1
2
PR702
PR703
137K_0402_1%
2.55K_0402_1%
PR705
2K_0402_1%
+CPU_B+
PC703
68P_0402_50V8J
1
2
PR708
33.2K_0402_1%
PR704
649 +-1% 0402
PH701
10K_0402_1%_ERTJ0EG103FA
VSUMG-
OCP setting=39.9~44.99A
VDD source use +5VS and PGOOD source use +3VS

Please confirm power on and down sequence,
make sure VGATE after CPU_CORE on.
PC705
6800P_0402_25V7K
1
Layout Note
Reduce Acoustic Noise
1. The AL bulk capacitor of B+ should be very
close to CPU_CORE MOSFET.
2. Input ceramic caps must place on symmetry
same location on top side and bottom side.
PC702
0.01UF_0402_25V7K
Close GFX choke
@ PC701
1000P_0402_50V7K
Layout Note
SVID routing
1. Alert# signal must be routed between
the Clock and Date lines to reduce the cross
talk between them. Signal order arrangement:
mobile order is Clock-Alert-Date.
2. SVID spacing requirement is 18mils(0.475mm).
3. Maximum total microstrip routing length of
each SVID signal must not exceed 6000mils(152.4mm).
4. The SVID bus must be ground reference, It cannot be
referenced to input (Vbat or 12V) power plans as they can
couple noise into the SVID bus as power states change.
5. Avoid routing under noisy circuit, e.g. switch node ,
Gate driver, B+, Vin, high speed signal.
6. When SVID signal changes Layer, GND return path
may be changed also. We need add GND via for GND
reference.
Sheet
E
49
of
55
VGA@EMI@ PL801
HCB2012KF-121T50_0805
+VGA_B+
VGA@EMI@ PL803
HCB2012KF-121T50_0805
3
2
1
22
VGA@ PR802
0_0603_5%
BOOT1_VGA
VGA@ PC805
0.22U_0603_10V7K
BOOT1_2_VGA
LGATE1_VGA
1
2
1
2
PC803
0.1U_0402_25V6
PC804
2200P_0402_50V7K
+VGA_CORE
2
1
+5VS
20
+VGA_B+
UGATE2_2_VGA
VGA_PWROK
18,37
VGA@ PR820
0_0603_5%
+3VSDGPU
VGA@ PC818
0.22U_0603_10V7K
2
BOOT2_2_VGA 1
1
2
VGA@
VGA@ PL804
0.22UH_FDUE0640J-H-R2_25A_20%
+5VS
VGA@ PR824
10K_0402_1%
LGATE2_VGA
VGA@
+3VS
3
2
1
@EMI@ PR823
4.7_1206_5%
Rds=2.7m(Typ)
3.3m(Max)
PHASE2_VGA
+VGA_CORE
7x7x4
3
1SNUB2_VGA 2
VGA@ PC819
1U_0402_6.3V6K
DCR: 0.97m5%
1
VGA@ PR822
2.2_0402_5%
VGA@
PC816
10U_0805_25V6K
5
VGA@ PR818
0_0603_5%
PC815
10U_0805_25V6K
19
PQ803
MDU1516URH_POWERDFN56-8-5
1
PR821
3.92K_0402_1%
@ PR814
0_0402_5%
VGA@
@EMI@ PC807
680P_0402_50V7K
BST1
HG1
EN_VGA
4
VCC_VGA
Thermistor near MOSFET

trigger point 110 degree C.
PVCC_VGA
BOOT2_VGA
VGA@
21
UGATE2_VGA
VGA@
7x7x4
VGA@ PC810
4.7U_0603_6.3V6K
22
VGA@ PU801
NCP81172MNTXG_QFN24_4X4
VGA@ PR819
10K_0402_1%
VREF
1
2
PH801
100K_0402_1%_TSM0B104F4251RZ
2
1
N14P-GV2 OpenVR config is B

Vmin=0.6V
Vmax=1.2V
Vboot=0.9V
Vstep=6.25mV
Number of Voltage Levels N=96
PWM Frequency FPWM=1.125MHz
PWM Minimum Pulse Width TDmin=9.26ns
VID Transient Time T < 100uS
VGA@ PC817
0.1U_0402_16V7K
PH2
23
3
2
1
VGA@ PR817
82K_0402_1%
+VGA_CORE
PSI
VID
LG2
VGA@ PR827
10_0402_1%
24
VGA@ PC814
100P_0402_50V8J
FB
COMP
3
2
1
1
2
COMP_VGA
VGA@ PC813
10P_0402_50V8J
2 FB2_VGA 1
2
PVCC
GND
VGA@ PR816
10K_0402_1%
12
PGND
FBRTN
25
Rds=2.7m(Typ)
3.3m(Max)
BST2
11
FS
HG2
FB_VGA
VGA@ PC812
VGA@ PR815
47P_0402_50V8J
51_0402_1%
1
2 FB1_VGA1
2
10
18
LG1
17
FS
PH1
VREF
16
VGA@ PR813
33.2K_0402_1%
VSSSENSE_VGA
VCCSENSE_VGA
VGA@EMI@
REFIN
VCC
TALERT#
VREF
15
REFIN
VGA@ PC808
0.01U_0603_50V7K
14
@ PR807
100K_0402_1%
TSNS
1
GV2@ PC809
2700P_0402_50V7K
VIDBUF
13
GV2@ PR810
2K_0402_1%
GV2@ PR812
18K_0402_1%
VGA@ PR826
10_0402_1%
GPU_VID
EN
GE@ PR812
27K_0402_1%
PGOOD
VREF
GE@ PC809
1800P_0402_50V7K
GV2@ PR809
20K_0402_1%
2
1 VIDBUF
VGA@
B+
@EMI@ PR804
4.7_1206_5%
1 SNUB1_VGA 2
PHASE1_VGA
VGA@
PQ802
5
GE@ PR809
39K_0402_1%
2
PR806
10K_0402_1%
GE@ PR808
30K_0402_1%
GV2@ PR808
20K_0402_1%
24
EN_VGA
GE@ PR810
3K_0402_1%
VGA@ PC811
1000P_0402_50V7K
@EMI@
VGA@ PL802
0.22UH_FDUE0640J-H-R2_25A_20%
PQ804
follow EZEL setting 0218
24
VGA@
DCR: 0.97m5%
PR805
0_0402_5%
2
1
VGA_ON
PC802
10U_0805_25V6K
VGA@
PR803
VGA@
39K_0402_1%
22,37,41
PC801
10U_0805_25V6K
UGATE1_2_VGA
22
VGA@
PSI
DGPU_VID
+3VS
PC806
0.1U_0402_16V7K
VGA@
5
VGA@ PR801
0_0603_5%
UGATE1_VGA
PQ801
MDU1516URH_POWERDFN56-8-5
2
1
@EMI@ PC820
680P_0402_50V7K
N14P-GE OpenVR config is C

Vmin=0.65V
Vmax=1.15V
Vboot=0.9V
Vstep=25mV
Number of Voltage Levels N=20
PWM Frequency FPWM=0.676MHz
PWM Minimum Pulse Width TDmin=74ns
VID Transient Time T < 100uS
4
N14P-GV2 TDP 25W

Ipeak=55A
Imax=25A
Iocp=72A
Fsw=450KHz
bulk cap 560uF*2
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
Title
+VGA_CORE
Size
Document Number
Custom
Date:

Sheet
50
Rev
1.0
of
55
PC948
22U_0805_6.3V6M
PC947
22U_0805_6.3V6M
PC946
22U_0805_6.3V6M
PC945
22U_0805_6.3V6M
PC944
22U_0805_6.3V6M
PC943
22U_0805_6.3V6M
PC964
1U_0402_6.3V6K
2
1
PC965
1U_0402_6.3V6K
2
1
PC966
1U_0402_6.3V6K
2
1
PC967
1U_0402_6.3V6K
2
1
PC968
1U_0402_6.3V6K
PC980
1U_0402_6.3V6K
2
1
PC981
1U_0402_6.3V6K
2
1
PC982
1U_0402_6.3V6K
2
1
PC983
1U_0402_6.3V6K
2
1
PC984
1U_0402_6.3V6K
+
2
1
2
1
PC995
330U_D2_2V_Y
PC994
10U_0603_6.3V6M
1
2
1
2
PC993
10U_0603_6.3V6M
1
2
1
2
PC963
1U_0402_6.3V6K
2
1
PC979
1U_0402_6.3V6K
2
1
2
1
PC992
10U_0603_6.3V6M
1
2
1
2
1
2
1
2
1
2
1
2
For TOP side
1
+
ESR=9m ohm
1
PC969
330U_D2_2V_Y
ESR=9m ohm
1
PC970
330U_D2_2V_Y
PC971
330U_D2_2V_Y
PC989
10U_0603_6.3V6M
PC962
1U_0402_6.3V6K
2
1
PC978
1U_0402_6.3V6K
2
1
PC991
10U_0603_6.3V6M
PC988
10U_0603_6.3V6M
PC961
1U_0402_6.3V6K
2
1
PC977
1U_0402_6.3V6K
2
1
PC987
10U_0603_6.3V6M
PC960
1U_0402_6.3V6K
2
1
PC976
1U_0402_6.3V6K
2
1
PC986
10U_0603_6.3V6M
PC959
1U_0402_6.3V6K
2
1
PC975
1U_0402_6.3V6K
2
1
PC985
10U_0603_6.3V6M
PC958
1U_0402_6.3V6K
2
1
PC974
1U_0402_6.3V6K
2
1
PC957
1U_0402_6.3V6K
2
1
PC973
1U_0402_6.3V6K
2
1
+CPU_CORE
PC956
1U_0402_6.3V6K
2
1
PC990
10U_0603_6.3V6M
2
1
+1.05VS_VTT
PC972
1U_0402_6.3V6K
2
1
PC955
22U_0805_6.3V6M
PC954
22U_0805_6.3V6M
PC953
22U_0805_6.3V6M
PC952
22U_0805_6.3V6M
PC951
22U_0805_6.3V6M
PC950
22U_0805_6.3V6M
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
PC933
10U_0603_6.3V6M
PC932
10U_0603_6.3V6M
1
2
1
2
PC931
10U_0603_6.3V6M
PC930
10U_0603_6.3V6M
1
2
PC929
10U_0603_6.3V6M
PC919
1U_0402_6.3V6K
1
2
PC918
1U_0402_6.3V6K
1
2
PC917
1U_0402_6.3V6K
PC916
1U_0402_6.3V6K
PC915
1U_0402_6.3V6K
PC914
1U_0402_6.3V6K
PC913
1U_0402_6.3V6K
2
1
PC912
1U_0402_6.3V6K
2
1
PC911
1U_0402_6.3V6K
2
1
PC910
1U_0402_6.3V6K
2
1
2
2
PC928
10U_0603_6.3V6M
PC942
330U_D2_2V_Y
PC941
330U_D2_2V_Y
PC949
22U_0805_6.3V6M
PC927
2.2U_0402_6.3V6M
2@
+-20% SGA00006100
PC909
2.2U_0402_6.3V6M
For BOT side
PC940
22U_0805_6.3V6M
Can connect to GND if motherboard only

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
PC926
2.2U_0402_6.3V6M
PC939
22U_0805_6.3V6M
Vaxg
PC925
2.2U_0402_6.3V6M
PC938
22U_0805_6.3V6M
PC924
2.2U_0402_6.3V6M
PC937
22U_0805_6.3V6M
PC923
2.2U_0402_6.3V6M
PC936
22U_0805_6.3V6M
PC935
22U_0805_6.3V6M
ESR=9m ohm
2
PC934
22U_0805_6.3V6M
+CPU_CORE
PC922
2.2U_0402_6.3V6M
PC921
2.2U_0402_6.3V6M
PC920
2.2U_0402_6.3V6M
PC908
2.2U_0402_6.3V6M
PC907
2.2U_0402_6.3V6M
PC906
2.2U_0402_6.3V6M
PC905
2.2U_0402_6.3V6M
PC904
2.2U_0402_6.3V6M
PC903
2.2U_0402_6.3V6M
+CPU_CORE
PC902
2.2U_0402_6.3V6M
+VGFX_CORE
PC901
1U_0402_6.3V6K
2
1
PWR Rule 17W@ULV(CR BGA1023_GT2) CPU2.9m

GFx3.9m
CPU 330uF/9m *3, 22uF(0805) *12, 2.2uF(0402)*16
GFX 330uF/9m*2, 22uF(0805)*6, 10uF(0603)*6, 1uF(0402)*11
1.05V 330uF*2,10uF(0603)*10,1uF(0402)*26
ESR=9m ohm
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
Title
CPU_CORE_CAP
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Custom
Rev
1.0
Date:
Sheet
E
51
of
55
VGA@ PC1008
4.7U_0603_6.3V6K
1
2
VGA@ PC1007
4.7U_0603_6.3V6K
1
2
VGA@ PC1006
4.7U_0603_6.3V6K
1
2
VGA@ PC1005
4.7U_0603_6.3V6K
1
2
VGA@ PC1004
4.7U_0603_6.3V6K
nVidia GB4-128 package

Under GPU
4.7uF 0603 * 10
0.1uF 0402 * 4
VGA@ PC1014
0.1U_0402_25V6
1
2
1
2
VGA@ PC1003
4.7U_0603_6.3V6K
2
1
2
VGA@ PC1013
0.1U_0402_25V6
VGA@ PC1002
4.7U_0603_6.3V6K
2
1
2
VGA@ PC1011
0.1U_0402_25V6
VGA@ PC1012
0.1U_0402_25V6
VGA@ PC1001
4.7U_0603_6.3V6K
+VGA_CORE
nVidia GB4-128 package

Near GPU
47uF 0805 *1
22uF 0805 *1
4.7uF 0805 *5 (0603)
330uF POS *1 <6m
+
2
1
+
VGA@ PC1021
4.7U_0603_6.3V6K
1
2
VGA@ PC1020
4.7U_0603_6.3V6K
1
2
VGA@ PC1019
4.7U_0603_6.3V6K
1
1
PC1027
330U_D2_2.5VY_R9M
VGA@ PC1018
4.7U_0603_6.3V6K
VGA@ PC1026
560U_2.5V_M
1
2
@ PC1024
4.7U_0603_6.3V6K
1
2
@ PC1023
4.7U_0603_6.3V6K
1
2
@ PC1022
4.7U_0603_6.3V6K
VGA@ PC1025
560U_2.5V_M
1
2
VGA@ PC1017
4.7U_0603_6.3V6K
1
2
VGA@ PC1016
22U_0805_6.3V6M
1
2
VGA@ PC1015
47U_0805_6.3V6M
+VGA_CORE
2@
Issued Date
Compal Secret Data
2013/02/04
Deciphered Date
EOP
Title
A
VGA_CORE CAP
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
E
52
of
55
RP8
R115
2.2K
4.7K
RP8
H14
PCH_SMBCLK
C9
PCH_SMBDATA
+3VALW_PCH
2.2K
R116
4.7K
Q5
2N7002
+3VS
D_CK_SCLK
200
D_CK_SDATA
202
DIMM1, 2
2N7002
PCH
VGA
0 @ MINI1_SMBCLK 30
0 @ MIN1I_SMBDATA 32
R432
R434
WLAN
N14M-GE
N14P-GV2
RP8
RP8
HM77
E14
PCH_SML1CLK
M16
PCH_SML1DATA
2.2K
2.2K
+3VALW_PCH
RP34
EC_SMB_DA2
2.2K
I2CS_SCL
T4
I2CS_SDA
T3
DMN66D0LDW
2.2K
2.2K
+3VSDGPU
DMN66D0LDW
EC_SMB_DA2
RP34
80
RP1001
EC_SMB_CK2
2N7002
EC_SMB_CK2
2.2K
Q1004
Q1006
2N7002
79
RP1001
+3VS
SCL2
SDA2
RP34
3
KBC
RP34
77
EC_SMB_CK1
78
EC_SMB_DA1
SCL1
2.2K
3
+3VALW_EC
2.2K
PR202
PR201
SDA1
100 ohm
100 ohm
4
3
BATTERY
CONN
KB9012
9
Charger IC
Issued Date
Compal Secret Data
2013/02/04
EOP
Deciphered Date
A
Title
SMBUS Block diagram

Custom
Date:

Sheet
53
Rev
1.0
of
55
Version change list (P.I.R. List)

Item
Page 1 of 1
for PWR
Reason for change
PG#
Modify List
Date
Phase
For 4S battery request
44
mount PR319,PR321,PR326,PQ307,PQ308
0310
change size to common part
45
PC419 change to 0603 common part
0310
HW sequence request
47
PR1003 to 30k
0311
EMI request
44
not mount PC307
0312
EMI request
44
add PC745 PC746 PC747
0313
EMI request
44
change PR311 PR310 to 2.2Ohm
0313
GFX_OCP
49
change PR707 to 576hm
0314
8
C
9
10
11
12
13
3/5
EVT
14
3/5
EVT
15
B
16
17
18
19
20
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
5
Title
PW PIR
Size
A3
Date:
Document Number
Rev
1.0

Sheet
1
54
of
55
-----------------------------------------------------------------------------------------0318
L24,L25 change from SM070001600 (12ohm USB3.0 common mode choke)
to SM070001R00 (Murata 67ohm )
-------------------------------------------------------------------------------------03/06
Change R1033 from 4.99K to 10K(ROM_SO VGA_DEVICE)
Change U51 N14P-GV2 from SA00006B500 to SA00006B510
Change Y6 P/N to SJ10000E800()
-------------------------------------------------------------------------------------0419
Add Touch screen feature and JTS1
----------------------------------------------------------------------------------------0422
Remove PEG 16X
-----------------------------------------------------------------------------------------------0425
Add HM70 NM70
Add FFR VRAM strap for N14M-GE N14P-GV2
-------------------------------------------------------------------------------0502
Update CPU,PCH,VRAM P/N
-----------------------------------------------------------------------------0505
Pop RP16 for LAN loopback
------------------------------------------------------------------------------0528
N14M-GE ROM_SO keep 10K pull low.
N14P-GV2 need change be to EVT R1033 as 4.99K_0402_1%
--------------------------------------------------------------------------------------03/11
Add net +XDPWR_SDPWR_MSPWR_R
Add share rom feature
Add R112 R140 R141 R144
Add EC_SPI_MISO_1 , PCH_SPI_MISO_1
Add EC_SPI_CS0# , PCH_SPI_CS0#
Add EC_SPI_CLK_1 , PCH_SPI_CLK_1
Add EC_SPI_MOSI_1 , PCH_SPI_MOSI_1
R541 pop 1K VGA@
R1101 470-->47 SD013470A80
D1000.3 VGA_PWROK changes into VGA_ON
SW3 @
Removed U15,R107,R108
Removed R151,R159,R160,R184,R97
Removed R524,R525,R526 RP13 5%--->1%
--------------------------------------------------------------------------------------03/12
Add C441 470pF(SE074471K80),EMC@, EMI solution
Change U51 N14P-GV2 SA00006B510-->SA00006B530 R3 P/N
Change U51 N14M-GE SA000068A00-->SA000068A10 R3 P/N
C142-->15pF(SE071150J80) to meet off mode timing

----------------------------------------------------------------------------0604
Correct page1 date code
Update page24 3D device/vga device notice
--------------------------------------------------------------------------------------0313a
Combine with PWR_Z5WE1_LA9535PR02_PWR_0313.DSN
0313b
Remove RP14,
PCH_GPIO2
PCH_GPIO3
PCH_GPIO53
RP13 5%--->1%(SD300002Y00)
0313C
2nd rom
Add U15,R107,R108
Add R97 R151 R159 R160 R184
Del R112 R140 R141 R144
----------------------------------------------------------------------------0314
R285 XEMC@-->EMC@
C329 22P-->10P, XEMC@-->EMC@
Add C230 0.1U for card reader enable

Board ID
R316 0ohm 8.2K
R314 @-->
C346 @-->
---------------------------------------0314C
R774 change from 10 to 56ohm
R1027,R1028,R1029,R1030,R1035,R1036,R1039,R1033,R1042
at N14M-GE SKU 10K_0402_5% change to 10K_0402_1%
A
0314d
L33 changes into SM010014520
------------------------------------------------------------------------------0315a
Add net CRT_4, CRT_11 for
R541 bom structure--->VGA@
C346 board ID cap@
5
Compal Secret Data

2013/02/04
Issued Date
Deciphered Date
EOP
4
Title
HW PIR
Size
Document Number
Custom
Rev
1.0
Date:
Sheet
1
55
of
55
www.s-manuals.com

Compal La-9535p r1.0 Schematics

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Compal La-9535p r1.0 Schematics

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EA/EG50_CX (Z5WE1) M/B Schematics Document

Compal Electronics, Inc.

Compal Secret Data

LA-9535P M/B Schematics

Friday, June 07, 2013

Nvidia N14P series

USB/B (port 1,2)

USB port 8 page 34

1.5V DDR3 1333/1600

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

Compal Electronics, Inc.

Compal Secret Data

LA-9535P M/B Schematics

Friday, June 07, 2013

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail for power circuit.

Core voltage for CPU

Core voltage for GPU

+0.675VSP to +0.675VS switched power rail for DDR terminator

+1.0VSDGPU switched power rail for GPU

+0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU

+1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU

+3VS to 1.8V switched power rail to CPU

+1.8VS to +1.8VSDGPU switched power rail for GPU

+3VALW always on power rail

B+ to +3VLP power rail for suspend power

+5VALWP to +5VALW power rail

+5VALW to +5VS switched power rail

+VSBP to +VSB always on power rail for sequence control

BTO Option Table

PCH SM Bus address

USB 3.0 Port

Mini Card (WLAN+BT)

UMA ONLY GPIO

Compal Electronics, Inc.

Compal Secret Data

LA-9535P M/B Schematics

USB Port(Left 3.0)

USB Port Table

VGA Internal Thermal Senser 1001 111x (0x9E)

Board ID / SKU ID Table for AD channel

+1.5V to +1.5VS switched power rail

+3VALW to +3VS power rail

+1.35VP to +1.35V power rail for DDRIIIL

+3VS to +3VSDGPU switched power rail for GPU

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Friday, June 07, 2013

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