2011 University/College IC Design Contest Full

Custom Category for Undergraduates

Voltage Booster

charge pump (voltage booster 1

)Charge pump clock
ILOAD

charge pump

1.
2.
3.
4.
5.
6.

test bench

page
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5
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1.
non-overlap clock
charge pump charge pump
charge pump non-overlap clock
non-overlap clock charge pump 2

charge pump nonoverlap clock

voltage booster

port
VDD
Gnd
Vout
CK

non-overlap clock charge pump

Ground

Clock , 10MHz

1.1. Charge pump

Charge pump


Vin
Charge pump

Vout
ph1, ph1a, ph2, ph2a
4
3 charge pump
3 Recape and Daga charge pump
p-channel MOSFET body effect
3 clock Vin
VoutM5M1 Cpump1 Vin Cpump2
Vout M4M2 Cpump2 Cpump1 Vout
charge pump clock ph1ph1aph2ph2a
MOSFET switchcharge pump
Cpump Caux charge pump
port

1.2. Non-overlap clock

4 5 6 non-overlap clock

Non-overlap clock

4 non-overlap clock clock nonoverlap clock 1 2 low 1 2 high

inverter 1 2 3 4 high
low 3 4 Delay processing
3 4
1.2.1. non-overlap clock

Non-overlap clock

5 non-overlap clock inverter

delay inverter 5
clock out1(b) clock out2(b) low 4 3 4

1.2.2. Delay processing

Delay processing

6 inverter n/p-channel Cdelay

clock high-low-high
3
3 clock ph1( ph2) ph1a( ph2a) low
ph1a( ph2a) high 6 P/N
clock in low Cdelay2 Cdelay1
VDD clock in high Cdelay2 Cdelay1
6

2.

1.

Charge pump
4

2.

voltage booster

charge pump charge

pump non-overlap clock

()

2.1.
Unit Min. Typica Max.
s
l
Power supply
V
1.6
1.8
2.0
Temperature range
0
27
85
1.6/1.8/2.0 0/27/85 corner
TT/SS/FF/SF/FS 45 all PVT
cptbcptbapvtvdtbvttbapvt

2.2.

Symbol
Eff

Vomin
Size

Descriptions
conditions
All PVT

conditions
clock

250ns

70%

>2.6V
<26000
um^2

3.
charge pump

cp.gds
Charge pump layout file
I
cp.src.net
Charge pump netlist
II
cp.drc
DRC report file calibre
cp.lvs
LVS report file calibre

III
voltage booster(non-overlap clock + charge pump)

vb.gds
Voltage booster layout file
I
vb.src.net
Voltage booster netlist
II
vb.drc
DRC report file calibre
vb.lvs
LVS report file calibre
5

III

I. Layout
DRC/LVS issue layout
file(GDSII format)Calibre tool topcell name
port name
Layout port 3(charge pump) 2( voltage booster)
Layout 2:1
II. Netlist
cp.src.net
LVS port 3 2port

Netlist cp.src.net.
subckt cp vout ph1 ph1a ph2 ph2a vdd
Mxx ...................
Mxxx .
.

.ends

Netlist vb.src.net.
.subckt vb vout ck vdd gnd
Mxx ...................
Mxxx .
.

.ends

cp.src.net vb.src.net netlist*

LVS
III.

1. all PVT pre-layout simulation &

post layout simulation
2.
3. charge pump
4. Caux1 Caux2
RC Parameter Extraction
PEX layout/netlist Calibre
option ( global net calibre DRC/LVS/PEX
Calibre PEX Capacitor(C+CC)
6

netlist

4.

test bench cptb.spvbtb.sp

.option method=gear accurate=3
.tran 2p 10u
(PVDD VDD )
VDD
VDD 0 PVDD
charge pump
V1
V3
V2
V4

ph1a 0 DC 0 PULSE 0 PVDD 2n 1n 1n 63n 100n

ph1 0 DC 0 PULSE 0 PVDD 7n 1n 1n 53n 100n
ph2 0 DC 0 PULSE PVDD 0 12n 1n 1n 43n 100n
ph2a 0 DC 0 PULSE PVDD 0 17n 1n 1n 33n 100n

Charge pump

Vck

voltage booster 10MHz

ck 0 DC 0 PULSE 0 PVDD 2n 1n 1n 49n 100n

.temp 27
Charge pump
.meas TRAN PO INTEG P(I1) from=250n to=10u
.meas TRAN PI INTEG P(VS) from=250n to=10u
.meas TRAN P1 INTEG P(V1) from=250n to=10u
.meas TRAN P2 INTEG P(V2) from=250n to=10u
.meas TRAN P3 INTEG P(V3) from=250n to=10u
.meas TRAN P4 INTEG P(V4) from=250n to=10u
.meas TRAN EFF PARAM='PO/(ABS(PI)+ABS(P1)+ABS(P2)+ABS(P3)+ABS(P4))*100'

Voltage booster

.meas TRAN PO INTEG P(I1) from=250n to=10u

.meas TRAN PI INTEG P(VS) from=250n to=10u
.meas TRAN PCK INTEG P(VCK) from=250n to=10u
.meas TRAN EFF PARAM='PO/(ABS(PI)+ABS(PCK))*100'

Vomin

.meas TRAN Vomin MIN V(Vout) from=250n to=10u

5.
full custom post layout
simulation result
charge pump voltage booster(charge pump + non-overlap
clock generator) voltage booster
charge pump

>50
Eff*20
Eff
All PVT
%

conditions
Eff >50%

clock
250ns
((Eff-0.5)*100)^1.35
all
Vomin
V
>2.5 Vomin<2.5

PVT

(Vomin-2.5)*10
Size laker um^2
<
26000

2600
GdsIn
26000-Size

0
(1)
1: 200um x 500um 2:1 2:1
250x500

6. Test Bench
Test bench netlist
/usr/cad/icc2011/ufc/tb.tar
test bench shell
script test bench
Test Bench
Test bench

cptb.sp
Charge pump test bench netlist
cptb
Charge pump test bench script
corner( cptb.sp, sed HSPICE)
cp.src.net
3 netlist test
bench
cptbapvt
cptb PVT script
vbtb.sp
Voltage booster test bench netlist
vbtb
cptb script
corner
vbtbapvt
cptbapvt PVT script
8

Script
cptb POWERSUPPLY TEMPRATURE PROCESSCORNER
vbtb POWERSUPPLY TEMPRATURE PROCESSCORNER

POWERSUPPLY

TEMPRATURE
PROCESSCORNE
corner
R
Test Bench

1.82.0
2785
TTFS

netlist cp.src.netmodel
file cic18.l hspice sed
cptbvbtbcbtbapvtvbtbapve chmod
( 8 )
Test bench cp.src.net vb.src.net
post layout simulation PEX subckt
port name

8
All PVT cptbapvt
// cptbapvt ( chmod
) cptb cptb.all

non-overlap clock charge pump

test bench vbtb vbtbapvt