http://www.edaplayground.

com/x/ELM
desing
-- sumador total
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity sumador_total is

port( ent1:in std_logic_vector(7downto 0);

ent2 :in std_logic_vector(7 downto 0);
carry:out std_logic;
resultado: out std_logic_vector(3 downto 0));

end sumador_total;

architecture behavioral of sumador_total is

COMPONENT sumador_medio
PORT(
A :in std_logic;
B :in std_logic;
cout:out std_logic;
suma: out std_logic);
END COMPONENT;

COMPONENT sumador_completo
PORT( cin:in std_logic;
A :in std_logic;

B :in std_logic;
cout:out std_logic;
suma: out std_logic);
END COMPONENT;

signal CO,C1: std_logic;

begin

Inst_sumador_medio:sumador_medio
port map(A=> ent1(0),
B=> ent2(0),
cout=>CO ,
suma=>resultado(0));

Inst_sumador_completo1:sumador_completo
port map(cin=>c1,
A=> ent1(1),
B=> ent2(1),
cout=>C1 ,
suma=>resultado(1));

Inst_sumador_completo2:sumador_completo
port map(cin=>CO,
A=> ent1(2),
B=> ent2(2),
cout=>CO ,
suma=>resultado(2));

Inst_sumador_completo3:sumador_completo
port map(cin=>C1,

A=> ent1(3),
B=> ent2(3),
cout=>carry,
suma=>resultado(3));

end behavioral;

--------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity calculadora is
Port( A,B:IN std_logic_vector(3 downto 0);
Sa,Sb:IN std_logic;
Cal:IN std_logic_vector(1 downto 0);
Sig:OUT std_logic;
Result:OUT std_logic_vector(7 downto 0));

end calculadora;

architecture Behavioral of calculadora is

--------------------------Declaracion de variables-------------------------------------signal k0,k1,k2,k3: std_logic_vector(2 downto 0);
signal Sp0,Sp1,Sp2,Sp3: std_logic_vector(7 downto 0);
-----------------------------------carrys-------------------------------------------------signal C0,C1: std_logic;
signal Va1,Va2,Va3,Va4: std_logic_vector(6 downto 0);

signal Ca1,Ca2: std_logic_vector(7 downto 0);

---------------------------------------------------------------------------------------signal S,E: std_logic_vector(5 downto 0);
signal R,G,I: std_logic;
signal O,T,M: std_logic_vector(6 downto 0);
signal Sgsum,Sgres,Sgmul: std_logic;
signal Rsuma,Rresta,Rmul: std_logic_vector(7 downto 0);

begin
---------------------------------------------------------------------------

--------------------------------------------------------------------------

Sig<=

Sgsum when Cal="00" else

Sgres when Cal="01" else
Sgmul when Cal="10" else
Sgmul;

Result <=

Rsuma

when Cal="00" else

Rresta

when Cal="01" else

Rmul when Cal="10" else

Rmul;

C0<= '0' when Sa = Sb else

'1';

Sp0(0)<=A(0) XOR B(0) XOR C0;

Sp0(1)<=A(1) XOR B(1) XOR k0(0);

Sp0(2)<=A(2) XOR B(2) XOR k0(1);

Sp0(3)<=A(3) XOR B(3) XOR k0(2);
k0(0)<=(B(0) AND C0) OR (A(0) and B(0)) OR (A(0) and C0);
k0(1)<=(B(1) AND k0(0)) OR (A(1) and B(1)) OR (A(1) and k0(0));
k0(2)<=(B(2) AND k0(1)) OR (A(2) and B(2)) OR (A(2) and k0(1));
Sp0(4)<=(B(3) AND k0(2)) OR (A(3) and B(3)) OR (A(3) and k0(2));
Sp0(5)<= '0';
Sp0(6)<= '0';
Sp0(7)<= '0';

Sp1(0)<=A(0) XOR (not B(0)) XOR C0;

Sp1(1)<=A(1) XOR (not B(1)) XOR k1(0);
Sp1(2)<=A(2) XOR (not B(2)) XOR k1(1);
Sp1(3)<=A(3) XOR (not B(3)) XOR k1(2);
k1(0)<=((not B(0)) AND C0) OR (A(0) and (not B(0))) OR (A(0) and C0);
k1(1)<=((not B(1)) AND k1(0)) Or (A(1) and (not B(1))) OR (A(1) and k1(0));
k1(2)<=((not B(2)) AND k1(1)) Or (A(2) and (not B(2))) OR (A(2) and k1(1));
Sp1(4)<= '0';
Sp1(5)<= '0';
Sp1(6)<= '0';
Sp1(7)<= '0';
------------------------------condiciones de suma -----------------------------------Rsuma <= Sp0 when Sa = Sb else
Sp1;

Sgsum<=Sa;
C1<= '1' when Sa = Sb else
'0';
------------------------------------------------------------------------------------------

Sp2(0)<=A(0)

XOR B(0) XOR C1;

Sp2(1)<=A(1)

XOR B(1) XOR k2(0);

Sp2(2)<=A(2)

XOR B(2) XOR k2(1);

Sp2(3)<=A(3)

XOR B(3) XOR k2(2);

k2(0)<=(B(0)

AND C1) OR (A(0) and B(0)) OR (A(0) and C1);

k2(1)<=(B(1)

AND k2(0)) OR (A(1) and B(1)) OR (A(1) and k2(0));

k2(2)<=(B(2)

AND k2(1)) OR (A(2) and B(2)) OR (A(2) and k2(1));

Sp2(4)<=(B(3)

AND k2(2)) OR (A(3) and B(3)) OR (A(3) and k2(2));

Sp2(5)<= '0';
Sp2(6)<= '0';
Sp2(7)<= '0';

Sp3(0)<=A(0) XOR (not B(0)) XOR C1;

Sp3(1)<=A(1) XOR (not B(1)) XOR k3(0);
Sp3(2)<=A(2) XOR (not B(2)) XOR k3(1);
Sp3(3)<=A(3) XOR (not B(3)) XOR k3(2);
k3(0)<=((not B(0)) AND C1) OR (A(0) and (not B(0))) OR (A(0) and C1);
k3(1)<=((not B(1)) AND k3(0)) OR (A(1) and (not B(1))) OR (A(1) and k3(0));
k3(2)<=((not B(2)) AND k3(1)) OR (A(2) and (not B(2))) OR (A(2) and k3(1));
Sp3(4)<= '0';
Sp3(5)<= '0';
Sp3(6)<= '0';
Sp3(7)<= '0';
------------------------------condicion de resta --------------------------------------Rresta <= Sp3 when Sa = Sb else
Sp2;
Sgres<=Sa;

G<='0';
----------------------------------mutiplicacion-----------------------------------------

Va1<=('0', '0', '0', (A(3) and B(0)), (A(2) and B(0)), (A(1) and B(0)), (A(0) and
B(0)));
Va2<=('0', '0', (A(3) and B(1)), (A(2) and B(1)), (A(1) and B(1)), (A(0) and
B(1)), '0');
Va3<=('0', (A(3) and B(2)), (A(2) and B(2)), (A(1) and B(2)), (A(0) and
B(2)), '0', '0');
Va4<=((A(3) and B(3)), (A(2) and B(3)), (A(1) and B(3)), (A(0) and B(3)), '0',
'0', '0'); ------------------------------resultado de suma---------------------------------

M(0)<=Va1(0) xOr Va2(0) XOR G;

M(1)<=Va1(1) xOr Va2(1) XOR S(0);
M(2)<=Va1(2) xOr Va2(2) XOR S(1);
M(3)<=Va1(3) xOr Va2(3) XOR S(2);
M(4)<=Va1(4) xOr Va2(4) XOR S(3);
M(5)<=Va1(5) xOr Va2(5) XOR S(4);
M(6)<=Va1(6) xOr Va2(6) XOR S(5);

S(0)<=(Va2(0) AND G)

OR (Va1(0) and Va2(0)) OR (Va1(0) and G);

S(1)<=(Va2(1) AND S(0)) OR (Va1(1) and Va2(1)) OR (Va1(1) and S(0));

S(2)<=(Va2(2) AND S(1)) OR (Va1(2) and Va2(2)) OR (Va1(2) and S(1));
S(3)<=(Va2(3) AND S(2)) OR (Va1(3) and Va2(3)) OR (Va1(3) and S(2));
S(4)<=(Va2(4) AND S(3)) OR (Va1(4) and Va2(4)) OR (Va1(4) and S(3));
S(5)<=(Va2(5) AND S(4)) OR (Va1(5) and Va2(5)) OR (Va1(5) and S(4));

I<=(Va2(6) AND S(5)) OR (Va1(6) and Va2(5)) OR (Va1(6) and S(5));

---------------------------suma------------------------------------O(0)<=Va3(0) XOR Va4(0) XOR G;

O(1)<=Va3(1) XOR Va4(1) XOR E(0);
O(2)<=Va3(2) XOR Va4(2) XOR E(1);

O(3)<=Va3(3) XOR Va4(3) XOR E(2);

O(4)<=Va3(4) XOR Va4(4) XOR E(3);
O(5)<=Va3(5) XOR Va4(5) XOR E(4);
O(6)<=Va3(6) XOR Va2(6) XOR E(5);

E(0)<=(Va4(0) and

G)

Or (Va3(0) and Va4(0)) OR (Va3(0) and G);

E(1)<=(Va4(1) and E(0)) or (Va3(1) and Va4(1)) OR (Va3(1) and E(0));

E(2)<=(Va4(2) and E(1)) or (Va3(2) and Va4(2)) OR (Va3(2) and E(1));
E(3)<=(Va4(3) and E(2)) or (Va3(3) and Va4(3)) OR (Va3(3) and E(2));
E(4)<=(Va4(4) and E(3)) or (Va3(4) and Va4(4)) OR (Va3(4) and E(3));
E(5)<=(Va4(5) and E(4)) or (Va3(5) and Va4(5)) OR (Va3(5) and E(4));

R<=(Va4(6) and E(5)) Or (Va3(6) and Va4(5)) OR (Va3(6) and E(5));

CA1<=(I, M(6), M(5), M(4), M(3), M(2), M(1), M(0));

Ca2<=(R, O(6), O(5), O(4), O(3), O(2), O(1), O(0));

Rmul(0)<=Ca1(0) XOR Ca2(0) XOR G;

Rmul(1)<=Ca1(1) XOR Ca2(1) XOR T(0);
Rmul(2)<=Ca1(2) XOR Ca2(2) XOR T(1);
Rmul(3)<=Ca1(3) XOR Ca2(3) XOR T(2);
Rmul(4)<=Ca1(4) XOR Ca2(4) XOR T(3);
Rmul(5)<=Ca1(5) XOR Ca2(5) XOR T(4);
Rmul(6)<=Ca1(6) XOR Ca2(6) XOR T(5);
Rmul(7)<=Ca1(7) XOR Ca2(7) XOR T(6);
---------------------------------------------------------------------T(0)<=(Ca2(0) and G) Or (Ca1(0) and Ca2(0)) OR (Ca1(0) and G);
T(1)<=(Ca2(1) and T(0)) Or (Ca1(1) and Ca2(1)) OR (Ca1(1) and T(0));
T(2)<=(Ca2(2) and T(1)) Or (Ca1(2) and Ca2(2)) OR (Ca1(2) and T(1));
T(3)<=(Ca2(3) and T(2)) Or (Ca1(3) and Ca2(3)) OR (Ca1(3) and T(2));

T(4)<=(Ca2(4) and T(3)) Or (Ca1(4) and Ca2(4)) OR (Ca1(4) and T(3));

T(5)<=(Ca2(5) and T(4)) Or (Ca1(5) and Ca2(5)) OR (Ca1(5) and T(4));
T(6)<=(Ca2(6) and T(5)) Or (Ca1(6) and Ca2(6)) OR (Ca1(6) and T(5));

Sgmul<='0' when Sa=Sb else

'1';

end Behavioral;

testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY calcul_tb IS
END calcul_tb;

ARCHITECTURE behavior OF calcul_tb IS

COMPONENT calculadora

PORT(

A,B:IN std_logic_vector(3 downto 0);

Sa,Sb:IN std_logic;
Cal:IN std_logic_vector(1 downto 0);
Sig:OUT std_logic;

Result:OUT std_logic_vector(7 downto 0));

END COMPONENT;

signal test_A: std_logic_vector(3 downto 0) := (others => '0');

signal test_B: std_logic_vector(3 downto 0) := (others => '0');
-----------ENTRADAS---------signal test_Sa : std_logic := '0';
signal test_Sb : std_logic := '0';
signal test_Cal : std_logic_vector(1 downto 0) := (others => '0');

-------------SALIDAS---------signal test_Sig : std_logic;

signal test_Result : std_logic_vector(7 downto 0);

BEGIN

dut: calculadora PORT MAP (

test_B,Sa => test_Sa,Sb =>

PROCESS
BEGIN
wait for 1 ps;

test_A<= "1010";
test_B<="0111";
test_Sa<='1';
test_Sb<='1';

A => test_A, B =>

test_Sb,Cal => test_Cal,Sig =>
test_Sig,Result=> test_Result);

test_Cal<="00";

wait for 1 ps;

test_A<= "1110";
test_B<="0101";
test_Sa<='1';
test_Sb<='1';
test_Cal<="00";

wait for 1 ps;

test_A<= "1011";
test_B<="0110";
test_Sa<='0';
test_Sb<='0';
test_Cal<="10";
wait for 1 ps;

test_A<= "1111";
test_B<="0101";
test_Sa<='0';
test_Sb<='1';
test_Cal<="11";

wait;
end process;

END;

tabla de verdad
B
Ci

Co

0
1
2
3
4
5
6
7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

0
0
0
1
0
1
1
1