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Andrew Stevens
Conclusion:
The implementation of this CPU using AHDL works and accomplishes the
demonstration of binary arithmetic and the state machine used for the control data
flow. This allows for implementation of many programs and with enough memory
can almost do any algorithmic operation. To improve the operation of this CPU there
are several things that could be implemented to improve performance and
functionality. For the ALU a look ahead adder could be implemented to cut down on
time spent within two of the steps. More pipe lining could be implemented in order
to have a larger through put. The design could be ported over to VHDL which is an
electrical engineering standard. More functionalities could be added such as
multiplication and divide operation. The application of minimal instruction set does
have it benefits. It allows for optimization of the computations within the ALU. It also
makes it easy to upscale to more digits and potentially adding additional CPUs to
work in tandem with little ease.
Andrew Stevens
Andrew Stevens
Andrew Stevens
Visabool Design for the Control Unit
Reset IR[7..0] C N Z;
s2.d = ~Reset st2 dir + ~Reset st2 imm + ~Reset st3 + ~Reset st4;
s1.d = ~Reset st1 + ~Reset st2 ind;
s0.d = ~Reset st0 + ~Reset st2 inh + ~Reset st2 imm + ~Reset st2 ind + ~Reset st4;
BCT = ~IR2 ~IR1 ~IR0 + ~IR2 ~IR1 IR0 C + ~IR2 IR1 ~IR0 N + ~IR2 IR1 IR0 Z + IR2 ~IR1 IR0 ~C +
IR2 IR1 ~IR0 ~N + IR2 IR1 IR0 ~Z;
Andrew Stevens
AHDL Code to Implement the TORO CPU
Subdesign Toro680
(
ClkM27, Reset_b, ClkSel[2..0]
:Input;
:Output;
:BIDIR;
)
Variable
Ctr[27..0], MemClk, CpuClk
:Dff;
OeAClk, OeAdelayed
:Dff;
:Dff;
PCt[7..0], Act[7..0]
:Tri;
:Node;
:Node;
:Node;
:Tri_State_Node;
State
:Machine
With States(I0,I1,A0,A1,A2,Ex);
Begin
Ctr[].clk = ClkM27;
Ctr[].d = Ctr[].q+1;
MemClk.clk = ClkM27;
MemClk.d = (ClkSel[]==0)&Ctr[27] # (ClkSel[]==1)&Ctr[26]
# (ClkSel[]==2)&Ctr[24] # (ClkSel[]==3)&Ctr[22]
# (ClkSel[]==4)&Ctr[20] # (ClkSel[]==5)&Ctr[18]
# (ClkSel[]==6)&Ctr[16] # (ClkSel[]==7)&Ctr[6];
MemClkO = MemClk.q; % Clock being sent to Memory board %
OeAClk.clk = ClkM27;
OeAClk.d = (ClkSel[]==0)&Ctr[25] # (ClkSel[]==1)&Ctr[24]
# (ClkSel[]==2)&Ctr[22] # (ClkSel[]==3)&Ctr[20]
# (ClkSel[]==4)&Ctr[18] # (ClkSel[]==5)&Ctr[16]
# (ClkSel[]==6)&Ctr[14] # (ClkSel[]==7)&Ctr[4];
Andrew Stevens
OeAdelayed.clk = OeAClk.q; % OeAClk is 4 times faster than MemClk %
OeAdelayed.d = OeA;
CpuClk.clk = ClkM27;
CpuClk.d = MemClk.q; % CpuClk is 1/27M sec (37 ns) behind MemClk %
PC[].clk = CpuClk;
IR[].clk = CpuClk;
AC[].clk = CpuClk;
C.clk = CpuClk;
State.clk = CpuClk;
ClkDisp = CpuClk;
Andrew Stevens
LdIR = I1;
LdA = Inh & A0 # Ex & Alu;
LdMAR = I0 # A0 # A1 # A2;
Wr = Ex & Sta;
OePC = I0 # A0;
OeA = Ex & Sta;
Rd = I1 # A1 # A2 # Ex & Br & BCT # Ex & Alu;
IncPC = I0 # A0;
Reset = !Reset_b;
Rd_b = !Rd;
Wr_b = !Wr;
State.clk = CpuClk;
Case State Is
When I0 =>
If Reset Then State = I0;
ELSE State = I1; END IF;
When I1 =>
If Reset Then State = I0;
ELSE State = A0; END If;
When A0 =>
If Reset Then State = I0; End If;
If !Reset & Inh Then State = I1; End If;
If !Reset & Ind Then State = A1; End If;
If !Reset & Dir Then State = A2; End If;
If !Reset & Imm Then State = Ex; End If;
When A1 =>
If Reset Then State = I0;
ElSE State = A2; End If;
When A2 =>
If Reset Then State = I0;
Andrew Stevens
ElSE State = Ex; End If;
When Ex =>
State = I0;
End Case;
% ALU Operation %
Sum[] = Cda & (0,B[]) #
Add & ((0,B[]) + (0,Ac[])) #
AndIt & ((0,B[]) & (0,Ac[])) #
OrIt & ((0,B[]) # (0,Ac[])) #
XorIt & ((0,B[]) $ (0,Ac[])) #
ShR & (0,Ac7, Ac[7..1]);
% Acumulator Operations %
Act[].in = Ac[];
Ac[] = LdA & Sum[7..0] # !LdA & Ac[];
% Bus Operaions %
BusOut[] = B[];
B[] = Act[].out;
B[] = Pct[].out;
B[] = Bus[];
Bus[] = B[];
Andrew Stevens
% IR operations %
IR[] = LdIR & B[] # !LdIR & IR[];
% PC operations %
Pct[].in = PC[];
Pct[].oe = OePC;
PC[] = !Reset & LdPC & B[] # !Reset & IncPC & (PC[] + 1) # !Reset & !LdPC & !IncPC & PC[];
End;
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