Analog Circuit Design On Digital CMOS

Analog Circuit Design on Digital CMOS
Why it is difficult, and which ideas help. Presented by HP. Schmid.
Background on Hanspeter Schmid

Dissertation on video-frequency integrated filters (ETH Zrich)
Analog IC Designer at Bernafon / William Demant Holding:
Analog electronics: LNAs, amplifiers, regulators, filters, standard
cells, circuits for wireless communication system.
System design, analog signal processing and signal integrity.
Communication facilitator between Danish and Swiss Teams.
IME: research projects (sensor systems, sigma-delta, etc.),

consulting, teaching.
ETH Zrich: teaching analog (integrated) signal processing
IEEE CAS:
Chair Analog Signal Processing Tech. Comm.
Associate Editor of TCAS-I
Hobbies: going for walks,

playing trombone, reading.
Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland
ISCAS 2009
Tutorial Philosophy
ISCAS 2009
Philosophy I: Be a fool!
multiparameter optimization
noise
distortion
power consumption
signal delay
chip area
offset
yield
mask costs
conscious vs. subconscious

conscious mind: 45 criteria
subconscious: 100? 200?
what it means to be a fool
ISCAS 2009
Philosophy II: Be a child

open for everything
playful
does not do
what she should do
a child has got time!
Advice for scientists by
Douglas Adams:
See first, think later, then
test. But always see first, or
you will only see what you
expect to see!
ISCAS 2009
Philosophy III: Be a climber

works hard to achieve a goal
is well trained
normally gets to the intended
goal
Is the intention good?
The direct path leads only to
the
goal!
Gide) new
The most exciting phrase in science,
the
one (Andr
that heralds
discoveries, is not Eureka! (I found it!), but
Will
That's funny
... the fool not fall down?
(Isaac Asimov)
Not if the fool also is a child.
ISCAS 2009
Tutorial Contents
Image from http://www.beatenbergbilder.ch/

ISCAS 2009
Introduction: What is new?

More metal layers
Small lateral distances
Thinner gates
more C
less Vdd
less gain
more weak inversion
Image from http://www.ndl.org.tw/cht/ndlcomm/P10_2/7.pdf

ISCAS 2009
Multi-metal cross section

Example: 6 Metal layers.
Lateral dimensions are smaller than vertical dimensions!
ISCAS 2009
Transconductance in Strong and Weak Inversion

Strong Inversion
Weak Inversion
Moderate Inversion: Superposition
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10
Maximum gain of single stage is reached in weak inversion

For a given supply current: gain is proportional to supply voltage!
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Weak inversion = matching problems?

For a 0.25u process:
Voltage offset
for identical supply current
Current offset
for identical gate-source voltage
Therefore: Differential pairs in weak inversion

Therefore: Current mirrors in strong inversion
from [Kinget07]
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Summary
Thinner gates (and higher gate tunnelling currents!)
more gate (overlap, ...) capacitance per area
No buried channels anymore
pMOS is not better anymore in terms of flicker noise!
Less supply voltage less signal
Less gain
same white noise at same supply current; less flicker noise
Sub-threshold leakage
ISCAS 2009
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Literature: What is new?

[Annema99] Anne-Johan Annema, "Analog Circuit Performance and Process Scaling",
IEEE Trans. Circuits and SystemsII, vol. 46, no. 6,
pp. 711725, June 1999.
[Huang98] Qiuting Huang et. al., "The Impact of Scaling Down to Deep Submicron on
CMOS RF Circuits," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 10231036, July
1998
[Kinget07] Peter Kinget, "Device Mismatch: An Analog Design Perspective", ISCAS, New
Orleans, pp. 12451248, May 2007.
[Tsividis02] Yannis Tsividis, Mixed Analog-Digital VLSI Devices and Technology, World
Scientific Publishers, 2002.
[Tsividis99] Yannis Tsividis, Operation and Modelling of the MOS Transistor, ed. 2,
McGraw-Hill 1999.
[Dijksterhuis06] Ap Dijksterhuis et. al., "On Making the Right Choice: The DeliberationWithout-Attention Effect," Science, vol. 311, pp. 10051007, 2006.
[Simons99] Daniel Simons et. al., "Gorillas in our midst: sustained inattentional
blindness for dynamic events," Perception, vol. 28, pp. 10591074, 1999.
ISCAS 2009
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ISCAS 2009
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Signal Integrity
Ground and Power Routing
Star Connections
Tapered Stars
Signal Grounds and Refs
Improving PSR (theory)
Finger capacitors and
MIM-capacitors
Demodulation by nonlinearity
Decoupling
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Why correct ground and power routing are important
ISCAS 2009
17
On PCB: Power plane? No!
ISCAS 2009
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On PCB: Split ground plane? Dangerous!
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Recommendations for PCB routing

[National05] recommend
Use a single, unified ground plane
use separate power planes for analog and digital
let trace routing control ground currents.
Low-power low-noise circuits:

require controlled power/gnd routing!
ISCAS 2009
20
The problem of the star connection on chip
ISCAS 2009
21
Calculation example: hearing aid system
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16 is not a lot!
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Solution: Tapered star
This means: we have full control of where the noise currents flow.
But: more chip area or more supply / ground wire resistance!
Paradox: most sensitive nodes are farthest away from pad.
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Local decoupling is sometimes needed

The question is: where shall the decoupling capacitor go?
Answer: to the reference of the signal!

But this may not be so easy.
Many "PSR problems" are really coupling problems or problems
with dirty references
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How to improve PSRR and CMRR in a system?

CMRR and PSRR are connected!
Proof: Gauge transformation
from [Sckinger91]
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Solution: Additional input from quiet ground

Now we have one more degree
of freedom
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Example: additional signal path
from [Loikkanen06]
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Example: additional signal path
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Recommendations for chip routing

Use "tapered" star connections
For every differential signal node, make sure that the signal is
referred to a clean signal.
Input reference
Problem:
the references can change
within a single circuit
Output reference
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Multi-metal Finger-Cap MIM-Cap combination
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Comparison for a six-metal 0.18um CMOS process
MIM capacitor (Metal 5 and Metal 6):
1.0 fF/m2
Finger structure (Metal 1 Metal 4):
1.3 fF/um2
MIM capacitor on top of Finger structure (all Metal):
2.3 fF/um2
MOSFET gate capacitance (non-linear):
10.0 fF/um2
Can we use a MOSFET gate capacitor for decoupling?
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Demodulation by a nonlinearity I: DC offset

Normal Operation with HF-Signal on Pad
(weak inversion)
Gives DC Offset! Inputs must be protected against this ...

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Demodulation by a nonlinearity II: receiver

Normal Operation with amplitude-modulated
HF-Signal on Pad (weak inversion)
Demodulates the signal and gives more DC offset!

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Realistic? Yes!
In all digitally driven class-D (PWM) amplifiers, the signal is
amplitude-modulated on the system clock frequency.
The square of this signal appears in the supply current.
If this strays back into a high-gain audio system:
huge distortion or even instability!
Solution:
decouple all inputs
... to the respective reference of the signal
... as close to the pad as possible
... with as big a capacitor as possible
ISCAS 2009
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Literature: Signal Integrity

[Loikkanen06] Mikko Loikkanen et. al., "PSRR Improvement
Technique for Amplifiers with Miller Capacitor," ISCAS 2006,
Kos, Greece, pp. 13941397.
[National05] National Semiconductor Analog University, Meeting
Signal-Path Design Challenges, High-performance seminar
series 2005, part no. 570012-001. (Can be ordered from
National for free.)
[Sckinger91] Eduard Sckinger et. al., "A General Relationship
Between Amplifier Parameters, And Its Application to PSRR
Improvement," IEEE Trans. Circuits and SystemsI, vol. 38,
no. 10, pp. 11731181, Oct 1991
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An amp within an amp

Weak inversion
Zero-Vgs amplifiers
Super-Transistors
Cascode current mirrors
Self-biased cascodes
Regulated cascodes
Matryoshka amplifiers
Regulated cascode OTAs
Nested Miller amplifiers
Image from http://www.souvenironline24.de/shop.aspx

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Weak Inversion = Sub-threshold Operation
from [Tsividis99]
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Zero-Vgs folded-cascode opamp in 0.18m technology
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Zero-Vgs folded-cascode opamp in 0.18m technology
VGS
VT=230 mV (!), L=min, ID=5uA

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Maximum gain of single stage is reached in weak inversion

For a given supply current: gain is proportional to supply voltage!
Less gain on (deep)

submicron
ISCAS 2009
42
Normal current mirror

Output resistance
Increase this with feedback!
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Cascode current mirror

Feedback loop:
For a constant signal current, the transistor M4 tries to keep the
drain voltage of M2 constant. The loop gain around M4 is
and the output resistance:
Problem: high voltage drop.

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Low-voltage cascode current mirror

Same feedback loop!
Careful design needed such that

M3 and M1 are always saturated
Bias voltage necessary
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Self-biased low-voltage cascode current mirror

Still same feedback loop!
But: for the same current, Vgs3 < Vgs1!

M1, M2 in strong inversion
M3, M4 in weak inversion
(makes Aloop small and M3,M4 huge)
M1, M2 normal-Vt transistors
M3, M4 low-Vt transistors
(requires low-Vt transistors, which
most submicron processes have)
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Different view: build super transistors
Then: build good super transistors!

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47
The regulated cascode

Increasing the loop gain ...
... gives much higher output resistance
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The "original" by Sckinger

simplest loop amplifier, but needs a lot of supply voltage
from [Sckinger90]
ISCAS 2009
49
Matryoshka-style regulated-cascode amplifier
several OTA
Slices
one OTA Slice

from [Treichler06]
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50
Matryoshka slice layout!
One OTA Slice

Full OTA
[Treichler06]
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Matryoshka Miller OpAmp: Two stages
from [Huijsing01]
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Matryoshka Miller OpAmp: Three stages
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Matryoshka Miller OpAmp: Four stages
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Conclusion
On modern digital technologies, we lose
supply voltage
gain
If we need gain:
we need to combine more gain stages
and, if possible, use weak inversion
Intuitive way to think about it:
An Amp within an Amp within an Amp
ISCAS 2009
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Literature: New uses of old parts

[Burger96] Thomas Burger and Qiuting Huang, "A 100dB 480MHz OTA in
0.7um CMOS for sampled-data applications," Proc. CICC,
pp. 101104, 1996.
[Huijsing01] Johan H. Huijsing, Operational AmplifiersTheory and Design,
Kluwer Academic Publishers, 2001.
[Sckinger90] Eduard Sckinger et. al, "A High-Swing, High-Impedance MOS
Cascode Circuit," IEEE J. Solid-State Circuits, vol. 25, no. 1,
pp. 289298, Feb 1990.
[Treichler06] Jrg Treichler et. al., "A 10-bit ENOB 50-MS/s Pipeline ADC in
130-nm CMOS at 1.2 V Supply," Proc. ESSCIRC, Montreux, Switzerland,
pp. 552555, 2006.
[Tsividis99] Yannis Tsividis, Operation and Modelling of the MOS Transistor,
ed. 2, McGraw-Hill 1999.
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Switched capacitors
Speed limit of SC filters
SC noise filtering
Switches and T-gates
Voltage doublers
for clock signals
for OTA tails
for control voltages
Flicker Noise
Autozero, CDS and Chopping
ISCAS 2009
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Simple SC resistor
Pole frequency of SC resistor

loaded with capacitance:
from [Gregorian86]
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59
SC becomes much faster on modern processes
from [Johns97]
ISCAS 2009
60
Huge SC resistor for noise filtering

"Bucket Chain" technique
Possible: 1s time constant!
Requires RC filters for antialiasing
e.g., 80fF, 160kHz, 13 elements 1 G
Beware of offset!!!
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Bad Layout: asymmetries of clock lines!

This can give huge offset.
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Good Layout: as symmetrical as possible
ISCAS 2009
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Types of switches
from [Johns97]
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Voltage-level limitation
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Benefitting from Narrow-Channel Effects
from [Tsividis96]
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Reduce switch threshold voltage by slicing
VT=610mV
0.18u Process
Normal-VT Transistors
VT=540mV
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Clock voltage doubler

"Doubling" pMOS gate voltages below VSS is also possible!
from [Basu99]
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What is flicker noise?
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Fllicker noise comes from a process with memory!
from [Keshner82]
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Why is it called "flicker" noise?
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On flicker noise:
the Yahoo Aaaaaargh!
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On flicker noise: the Yahoo Aaaaaargh!
from [Schmid07]
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Nature of Memory in MOSFETs

Mainly interface traps at the channel-to-oxide and gate-to-oxide
interfaces:
Spectrum caused by a single trap with time constant :
Distribution of the time constants:
Flicker noise slope is a physical property.

Flicker noise magnitude is related to the absolute number of
interface traps.
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Model of scaling-invariant memory
from [Schmid08]
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RMS behaviour of flicker noise
ISCAS 2009
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Reducing flicker noise by deleting memory I
from [Klumperink00]
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Sampling noise
from [Schmid08]
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Reducing offset and flicker noise by auto-zeroing
Autozero
1: Vos
2: Vin+Vos
21: Vin
Correlated
Double
Sampling
1: Vin+Vos
2: Vin+Vos
21: 2Vin
from [Enz96]
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Reducing offset and flicker noise by auto-zeroing
ISCAS 2009
80
Reducing offset and flicker noise by chopping
from [Enz96]
ISCAS 2009
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Simulated chopped noise
ISCAS 2009
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Chopper circuit
from [Schmid08]
ISCAS 2009
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Matryoshka Chopper
from [Schmid08]
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84
Multipath Chopper
Chopped
High
Gain
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Reducing offset and 1/f noise by correlated double sampling

Auto-zeroing: sample offset in one phase; sample signal in
other phase while compensating offset.
Auto-zeroing works in sampled time.
Chopping: modulate input signal to a higher frequency;
modulate signal back after amplifier, and therefore modulate
offset and 1/f noise to higher frequencies.
Chopping works in continuous time!
Correlated double sampling combines both: first sample signal,
then sample inverse, then subtract.
Correlated double sampling works in sampled time.
CDS can be used most effectively in capacitive sensor systems
where the sensor can be controlled to give normal or inverse
output signals! Then sensor offset and 1/f noise is reduced too.
In auto-zero and CDS, the transistor bias history must be
the same for both samples!
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Literature: Switched capacitors

[Basu99] S. Basu and G. Temes, "Simplified Clock Voltage Doubler," Electronics Letters, vol. 35, no. 22, pp. 19011902, Oct 1999.
[Duisters98] Tonny A. F. Duisters and Eise Carel Dijkmans, "A 90-dB THD rail-to-rail input opamp using a new local charge pump in
CMOS," IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 947955, Jul. 1998.
[Enz96] Christian Enz and Gabor Temes, "Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated
Double Sampling, and Chopper Stabilization," Proc. IEEE, vol. 84, no. 11, pp. 15841614, Nov 1996.
[Gregorian86] Roubik Gregorian and Gabor Temes, Analog MOS Integrated Circuits for Signal Processing, John Wiley & Sons 1986.
[Johns97] David Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons 1997.
[Keshner82] Marvin Keshner, "1/f Noise," Proc. IEEE, vol. 70, no. 3, pp. 212218, March 1982.
[Klumperink00] Eric Klumperink et. al., "Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing," IEEE J. Solid-State
Circuits, vol. 35, no. 7, pp. 9941001, Jul. 2000.
[Schmid02] Hanspeter Schmid, "An 8.25-MHz 7th-Order Bessel Filter Built with Single-Amplifier Biquadratic MOSFET C Filters", Analog
Integrated Circuits and Signal Processing, NORCHIP special issue, vol. 30, no. 1, pp. 6981, January 2002.
[Schmid07] Hanspeter Schmid , "Aaargh! I Just Loooove Flicker Noise," IEEE Circuits and Systems Magazine, pp. 3235, First Quarter
2007.
[Schmid08] Hanspeter Schmid, "Offset, flicker noise, and ways to deal with them": Chapter in Circuits at the Nanoscale, CRC Press,
2008, edited by Krzysztof Iniewski.
[Wel07] Arnoud P. van der Wel et. al., "Low-Frequency Noise Phenomena in Switched MOSFETs," IEEE J. Solid-State Circuits, vol. 42,
no. 3, pp. 540550, March 2007.
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Feedback or no feedback
The benefit of feedback
Current mode and
voltage mode
Example: Open-Loop SigmaDelta A/D converter
Case study with CSEM Zrich:
Low-feedback approach
applied to buffer design
Image from [Black34]

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Feedback (in Black's words)

Advantages:
constancy of amplification
freedom from nonlinearity
reduced delay and delay distortion, reduced noise disturbance from
the power supply circuits
Disadvantages:
[difficult] because of the [] special control required of phase shifts
Unless these relations are maintained, singing will occur
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No free lunch!
The famous no-free-lunch theorem states that even if we say, e.g.,
"A system with feedback gives us low distortion for free", it is not
really for free, we just cannot possibly optimize power by trading in
distortion or other parameters.
A more scientific version of the no-free-lunch theorem states:
A general-purpose optimization strategy is impossible, and
the only way one strategy can outperform another is if it is
specialized to the structure of the specific problem under
consideration.
from [Ho01]
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High-Impedance node in AD844 current-feedback amplifier
ISCAS 2009
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Simple example: voltage-controlled current source
ISCAS 2009
93
AD844: the first stage is a Current Conveyor (CCII)
ISCAS 2009
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Current Amplifier without high-impedance node
from [Schmid00]
ISCAS 2009
95
Real difference
from [Schmid03]
ISCAS 2009
96
Very simple, very fast voltage integrator
from [Nauta92]
ISCAS 2009
97
Impedance mismatch
to decouple
feedback couples again
no FB
decoupled
optimization is much faster
optimization space becomes tidier
the child finds out more in a shorter time
the fool won't fall
Example
aggressive design time
first time right
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ISCAS 2009
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Case Study: Low-feedback approach applied to buffer design

Hanspeter Schmid, IME/FHNW
Simon Neukom and Yue-Li Schrag, CSEM Zrich
ISCAS 2009
100
Standard SC amplifier
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101
Why an open-loop solution?

We needed
Voltage level shift from arbitrary low voltage to 1.6V
Less supply current variation (lowered by 20dB)
12-bit precise settling at 4 MHz sample rate, 12-bit precise offset
Our open-loop continuous-time solution gave
less offset (3=3.3mV compared to SC amp's 3=11.4mV)
less power (14mW compared to SC amp's 63.5mW)
Disadvantages are:
more harmonic distortion
more noise
but since this is an output driver after high-gain pre-amplifier chain,
both disadvantages do not matter in our application.
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102
Operation principle: (with matched resistors)

Stage 1: single-ended voltage to differential current
Stage 2: current to voltage
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103
Offset compensation with current-output Track&Hold

Signal is processed in "Hold" mode
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Offset compensation with current-output Track&Hold

Offset is compensated in "Track" mode individually for each output path
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The remaining offset comes only from the T&H OTA!

All other offsets, including random offsets in the gnd references, are cancelled.
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Input transconductor
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Output transresistance amplifier
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Track&Hold amplifier
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Static offset: value settled at the end of calibration cycle

Dynamic offset: mean value of full-scale settled values
Static Offset
Durch Bild oder Grafik

ersetzen
(Grsse und Position beibehalten)
Dynamic Offset
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Static and dynamic offset

correlate very well
Offsets of two channels do

not correlate well
digital correction possible!
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111
Supply current for full-scale steps

The current peaks are much smaller than for SC amplifiers
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112
Monte-Carlo simulation of third-order (left)

and second-order (right) harmonic distortion (full scale, full speed)
Efficient Simulation of Harmonic Distortion in Discrete-Time Circuits

Wednesday May 27, 2009 from 15:30 - 17:00 in Room 101B.
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What causes
non-idealities?
odd-order distortion
even-order distortion
gain error
NOISE
offset
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Design time!
two weeks including all
simulations and layout
has been used on
three chips
first time right;
meets specs
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Literature: Feedback or no feedback

[Black34] Harold S. Black, "Stabilized Feed-Back Amplifiers," Electrical Engineering, vol. 53, no. 1,
pp. 114120, Jan 1934. Reprinted in Proc. IEEE, vol. 87, no. 2, pp. 379385, Feb 1999.
[Ho01] Y-C. Ho, D. Pepyne, "Simple Explanation of the No Free Lunch Theorem of Optimization",
Proc. 40th IEEE Conf. on Decision and Control, Orlando, pp. 44094414, Dec. 2001.
[Mahattanakul98] Jirayuth Mahattanakul, "Current-Mode Versus Voltage-Mode Gm-C Biquad Filters:
What the Theory Says," IEEE Trans. CASI, vol. 45, no. 2, pp. 173186, Feb 1998.
[Nauta92] Bram Nauta, "A CMOS Transconductance-C Filter Technique for Very High Frequencies,"
IEEE J. Solid-State Circ., vol. 27, no. 2., pp. 142153, Feb 1992.
[Schmid00] Hanspeter Schmid, "Approximating the Universal Active Element." IEEE Trans. CASI,
vol. 47, no. 11, pp. 11601169, Nov 2000.
[Schmid03] Hanspeter Schmid, "Why 'Current Mode' Does Not Guarantee Good Performance,"
Analog Integrated Circuits and Signal Processing, vol. 35, no. 1, pp. 7990, April 2003.
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Thank you for coming!

Hanspeter Schmid
Institute of Microelectronics
Steinackerstrasse 1
5210 Windisch
Switzerland
Tel +41 56 462 46 25
Fax +41 56 462 46 15
hanspeter.schmid@fhnw.ch
Lab: http://www.fhnw.ch/technik/ime/
Publications: http://www.schmid-werren.ch/hanspeter/
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Analog Circuit Design On Digital CMOS

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Analog Circuit Design On Digital CMOS

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Analog Circuit Design on Digital CMOS

Why it is difficult, and which ideas help. Presented by HP. Schmid.

Background on Hanspeter Schmid

IME: research projects (sensor systems, sigma-delta, etc.),

Hobbies: going for walks,

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

conscious vs. subconscious

what it means to be a fool

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Philosophy II: Be a child

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Philosophy III: Be a climber

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Image from http://www.beatenbergbilder.ch/

Introduction: What is new?

Image from http://www.ndl.org.tw/cht/ndlcomm/P10_2/7.pdf

Multi-metal cross section

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Transconductance in Strong and Weak Inversion

Moderate Inversion: Superposition

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Maximum gain of single stage is reached in weak inversion

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Weak inversion = matching problems?

Therefore: Differential pairs in weak inversion

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Literature: What is new?

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Why correct ground and power routing are important

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

On PCB: Power plane? No!

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

On PCB: Split ground plane? Dangerous!

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Recommendations for PCB routing

Low-power low-noise circuits:

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

The problem of the star connection on chip

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Calculation example: hearing aid system

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Solution: Tapered star

Local decoupling is sometimes needed

Answer: to the reference of the signal!

How to improve PSRR and CMRR in a system?

Solution: Additional input from quiet ground

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Example: additional signal path

Example: additional signal path

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Recommendations for chip routing

Multi-metal Finger-Cap MIM-Cap combination

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Comparison for a six-metal 0.18um CMOS process

MIM capacitor (Metal 5 and Metal 6):

Finger structure (Metal 1 Metal 4):

MIM capacitor on top of Finger structure (all Metal):

MOSFET gate capacitance (non-linear):

Can we use a MOSFET gate capacitor for decoupling?

Hanspeter Schmid, Institute of Microelectronics, FHNW, Windisch, Switzerland

Demodulation by a nonlinearity I: DC offset