Professional Documents
Culture Documents
The execution of project based lab planned in two phases:Phase I: Experiments Based: First six weeks student need to work out and execute the list of
programs /experiments as decided by the instructor. These lists of programs /Experiments must cover
all the basics required to implement any project in the concerned course.
Phase II: Project Based: After six weeks student needs to work out on the project on the concerned
course designed by faculty or he/she may be allowed to do implement his/her own idea in the
concerned course.
Proposed Dates:will be announced during course work
Assessment Approach:The Project based Lab will be undertaken through External and Internal evaluation. The following
Table reflects various evaluation components that will be used to assess the performance of the
students.
Type of
Evaluation
External
Evaluation
Internal
Evaluation
Max Marks
allocated
Evaluation
component
60
End Semester
External
evaluation
40
Attendance
Continuous
Assessment
End Semester
Internal
examination
Marks
allocated
60
05
15
20
Subdivision of
the evaluation
component
Report
Viva Voce
Execution
*Demonstration
Viva Voce
Record
Report
Viva Voce
Execution
Demonstration
Marks
Allocated
20
20
10
10
5
10
05
5
5
5
5
*A part of the project work done should be assessed in the End Semester External evaluation to
identify the capability of the student Hands on experience &Practical knowledge gained in the Lab.
No student of the same batch (project based lab experiment batch) shall be tested by allotting the same
experiment.
Signature of HOD
= 1 0r 0 at multiplexer and m-input channel select pins for ''m ''literals of an SOP Boolean function .
Theory:While Multiplexers are primarily thought of as data selectors because they select one of several
Inputs to be logically connected to the output, they can also be used to implement Boolean functions.
Similarly, while n-bit Decoders are primarily thought of as n-bit binary to 1 of 2n code converters or
as Demultiplexers, they can also be used to implement Boolean functions of n variables. Consider the
following truth table that describes a function of 4 Boolean variables. A 16 to 1 Multiplexer with A,
B,C, and D applied to its S3, S2, S1, and S0 inputs respectively would select one of its 16 inputs for
each of the 16 possible combinations of A, B,C, and D. We can implement the function described by
the truth table by connecting a voltage source for logic level 1 or ground for a logic level 0 to each of
the Multiplexer inputs corresponding to the required value of the function associated with the
combination of A, B, C, and D that selected the input. Therefore, the inputs to the Multiplexer will be
the same as the F entries in the truth table provided A, B,C, and D are connected to the Multiplexer
select inputs in the right order.
Circuit Diagram:-
2. The input lines corresponding to these numbers are to be connected to logic 1 level and all other
input lines are connected to logic 0.
3. Then the select inputs are to be applied to the select lines.
Using Logisim, to insert a logic gate, expand the folder Gates and click on the desired logic gate.
Once the gate is selected, the mouse will turn into the shape of the selected gate.
Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on to p (
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle
(
).
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
Circuit diagram
Output 1 of register A is connected to input 0 of MUX 1because this input is labelled A1.The diagram
shows that the bits in the same significant position in each register are connected to the data inputs of
one multiplexer to form one line of the bus. Thus MUX 0 multiplexes the four 0 bits of the registers,
MUX 1 multiplexes the four 1 bits of the registers, and similarly for the other two bits
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle (
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
).
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle (
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
).
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle (
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
).
A dark green colour means that the current value on the wire is a logical 0, while a light green
colour signies a 1.
Other wire colours: blue = unknown value, gray = unconnected, red = conict.
Observations and Result:
The number of gate levels for the carry propagation can be found from the circuit of full adder. The
signal from input carry Cin to output carry Cout requires an AND gate and an OR gate, which
constitutes two gate levels. So if there are four full adders in the parallel adder, the output carry C5
would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to
propagate through.
Design Issues:
The corresponding Boolean expressions are given here to construct a carry look ahead adder. In the
carry-look ahead circuit we need to generate the two signals carry propagator (P) and carry generator
(G),
Pi = Ai Bi
Gi = Ai Bi
The output sum and carry can be expressed as
Sumi = Pi Ci
Ci+1 = Gi + ( Pi Ci)
Having these we could design the circuit. We can now write the Boolean function for the carry output
of each stage and substitute for each Ci its value from the previous equations:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 P3 G2 P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
Circuit Diagram:-
Procedure:To insert a logic gate, expand the folder Gates and click on the desired logic gate.
Once the gate is selected, the mouse will turn into the shape of the selected gate.
Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on to p (
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle
(
).
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is selected.
Also, the directional movement of the data through a shift register can be either to the left,
(left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right
shifting within the same register thereby making it bidirectional. In this tutorial it is assumed
that all the data shifts to the right, (right shifting).
Universal Shift Register :-
Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory, delay information such as the SISO
or PIPO configuration modes or transfer data from one point to another in either a serial or
parallel format. Universal shift registers are frequently used in arithmetic operations to shift
data to the left or right for multiplication or division.
Circuit Diagram:-
Procedure:Using Logisim, to insert a logic gate, expand the folder Gates and click on the desired logic
gate.
Once the gate is selected, the mouse will turn into the shape of the selected gate.
Place the gate in the circuit area on the right.
To connect the gates, select the arrow icon on to p (
).
Then drag from the output of one gate to the input of another gate.
You can connect to any of the small blue dots on the gate symbol.
To create an input to the circuit, select the Add Pin icon with an outline of a square (
).
Similarly, add an output to the circuit by using the Add Pin icon with an outline of a circle
(
).
To assign a name to the input/output pin, click on the pin while the arrow icon (
) is
selected.
You may then add the label for the pins.
Once you have connected the circuit, you will notice the color of the wire changes.
A dark green color means that the current value on the wire is a logical 0, while a light
green color signies a 1.
Other wire colours: blue = unknown value, gray = unconnected, red = conict.
Observations and Result:
7.Design
of 4-bit ALU
Examining behaviour of arithmetic logic unit for the working module and module designed
by the student as part of the experiment.
Components: To build any 4 bit ALU, we need
AND gate, OR gate, XOR gate
Full Adder,
4-to-1 MUX
Simulator or Logisim.
Objective:Understandingbehaviourofarithmeticlogicunitfromworkingmoduleandthe
moduledesignedbythestudentaspartoftheexperiment
In case of counters the number of flip-flops depends on the number of different states in the
counter.
ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,
subtraction, division, multiplication and logical operations like and, or, Ex-or, NAND, NOR
etc. A simple block diagram of a 4 bit ALU for operations and, or, Ex-or and Add is shown
Design Issues:
The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal
S1 and S0 the circuit operates as follows:
For Control signal S1 = 0, S0 = 0, the output is A And B,
For Control signal S1 = 0, S0 = 1, the output is A Or B,
For Control signal S1 = 1, S0 = 0, the output is A Xor B,
For Control signal S1 = 1, S0 = 1, the output is A Add B.
The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:
Required functionality of ALU (inputs and outputs are active high)
Mode Select
Inputs
S2
S1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
S3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
S0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Loading data in the arithmetic logic unit (refer to procedure tab for further detail and
experiment manual for pin numbers):
Load the two input numbers as:
o
o
o
check output:
o
o
check output:
o F3=1, F2=1, F1=0, F0=1
o cout=0 `
check output:
o F3=0, F2=1, F1=0, F0=1
o cout=0 `
check output:
o F3=0, F2=1, F1=0, F0=1
o cout=1
Likewise the 16 bit arithmetic logic unit can be designed and tested
by cascading 4 bit ALUs only the carry will propagate to the next level for ADD
operation
Test plan:
1. Set inputs 0101 and 0011 and check output for all possible select input combinations.
2. Set any two 16-bit number and check output for all possible select input
combinations.
Use Display units for checking output. Try to use minimum number of components to build.
The pin configuration of the canned components is shown when mouse hovered over a
component.
Assignment Statements:
1. Design a 4 bit ALU comprising only the AND, OR, XOR and Add operations.
2. Design a 16-bit ALU with capabilities similar to 74181
8.Combinational Multiplier
Aim: To construct a 4x4 combinational multiplier from an array of AND gates, half-adders
and full-adders.
Components: To build a Combinational Multiplier, we need
1.
2.
3.
4.
5.
Objective: Examining behaviour of combinational multiplier for the working module and
module designed by the student as part of the experiment
1. understanding behaviour of combinational multiplier from module designed by the
student as part of the experiment
2. understanding the scheme implemented for the multiplication which is as follows
(along with the logic diagram bellow):
o it can be designed by unrolling the multiplier loop
o instead of handling the carry out of partial product summation bit, the carry
out can be sent to the next bit of the next step
o this scheme of handling the carry is called carry save addition
Combinational Multipliers do multiplication of two unsigned binary numbers. Each bit of the
multiplier is multiplied against the multiplicand, the product is aligned according to the
position of the bit within the multiplier, and the resulting products are then summed to form
the final result. Main advantage of binary multiplication is that the generation of intermediate
products are simple: if the multiplier bit is a 1, the product is an appropriately shifted copy of
the multiplicand; if the multiplier bit is a 0, the product is simply 0.The design of a
combinational multiplier to multiply two 4-bit binary number is illustrated below
If two n-bit numbers are multiplied then the output will be less than or equals to 2n bits.
Logic diagram:
Loading data in the combinational multiplier, load the two input numbers as:
o
o
Test plan:
1. Set one input to zero (0) and check the output.
2. Set one input to one (1) and check the output.
Assignment Statements:
1. Create a combinational multiplier circuit to multiply two 4-bit binary numbers. Use
half adders, full adders and logic gates and test it by giving proper input.
Observations and Result: