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Friday,November14,2014

GATEPreviousQuestionsonAsynchronous&
SynchronousCounterswithSolutions(19872014)

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1987
1.AripplecounterusingnegativeedgetriggeredDflipflopsisshownbelow.Theflip
flopsareclearedto0attheRinput.Thefeedbacklogicistobedesignedtoobtainthe
countsequenceshowninthesamefigure.Thecorrectfeedbacklogicis:

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Bethefirstofyourfriendstolikethis

Solution:https://www.youtube.com/watch?v=qljzFR3B6TM

1990
Adsense

1.A4bitmodulo16ripplecounterusesJKflipflops.Ifthepropagationdelayofeach
flipflopis50nsec,themaximumclockfrequencythatcanbeusedisequalto
a.20MHz
b.10MHz
c.5MHz
d.4MHz
Solution:https://www.youtube.com/watch?v=v4RIzGm0DGY

1993
GATE paper
google.com/+GATEpaperIn
Solutions to GATE Previous Papers &
Conceptual GATE Video Lectures

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1.Apulsetrainwithafrequencyof1MHziscountedusingamodulo1024ripplecounter
builtwithJKflipflops.Forproperoperationofthecounter,themaximumpermissible
propagationdelayperflipflopstageis____nsec.
Solution:https://www.youtube.com/watch?v=VXYFD01hQDU

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BlogArchive

2015(34)

2.Aclockedsequentialcircuithasthreestates,A,BandCandoneinputX.Aslongas
theinputXis0,thecircuitalternatesbetweenthestatesAandB.iftheinputXbecomes
1(eitherinstateAorinstateB),thecircuitgoestostateCandremainsinstateCaslong

2014(143)

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December(14)
November(12)
GATEAnalogCircuitsFiveMarkQuestionswith
Solu...
PreviousGATEQuestionsonAnalogtoDigital&
Dig...

asXcontinuestobe1.ThecircuitreturnstostateAiftheinputbecomes0onceagain
andfromthenonrepeatsitsbehavior.AssumethatthestateassignmentsareA=00,B=01
andC=10.
a.Drawthestatediagramofthecircuit.
b.Givethestatetableofthecircuit.
c.DrawthecircuitusingDflipflops.

PreviousGATEQuestionsonMicroprocessors
andMem...

Solution:https://www.youtube.com/watch?v=uEwqg5Ho7Vo

GATEPreviousQuestionsonMemories(ROM,
PLAandP...
GATEPreviousQuestionsonAsynchronous&
Synchron...

1994

GATEPreviousQuestionsonLatches&Flip
Flops...

1.Synchronouscountersare________thantheripplecounters.
Solution:https://www.youtube.com/watch?v=1qBwgRPMMU8

PreviousGATEQuestionsonICLogicFamilies
with...
PreviousGATEQuestionsonMultiplexers
(MUX)with...
PreviousGATEQuestionsonCombinational
Circuits...

2.Aringoscillatorconsistingof5invertersisrunningatafrequencyof1MHz.the
propagationdelaypereachgateis________nsec.

PreviousGATEQuestionsonKMap,SOPand
POSexpr...

Solution:https://www.youtube.com/watch?v=aAm0ZPJhAM

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toTi...
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Subtra...
October(20)
September(7)

1996
1.Astatemachineisrequiredtocyclethroughthefollowingsequenceofstates:
ABC:000>010>111>100>011>101.

August(8)
July(5)
June(6)
May(20)
April(27)
March(24)

Onepossibleimplementationofthestatemachineisshowninfigure.Specifywhatsignals
shouldbeappliedtoeachofthemultiplexerinputs.
Solution:https://www.youtube.com/watch?v=fNIP5XoARP0

1997
1.Asequencegeneratorisshowninfigure.Thecounterstatus(Q0Q1Q2)isinitializedto
010usingpreset/clearinputs.

Theclockhasaperiodof50nsandtransitionstakeplaceattherisingclockedge.
a.GivethesequencegeneratesatQ0tillrepeats.
b.Whatistherepetitionrateofthegeneratedsequence?
Solution:https://www.youtube.com/watch?v=iOk6PXkY8

1998
1.ThefigureisshowsamodKcounter,hereKisequalto
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a.1
b.2
c.3
d.4
Solution:https://www.youtube.com/watch?v=M521kKIu3U
2.Themod5counterisshowninthefigurecountsthroughstatesQ2Q1Q0=000,001,
010,011and100.

a.Willthecounterlockoutifithappentobeinanyoneoftheunusedstates?
b.Findthemaximumrateatwhichthecounterwilloperatesatisfactorily.Assume
thepropagationdelaysofflipflopandANDgatetobetFFandtArespectively.
Solution:https://www.youtube.com/watch?v=We99dI2DCJw

1999
1.Theripplecountershowninthegivenfigureisworksasa

a.Mod3upcounter
b.Mod5upcounter
c.Mod3downcounter
d.Mod5downcounter
Solution:https://www.youtube.com/watch?v=JYOaavMXJzE
2.Thecircuitdiagramofasynchronouscounterisshowninthegivenfigure.Determine
thesequenceofstatesofthecounterassumingthattheinitialstateis000.Giveyour
answerinatabularformshowingthepresentstateQA,QB,QC,JKinputs(JA,KA,JB,KB,
JC,KC)andthenextstateQA+ ,QB+ ,QC+ .Fromthetable,determinethemodulusofthe
counter.

Solution:https://www.youtube.com/watch?v=wnKE1bQlfhg

2000
1.Inthegivenfigure,theJandKinputsofallthefourflipflopsaremadehigh.The
frequencyofthesignalatoutputYis

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a.0.833KHz
b.1.0KHz
c.0.91KHz
d.0.77KHz

Solution:https://www.youtube.com/watch?v=ed2xKY4lc2c

2001
1.Fortheringoscillatorshownintehfigure,thepropagationdelayofeachinverteris100
picosec.Whatisthefundamentalfrequencyoftheoscillatoroutput?

a.10MHz
b.100MHz
c.1GHz
d.2GHz
Solution:https://www.youtube.com/watch?v=HefE3DzUfOo
2.Thedigitalblockinthefigure,realizedusingtwopositiveedgetriggeredDflipflops.
Assumethatfort<t0,Q1=Q2=0.Thecircuitinthedigitalblockisgivenby

Solution:https://www.youtube.com/watch?v=gkkCKeFhQs

2002
1.Itisrequiredtodesignabinarymod5synchronouscounterusingABflipflop,such
thattheoutputQ2Q1Q0changesas000>001>010.....andsoon.Thetruthtableforthe
ABflipflopisgiveninfigure.

a.Writedownthestatetableforthemod5counter
b.ObtainsimplifiedSOPexpressionsfortheinputsA2,B2,A1,B1,A0andB0in
termsofQ2,Q1,Q0andtheircomplements.
c.Hencecompletethecircuitdiagramforthemod5countergiveninthefigure
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usingminimumnumberof2inputNANDgateonly.
Solution:https://www.youtube.com/watch?v=2HJzJKC38Y

2003
1.A0to6counterconsistsof3flipflopsandacombinationcircuitof2inputgate(s).The
combinationcircuitconsistsof
a.oneANDgate
b.oneORgate
c.oneANDgateandoneORgate
d.twoANDgates
Solution:https://www.youtube.com/watch?v=eQA5gMcQSuw
2.A4bitripplecounteranda4bitsynchronouscounteraremadeusingflipflopshaving
apropagationdelayof10nseach.Iftheworstcasedelayintheripplecounterandthe
synchronouscounterbeRandSrespectively,then
a.R=10ns,S=40ns
b.R=40ns,S=10ns
c.R=10ns,S=30ns
d.R=30ns,S=10ns
Solution:https://www.youtube.com/watch?v=cAStF7mPky8

2004
1.Inthemodulo6ripplecountershowninthegivenfigure,theoutputofthe2inputgate
isusedtocleartheJKflipflops.

The2inputgateis
a.NANDgate
b.NORgate
c.ORgate
d.ANDgate
Solution:https://www.youtube.com/watch?v=2b1wBH220Oo

2005
1.Thegivenfigureshowsaripplecounterusingpositiveedgetriggeredflipflops.Ifthe
presentstateofthecounterisQ2Q1Q0=011,thenitsnextstateQ2Q1Q0willbe

a.010
b.100
c.111
d.101
Solution:https://www.youtube.com/watch?v=iZWdwF2lfmw

2006
1.TwoDflipflopsaretobeconnectedasasynchronouscounterasshownbelow,that
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goesthroughthefollowingQ1Q0sequence00>01>11>10>00>..
TheinputsD0andD1respectivelyshouldbeconnectedas

Solution:https://www.youtube.com/watch?v=u3fgelNywPs

2007
1.Forthecircuitshown,thecounterstate(Q1Q0)followsthesequence

a.00,01,10,11,00..
b.00,01,10,00,01..
c.00,01,11,00,01..
d.00,10,11,00,10..
Solution:https://www.youtube.com/watch?v=aLGSUebXUW4

2008
1.ForeachofthepositiveedgetriggeredJKflipflopusedinthefollowingfigure,the
propagationdelayisT.

WhichofthefollowingwaveformscorrectlyrepresentstheoutputatQ1?

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Solution:https://www.youtube.com/watch?v=N7ZYplccPcA

2009
1.Whatarethecountingstages(Q1,Q2)forthecountershowninthefigurebelow?

a.11,10,00,11,10.
b.01,10,11,00,01.
c.00,11,01,10,00..
d.01,10,00,01,10..
Solution:https://www.youtube.com/watch?v=marTcMTzg0Y

2010
1.Assumingthatallflipflopsareinresetconditioninitially,thecountsequenceobserved
atQAinthecircuitshownis

a.0010111.
b.0001011.
c.0101111.
d.0110100.
Solution:https://www.youtube.com/watch?v=UsicxIAMqx0

2011
1.WhentheoutputYinthecircuitbelowis1,itimpliesthatdatahas

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a.Changedfrom0to1
b.Changedfrom1to0
c.Changedineitherdirection
d.Notchanged
Solution:https://www.youtube.com/watch?v=amudsVzHy88
2.Theoutputofa3stageJohnson(twistedring)counterisfedtoadigitaltoanalog(D/A)
converterasshowninthefigurebelow.Assumeallstatesofthecountertobeunset
initially.ThewaveformwhichrepresentstheD/AconverteroutputVois

Solution:https://www.youtube.com/watch?v=g9vVeVizDIM
3.TwoDflipflopsareconnectedasasynchronouscounterthatgoesthroughthe
followingQBQAsequence00>11>01>10>00>.Theconnectionsofthe
inputsDAandDBare

Solution:https://www.youtube.com/watch?v=_9k8tNpWn7w

2012
1.Thestatetransitiondiagramforthelogiccircuitshownis

Solution:https://www.youtube.com/watch?v=S2ytlAcBkFk
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2014
1.FiveJKflipflopsarecascadedtoformthecircuitshowninfigure.Clockpulsesata
frequencyof1MHzareappliedasshown.Thefrequency(inKHz)ofthewaveformatQ3
is

Solution:https://www.youtube.com/watch?v=ID70DQCpDCg
2.ThedigitallogicshowninthefiguresatisfiesthegivenstatediagramwhenQ1is
connectedtoinputAoftheXORgate.SupposetheXORgateisreplacedbytheXNOR
gate.Whichoneofthefollowingoptionspreservesthestatediagram?

Solution:https://www.youtube.com/watch?v=tBqtKpt1oSE
3.Inthecircuitshown,choosethecorrecttimingdiagramoftheoutput(y)fromthegiven
waveformsW1,W2,W3andW4.

a.W1
b.W2
c.W3
d.W4

Solution:https://www.youtube.com/watch?v=E3XeZjGgzqY

4.TheoutputsofthetwoflipflopsQ1,Q2inthefigureshownareinitializedto0,0.The
sequencegeneratedatQ1uponapplicationofclocksignalis

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a.01110.
b.01010..
c.00110.
d.01100..
Solution:https://www.youtube.com/watch?v=wNoctGWwcfs
5.Thecircuitshowninthefigureisa

a.Toggleflipflop
b.JKflipflop
c.SRLatch
d.MasterSlaveDflipflop
Solution:https://www.youtube.com/watch?v=AvKzOVpre_k

PostedbyGATEpaperat15:32

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Labels:Counters,GATEQuestions

3 comments

Add a comment as Dhruv Chauhan

Top comments

Sindhu Gaddam 3 months ago - Shared publicly

max
error=quantised error + cummulative error
quantised error= full scale voltage/2^number of bits
=2.55/2^8 =10mv(approx)
now max error= 10mv+2.55mv =12.55mv
+2
3

1 Reply

shubhranshu kumar 2 days ago

thanks but sorry

Monika Kunwal 5 months ago - Shared publicly

can you u please solve this question
Sir,
An 8-bit ADC has full scale of 2.55volt. If other cumulative error has 2.55 mV.
determine maximum error.
(a)10m V (b) 12.55mV (c) 7.45 mV (d) 2.55 mV
+4
5

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