Week 7 Chapter 3

FET Small Signal Analysis

 Objective

forAble to discuss and analyze the ac analysis √

various MOSFET configuration using the FET ac
equivalent circuit

Able to relate the dc analysis and ac analysis for √

FET and MOSFET configuration or
network system
 Introduction
FETs provide
• excellent voltage gain

• high input impedance

• low-power consumption

• good frequency range

• small in size and weight

 Introduction

Transconductance

The relationship of VGS (input) to ID (output) is called

.transconductance

The transconductance is denoted gm. Unit is siemens (S)

ID
gm 
VGS
 Introduction
Graphical determination of gm
 Introduction
ID
gm 
ΔVGS
2IDSS  VGS 
gm  1
VP  VP 

Using differential calculus

Maximum gm at VGS =0V: 2IDSS  VGS 

gm0  gm  gm0 1
VP 
 VP 

Effect of ID on gm for
VGS ID VGS ID
1  gm  gm0(1 )  gm0
VP IDSS VP IDSS

Mathematical Definition of gm
 Introduction
FET Impedance
:Input Impedance Zi Zi  
1
:Output Impedance Zo Zo  rd 
Yos

VDS
rd 
ID VGS  constant

Yos: admittance equivalent circuit parameter listed

.on FET specification sheets
.Yos: admittance equivalent circuit parameter listed on FET specification sheet
 Introduction

FET AC Equivalent Circuit

 Introduction

To do the AC analysis, remember these 4 STEPs:

1) Set all the DC sources to zero and replace

them by a short circuit equivalent.
2) Replace all capacitors by a short circuit
equivalent
3) Remove all elements bypassed by the short
circuit equivalents as introduced by Step 1
and Step 2
4) Redraw the network in a more convenient
and logical form.
 JFET CS Fixed-Bias

.The input is on the gate and the output is on the drain

JFET Common-Source (CS) Fixed-Bias
 JFET CS Fixed-Bias

JFET Common-Source (CS) Fixed-Bias

 JFET CS Fixed-Bias

AC Equivalent Circuit
 JFET CS Fixed-Bias
Impedances

Zi  RG Zo  RD || rd Zo  RD rd  10RD
 JFET CS Fixed-Bias

Voltage Gain
Vo
Av   gmRD
Vi rd  10RD

Vo
Av   gm(rd || RD)
Vi
 JFET CS Fixed-Bias
Phase Relationship
A CS amplifier configuration has a 180-
.degree phase shift between input and output
 JFET Fixed-Bias
Example:
Fixed-bias configuration has an operating point defined by VGSQ = -2V and IDQ =
5.625 mA, with IDSS = 10mA and VP = -8V. The value of yos is provided as 40 µS.
Determine:
a) gm
b) Zi
c) Zo
d) AV
e) AV ignoring the effects
of rd
 JFET Fixed-Bias
Solution:
JFET CS Self-Bias

Bypass
capacitor
JFET CS Self-Bias
JFET CS Self-Bias
 JFET CS Self-Bias

Input Impedance: Zi  RG
Output Impedance:
Zo  rd || RD Zo  RD
rd  10RD
 JFET CS Self-Bias

Voltage Gain

Av  gm(rd || RD)

Av  gmRD
rd 10RD

A CS amplifier configuration has a 180-degree phase shift between input and

output.
 JFET CS Self-Bias
Unbypassed C

If Cs is removed, it affects the gain of the circuit.

JFET CS Self-Bias
Unbypassed C
AC Equivalent Circuit
 JFET CS Self-Bias
Unbypassed C
Input Impedance:

Output Impedance:
JFET CS Self-Bias
Unbypassed C
JFET CS Self-Bias
Unbypassed C
JFET CS Self-Bias
Unbypassed C
Voltage Gain
Example
Solution
Solution
JFET CS Voltage Divider
JFET CS Voltage Divider

AC Equivalent Circuit
 JFET CS Voltage Divider
Impedance

Input Impedance: Zi  R1 || R2 Output Impedance:

Zo  rd || RD
Zo  RD
rd  10RD
JFET CS Voltage Divider

Voltage Gain

Av  gm(rd || RD)

Av  gmRD
rd 10RD
 JFET CS Voltage Divider

EXAMPLE:
If Vi =20mV,determine:
(i) Zi
(ii) Zo
(iii)Vo
with CS and without CS.
 Depletion-Type MOSFETs

1. D-MOSFETs have similar AC equivalent models.

2. D-MOSFETs has the same equation for gm as like

JFET.

3. The only difference is that VGS can be positive for n-

channel devices and negative for p-channel devices.

4. This means that gm can be greater than gm0.

 Depletion-type MOSFET in Depletion Mode

Depletion mode
The characteristics are similar to the JFET.
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS VGS 2
ID  IDSS(1  )
The formula used to plot the Transfer Curve still applies: VP
D-MOSFET AC Equivalent Model
 D-MOSFET AC Equivalent Model

Example: Given VGSQ =0.35V and IDQ = 7.6mA, analyze the network given
and calculate:
a. gm
b. rd
c. Zi
d. Zo
e. Av
 D-MOSFET AC Equivalent Model

Solution:
2IDSS 2(6m)
gm0    4mS
VP 3
 VGS   0.35 
gm  gm0 1    4mS1    4.47mS
 VP   -3 
1 1
rd    100kohm
Yos 10uS
Zi  R1 // R 2  10M // 110 M  9.17Mohm

Zo  rd // RD  100k // 1.8k  1.77kohm

since rd  10RD therefore

AV  gmRD  8.05
 Enhancement-Type MOSFETs

There are two types of E-MOSFETs:

nMOS or n-channel MOSFETs

pMOS or p-channel MOSFETs
 E-MOSFET AC Equivalent Model

Forward transfer admittance

gm and rd can be found in the specification sheet for the FET.

E-MOSFET CS Drain-Feedback Configuration
AC Equivalent Circuit
 Impedances

Input Impedance: RF  rd || RD Output Impedance:

Zi 
1 gm(rd || RD)

RF
Zo  RF || rd || RD
Zi 
1 gmRD RF  rd || RD, rd 10RD
Zo  RD
RF  rd || RD, rd 10RD
 Voltage Gain

Av  gm(RF || rd || RD)

Av  gmRD
RF  rd || RD, rd 10RD
 Phase Relationship

This is a CS amplifier configuration therefore it has 180-degree phase shift between input
and output.
E-MOSFET CS Voltage-Divider Configuration
E-MOSFET CS Voltage-Divider Configuration

AC Equivalent Circuit
 E-MOSFET CS Voltage-Divider Configuration

Impedances

Input Impedance:
Zi  R1 || R2

Zo  rd || RD
Output Impedance:

Zo  RD
rd  10RD
E-MOSFET CS Voltage-Divider Configuration

Voltage Gain

Av  gm(rd || RD)

Av  gmRD
rd 10RD
Summary Table
Summary Table
 Design FET Amplifier Networks

Example: Design the fixed bias network shown in the figure with AC gain
equals to 10.
a. Determine value of RD
 Design FET Amplifier Networks

Solution:
2IDSS 2(10m)
gm0    5mS
VP 4
 VGS   0
gm  gm0 1    5mS1    5mS
 VP   - 3
1 1
rd    50kohm
Yos 20uS
AV  gm (rd // RD)  10
(rd // RD)  10 /  5mS  2kohm
Zo  rd // RD  2kohm
rdRD / rd  RD  2k
50k (RD) / 50k  RD  2k
therefore RD  2.08kohm
 Effect of RL and Rsig

1. Effect of source resistance and load resistance on the

AC gain

2. Analysis using AC model or two port equations.

3. The two-port equations for FET are exactly same as

BJT because quantities of interest are at the input and
output terminals (not the components).

4. The loaded gain is always less than the no-load gain.

5. AVNL > AV
 Effect of RL and Rsig

TWO-PORT SYSTEM

 RL 
AV    AVNL
 RL  RO 
AVNL is no load voltage gain
 Effect of RL and Rsig

Rsig RL

 VO 
AV     gm (rd // RD // RL )
 Vi 
 Effect of RL and Rsig
Using two-port approach:

Overall again for two - port system

 RL   RL 
AV    AVNL     gm (rd // RD)
 RL  RO   RL  RO 
but RO  rd // RD
therefore
 RL 
AV     gm (rd // RD)
 RL  RO 
 RL 
   gm (rd // RD)
 RL  (rd // RD) 
 gm (rd // RD // RL)
 Cascade Configuration

Voltage gain, AV  AV1AV2

Cascade Configuration

Impedances

Zi  Rg1

Zo  RD2
 Practical Applications

• Three-Channel Audio Mixer

• Silent Switching

• Phase Shift Networks

• Motion Detection System