Transistor Bias

Circuits
Nsilo Greene
FRANK KING

[Document subtitle]

Abstract
In this lab, there will be an analysis of the
bipolar junction transistor. All transistors follow
the same theory but they dont all perform the
same. Based on the understanding of how the
transistor works, the analysis will help to
understand the differences of how this transistor
performs when the voltage varies compared to
others and how they all are similar, and what
are the advantages.
Introduction
This lab requires the engineer to investigate
three common bias circuits. The circuits are:
(1) base bias and a form of base bias called
emitter-feedback bias. (2) voltage-divider bias,
and (3) collector-feedback bias. The engineer
will test each of the three transistors, one at a
time, in various bias circuits, starting with fixed
base bias. These basic bias circuits are
described in the text for npn transistors, which
are used here.
Procedures
Components Needed
Part 1: Three Bias Circuits
Resistors (one of each): 680, 1.5k, 2.0k,
6.8k, 33k, 360k, 1.0M.
Three small signal 2N3904 npn transistor (or
equivalent)
Part 1: Three Bias Circuits
1. Measure and record the resistance of the resistors
listed in Table 5-1.
2. Fixed base bias will be investigated first, but it is
the most sensitive to differences in DC. Transistors
of the same type can have widely different values of
DC, which generally restricts the fixed base bias to
more specialized applications such as switching
circuits such as used in the last experiment. In step
four, the fixed bias has to be modified with an

emitter resistor. This will add stability to this type

of circuit. (RE is not used in the first circuit.)
The manufacturers specification sheet for the
2N3904 shows DC can range from 100 to 300, a
factor of 3, which implies that the collector current
can also vary by a factor of 3 with the base bias!
Assuming the DC for a 2N3904 is in the middle of
its specified range (200), compute the parameters
listed in Table 5-2 for the fixed base bias circuit
shown in Figure 5-1. Start by computing the
voltage across the resistor, VRB, and the current in
this resistor, IB. Using DC, find the collector current,
Ic, the voltage across the collector resistor, VRC, and
the voltage from collector to ground, VC.
3. Label each of three npn transistors as Q1, Q2,
and Q3 in a manner that allows you to keep track of
each transistor. Construct the circuit shown in
Figure 5-1 using Q1. Measure the voltages listed in
Table 5-2 for Q1. Then remove Q1 from the circuit
and test the other two transistors in the same circuit.
Record the data in Table 5-2.
Emitter-Feedback Bias
4. Emitter-feedback bias is a form of base bias but
with increased stability due to the addition of an
emitter resistor. Add the emitter resistor to the base
bias circuit in Figure 5-2 and enter the calculations
in the table. Use the method described in the text.
Use DC as 200 for the calculated value.
5. Construct the circuit and measure the parameters
in Table 5-3 for each of the three transistors tested
before.
Voltage-Divider Bias
6. Although the emitter-stabilized base bias you
tested in step 5 has better stability than fixed base
bias, you may have noticed that parameters still
vary between transistors. A more stable form of
bias is voltage-divider bias, which you will test next
using the same three transistors. The circuit meets
the condition that RE.10R2, so the approximate
analysis method, given in Section 5-2 of the text,
can be used.
Measure and record the values of the resistors listed
in Table 5-4.
7. Compute the parameters listed I Table 5-5 for the
circuit shown in Figure 5-3 using the approximate
method for all calculations.

8. Substitute the same three resistors into the

voltage-divider circuit and measure the parameters
listed in Table 5-5. Record your data in the table.

Table 5-2

Collector-Feedback Bias
9. Measure and record the values of the resistors
listed in Table 5-6.
10. Compute the parameters listed in Table 5-7 for
the circuit shown in Figure 5-4. The equations for
collector-feedback bias are developed in the text on
page 235.
Notice there is no emitter resistor. For this case, the
collector current is found from Equation 5-11.
Assume DC is 200 for the calculation. Calculate the
voltage across the collector resistor, VRC, and the
collector voltage, Vc based on this assumption.
11. Construct the circuit shown in Figure 5-4 using
transistor Q1. Measure the voltages listed in Table
5-7 for Q1. Then remove Q1 from the circuit and
test the other two transistors in the same circuit.
Record all measurements in Table 5-7.
Results
Resistor
RB
RC
RE
Table 5-1

DC
Paramete
r
VRB
IB
IC
VRC
VC

Listed Value
1.0 M
2.0k
1.5k

Compute
d
Value
11.3V
10.98A
2.2mA
4.4V
7.6V

Figure 5-1
DC
Paramete
r
VRB
IB
IC
VRC
VC
Table 5-3

Compute
d
Value
8.75V
8.75A
1.75mA
3.5V
8.5V

Q1

Q2

Q3

8.6

8.5

8.5

3.3
8.7

3.3
8.6

3.3
8.6

Measured
Value
1.029M
1.9519k
1.5k

Q1

Q2

Q3

11.3

11.3

11.3

Figure 5-2

4.3
7.7

4.4
7.6

4.4
7.6

Resistor
R1
R2
RE
RC
Table 5-4

Listed Value
33k
6.8k
680
2.0k

Measured
Value
32.5k
6.66k
672
1.9519k

Figure 5-3
DC
Paramete
r
VB
VE
IEIC
VRC
VC
Table 5-5

Figure 5-4
Compute
d
Value
2.04V
1.284V
1.91mA
3.82V
8.176V

Q1

Discussion
The circuit with all four resistors showed the least
variation among the transistors observed in the
experiment.

1.98
1.3

1.98
1.32

3.8
8.2

3.8
8.18

3.8
8.18

Listed Value

RB
RC
Table 5-6

360k
2.0k
Compute
d
Value
3.13mA
6.26V
5.74V

Q3

1.99
1.3

Resistor

DC
Paramete
r
IC
VRC
VC
Table 5-7

Q2

Measured
Value
322k
1.9519k

Q1

Q2

Q3

6.18
5.7

6.2
5.7

6.28
5.73

Adding the emitter resistor to a circuit the bias

stability is improve, because it creates a resists just
before the ground putting a voltage on the emitter
increasing the transistor bias stability.

Conclusion
As the results show there are variations in the
of the three transistors in this experiment. The
variations are very small in nature compared
what is seen in the field, but they are there and
most be accounted for to get the best
performance out of the transistor and the
circuit.

References
D. Buchla and S. Wetterling, Laboratory Exercises
For Electronic Devices, Upper Saddle River, NJ:
Prentice Hall.