MOTOROLA m™ SEMICONDUCTOR — —EEEEyyEEEEE TECHNICAL DATA MC68010 Technical Summary Rl 16-/32-Bit Virtual Memory Microprocessor This document contains an MC68010 summary and a detailed set of para- metrics. For detailed information on the MC68010, refer to the M68000UM/AD, M6800 8-'16-32-Bit Microprocessor User's Manual. The MC68010 is a member of the M68000 Family of advanced microprocessors. Utilizing VLSI technology, the MC6B010 is a fully implemented 16-bit micro- processor with 32-bit registers, a rich basic instruction set, and versatile ad- dressing modes. The following resources are available to the MC68010 user: © 17 32-Bit Data and Address Registers 16-Mbyte Direct Addressing Range Virtual Memory/Machine Support 57 Powerful Instruction Types High-Performance Looping Instructions Operations on Five Main Data Types Memory-Mapped 1/0 14 Addressing Modes “This document contains information on nw prod, Speciiestions and normation herein are subject ochange without note 3-136 ‘68000 FAMILY REFERENCE MANUAL MOTOROLAINTRODUCTION The MC68010 is fully user object-code compatible with the earlier members of the M68000 Family and has added features of virtual memory support and enhanced instruction execution timing. The MC68010 is pin-for-pin compatible with the MC68000. The MC68010 possesses an asynchronous bus structure with a 24-bit address bus and a 16-bit data bus. As shown in the user and supervisor programming models (see Figures 1 and 2), the MC68010 offers 17, 32-bit, general-purpose registers, a 32-bit program counter, a 16-bit status register, a 32-bit vector base register, and two 3-bit alternate function code registers. The first eight registers (D0-D7) are used as data registers for byte (8-bit), word (16-bit), and long-word (32-bit) operations. The second set of seven registers (A0-A6) and the stack pointers (SSP and USP) may be used as software stack pointers and base address registers. In addition, the address registers may be used for word and long-word operations. All 17 registers may be used as index registers. MOTOROLA M6800 FAMILY REFERENCE MANUAL 3.4370 C i o 2 i | para is i oe REGISTERS CL H bs L : ne C i co i 6 5 ° 0 L : a3 r i 7 poppe ie FESBTERS M r Ts a6 sen stack, L PONTER Pt PRocnaw counie ‘conoIMoN CoO Reosren Figure 1. User Programming Mode! at 1615 surepuson >. or STACKPONTER er 1s a7 ° srarus REOSTER onset vecToR ease ROSTER dS ALTERWATE FuNctION tebe CODE REGISTERS re Figure 2. Supervisor Programming Model Supplement 3-138 68000 FAMILY REFERENCE MANUAL MOTOROLAThe status register (SR) (see Figure 3) contains the interrupt mask (eight levels available) as well as the condition codes: extend (X), negative (N}, zero (Z), overflow (V), and carry (C). Additional status bits indicate that the processor is in a trace (T) mode and in a supervisor (S) or user state. SYSTEM BYTE User ave TRACE MODE SUPERS SME inreraer Mask | ere — a — ecanie ——— SF eA ———————______] °°) ovearuow — canny — — | Figure 3. Status Register The vector base register (VBR) is used to determine the location of the exception vector table in memory to support multiple vector tables. The alternate function code registers allow the supervisor to access user data space or emulate CPU space cycles. DATA TYPES AND ADDRESSING MODES Five basic data types are supported 1, Bits 2. BCD Digits (4 Bits) 3. Bytes (8 Bits) 4. Words (16 Bits) 5. Long Words (32 Bits) In addition, operations on other data types, such as memory addresses, status word data, etc., are provided in the instruction set. MOTOROLA M6800 FAMILY REFERENCE MANUAL 3139Most instructions can use any of the 14 addressing modes listed in Table 1. These addressing modes consist of six basic types: Register Direct Register Indirect Absolute Program Counter Relative Immediate 6. Implied Included in the register indirect addressing modes is the capability to perform postincrementing, predecrementing, offsetting, and indexing. The program counter relative mode can also be modified via indexing and offsetting, gaere Table 1. Addressing Modes Addressing Modes ‘Syntax Register Direct Addressing Data Register Direct Dn Address Register Direct, Jan [Absolute Data Addressing ‘Absolute Short oxW ‘Absolute Long pow Program Counter Relative Addressing Relative with Offset /dyg(PC) Relative with Index Offset Ldg(PC.Xn) Register Indirect Addressing Rogister indirect (ani Postincrement Register Indirect (an) + Predecrement Register Indirect ~1An) Rogister Indirect with Offset ig(Ant Indexed Register Indirect with Offset _| dgiAn, Xn) Immediate Data Addressing Immediate oo Quick Immediate #1168 Implied Addressing Implied Register SRIUSPISPIPC NOTES: Dn = Data Register An = Address Register ‘Address of Data Register Used as Index Register Status Register PC = Program Counter ‘Stack Pointer User Stack Pointer Effective Address 8-Bit Offset (Displacement) 16:Bit Offset (Displacement) xx = Immediate Data s 3-140 M8000 FAMILY REFERENCE MANUAL MOTOROLAThe MC68010 instruction set is listed in Table 2. Some additional instructions that are variations or subsets of these instructions are listed in Table 3. Special emphasis is given to the instruction set’s support of structured high-level lan- guages to facilitate ease of programming. Each instruction, with few exceptions, Operates on bytes, words, and long words, and most instructions can use any Of the 14 addressing modes. By combining instruction types, data types, and addressing modes, over 1000 useful instructions are provided. These instruc- tions include signed and unsigned multiply and divide, quick arithmetic op- erations, BCD arithmetic, and expanded operations (through traps). Also, 33 instructions may be used in the loop mode with certain addressing modes and the DBce instruction to provide 230 high-performance string and block manip- INSTRUCTION SET OVERVIEW ulations and extended arithmetic operations. Table 2. Instruction Set Summary Wemonie Desripton Moomonie Tacos |Add Decimal with tena wove [Move moor [aga Mus — [Signe Mutiny ANd® — [ogc No MOL __|Ussones uly ASC farthmete Shit Le 5 eae see __|arthmets Sit igh NRC" ]Negere Desa with Exons tc Branch Condtonaliy NOP | No-Bperton 8cHG Beat ond change NOT ___ [Ones Comsioment sein fa est ana Cen : BRA Branch Always iL Logical OF. ser [vest and Sx PEA [Push Etec Adorn Bt [Branento Subroutine RESET |Reset Exteel Devices BIST. Bit Test ROL* Rotate Left without Extend CHK |Cnoee Reiser aganet Bounds | | RoR [Rola ant wanout Cece Gite [Ear operan ROxL: [Rowe tot wah Een cu |comare ROxR* ——[Rowte Right wih Extend Deez est ondion Devremanrand | [RID | Ret and Deaton ranch tir row ona Resore ovs ——_|signoybvise mand Reso Divu Unsigned Divide aa Satin omeube cORféscusive On gecor | subir Decimal wan Extend Exo [Exchange Reisters se, feats ext____| stanton stor ston oP faump Swae | Snap Data Rogier Halves een OC TAS: Test and Set Operand Ue Tloed Etectveadesa, Taap [op tink | soc TRaPV [Trap on Overiom iste [Logcat Shite ir Free tSe___[Loueas sunt rghe a *Loopaba havetons MOTOROLA 168000 FAMILY REFERENCE MANUAL aaTable 3. Variations of Instruction Types Instruction Tyee Variation Description ADD [AD Aad ADDY JAdd Address ADDO Add Quick ‘Ao! JAdd Immediate JADDX* Ada with Extend [AND ‘AND® Logical AND ANDI AND Immediate ANDI to CCR | AND Immediate to Condition Codes ANDIto SR__| AND immediate to Status Register CMP: cme [Compare cMPAt Compare Address /cmpm [Compare Memory coi [Compare immediate EOR EOR* Exclusive OR EORI Exclusive OR Immediate EORI to CCR Exclusive OR Immediate to Condition Codes. EOAIto SR___| Exclusive OR Immediate to Status Register MOVE MOVE [Move Source to Destination MOVEA* Move Address Movec /Move Contro Register MOVEM Move Multiple Registers Mover Move Peripheral Data Moved Move Quick Moves Move Alternate Address Space MOVE from SR |Move from Status Register MOVE to SR__|Move to Status Register MOVE from CCR| Move from Condition Codes MOVE to CCR |Move to Condition Codes Move USP _|Move User Stack Pointer NEG NEG? Negate NEGX" Negate with Extend lor OR Logical OR OR! ]OR immediate ORIto CCR —_ OR Immediate to Condition Codes ORI to SR, JOR immediate to Status Register sua SUB [Subtract SUBA* Subtract Address SUBI Subtract Immediate susa ‘Subtract Quick SUBK* ‘Subtract with Extend *Leopabie Instructions 3.142 : ‘Meg000 FAMILY REFERENCE MANUAL MOTOROLAVIRTUAL MEMORY/MACHINE CONCEPTS In most systems using the MC68010 as the central processor, only a fraction of the 16-Mbyte addressing space will actually contain physical memory. How- ever, by using virtual memory techniques, the system can be made to appear to the user to have 16-Mbytes of physical memory available. These techniques have been used for several years in large mainframe computers and more recently in minicomputers and now, with the MC68010, can be fully supported in microprocessor-based systems. In a virtual memory system, a user program can be written as though it has a large amount of memory available to it when only a small amount of memory is physically present in the system. In a similar fashion, a system can be de- signed which allows user programs to access other types of devices that are not physically present in the system. With proper software emulation, a physical system can be made to appear to a user program as any other computer system, and the program may be given full access to all resources of that emulated system. Such an emulated system is called a virtual machine. The MC68010 supports these modes through its instruction continuation mech- anism. When an address error or bus error is encountered, the MC68010 will Place its internal state on the supervisor stack. The appropriate exception han- dler is erased and, upon completion, causes the MC68010 to reload its internal state and resume execution. Loop mode takes advantage of the fact that the MC68010 can contain three elements of the instruction stream internally. When these elements are 1) a foopable instruction, 2) the DBcc instruction, and 3) a branch displacement to the loopable instruction, the MC68010 will enter the loop mode in which no instruction accesses are made; only data accesses are performed. This allows extremely fast data transfers as well as providing the bus access made by the MC68010. MOTOROLA M6800 FAMILY REFERENCE MANUAL 3.183SIGNAL DESCRIPTION The input and output signals are functionally grouped in Figure 4 and are described in the following paragraphs. me Ki 15.00 is PROCESSOR: tS” 4 ASYNCHRONOUS ve git beahe aay ke Figure 4, Functional Signal Groups ADDRESS BUS (A1-A23) This 23-bit, unidirectional, three-state bus is capable of addressing 16 Mbytes of data. It provides the address for bus operation during all cycles except CPU space cycles DATA BUS (D0-D15) This 16-bit, bidirectional, three-state bus is the general-purpose data path, It can transmit and accept data in either word or byte length. ASYNCHRONOUS BUS CONTROL ‘Asynchronous data transfers are handled using the following control signals: address strobe, read/write, upper and lower data strobes, and data transfer acknowledge. 3144 Mg8000 FAMILY REFERENCE MANUAL MOTOROLAAddress Strobe (AS) This signal indicates a valid address on the address bus. Read/Write (R/W) This signal defines the data bus transfer as a read or write cycle. RAW also works in conjunction with the data strobe as explained in the following para- graph. Upper and Lower Data Strobe (UDS, LDS) Ea These signals contro! the flow of data on the data bus, as listed in Table 4. When RiW is high, the processor will read from the data bus as indicated. When RIW is low, the processor will write to the data bus as shown in Table 4 Table 4. Data Strobe Control of Data Bus uos [tos [ aw | oe-pis, 0-07 + [i [= J te vatia bata_[ No Valid Data 0 | o [+ | Vali Data Bits | Vali Data Bits 8-15 o7 1 [0 [4 | Novatia Data | Valid Deta Bits o [1 [4 | Valid Date Bits [No Vaid Data 815 0 | 0 | 0 | Valid Date Bits | vali Data Bits 8-15 07 1 | 0 | 0 | Valid Bate sits | valid Data Bits 0-7 07 o | 1 [0 | valid Data its | Vata Data Bits 8-15 815% ‘These conditions are a result of eu ‘may not appear on future devices. nt implementation and Data Transfer Acknowledge (DTACK) This input indicates that the data transfer is complete. When the processor recognizes DTACK during a read cycle, data is latched and the bus cycle is terminated. When DTACK is recognized during a write cycle, the bus cycle is terminated. MOTOROLA M8000 FAMILY REFERENCE MANUAL 3145,BUS ARBITRATION CONTROL Bus request, bus grant, and bus grant acknowledge form a bus arbitration circuit to determine which device will be the bus master, Bus Request (BR) This input is wire-ORed with all other devices that could be bus masters. This input indicates to the processor that some other device desires to become the bus master. Bus Grant (BG) This output indicates to all other potential bus master devices that the processor will release bus control at the end of the current bus cycle. Bus Grant Acknowledge (BGACK) This input indicates that some other device has become the bus master. This signal should not be asserted until the following four conditions are met 1. A bus grant has been received. 2. Address strobe is ina using the bus. e, which indicates that the microprocessor is not 3. Data transfer acknowledge is inactive, which indicates that neither mem- ory nor peripherals are using the bus. 4, Bus grant acknowledge is inactive, which indicates that no other device is still claiming bus mastership. INTERRUPT CONTROL (IPLO, IPL1, IPL2) These pins indicate the encoded priority level of the device requesting an interrupt. Level 7 is the highest priority; level 0 indicates that no interrupts are requested, Level 7 cannot be masked. The least significant bit is IPLO and the most significant bit is IPL2. These lines must remain stable until the processor signals interrupt acknowledge (FCO-FC2 are all high, A16-A19 are all high) to ensure that the interrupt is recognized. 3146 68000 FAMILY REFERENCE MANUAL MOTOROLASYSTEM CONTROL The three system control inputs are used to reset or halt the processor and to indicate to the processor that bus errors have occurred, Bus Error (BERR) This input informs the processor that there is a problem with the cycle currently being executed. Problems may be a result of: 1. Nonresponding devices 2. Interrupt vector number acquisition failure 3. Illegal access request as determined by a memory management unit 4. Other application-dependent errors The bus error signal interacts with the halt signal to determine if the current bus cycle should be re-executed or if exception processing should be per- formed. Reset (RESET) This bidirectional signal resets (starts a system initialization sequence) the processor in response to an external reset signal. An internally generated reset {result of a RESET instruction) causes all external devices to be reset, and the internal state of the processor is not affected. A total system reset (processor and external devices) is the result of external HALT and RESET signals applied simultaneously. Halt (HALT) When this bidirectional signal is driven by an external device, it causes the processor to stop at the completion of the current bus cycle, When the processor is halted using this input, all control signals are inactive, and all three-state lines are put in their high-impedance state, When the processor stops executing instructions, such as in a double bus fault condition, the HALT line is driven by the processor to indicate to external devices that the processor has stopped. M6800 PERIPHERAL CONTROL ‘These control signals are used to interface synchronous M6800 peripheral de- vices with the asynchronous MC68010. MOTOROLA (68000 FAMILY REFERENCE MANUAL 3147Enable (E) This signal is the standard enable signal common to all M6800-type peripheral devices. The period for this output is 10 MC68010 clock periods (six clocks low, four clocks high). Enable is generated by an internal ring counter which may come up in any state (ie., at power-on, it is impossible to guarantee phase relationship of E to CLK). E is a free-running clock and runs regardless of the state of the bus on the MPU Valid Peripheral Address (VPA) This input indicates that the device addressed is an M68000 Family device and that data transfer should be synchronized with E. This input also indicates that the processor should use automatic vectoring for an interrupt. Valid Memory Address (VMA) This output is used to indicate to M6800 peripheral devices that a valid address exists on the address bus and the processor is synchronized to E. This signal only responds to a VPA input, which indicates that the peripheral is an M68000 Family device PROCESSOR STATUS (FCO, FC1, FC2) These function code outputs indicate the state (user or supervisor) and the address space of the bus cycle currently being executed (see Table 5). The information indicated by the function code outputs is valid whenever AS is active. Table 5. Function Code Outputs Fain tas cin Cle Bas As space ooo Weer *Aadress space 3's reserved for user definition; 0 and 4 are reserved for future use by Motorola, 3.148, 68000 FAMILY REFERENCE MANUAL MOTOROLACLOCK (CLK) The clock input is a TTL-compatible signal that is internally buffered for de- velopment of the internal clocks needed by the processor. The clock input should not be gated off at any time, and the clock signal must conform to minimum and maximum pulse-width times. Vcc and GND Power is supplied to the processor using these two signals. SIGNAL SUMMARY Table 6 is a summary of all the signals discussed in the previous paragraphs. Table 6. Signal Summary ReadWrite RW Output Read—High No Yes Interrupt Priority Level IPLO, IPLT, iPL2 Input Low = Bus Error BERR Input Low. = = Reset RESET Input/Output Low No* No*DATA TRANSFER OPERATIONS Transfer of data between devices involves the following leads: 1, Address bus A1-A23 2. Data bus DO-D15 3. Control signals The address and data buses are separate parallel buses used to transfer data using an asynchronous bus structure, In all cycles, the bus master assumes responsibility for deskewing all signals it issues at both the start and end of a cycle. In addition, the bus master is responsible for deskewing the acknowledge and data signals from the slave device. The following paragraphs explain the read, write, and read-modify-write cycles. The indivisible read-modify-write cycle is the method used by the MC68010 for interlocked multiprocessor communications. READ CYCLE During a read cycle, the processor receives data from the memory or a pe- ripheral device. The processor reads bytes of data in all cases. If the instruction specifies a word {or double word) operation, the processor reads both upper and lower bytes simultaneously by asserting both upper and lower data strobes. When the instruction specifies byte operation, the processor uses an internal A0 bit to determine which byte to read and then issues the data strobe required for that byte. For byte operations, when AO equals zero, the upper data strobe is issued. When AO equals one, the lower data strobe is issued. When the data is received, the processor correctly positions it internally. If DTACK, BERR, or VPA is not asserted for the required setup time before the falling edge of state 4, a wait cycle will be inserted in the bus cycle, and DTACK will be sampled again on the falling edge of each wait cycle. The MC68010 will continue to insert wait cycles until DTACK, BERR, or VPA is recognized, WRITE CYCLE During a write cycle, the processor sends data to either the memory or a peripheral device. The processor writes bytes of data in all cases. If the instruc- tion specifies a word operation, the processor writes both bytes. When the instruction specifies a byte operation, the processor uses an internal A0 bit to determine which byte to write and then issues the data strobe required for that byte. For byte operations, when AO equals zero, the upper data strobe is issued. When AO equals one, the lower data strobe is issued. If DTACK, BERR, or VPA is not asserted for the required setup time before the falling edge of state 4, a 3.150 M68000 FAMILY REFERENCE MANUAL MOTOROLAwait cycle will be inserted in the bus cycle, and DTACK will be sampled again on the falling edge of each wait cycle. The MC68010 will continue to insert wait cycles until DTACK, BERR, or VPA is recognized. READ-MODIFY-WRITE CYCLE The read-modify-write cycle performs a read, modifies the data in the arithmetic logic unit, and writes the data back to the same address. In the MC68010, this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses this cycle to provide meaningful communication between processors in a multiple processor environment. TAS is the only instruction that uses the read-modify-write cycles; since TAS only operates on bytes, all read-modify-write cycles are byte operations. CPU SPACE CYCLE During a CPU space cycle, the MC68010 reads a peripheral-device vector num- ber or indicates a breakpoint instruction. If the cycle is to read a vector number, itis referred to as an interrupt acknowledge cycle. A CPU space cycle is indicated when the function codes are all high. The address bus then defines what type Of CPU space cycle is being executed. The MC68010 defines two types of CPU space cycles, the interrupt acknowledge cycle and the breakpoint cycle. The interrupt acknowledge cycle on an M68000 Family compatible processor is defined as a CPU space cycle with the most significant address lines high; on the MC68010, this cycle means that A4-A23 will be high. The level of the interrupt being acknowledged is encoded on address lines A1-A3. An interrupt acknowledge cycle is terminated in the same manner as a normal read cycle. The processor expects a peripheral device to respond to an interrupt ac- knowledge cycle with a vector number that will be used to transfer control to an interrupt handler routine, The breakpoint read cycle is executed by the MC68010 in response to a break- point illegal instruction. A breakpoint cycle on the MC68010 is defined as a CPU space cycle with all of the address lines low. The processor does not accept or send any data during this cycle. The breakpoint cycle may be terminated by DTACK, BERR, or VPA. PROCESSING STATES The MC68010 is always in one of three processing states: normal, exception, or halted. MOTOROLA M8000 FAMILY REFERENCE MANUAL 3-181NORMAL PROCESSING The normal processing state is that associated with instruction execution; the memory references are to fetch instructions and operands and to store results. A special case of the normal state is the stopped state which the processor enters when a stop instruction is executed. In this state, no further references are made. EXCEPTION PROCESSING The exception processing state is associated with interrupts, trap instructions, tracing, and other exception conditions. The exception may be internally gen- erated by an instruction or by an unusual condition arising during the execution of an instruction, Externally, exception processing can be forced by an interrupt, a bus error, or a reset. Exception processing is designed to provide an efficient context switch so that the processor may handle unusual conditions. HALTED PROCESSING The halted processing state is an indication of catastrophic hardware failure. For example, if, during the exception processing of a bus error, another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor. Note that a processor in the stopped state is not in the halted state, nor vice versa. INTERFACE WITH M6800 PERIPHERALS Motorola's extensive line of M6800 peripherals are directly compatible with the MC68010. Some devices that are particularly useful are as follows: MC6821 Peripheral Interface Adapter MC6840__ Programmable Timer Module MC6843_ Floppy Disk Controlter MC6845_ CRT Controller MC6850 Asynchronous Communications Interface Adapter MC6854 Advanced Data Link Controller To interface the synchronous M6800 peripherals with the asynchronous MC68010, the processor modifies its bus cycle to meet the M6800 cycle re- quirements whenever an M6800 device address is detected. This modification is possible since both processors use memory-mapped 1/O. 3-182 ‘68000 FAMILY REFERENCE MANUAL MOTOROLAELECTRICAL SPECIFICATIONS MAXIMUM RATINGS ‘The devico contains circuitry Rating Symbol [Value | Unie | tomrowrt ne nuts aoanet Jamage due to high state Supply Voltage vec_|-o3r0 +70] v_| Cotages or elects hele sa Velage owever, normal preeau tnt Voiag Vin _{—03t0 +70] V_| ccreshouidtetatente ovoid Operating Temperature Range Ta | tuiota | -c | sppteaton otvatagesngher nacos0r0 Ga than maximumrated vol Mcé80100 Moines ages to these high imped ance cet: Tying unused Storage Temperature Tatg_[ =85t0 150 | -c_| inputs to the appropriate logic votoge lve! (ag, ether GND oF Voc) enhances rh ability of operatio THERMAL CHARACTERISTICS Characteristic ‘Symbol | Value | Symbol | Value | Rating Thermal Resistance (Stil Ain) | Oy We “cw Ceramie, Type LLC 30 18 Ceramic, Type RRC 33 5 Plastic, Type P 30 15 Plastic, Type FN 45 25 “Estimated POWER CONSIDERATIONS The average die-junction temperature Ty in °C can be obtained from: Ty=Ta+(Pp + ja) a) where: Ta =Ambient Temperature, °C 8Ja =Package Thermal Resistance, Junction-to-Ambient, °C/W Po =PInT+PVO PINT =Iccx Vcc, Watts — Chip Internal Power Po Power Dissipation on input and Output Pins — User Determined For most applications Pjq be > | Notes, 1. This ouput ting aplcble tal parameters speciied elave tothe sising edge ofthe Cock 2 Ths ouput tng is apaleabe [al paramore spected ilatve tothe tang edge ol be ace 28. This npit bing appbeable oa pramelers species eativo toe ting edge ol te clock 4: This inputting i appieabl eal parameters species reiative toe fling edge of Bo clock 5. Tis timing is appcabe fo all porametorsspecedrelave lo the aceervorinegatien ot ante sig LeceNo: ‘A Maximum output delay specifestin. 8, Minium output hod me, Minimum input sop tie specifeaton D. Miriam input hold time epefeaton. E Signal vabdw signal vad epecfeaton (maximum or minime). F Signal vabd io sgnal val specication (manor ort). Figure 6. Drive Levels and Test Points for AC Spe MOTOROLA M68000 FAMILY REFERENCE MANUAL 3157DC ELECTRICAL SPECIFICATIONS jvcc-s0 vec= 3%} GND = 0 Vdc; TA=TL to TH) ‘Characteietie ‘Symbot | Min | Max [Unit Input High Voltage vin [20 | voc | v Input Low Voltage vu [eno 03] 08 | v Input Leakage Current BERR, BGAGK, BA, DTAGK, CLK, IPLOMIPLD iN — [as faa e525 V =| Three State (OF State! Input Current rst — | a [ua ww 2av04V Output High VoRage loH= —400 uA Vou [Vcc 075 v ign 400 wal 2a_| 24 Ouipat Low Volage Vou v (lou = 1.6 ma) FACT os, igh =32 mal AAt-A2s, 8G, Feo-Fc2 = | os ligt 5.0 mal _ FESET| = | os gh 53 mal £, BS, 00-0165, (0S, RW, UDS, vMA =| os Power Dissipation [see POWER CONSIDERATIONS) Po! —|[w [Capacitance WVin=0 V. Ta= 26°C, Frequency —1 MHaI™ Cn — [aon [or Load Capacitance: Hacr] — | 0 [or All Others =| 30 With external pullup resistor of 11 2 Capacitance ig periodically sampled rather than 100% tested **-Durng normal operation, instantaneous Voc eurtent requirements may be as high as 1.5 A AC ELECTRICAL SPECIFICATIONS — CLOCK TIMING tse Figure 7) amme= | 1oMHe | 125 Mine Num. Characteristic Symbol Uni ier in cf <9 O> KO Om > <6 NOTE: Timing measurements ae reletenced to and trom a low volage of 0.8 V anda high votage of 20 V, unos ethomwise noted. The votage swing tough ths range should start outsdo ane pass trough he ra betwoun 08 Vand 20 v "ge such hat the ie rfl wa be nose Figure 7. Clock Input Timing Diagram 3-188 M8000 FAMILY REFERENCE MANUAL MOTOROLAAC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (ec =5.0 Vde= 8%; GND=0 Vdc; Ta=Ti to TH: see Figures 8 and 9} om Ccharactoriste Symbot -S Mr” | iet | 125 we | Unie ‘ain [Max | in [ Wat | Min | Mon © [Clack Low to Address Valid fara e[—| | —| | « 6A_[Ctock High to Fe Vat tcuecv w[—[m/-| «| os 7 Jee Woh to Adds, wt ue ah pean [cnaDe | — |» | ms [Goa High to Adcress, FE nvais minimum | eonani | 0 of-[ = 91 [Clock High to AS, DS Asvertoe wows | 2[ oo] s[ [| 3] ol 11? [Adaress Vali 1 AS, DS Assorted (Reaah AS wwe | @[—] | —| oe] —] = Assorted (Wrtel TA? [Fevaia io AS, DS Assered Reaa) AS Assented [cvs | 90 | — | 79 [ — | oo] — | om vir) 127 [crock Low wo AS, BS Negoted ‘cast e[-[]-| «| n 152 [AS, DS Negated to Address, FC val sua | af — | 0] — | wo 1 12 [FS land DS Read) With Asserec ‘s_| 20 v5 | — [ro [— [me 14a? [BS wrath Assert (write ‘ost_[ 700 | — [| — | os 187 [AS BS woth Negated ‘su | 50 ws} — [| —[ 16 _[elocs High wo Control Bus High impedence ccnez | — | oo 70 | — [eo] ms 172_[FS.05 negated to RW invais ‘sun | 0 [| | — [os 187 |Ctock High to AW High Read) ‘cnn | 0 of sf of «| os 201 _|Ciock High to AW Low (wri wom | of | of w[ of a] ve 0A °|AS Asserted to AW Vals Write) tase wf — [oo 10 | 212 [Adress Vali o AW Low (Wee) wn | {—| o[-] © a 21h [Fc Vals to Ra Low (write) ‘seve | 60 | — | 20 wo — |e 222_[RW Low 1 DS Assad Wii) ‘ust | of — | »] — | 2 7 25 [Cock Low to Dat-Out Vali Wine) ‘ei00 w|—[s[—-| al 257 _[FS, DS Nogated to Dat Out Invais Wr) ‘suoor] | — | | — | » ms 262 _[DatoOu Valid to DS Acsoted (Wri ‘woos. | »{—| »[—[o 2 [ostein Valid to Clock Low Sewp Time of Reed) | tice | wo] — | | —| | — | os 2708 [Late BERR Assored 0 Cook Low (Sewp Tine) | were | 45 «[—|«f—[o 26? [AS BS Negoted vo DTACK Negated soar] of aot 0] | of v0 | ne ‘Asynchronous Hod) 29 |S, DS Negated wo Datatn Inva Tsun} of -] ef -]| 0 7 Hold Time on Rea 29A_[FS. 05 Negoted to Data in High Impedance ‘sH0z war | — [| 150 0 | ve 30_[AS DS Negatod to BERR Nogated ‘suse | 0 2 o[—[ 312 © [BTACK Assorted to Data Vali Setup Time) | toauns | — | 90 @[—|s| 32_|RALT ana RESET Input Trnsivon Time swt | ©] 200[ 0 | oo [ 0 | 200] we 35_[Gieek High to 8G Assenea wou. | — | @]—[ o[— | of me 34_|Ctock High to 85 Negetea wcnon | — | | — | 50 a | mm 35 [BR Assorted to BG Assoned venue [18 [as [15 | 35 [v9 | a0 | cus 36? [BR negated to BG Negated voaucn| 15 | a8 | 15 | 35] vs | as | cis 37_[BGACK Assorted to BG Neate can] 15 | a5 | 1s | 25 | vs | 35 | ons MOTOROLA 68000 FAMILY REFERENCE MANUAL 3-189AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES (Continued) ‘amie | iomne | 125 Mine Num Characteristic. Symbol tae met ie eed Un {a7A® [BGAGK Assorted to BR Negated ficauan} 20 [15 | zo] as] a [as | ne chs cus chks 38 [8G Assorted to Control, Address, Data Bus Wigh | toiz wo] —| 7% 0 | ne Impedance (AS Negaied 29_[BG woeth Neaetea won| 15 15 15 | — | ce 20 _[elock Low to WA Assented ewe | — | 70 [ — | | — [m0 [ os. 41 [Cock Low 10 € Transition oer | — [|] el [| os 42_[E Oviput Rise and Fal Time tent 38 15 15 [ns 43 [FMA Ascortoa to E High twaes | 200 150 0 ne ‘44 _[RS. 05 Negated to VPA Negates tsuven| o| 2] of | of 7 | ns 45 [E Low 19 Control, Address Bus valid ‘evca | 20 10 10 ne (adress Hols Time} 45 [BGACK Wath Low toa [15s] —[os[— [os [— [om 17 [Asynchronous Input Setup Time tasi_| 10 | — [wo 10 na {482.15 [DTACK Assorted to BERR Assorted frome! — | of — | ss] — [as | ns 198 _[AS, 08, Negated 19 E Low sgner | 70 [ 70 [ss] ss [as] as [ne 0 [ewiatn Hah sen | 50 | — [350 | — | 200 [ — [ns te wath Low e_| m0 | — | s50 [ — [ao [— [os 52 _[Dats Out How rom Clock High ‘cuoo| 9 ° @ 8 4_[E Low to Data Out Invalid ‘evo [30 Fs ee 35_|RW Assorted to Data Bus Impadance Change | taupap | 30 20 0 ns 96° [ALT RESET Pulse Wicth wrew [10 [| — [0 a ks 57 [BGACK Negatod to AS, 0S, RW Deven wasp | 18 15 6 ike ‘357A _[BGACK Negated 10 FC, VATA Driven wero | 1|—-| 1] —-[ 7[— [aw 587 [BR Negated 10S, OS, RW Driven tauso | 15 | — [is | ~ [ts | ~ | eas 138A? [BR Negated to FC. VMA Driven vaneo | 1 [| 1-7 1] = Taw ‘Theve specications represent an improvement over previously published specications for the 8, 10, and 125 MH MCBEOTO and are valid ony fr produet bearing date codes of 8821 and later. Notes Fora loading capacitance of less than or aqua to 50 pF. subtract 6 ns from the value given inthe maximum columns. ‘cial value cepends on clock pore’ In the absence of DTACK, BERR isan asynchronous input using the asynchronous input setup time #87 For power-up, the M6800 must be held in the RESET state for 100 ms to allow stabilization of on-chip circuitry. Ater the system is powered up, #56 refers to the minimum pulse width requited to reset the processor. Wine asynchronous input setup time (#47) requirement ie satisfied for OTACK, the OTACK asserted to data setup time (#21) and DTACK asserted to BERR asserted setup time [#46) requirements can be ignored. The data must only Satisty the data-n to clock ow setup time [#27] for the following clock eye, and BERR must ony satiaty the ate BERR asserted to closkiow setup time (427A) far the following clock eye 6, When AS and A W are equaiy loaded (20%) subtract 5 ns from the valves given in these columns 7. The processor will negate BG and begin driving the bus again if external arbitration logie negates BR before asserting BGRCK. 8. The minimum value must be met to guarantee proper operation, Hf the maximum value is exceeded, 6G may be 8. The falling edge of $6 tiggers bath the negation of the strobes (AS and xDS) and the falling edge of E. Either ofthese ‘events can occur fist, depending upon the loading on each s\gral. Speciication #49 indicates the absolute maximum ‘kw that will occur Between the rising edge ofthe strobes and the falling edge of E 3-160 68000 FAMILY REFERENCE MANUAL MOTOROLA,x rete pee es/008 DATA "NOTE? ACT RESET asmicnronous noe notes: Selup time fr tho asynchronous inputs IPLE-PLD and VBA (#47) quaantens hor recegniton at ne £2 lling age of re cock 2. BF reed fal ahs imo ony eerste beng recognized a the end of ne bus eyo 5. Timiag messuremenis are reterenoed to and tem alow vtiage of €8V anda Fgh vlage of 20 V. unless oterwise nota. The volage swing tough Is range shoul tat out and pase ough he range such hale oa is ine batween 08 Vand'2 0. lure 8. Read Cycle Timing Diagram MOTOROLA 68000 FAMILY REFERENCE MANUAL 3161reese 8 ni Drm oxraout RR inate) ct RESET ". Timing massuroment re referenced and tom a lw voiage of 8 Vand a high voiage of20V, uniogs oferwis rele. The voltage swing vugh is range shoud start eutsde and pass Hough the ‘ange suzh Pat the ie o fa naar batwegn 0.8 V and? OV. 2, Because of eating variations, FW maybe val ater AS oven heugh Doh are ated by fe ricng eee 0f 82 (spciicaton #204) Figure 9. Write Cycle Timing Diagram 3-162 68000 FAMILY REFERENCE MANUAL MOTOROLAAC ELECTRICAL SPECIFICATIONS — PERIPHERAL CYCLES TO M6800 (Weo=5.0 Vae=5%: GND=0 Ve: Ta=TL to TH, see Figures 10 and 11) Norn, Characteriate Symbot pee _}_ to tet | 28 te nit ‘ain [Max | Win [ Max | Min [ Max 127 [tock Low to AS, BS Negated vasa |— | @ o|—[ «les 187 [etock Won to AW High eas) wou | Of | of | of «0 | as 205 [Clock Hh to RW Low (Write) tom [oss [of [of [oe 23 [lock Low to Data Out Vata (Wi ‘oo | | | — [0 0 | 27 _[bstan Valid wo Clock Low (Setup Tine ofeadh | toe | | — | | —| wl — | os 29. |S, DS Nopated to Dsta-in nvaia ‘swon | of -| of -] © m (Hola Time on Read 40 [Glock Low to WMA Assorted ‘cv | —[~[—| | ws [Glock Low to Transition twer | — | a | — [os [os 22_|E Output Rise and Fall Time er | — | 5 | — [5] 1 23,_[ HWA Assorted to E High wwmen | 200 | — | 160 | — [os {| AS, DS Nogate to VPA Nogotea ‘sven | of of o | of 7 | os 4 [E Low to Cont, Adress Bus Ivan ‘ica | | - | wo P| os (Breas Hots Tiel a7_[Asmachronovs Inout Setup Time ws | o[—] w[—] 7 492 _[RS. 5. Negated toE Low ‘wer [70] 7 [ss | os | a5| 6 | os 20_|E wiaen Hoh ven | 0 | — | 50 — [20] — [os Bie wiath Low teu) 700 sso | — | 0 | — | os 58 _[E tow to Dasa Out nvala ‘ewo | »[—| 1s | — [vs “These speciestions represent an improvement over previously published specifications for the 8, 10, and 125:MHr MCSEO10 and are valid nly for product bearing date codes of $82? and later NOTES Fora loading capacitance of les than or equal to 50 pF. subtract 5 ns from the value given in the maximum columns 2, The falling edge of $6 triggers both the negation ofthe strobes (AS and x08} and the faling edge of E, Either ofthese {events can occur frst, depercing upon the loading on wach signal. Specification #49 indicates the absolute maximum skew that will occur between the ising edge ofthe strobes and the failing edge of E MOTOROLA, 68000 FAMILY REFERENCE MANUAL 3.163baraour AR | NOTE: This tming diagram inca for hose who wish to design nec oan cic gonerate VR, shows he best case possi atainanie, Figure 10. MC68010 to M6800 Peripheral Timing Diagram (Best Case) 3-164 68000 FAMILY REFERENCE MANUAL MOTOROLA{ase isso) weaBerg Guswy jesaydiiad OOSIW OF OLOSIOW ‘LL 22nB14 ‘Srgeuewe Agss0d ose» 10M oul SAGYS YHA 8210426 cL oNe Uo HON UBIsap ct sim CLM B80 0] papRPU | WBE Buu SUL SLON niwtvo ese novia >= ><® | am am eH | j , van De |< rg O : <= = 1 ws > Sa | | Oo | e<@® I I T T T wey RAR RARAARARARRARAAARR Bisse AR MRK RM RH RMR RK RR RM RM Rw Rw NG ES IS OE 68000 FAMILY REFERENCE MANUAL 3-165 MOTOROLAAC ELECTRICAL SPECIFICATIONS — BUS ARBITRATION Wc =5.0 Vde~ 5%; GND=0 Vde; Ta=Tl to THs see Figures 12-16) Num ‘Characteristic ‘Symbol |= Arte 710 ee 125 ent ‘in [ Max | min [max | min | tox 7 [elock High to Address, Data Bus High tcnanz| — | 20 | — | | — | @ | os Irmpadance (Meximur 76_[Ciock High to Conto! Bus High Impedance toucz | — | 0 | — | 70 co [ns 33_|ciock High to 8G Assorted roncr | — | 2 | — [oo | — [00 [ne 34_[Ciock High to BG Negated tool es es ee 35_[BR Assorted wo 8G Assented orc | 15 [a5 [1s | a5 | 1s | as | cue 36° [BR Negated to BG Negates wwmucn | 15 | 35 [15 [a5 | 15 | as | cus 37_[BGACK Assorted to BG Negates toacu | 15 | a5 [as [a5 | 15 | as [cus a7A? | BGACK Asserted 10 BR Nogated caer] 20 [15 | 20 | 15 | 20 | 15 | os ks cis cis 38 [BG Assorted vo Contat, Address. Data Bus wiz |—]o|— |» 60 | ne High impedance (AS Negated) 39 [56 wiatn Negatea ga_| 15 15 a5 | = [ens 46 _[BGACK wietn Low toa. 115 { — [as[— [os] — | cue 127_[Asynenronous Input Setup Time ws: [10 | — [0 [— [oo ne 51 _|BGACK Negotce to AS, DS, AW Drven wgaso [is [— [as] — [is | — [os 37A_ | BGACK Nogstod to FC, VIA Driven \GAFD 1 1 |= Tots 58° [BR Negated to AS, DS, AW Driven tmuso | 15 | — [ae | — [15 | — [ons 5887 [BR Negatod to FC, VA Driven mo | + | — | 1 f— Ts lke “These specifications represent an improvement over previously publishes specifications for the @, 10-, and 12.-™He IMCBB010 and are vaid only for praduct bearing date codes of 8827 and ater. NOTES 1. The processor will negate BG and bogin driving the bus again if exornal arbitration logic negates BR before asserting BGACK 2. The minimum value must be met to guarantee proper operation, I the maximum value i exceeded, BG may be asserted. 3-168 ‘Meg000 FAMILY REFERENCE MANUAL MOTOROLABuju, uonenquy sng ‘ZL o1nBLy 1201 ap Jo a8p0 6 "uae sind srovontoutee au. ou 04 18 vaquBe01 1049 sooueven8 Yan PUE Ondl Zid! YO¥LO HE YovDS (ay#} eo ow ot aun dmieg LON pe ats 3.167 (68000 FAMILY REFERENCE MANUAL MOTOROLA«APIA awa T ae ne a i @ Feerco NOTE: Wavetorm measurements fr al inputs and outpus are spocited at: logi high = 2.0 V, logiclow = 08 V. Figure 13. Bus Arbitration Ti 19 — Idle Bus Case 3-168 Me8000 FAMILY REFERENCE MANUAL MOTOROLANOTE: Wavelom measurement loa input an eupu are specifed at: Wglchigh = 20, ogc ow = 0.8. Figure 14. Bus Arbitration Timing — Active Bus Case MOTOROLA ‘68000 FAMILY REFERENCE MANUAL 3-169Fearon 700 es NOTE. Wavolrm maasurnts fo linpu and oupus are specie a: loi high = 20, gic low = 08 V. 3.170 Figure 15. Bus Arbitration Timing — Multiple Bus Requests Me8000 FAMILY REFERENCE MANUAL MOTOROLAPIN ASSIGNMENTS 64-LEAD DUAL-IN-LINE PACKAGE ocfe otek Bouck cw J ws e [> av vA «5 ae ana 2 Fias i oF ae ce 6 [5 ana ima 0 ae Fee sho Fo ® Foo af a [> 2 asf ar “ ot FS ae mM ss fas MOTOROLA M8000 FAMILY REFERENCE MANUAL 347168-LEAD QUAD PACKAGE Hors Bore Bors Davo Biot a8 faz par Bc fan bass paw pair paw pass pa pias 68-LEAD PIN GRID ARRAY oo0 No Fo2 Feo 9,0 9 BiRe Ro ee RozORO ZoR070z0 20202050 ° Mesgo1o FALT RESET [pti view) O° clk oho °° BR Mee 08 9 BOK BG “Ra OS O. OTRCR(S UD O19 0 We |S OF fo OBORO 02080 OLOROS SO g0RO® 3.172 68000 FAMILY REFERENCE MANUAL MOTOROLA