P5.

1 BLOQUES COMBINACIONALES
Llus Ters
Instituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)
Universitat Autnoma de Barcelona (UAB)

P5.1

1SELECCINdeENTRADA

seleccinentrada

Especificacin Funcional
loop
caseinstructionis
when(ASSIGN_VALUE,k,A)=>
to_reg :=A;
when(DATA_INPUT,k,j)=>
to_reg :=IN(j);
when(OPERATION,i,j,k,f)=>
to_reg :=result;
whenothers=>
to_reg :=don'tcare;
endcase;
endloop;

Circuito Combinacional:
to_reg es una funcin deinstruction,IN0,,IN7y
result.

instruction
ASSIGN_VALUE
DATA_INPUT
OPERATION
others

input_control
00
01
10

Seales decontrol

(seleccindeentrada)
instruction
ASSIGN_VALUE
DATA_INPUT
OPERATION
others

input_control
00
01
10

Especificacin Funcional
loop
caseinstructionis
when(ASSIGN_VALUE,k,A)=>
to_reg :=A;
when(DATA_INPUT,k,j)=>
to_reg :=IN(j);
when(OPERATION,i,j,k,f)=>
to_reg :=result;
whenothers=>
to_reg :=don'tcare;
endcase;
endloop;

P5.1
seleccinentrada

loop
caseinput_control is
when00=>
to_reg :=A;
when01=>
to_reg :=IN(j);
when10=>
to_reg :=result;
when11=>
to_reg :=don'tcare;
endcase;
endloop;

P5.1

(seleccindeentrada)
Implementacion directa:
seleccinentrada

loop
caseinput_control is
when00=>
to_reg :=A;
when01=>
to_reg :=IN(j);
when10=>
to_reg :=result;
when11=>
to_reg :=don'tcare;
endcase;
endloop;

(seleccindeentrada:modeloVHDL)

P5.1

package main_parameters is
constant m:natural :=8; mbitprocessor
end main_parameters;
library IEEE;use IEEE.std_logic_1164.all;
use work.main_parameters.all;

seleccinentrada

entity input_selection is
port (
IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7:
instd_logic_vector(m1downto 0);
A,result:instd_logic_vector(m1downto 0);
j:instd_logic_vector(2downto 0);
input_control:instd_logic_vector(1downto 0);
to_reg:outstd_logic_vector(m1downto 0)
);
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end input_selection;

(seleccindeentrada:modelo VHDL)

P5.1

architecturestructureof input_selection is
signal selected_port:std_logic_vector(m1downto 0);
begin
primer_mux:process(j,IN0,IN1,IN2,IN3,IN4,IN5,IN6,IN7)
begin
case jis
when "000"=> selected_port <= IN0;
when "001"=> selected_port <= IN1;

when "110"=> selected_port <= IN6;

whenothers => selected_port <= IN7;
endcase;
endprocess;
6

(seleccindeentrada:modelo VHDL)

P5.1

segundo_mux:
process(input_control,A,selected_port,result)
begin
case input_control is
when "00"=> to_reg <= A;
when "01"=> to_reg <= selected_port;
when "10"=> to_reg <= result;
whenothers => to_reg <= (others=> '0');
endcase;
endprocess;
endstructure;
7

P5.1

2RECURSOSDECLCULO
Modelo VHDL:

Especificacin Funcional
iff=0thenresult:=left_in +right_in;
elseresult:=left_in right_in;
endif;
Circuito Combinacional:
result es una funcin def,left_in andright_in.
(unsumador /restador)

library ieee;use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.main_parameters.all;
entity computation_resources is
port (
left_in,right_in:instd_logic_vector(m1downto 0);
f:instd_logic;
result:out std_logic_vector(m1downto 0)
);
end computation_resources;
8

(recursosdeclculo:modeloVHDL)

P5.1

Modelo VHDL:
Especificacin Funcional
iff=0thenresult:=left_in +right_in;
elseresult:=left_in right_in;
endif;

architecture behaviorof computation_resources is

begin
process(f,left_in,right_in)
begin
if f='0'then result<= left_in + right_in;
else result<= left_in right_in;
endif;
endprocess;
endbehavior;
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RESUMEN

P5.1

Modelos VHDLdebloques combinacionales:

seleccin deentrada,
recursos declculo.

10

P5.2 BLOQUES SECUENCIALES

Llus Ters
Instituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)
Universitat Autnoma de Barcelona (UAB)

P5.2

1SELECCINDESALIDA
seleccindesalida

Circuito secuencial:
OUT0,,OUT7sonsalidas registradas
Especificacin Funcional
loop
caseprogram(number)is
when(DATA_OUTPUT,i,j)=>
OUT(i):=reg;
when(OUTPUT_VALUE,i,A)=>
OUT(i):=A;
endcase;
endloop;

instruction
DATA_OUTPUT
OUTPUT_VALUE
others

out_en
1
1
0

out_sel
1
0

Seales decontrol

12

(seleccindesalida)
instruction
DATA_OUTPUT
OUTPUT_VALUE
others

out_en
1
1
0

out_sel
1
0

Especificacin Funcional
loop
caseprogram(number)is
when(DATA_OUTPUT,i,j)=>
OUT(i):=reg;
when(OUTPUT_VALUE,i,A)=>
OUT(i):=A;
endcase;
endloop;

P5.2

seleccindesalida

loop
case(out_en,out_sel)is
when11=>
OUT(i):=reg;
when10=>
OUT(i):=A;
whenothers=>
null;
endcase;
endloop;
13

(seleccindesalida)

P5.2

Implementacin directa:
seleccindesalida

loop
case(out_en,out_sel)is
when11=>
OUT(i):=reg;
when10=>
OUT(i):=A;
whenothers=>
null;
endcase;
endloop;
14

(seleccindesalida:modeloVHDL)

P5.2

Modelo VHDL:
library ieee;use ieee.std_logic_1164.all;
use work.main_parameters.all;

seleccindesalida

entity output_selection is
port (
A,reg:instd_logic_vector(m1downto 0);
clk,out_en,out_sel:instd_logic;
i:instd_logic_vector(2downto 0);
OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6,OUT7:
outstd_logic_vector(m1downto 0)
);
end output_selection;
15

(seleccindesalida:modeloVHDL)

P5.2

architecturestructureof output_selection is
signal DEC_OUT:std_logic_vector(0to 7);
signal EN:std_logic_vector(0to 7);
signal to_ports:std_logic_vector(m1downto 0);
begin
decoder:process(i)
begin
case i is
when "000"=> DEC_OUT<= "10000000";
when "001"=> DEC_OUT<= "01000000";

when "110"=> DEC_OUT<= "00000010";

whenothers => DEC_OUT<= "00000001";
endcase;
endprocess;
and_gate:process(DEC_OUT,out_en)
variable i:integer;
begin
for i in 0to 7loop EN(i)<= DEC_OUT(i)AND out_en;
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endloop;
endprocess;

(seleccindesalida:modeloVHDL)

to_ports

P5.2

multiplexer:process(out_sel,A,reg)
begin
if out_sel ='0'then to_ports <= A;
else to_ports <= reg;endif;
endprocess;
output_registers:process(clk)
begin
if clk'event and clk ='1'then
case ENis
when "10000000"=> OUT0<= to_ports;
when "01000000"=> OUT1<= to_ports;

when "00000001"=> OUT7<= to_ports;

whenothers=>null;
endcase;
endif;
endprocess;
endstructure;

17

RESUMEN

P5.2

Modelo VHDLdebloques secuenciales:

Seleccin desalida.

18