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Physical Design Flow

Physical Design Flow

In integrated circuit design, physical design is a step in the standard design cycle which follows after the
circuit design. At this step, circuit representations of the components (devices and interconnects) of the
design are converted into geometric representations of shapes which, when manufactured in the
corresponding layers of materials, will ensure the required functioning of the components. This geometric
representation is called integrated circuit layout. This step is usually split into several sub-steps, which
include both design and verification and validation of the layout.

Modern day Integrated Circuit (IC) design is split up into Front-end design using HDL's, Verification and
Back-end Design or Physical Design. The next step after Physical Design is the Manufacturing process or
Fabrication Process that is done in the Wafer Fabrication Houses. Fab-houses fabricate designs onto
silicon dies which are then packaged into ICs.
Each of the phases mentioned above have Design Flows associated with them. These Design Flows lay
down the process and guide-lines/framework for that phase. Physical Design flow uses the technology
libraries that are provided by the fabrication houses. These technology files provide information regarding
the type of Silicon wafer used, the standard-cells used, the layout rules, etc.
Technologies are commonly classified according to minimal feature size. Standard sizes, in the order of
miniaturization, are 2m, 1m , 0.5m , 0.35m, 0.25m, 180nm, 130nm, 90nm, 65nm, 45nm, 28nm,
22nm, 18nm... They may be also classified according to major manufacturing approaches: n-Well
process, twin-well process, SOI process, etc.
The main steps in the flow are:

Design Netlist (after synthesis)

Floor Planning

Partitioning

Placement

Clock-tree Synthesis (CTS)

Routing

Physical Verification

GDS II Generation

These steps are just the basic. There are detailed PD Flows that are used depending on the Tools used
and the methodology/technology. Some of the tools/software used in the back-end design are :
Cadence (SOC Encounter, VoltageStorm, NanoRoute)

Synopsys (Design Compiler, IC Compiler, PrimeTime)

Magma (BlastFusion, Talus )

Mentor Graphics (Olympus SoC, IC-Station, Calibre)

Sanity Checks

We need to perform some sanity checks before we start our physical design flow, Sanity check will ensure
that input which we received from various team such as synthesis team, library team etc are correct. If we
missed this checks than it can create problem in later stage.
Below are input fies which we are mainly checking
1. Netlist
2. SDC Files
3. Library Files
4. Design Data

Floor Planning

Introduction To Floor Planning

This is the first major step in getting your layout done, and this is the most
important one.Your floorplan determines your chip quality. Floorplanning
includes
1.
Define the size of your chip/block and Aspect ratio
2.

Defining the core area and IO core spacing

3.

Defining ports specified by top level engineer.

4.
Design a Floor Plan and Power Network with horizontal metal layer such
that the total IR Drop must be less than 5% (VDD+VSS) of VDD to operate within
the power budget.
5.

IO Placement/Pin placement

6.

Allocates power routing resources

7.
Place the hard macros (fly-line analysis) and reserve space for standard
cells. (Please referrules for placing hard macros)
8.

Defining Placement and Routing blockages blockages

9.
If we have multi height cells in the reference library separate placement
rows have to be provided for two different unit tiles.
10.

Creating I/O Rings

11.

Creating the Pad Ring for the Chip

12.

Creating I/O Pin Rings for Blocks

Every subsequent stage like placement, routing and timing


closure is dependent on how good your foorplan is. In a real time design, you go
through many iterations before you arrive at an optimum floorplan.

Floorplanning takes in some of the geometrical constraints in a design.


Examples of this are:

Bonding pads for off-chip connections (often using wire bonding) are
normally located at the circumference of the chip.
Line drivers often have to be located as close to bonding pads as possible.
Chip area is therefore in some cases given a minimum area in order to fit in
the required number of pads.

Areas are clustered in order to limit data paths thus frequently featuring
defined structures such as cache RAM, multiplier, barrel shifter, line driver and
arithmetic logic unit.

Purchased intellectual property blocks (IP-blocks), such as a processor


core, come in predefined area blocks.

Some IP-blocks come with legal limitations such as permitting no routing


of signals directly above the block.

Inputs for Floor Planning Stage


1.
2.
3.
4.
5.
6.
7.
8.

Synthesized Netlist (.v, .vhdl)


Logical and Physical Libraries
TLU+ Files
Physical partitioning information of the design
Design Constrains (SDC)
Physical information of your design (rules for targeted technology)
Floorplan parameters like height, width, utilization, aspect ratio etc.
Pin/pad Position

Outputs of Floor Planning Stage

Die/Block area

I/O pad/placed

Macro placed

Power grid design

Power pre-routing

Standard cell placement areas.

Purpose of Floor Planning

The first step in the Physical Design flow is Floor Planning. Floorplanning is the
process of identifying structures that should be placed close together, and allocating
space for them in such a manner as to meet the sometimes conflicting goals of
available space (cost of the chip), required performance, and the desire to have
everything close to everything else.
Based on the area of the design and the hierarchy, a suitable floorplan is decided
upon. Floor Planning takes into account the macro's used in the design, memory, other
IP cores and their placement needs, the routing possibilities and also the area of the
entire design. Floor planning also decides the IO structure, aspect ratio of the design. A
bad floor-plan will lead to waste-age of die area and routing congestion.
In many design methodologies, Area and Speed are considered to be things that
should be traded off against each other. The reason this is so is probably because there
are limited routing resources, and the more routing resources that are used, the slower
the design will operate. Optimizing for minimum area allows the design to use fewer
resources, but also allows the sections of the design to be closer together. This leads to
shorter interconnect distances, less routing resources to be used, faster end-to-end
signal paths, and even faster and more consistent place and route times. Done correctly
, there are no negatives to Floor-planning.
As a general rule, data-path sections benefit most from Floorplanning, and random
logic, state machines, and other non-structured logic can safely be left to the placer
section of the place and route software.
Data paths are typically the areas of your design where multiple bits are processed in
parallel with each bit being modified the same way with maybe some influence from
adjacent bits. Example structures that make up data paths are Adders, Subtractors,
Counters, Registers, and Muxes.Power

Power Planning Basic :

Power Planning is one of the most important stage in Physical design. Power network is being
synthesized, It is used provide power to macros and standard cells within the given IR-Drop
limit. Steady state IR Drop is caused by the resistance of the metal wires comprising the power
distribution network. By reducing the voltage difference between local power and ground,
steady-state IR Drop reduces both the speed and noise immunity of the local cells and
macrosPower planning management can be divided in two major category first one is core cell
power management and second one I/O cell power management. In core cell power planning
power rings are formed around the core and macro.In IO cell power planning power rings are
formed for I/O cells and trunks are created between core power ring and power pads.
In addition trunks are also created for macros as per the power requirement.
power planning is part of floor plan stage. In power plan, offset value for rings around
the core and vertical and horizontal straps is being define
I/O cell library contains I/O cell and VDD/VSS pad cell libraries. It also contain IP libraries
for reusable IP like RAM, ROM and other pre designed, standard, complex blocks.
Input Required In Power Planning
1. Database with valid floorplan
2. power rings and power straps width
3. Spacing between VDD and VSS Straps
Output Of Power Planning
Design with Power Structure

Detailed Power planning Concepts

Detailed Power planning Concept

There are two types of power planning and management. They are core cell power
management and I/O cell power management. In former one VDD and VSS power
rings are formed around the core and macro. In addition to this straps and trunks are
created for macros as per the power requirement. In the later one, power rings are formed
for I/O cells and trunks are constructed between core power ring and power pads. Top to
bottom approach is used for the power analysis of flatten design while bottom up approach
is suitable for macros.
The power information can be obtained from the front end design. The synthesis tool
reports static power information. Dynamic power can be calculated using Value Change
Dump (VCD) or Switching Activity Interchange Format (SAIF) file in conjunction
with RTL description and test bench. Exhaustive test coverage is required for
efficient calculation of peak power. This methodology is depicted in Figure (1).
For the hierarchical design budgeting has to be carried out in front end. Power is
calculated
from each block of the design. Astro works on flattened netlist. Hence here top to
bottom
approach can be used. JupiterXT can work on hierarchical designs. Hence bottom up
approach for power analysis can be used with JupiterXT. IR drops are not found in
floor planning stage. In placement stage rails are get connected with power rings,
straps,
trunks. Now IR drops comes into picture and improper design of power can lead to large
IR drops and core may not get sufficient power.

Figure (1) Power Planning methodology

Below are the calculations for flattened design of the SAMM. Only static power reported
by

the Synthesis tool (Design Compiler) is used instead of dynamic power.


The number of the core power pad required for each side of the chip
= total core power / [number of side*core voltage*maximum allowable current for a I/O pad]
= 236.2068mW/ [4 * 1.08 V * 24mA] (Considering design SAMM)
= 2.278
~2
Therefore for each side of the chip 2 power pads (2 VDD and 2 VSS) are added.
Total dynamic core current (mA)
= total dynamic core power / core voltage
= 236.2068mW / 1.08V
= 218.71 mA
Core PG ring width

= (Total dynamic core current)/ (No. of sides * maximum current density of the metal
layer
used (Jmax) for PG ring)=218.71 mA/(4*49.5 mA/m)~1.1 m~2 m
Pad to core trunk width (m)

= total dynamic core current / number of sides * Jmax where Jmax is the maximum current
density of metal layer used
= 218.71 mA / [4 * 49.5 mA/m]
= 1.104596 m
Hence pad to trunk width is kept as 2m.

Using below mentioned equations we can calculate vertical and horizontal strap width
and
required number of straps for each macro.

Block current:
Iblock= Pblock / Vddcore

Current supply from each side of the block:


Itop=Ibottom= { Iblock *[Wblock / (Wblock +Hblock)] }/2
Ileft=Iright= { Iblock *[Hblock / (Wblock +Hblock)] }/2

Power strap width based on EM:


Wstrap_vertical =Itop / Jmetal
Wstrap_horizontal =Ileft / Jmetal

Power strap width based on IR:


Wstrap_vertical >= [ Itop * Roe * Hblock ] / 0.1 * VDD
Wstrap_horizontal >= [ Ileft * Roe * Wblock ] / 0.1 * VDD

Refresh width:
Wrefresh_vertical =3 * routing pitch +minimum width of metal (M4)
Wrefresh_horizontal =3 * routing pitch +minimum width of metal (M3)

Refresh number
Nrefresh_vertical = max (Wstrap_vertical ) / Wrefresh_vertical
Nrefresh_horizontal = max (Wstrap_horizontal ) / Wrefresh_horizontal

Refresh spacing
Srefresh_vertical = Wblock / Nrefresh_vertical
Srefresh_horizontal = Hblock / Nrefresh_horizontal

Placement
Introduction
After you have done floorplanning, i.e. created the core area, placed the macros, and
decided the power network structure of your design, it is time to let the tool to do standard
cell placement. The tool determines the location of each of the components (in digital
design, standard cell instantiations) on the die. Various factors come into play, like the
timing requirement of the system, the interconnect lengths and hence the connections
between cells, power dissipation etc. The interconnect lengths depend on the placement
solution used, and it is very important in determining the performance of the system as the
geometries shrink. Placement also determines the routability of your design.
Placement does not just place the standard cells available in the synthesized netlist. It also
optimizes the design, thereby removing any timing violations created due to the relative
placement on die.

Inputs To Placement Stage

Netlist

Mapped and Floorplannned Design

Logical and Physical Libraries

Design Constraints

Output of Placement Stage

Physical Layout Information

Cell placement location

Physical Layout, timing, and technology information of logical libra ries

Below are key task perfomed during Placement stage


1. Special Cell Placement :- Placement of Well-Tap Cells, End-Cap Cells, Spare Cells,
Decap Cells, JTAG and Other Cells Close to the I/Os

2. Optimizing and Reordering Scan Chains


3. Plaement Methodology :- Congestion Driven Placement Timing Driven Placement
4. Logic optimization In Placement
5. Major Placement Steps :- Virtual Placement, HFN synthesis, Initial (Global) Placement,
Detailed, placement (Legalization) Refine Placement

Post Placement Analysis1. Timing, Congestion Analysis


2. Placement Congestion: cell density
3. Global Route Congestion

IO Placement / Pin placement


If you are doing a digital-top design, you need to place IO pads and IO buffers of the chip.Take a
reactangular or square chip that has pads in four sides.To start with, you may get the sides and
relative positions of the PADs from the designers. You will also get a maximum and minimum
die size according to the package you have selected. To place IOs, people mainly use a perl
script to place them.

Routing

Routing Concept In Physical Design


After the floorplanning and placement steps in the design, routing needs to be done. Routing
is nothing but connecting the various blocks in the chip with one another. Until now, the
blocks were only just placed on the chip. Routing also is spilt into two steps

1. Global Routing:
It basically plans the overall connections between all the blocks and the nets. Its main aim is
to minimize the total interconnect length, minimize the critical path delay. It determines the
track assignments for each interconnect.
a. The chip is divided into small blocks. These small blocks are called routing bins. The size
of the routing bin depends on the algorithm the tool uses. Each routing bin is also called a
gcell. The size of this gcell depends on the tool.Each gcell has a finite number of horizontal
and vertical tracks. Global routing assigns nets to specific gcells but it does not define the
specific tracks for each of them. The global router connects two different gcells from the
centre point of each gcell.
b. Track Assignment: The Global router keeps track of how many interconnections are going
in each of direction. This is nothing but the routing demand. The number of routing layers
that are available depend on the design and also, if the die size is more, the greater the
routing tracks. Each routing layer has a minimum width spacing rule, and its own routing
capacity. For Example: For a 5 metal layer design, if Metal 1, 4, 5 are partially up for inter-cell
connections, pin, VDD, VSS connections, the only layers which are routable 100% are Metal2
and Metal3. So if the routing demand goes over the routing supply, it causes Congestion.
Congestion leads to DRC errors and slow runtime

2. Detailed Routing:
In this step, the actual connection between all the nets takes place. It creates the actual via
and metal connections. The main objective of detailed routing is to minimize the total area,
wire length, delay in the critical paths. It specifies the specific tracks for the interconnection;
each layer has its own routing grid, rules. During the final routing, the width, layer, and
exact location of the interconnection are decided.After detailed routing is complete, the
exact length and the position of each interconnect for every net in the design is known. The
parasitic capacitance, resistance can now is extracted to determine the actual delays in the
design. The parasitic extraction is done by extraction tools. This information is back
annotated and the timing of the design is now calculated using the actual delays by the
Static Timing Analysis Tool. After timing is met and all other verification is performed such as
LVS, etc, the design is sent to the foundry to manufacture the chip.

Clock Tree Synthesis


Inputs for Clock Tree Synthesis

Placed Cell

CTS Constraints
Non Default Routing Rules {NDR , Bcoz during clock signal
(routingclock_route.tcl)Clock nets are largely pruned to Cross Talk effect }
Goal of Clock Tree Synthesis
To Balance Insertion Delay

To make Skew Zero. For this we this reason we will need to synthesize the clock tree

After CTS you should meet all the Hold Violations.

Checks

Is Skew is minimum and Insertion delay balanced.

Is Timing {Especially Hold} met, if not why?

If there are timing violations are all the constraints constrained properly.{like not
defining false paths, asynchronous paths, multicycle paths}.

Is std Cell Utilization acceptable at this stage

Check for Global Route Congestion

Check for Placement Legality.

Clock Tree Synthesis


The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not propagated
before CTS as shown in the picture. After CTS hold slack should improve. Clock tree begins at .sdc
defined clock source and ends at stop pins of flop. There are two types of stop pins known as ignore pins
and sync pins. Dont touch circuits and pins in front end (logic synthesis) are treated as ignore circuits or
pins at back end (physical synthesis). Ignore pins are ignored for timing analysis. If clock is divided then
separate skew analysis is necessary.

Global skew achieves zero skew between two synchronous pins without considering logic
relationship.

Local skew achieves zero skew between two synchronous pins while considering logic
relationship.

If clock is skewed intentionally to improve setup slack then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. Higher the rigidity tighter is the
constraints.
In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But
shielding increases area by 12 to 15%. Since the clock signal is global in nature the same metal layer
used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer

relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in
placement and post placement optimization before CTS stages while neglecting hold slack. In post
placement optimization after CTS hold slack is improved. As a result of CTS lot of buffers are added.
Generally for 100k gates around 650 buffers are added
You may be also interested in below topics related to CTS

Terminology related to CTS

How To fix Setup time Violation

How To Fix Hold Time Violations

Non Default Rules (NDR)

HVT LVT SVT Cells

Crosstalk

Clock Buffer VS Normal Buffer

Physical Verification
Physical Verification Introduction
After routing, your layout is complete. Now a number of checks are performed to verify that the
drawn layout works as intended.
1.

Physical verification

2.

Equivalence Checking

3.

Timing Analysis

Equivalence check will compare the netlist we started out with (pre-layout/synthesis netlist) to the
netlist written out by the tool after PnR(postlayout netlist).Physical verification will verify that the postlayout netlist and the layout are equivalent. i.e. all connections specified in the netlist is present in the
layout.This article explains physical verification.
Physical Verification

After routing, your PnR tool should give you zero DRC/LVS violations. However, the PnR tool deals
with abstracts like FRAM or LEF views. We use dedicated physical verification tools for signoff LVS
and DRC checks. Some of these are Hercules from Synopsys, Assura from Cadence and Calibre
from MentorGraphics.
The major checks are:

1.

DRC

DRC checks determine if the layout satisfies a set of rules required for manufacturing.
The most common of these are spacing rules between metals, minimum width rules, via
rules etc.There will also be specific rules pertaining to your technology. An input to the
design rule tool is a design rule file (called a runset by Synopsys hercules). The design
rules ensure sufficient margins to correctly define the geometries without any
connectivity issues due to proximity in the semiconductor manufacturing processes, so
as to ensure that most of the parts work correctly. The minumum width rules exists for
all mask layers, and spacing between the same layers are also specified. Spacing rules
may change depending on the width of one or both of the layers as well. There can also
be rules between two different layers, and specific via density rules etc. If the design
rules are violated, the chip may not be functional.

DRC Spacing & Width checks


DRC checking software, like Assura, Hercules or Calibre usually takes the layout
in any of the supported formats, like GDSII.

2.

LVS

LVS is another major check in the physical verification stage. Here you are
verifying that the layout you have created is functionally the same as the
schematic/netlist of the design-that you have correctly transferred into
geometries your intent while creating the design. So all the connections should
be proper and there shouldnt any missing connections etc.
The LVS tool creates a layout netlist, by extracting the geometries. This layout
netlist is compared with the schematic netlist. The tool may require some steps
to create either of these netlists(e.g. nettran run in synopsys)
If the two netlists match, we get an LVS clean result. Else the tool reports the
mismatch and the component and location of the mismatch. Along with formal
verification, which verifies if your pre-layout netlist matches the post-layout
netlist,LVS verifies the correctness of the layout w.r.t intended functionality.
Some of the LVS errors are:

Shorts Wires that should not be connected are overlapping.

Opens Connections are not complete for certain nets.

Parameter mismatch LVS also checks for parameter mismatches. e.g. It

may match a resistor in both layout and schematic, but the resistor values may be
different. This will be reported as a parameter mismatch.

Unbound pins If the pins dont have a geometry, but all the connection to

the net are made, and unbound pin is reported.


3.

Antenna
Process antenna effect or plasma induced gate oxide damage is a
manufacturing effect. i.e. this is a type of failure that can occur solely at the
manufacturing stage. This is a gate damage that can occur due to charge
accumulation on metals and discharge to a gate through gate oxide.
Let us see how this happens. In the manufacturing process, metals are built layer
by layer. i.e. metal1 is deposited first, then all unwanted portions are etched
away, with plasma etching. The metal geometries when they are exposed to
plasma can collect charge from it. Once metal1 is completed, via1 is built, then
metal2 and so on. So with each passing stage, the metal geometries can build up
static electricity. The larger the metal area that is exposed to the plasma, the
more charge they can collect. If the charge collected is large enough to cause
current to flow to the gate, this can cause damage to the gate oxide. This
happens because since the layers are built one-by-one, a source/drain implant
may not be available for discharge as in fig.b.

Process Antenna
Antenna rules are normally expressed as an allowable ratio of metal area to gate
area. Each foundry sets a maximum allowable antenna ratio for its processes. If
the metal areawhich is cumulative, i.e. the sum of the ratios of all lower layer
interconnects in addition to the layer in checkis greater than the allowable area,
the physical verification tool flags an error.For example, lets say maximum
allowable antenna ratio for metal1 is 400. If the gate area is 1 sq.u and if the
metal area connecting to the gate is 500 sq.u, there will be a process antenna
violation.

4.

ERC

ERC (Electrical rule check) involves checking a design for all electrical connections that
are considered dangerous.

Floating gate error If any gate is unconnected, this could lead to leakage

issues.

VDD/VSS errors The well geometries need to be connected to

power/Ground and if the PG connection is not complete or if the pins are not defined,
the whole layout can report errors like NWELL not connected to VDD.

Signal Integrity :

Signal integrity
Signal Integrity is the ability of an electrical signal to carry information reliably and to resist the effects of
high-frequency electromagnetic interference from nearby signals. Effects: CrossTalk, EM, Antennae
Effects.

Crosstalk:
Switching of the signal in one net can interference neighboring net due to cross coupling
capacitance. This affect is known as cross talk. Crosstalk can lead to crosstalk-induced delay
changes or static noise.

Techniques to solve Crosstalk

Double spacing => more spacing=>less capacitance=>less cross talk


Multiple vias

=> less resistance=>less RC delay

Shielding

=> constant cross coupling capacitance =>known value of crosstalk

Buffer insertion => boost the victim strength.


Net ordering

=> in same metal layer change the net path.

Layer assignment=> Change the metal layer of two nets if possible. (One s/g in mtl3 and one
signal in 4).

Signal Electro Migration:

Electromigration is the permanent physical movement of metal in thin wire connections resulting
from the displacement of metal ions by flowing electrons. ectromigration can lead to shorts and
opens in wire connections, causing functional failure of the IC device.
High current densities cause wearing of metal due to EM.

Techniques to solve EM:

1) Increase the width of the wire


2) Buffer insertion
3) Upsize the driver
4) Switch the net to higher metal layer
Antennae effects

The antenna effect [plasma induced gate oxide damage] is an effect that can potentially cause
yield and reliability problems during the manufacture of MOS integrated circuits. The IC fabs
normally supply antenna rules that must be obeyed to avoid this problem and violation of such
rules is called an antenna violation. The real problem here is the collection of charge.
A net in an IC will have atleast one driver (which must contain a source or drain diffusion or in
newer technology implantation is used), and at least one receiver (which will consist of a gate
electrode over a thin gate dielectric). Since the gate dielectric is very thin, the layer will
breakdown if the net somehow acquires a voltage somewhat higher than the normal operating
voltage of the chip. Once the chip is fabricated, this cannot happen, since every net has at least
some source/drain implant connected to it. The source/drain implant forms a diode, which
breaks down at a lower voltage than the oxide (either forward diode conduction, or reverse
breakdown), and does so non-destructively. This protects the gate oxide. But during the
construction phase, if the voltage is build up to the breakdown level when not protected by this
diode, the gate oxide will breakdown.
Antenna rules are normally expressed as an allowable ratio of metal area to gate area. There is
one such ratio for each interconnect layer. Each oxide will have different rule.
Antenna violations must be fixed by the router. Connecting gate oxide to the highest metal layer,
adding vias to near the gate oxide to connect to highest layers used and adding diode to the net
near the gate are some fixes that can be applied. Adding diode rises the capacitance and
makes circuit slower and consumes more power.

Techniques to solve Antennae violation

1. Jumper insertion
2. Diode insertion near logic gate input pin
3. Buffer Insertion

Signal Integrity Effects

Signal integrity is the ability of an electrical signal to carry information reliably and resist the
effects of high-frequency electromagnetic interference from nearby signals.
There are various kind signal integrity violation, In Order to do successful tapeout, one need
to overcome all these violation.
Some of the signal integrity effects might occur in your design

1. Crosstalk
Crosstalk is the undesirable electrical interaction between two or more physically adjacent nets due to
capacitive cross-coupling. As integrated circuit technologies advance toward smaller geometries,
crosstalk effects become increasingly important compared to cell delays and net delays.

Cross talk noise effects:


A signal should be constant for some time. But during the transition in adjacent signal causes anoise
bump / glitch on constant signal. If the glitch is significantly high , it can cause incorrect logic to be
propagated.
How To fix Crosstalk Issue
Double spacing=>more spacing=>less capacitance=>less cross talk
Multiple vias=>less resistance=>less RC delay
Shielding=> constant cross coupling capacitance =>known value of crosstalk
Buffer insertion=>boost the victim strength

2. Electromigration and its issues prevention


3.Antennae Effect
The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially
cause yield and reliability problems during the manufacture of MOS integrated circuits. Fabs normally
supply antenna rules, which are rules that must be obeyed to avoid this problem. A violation of such rules
is called an antenna violation. The word antenna is something of a misnomer in this contextthe problem
is really the collection of charge, not the normal meaning of antenna, which is a device for converting
electromagnetic fields to/from electrical currents. Occasionally the phrase antenna effect is used in this
context, but this is less common since there are many effects, and the phrase does not make clear which
is meant.

How to Prevent Antennae Effect

Change the order of the routing layers. If the gate(s) immediately connects to the highest metal
layer, no antenna violation will normally occur.

Add vias near the gate(s), to connect the gate to the highest layer used. This adds more vias, but
involves fewer changes to the rest of the net.

Add diode(s) to the net. A diode can be formed away from a MOSFET source/drain, for example,
with an n+ implant in a p-substrate or with a p+ implant in an n-well. If the diode is connected to metal
near the gate(s), it can protect the gate oxide. This can be done only on nets with violations, or on
every gate (in general by putting such diodes in every library cell). The "every cell" solution can fix
almost all antenna problems with no need for action by any other tools. However, the extra
capacitance of the diode makes the circuit slower and more power hungry.

Blockages
BLOCKAGES
Placement blockages prevent the placement engine from placing cells at specific locations. Routing
blockages block routing resources on one or more layers and it can be created at any point in a design
flow. In general placement blockages are created at floor planning stage and routing blockages are
created before using any routers. It acts like guidelines for placement of standard cells. Blockages will not
be guiding the tool to place the standard cells at some particular area, but it wont allow the tool to place
the standard cell in the blocked areas (in both placement and routing blockages). This is how the
blockages acts like guidelines for standard cell placement. During the CTS process (Clock Tree
Synthesis) in order to balance the skew, more number of buffers and inverters are added and blockages
are used to reserve space for buffers and inverters.

Placement blockages
Use placement blockages to:
o

Define std-cells and macro area

Reserve channels for buffer insertion

Prevent cells from being placed at or near macros

Prevent congestion near macros

Soft (Non buffer blockage)


o

Only buffers can be placed and standard cells cannot be placed.

Hard (Std-cell blockage)


Blocks all std-cells and buffers to be placed. Std-cell blockages are mostly used to:
o

Avoid routing congestion at macro corners

Restrict std-cells to certain regions in the design

Control power rails generation at macro cells

Partial blockages
By default a placement blockage has a blockage factor of 100%. No cells can be placed in that area, but
flexibility of blockages can be chosen by partial blockages. To reduce placement density without blocking
100% of the area, changing the blockage factor of an existing blockage to lower value will be a better
option.

Keepout Margin (Halo)

fig-1: Halo
o

Its the region around the boundary of fixed macros in design in which no other macros or stdcells can be placed. It allows placement of buffers and inverters in its area. Pictorial representation
of halo is mentioned in the figure-1.

Halos of adjacent macros can overlap; there the size of halo determines the default top level
channel size between macros. Prevent cells from being placed at or near the macros.

If the macros are moved from one place to another, hallows will also be moved.

Some Basic Rules For Placing Macros


Macro placement
Once you have the size & shape of the floorplan ready and initialized the floorplan, thereby creating
standard cell rows, you are now ready to hand place your macros. Do not use any auto placement, I have
not seen anything that works. Flylines in your tool will show you the connection between the macros and
standard cells or IOs.

1.
Use flylines and make sure you place blocks that connects to each other closer
2.
For a full-chip, if hard macros connect to IOs, place them near the respective IOs
3.
Consider the power straps while placing macros. You can club macros/memories
4.
Creating Power Rings and Straps
5.
Avoided the placement of macros in front of ports.
6.
Arranged the macros to get contiguous core area.
7.
Macro spacing given by space={[(no. of pins) * pitch] + space} / (no of metal layers in horizontal
or vertical direction)

Aspect Ratio

Aspect Raio of Core/Block/Design

The Aspect Ratio of Core/Block/Design is given as:

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

The aspect ratio effects the routing resources available in the design
The aspect ratio effects the congestion
The floorplanning need to be done depend on the aspect ratio
The placement of the standard cells also effect due to aspect ratio
The timing and there by the frequency of the chip also effects due to aspect ratio
The clock tree build on the chip also effect due to aspect ratio
The placement of the IO pads on the IO area also effects due to aspect ratio
The packaging also effects due to the aspect ratio
The placement of the chip on the board also effects

Ultimately everything depends on the aspect ratio of core/block/design The all the points are drawn
attention in future articles

Design Netlist
Physical design is based on a netlist which is the end result of the Synthesis process. Synthesis converts
the RTL design usually coded in VHDL or Verilog HDL to gate-level descriptions which the next set of
tools can read/understand. This netlist contains information on the cells used, their interconnections, area
used, and other details. Typical synthesis tools are:

Cadence RTL Compiler/Build Gates/Physically Knowledgeable Synthesis (PKS)

Synopsys Design Compiler

During the synthesis process, constraints are applied to ensure that the design meets the required
functionality and speed (specifications). Only after the netlist is verified for functionality and timing it is
sent for the physical design flow

Core Utilization

Utilization:
Utilization defines the area occupied by standard cell, macros and blockages. In general 70 to
80% of utilization is fixed because more number of inverters and buffers will be added during
the process of CTS (Clock Tree Synthesis) in order to maintain minimum skew.

Core utilization = (standard cell area+ macro cells area)/ total core area
A core utilization of 0.8 means that 80% of the area is available for placement of cells, whereas
20% is left free for routing.

IR Drop

IR Drop:
Voltage transfer in metal a drop occurs due to resistance of metal this is known as IR drop.
IR drops are two types
1. Static IR drop
Independent of the cell switching the drop is calculated with the help of wire
resistance. Methods to Improve static IR drop
1. Increase the width of wire
2. Provide more number of wire
2 . Dynamic Power Drop
Dynamic IR drop:ir drop is calculated with the help of the switching of the cells.
improve dynamic IR drop by below methods:
1. Placing dcap cells in between them
2. Increase the no of straps.
Calculation related to IR drop
1. Average Current Through Each Strap=Istrapavg=(Itotal)/(2*Nstraps)mA
2. Appropriate Ir Drop At The Center Of The Strap=Vdrop or IRdrop
=IstrapAvg*Rs*(W/2)*(1/Wstrap)
3. Number Of Straps Between Two Power Pads
Nstrappinspace=Dpadspacing/Lspace.
MIN Ring Width = wring = Ip/Rj Microm

We can

Calculation Related to power Planning

Power Calculations
1. Number Of The Core Power Pad Required For Each Side Of Chip=(Total Core Power)/{(Number
Of Side)*(Core Voltage)*Maximum Allowable Current For A I/O Pad)}
2. Core Current(mA)=(CORE Power)/(Core Voltage )
3. Core P/G Ring Width=(Total Core Current)/{(N0.Of.Sides)*(Maximum Current Density Of The Metal
Layer Used For Pg Ring)}
4. Total Current =Total Power Consumption Of Chip(P)/Voltage(V)
5. No.Of Power Pads(Npads) = Itotal/Ip
6. No.Of Power Pins=Itotal/Ip
Where,
Itotal =TOTAL Current
Ip Obtained From Io Library Specification.
7. Total Power=Static Power+Dynamic Power
=Leakage Power+[Internal Power+Ext Switching Power]
=Leakage Power+[{Shortckt+Int Power}]+Ext Switching Power]
=Leakage Power+[{(Vdd*Isc)+(C*V*V*F)+(1/2*C*V*V*F)]

Types of Cell
There are different types of cells used in order to meet the physical design
requirements. I have tried to list the down some important cells which will come across
frequently

1.
2.
3.
4.
5.
6.

Well Tap Cells


End Cap Cells
Decap cells
Spare cells
Tie Cells
Filler cells

Special cells are required for implementing a Multi-Voltage design.


1.
Level Shifter
2.
Isolation Cell
3.
Enable Level Shifter
4.
Retention Flops
5.
Always ON cells
6.
Power Gating Switches/MTCMOS switch

Double Patterning
What is Double patterning?

Double patterning is a technique used in the lithographic process that defines the
features of integrated circuits at advanced process nodes. It will enable designers to develop
chips for manufacture on sub-nanometer process nodes using current optical lithography
systems.

The downsides of using double patterning include increased mask (reticle) and
lithography costs, and the imposition of further restrictions on the ways in which circuits can be
laid out on chip. This affects the complexity of the design process and the performance,
variability and density of the resultant devices.

What does double patterning do and why do we need it?


Double patterning counters the effects of diffraction in optical lithography, which happens
because the minimum dimensions of advanced process nodes are a fraction of the 193nm
wavelength of the illuminating light source. These diffraction effects makes it difficult to produce
accurately defined deep sub-micron patterns using existing lighting sources and conventional

masks: sharp corners and edges become blurs, and some small features on the mask wont
appear on the wafer at all.

Non Default Rules (NDR)

NDR are mainly used in place & routing section of design flow. when they actually route the design.
The Default routing guideline for the router would be provided by tech Lef (incase of Encounter) or techfile
(incase of ICC). However when we are routing special nets especially CLOCK, we would like provide
more width & more spacing for them. Instead of default 1unit width & 1 unit spacing specified in tech LEF,
NDR will have double width , double spacing or triple width double spacing rules coded in them. when the
CLOCK net is routed using NDR , they would have better Signal Integrity, lesser cross talk, lesser Noise.
but we cannot increase the width & spacing to some large value as it will affect the area of chip. hence
backend designer needs to make a call on timing VS noise VS Area on finalizing about NDR rules.

Low Power Design

In today's scenario of VLSI, low power designs are major concern. As VLSi technology is shrinking the
power related problems are increasing. I have tried to capture few techniques which are being used to
achieve low power design.

Clock Gating
Details of Clock Gating

Power Gating Switches/MTCMOS switch


Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt
gates are used for speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as
header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly
reduced. MTCMOS switches can be implemented in various different ways. First, they can be
implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be
implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be
either built into every standard cell, or they can be used to switch off a large design block of standard
cells.

Always ON cells
Always ON cells: Generally these are buffers, that remain always powered irrespective of where they are
placed. They can be either special cells or regular buffers. If special cells are used, they have thier own
secondary power supply and hence can be placed any where in the design. Using regular buffers as
Always ON cells restricts the placement of these cells in a specific region.
In a nut-shell, "If data needs to be routed through or from sleep blocks to active blocks and If the routing
distance is excessively long or the driving load is excessively large, then buffers might be needed to drive
the nets. In these cases, the always-on buffers can be used."

Retention Flops
Retention Flops: These cells are special flops with multiple power supply. They are typically used as a
shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading
to this register need to be 'always_on' and hence special care must be taken to synthesize/place/route
them. In a nut-shell, "When design blocks are switched off for sleep mode, data in all flip-flops contained
within the block will be lost. If the designer desires to retain state, retention flip-flops must be used".
The retention flop has the same structure as a standard master-slave flop. However, the retention flop has
a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the
data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the
data can be written back into the flip-flop.

Isolation Cell
Isolation Cell: These are special cells required at the interface between blocks which are shut-down and
always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always
on' region only and the enable signal of the isolation cell needs to be 'always_on'. In a nut-shell, an
isolation cell is necessary to isolate floating inputs.

There are 2 types of isolation cells (a) Retain "0 (b) Retain "1

Enable Level Shifter


Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.

Use of Multi VT Cells


Multi Voltage cells

Design Exchange Format (DEF) Files

DEF Files :

A specification for representing logical connectivity and physical layout of and integrated circuit
in ASCII format

A DEF file is used to describe all the physical aspects of a design, including
- Die size
- Connectivity

- Physical location of cells and macros on the chip.

It contains floor-planning information such as


- Standard cell rows, groups
- Placement and routing blockages
- Placement constraints
- Power domain boundaries.

It also contains the physical representation for pins, signal routing, and power routing, including
rings and stripes.

Library Exchange Format (LEF) Files

LEF(Layer Exchange Format)The LEF file provides technology information, such as metal layer and via
layer information
and via generate rules. The LEF file contains all the physical information for the design.
GDSII files contains all teh information related to your design.One the design meets all teh constraints for
Timing, SI, Power Analysis & DRC & LVS it means that the design is ready for Tape out.This GDSII file is
used by FAB.

Latch Up Effect
A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the
inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit,
triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its
destruction due to overcurrent. A power cycle is required to correct this situation.
A single event latch-up is a latch-up caused by a single event upset, typically heavy ions or protons from
cosmic rays or solar flares.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a
PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is
conducting, the other one begins conducting too. They both keep each other in saturation for as long as
the structure is forward-biased and some current flows through it - which usually means until a powerdown. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair
on the output drivers of the gates.

How to Prevent Latch Up Effect

by adding tap wells, for example in an Inverter for NMOS add N+ tap in n-well and conncet it to

Vdd, and for PMOS add P+ tap in p-substrate and connect it to Vss.
an increase in substrate doping levels with a consequent drop in the value of Rs.
reducing Rp by control of fabrication parameters and by ensuring a low contact resistance to Vss.
By Providing Guard rings

CMOS Fundamentals
Before Going through complete physical design course one need to know basic fundamentals of CMOS,
which will help you to understand other advance concept easi

NMOS

PMOS

CMOS Inverters

Wafer Fabrication Techniques

Transistor Sizing

Temperature Inversion

NAND Vs NOR

Latch Up Effect

Latch Vs Flipflop

NMOS
N-type metal-oxide-semiconductor logic uses n-type field effect transistors (MOSFETs) to
implement logic gates and other digital circuits. These nMOS transistors operate by creating an inversion
layer in an p-type transistor body. This inversion layer, called the n-channel, can
conduct electrons between n-type "source" and "drain" terminals. The n-channel is created by applying
voltage to the third terminal, called the gate. Like other MOSFETs, nMOS transistors have four modes of
operation: cut-off (or subthreshold), triode, saturation (sometimes called active), and velocity saturation.
The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the logic gate
output and negative supply voltage, while a resistor is placed between the logic gate output and the
positive supply voltage. The circuit is designed such that if the desired output is low, then the PDN will be
active, creating a current path between the negative supply and the output.

PMOS
P-type metal-oxide-semiconductor logic uses p-channel metal-oxide-semiconductor field effect
transistors (MOSFETs) to implement logic gates and other digital circuits. PMOS transistors operate by
creating an inversion layer in an n-type transistor body. This inversion layer, called the p-channel, can
conduct holes between p-type "source" and "drain" terminals.
The p-channel is created by applying voltage to the third terminal, called the gate. Like other MOSFETs,
PMOS transistors have four modes of operation: cut-off (or subthreshold), triode, saturation (sometimes
called active), and velocity saturation.
The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output
and positive supply voltage, while a resistor is placed between the logic gate output and the negative
supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active,
creating a current path between the positive supply and the output.
While PMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor,
so the whole circuit can be made with PMOS FETs), it has several shortcomings as well. The worst

problem is that there is a direct current (DC) through a PMOS logic gate when the PUN is active, that is,
whenever the output is high, which leads to static power dissipation even when the circuit sits idle.
Also, PMOS circuits are slow to transition from high to low. When transitioning from low to high, the
transistors provide low resistance, and the capacitative charge at the output accumulates very quickly
(similar to charging a capacitor through a very low resistance). But the resistance between the output and
the negative supply rail is much greater, so the high-to-low transition takes longer (similar to discharge of
a capacitor through a high resistance). Using a resistor of lower value will speed up the process but also
increases static power dissipation.
Additionally, the asymmetric input logic levels make PMOS circuits susceptible to noise

CMOS Inverter

CMOS circuits are constructed in such a way that all PMOS transistors must have either an input from the
voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input
from ground or from another NMOS transistor. The composition of a PMOS transistor creates
low resistance between its source and drain contacts when a low gate voltage is applied and high
resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor
creates high resistance between source and drain when a low gate voltage is applied and low resistance
when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every
nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the
gates will cause the nMOSFET to conduct and the pMOSFET to not conduct, while a low voltage on the
gates causes the reverse. This arrangement greatly reduces power consumption and heat generation.
However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one
state to another. This induces a brief spike in power consumption and becomes a serious issue at high
frequencies.
The image below shows what happens when an input is connected to both a PMOS transistor (top of
diagram) and an NMOS transistor (bottom of diagram). When the voltage of input A is low, the NMOS
transistor's channel is in a high resistance state. This limits the current that can flow from Q to ground.
The PMOS transistor's channel is in a low resistance state and much more current can flow from the
supply to the output. Because the resistance between the supply voltage and Q is low, the voltage drop
between the supply voltage and Q due to a current drawn from Q is small. The output therefore registers
a high voltage.

On the other hand, when the voltage of input A is high, the PMOS transistor is in an OFF (high resistance)
state so it would limit the current flowing from the positive supply to the output, while the NMOS transistor
is in an ON (low resistance) state, allowing the output from drain to ground. Because the resistance
between Q and ground is low, the voltage drop due to a current drawn into Q placing Q above ground is
small. This low drop results in the output registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are complementary such that when the input is
low, the output is high, and when the input is high, the output is low. Because of this behavior of input and
output, the CMOS circuit's output is the inverse of the input.
The power supplies for CMOS are called VDD and VSS, or VCC and Ground(GND) depending on the
manufacturer. VDD and VSS are carryovers from conventional MOS circuits and stand for the drain and
source supplies. These do not apply directly to CMOS, since both supplies are really source supplies.
VCC and Ground are carryovers from TTL logic and that nomenclature has been retained with the
introduction of the 54C/74C line of CMOS.

Wafer Fabrication Techniques


Wafer fabrication is a procedure composed of many repeated sequential processes to produce
completeelectrical or photonic circuits. Examples include production of radio frequency (RF) amplifiers,
LEDs, optical computer components, and CPUs for computers. Wafer fabrication is used to build
components with the necessary electrical structures.
The main process begins with electrical engineers designing the circuit and defining its functions, and
specifying the signals, inputs, outputs and voltages needed. These electrical circuit specifications are

entered into electrical circuit design software, such as SPICE, and then imported into circuit layout
programs, which are similar to ones used for computer aided design. This is necessary for the layers to
be defined for photomask production. The resolution of the circuits increases rapidly with each step in
design, as the scale of the circuits at the start of the design process is already being measured in
fractions of micrometers. Each step thus increases circuit density for a given area.
The silicon wafers start out blank and pure. The circuits are built in layers in clean rooms. First,
photoresistpatterns are photo-masked in micrometer detail onto the wafers' surface. The wafers are then
exposed to short-wave ultraviolet light and the unexposed areas are thus etched away and cleaned. Hot
chemical vapors aredeposited on to the desired zones and baked in high heat, which permeate the
vapors into the desired zones. In some cases, ions, such as O2+ or O+, are implanted in precise patterns
and at a specific depth by using RF-driven ion sources.
These steps are often repeated many hundreds of times, depending on the complexity of the desired
circuit and its connections.
New processes to accomplish each of these steps with better resolution and in improved ways emerge
every year, with the result of constantly changing technology in the wafer fabrication industry. New
technologies result in denser packing of minuscule surface features such as transistors and micro-electromechanical systems (MEMS). This increased density continues the trend often cited as Moore's Law.
A fab is a common term for where these processes are accomplished. Often the fab is owned by the
company that sells the chips, such as AMD, Intel, Texas Instruments, or Freescale. A foundry is a fab at
which semiconductor chips or wafers are fabricated to order for third party companies that sell the chip,
such as fabs owned by Taiwan Semiconductor Manufacturing Company (TSMC), United Microelectronics
Corporation (UMC) and Semiconductor Manufacturing International Corporation (SMIC).

Transistor Sizing:

First of all, let us consider the sizing of an inverter. We have already seen that the propagation delay
of the gate is proportional to (Rp + Rn)CL. The delay of an inverter can be minimized by keeping the
output capacitance small or by decreasing the on resistance of the transistor. The C L consists of the
diffusion capacitance of the transistors, the interconnect capacitance and the fan-out capacitance.
Careful layout helps to reduce the diffusion and interconnect capacitances. The on-resistance of the
transistor is inversely proportional to the W/L ratio of the device. It is known that the mobility of holes
are approximately 2.5 times lower than that of electrons in Silicon. Thus, a 2.5 time wider PMOS
transistor is needed to match its on-resistance to that of pull-down NMOS device. With such a sizing
of NMOS and PMOS width, we can design an inverter with a symmetrical VTC (Voltage Transfer
Characteristics) and equal high-to-low and low-to-high propagation delays. The diffusion capacitance
is also increased with increasing widths and careful optimization is required.

Temperature Inversion:

It is known that with increase in temperate, the resistance of a metal wire(conductor)


increases. The reason for this phenomenon is that with increase in temperature, thermal
vibrations in lattice increase. This gives rise to increased electron scattering. One can
visualize this as electrons colliding with each other more and hence contributing less to the
streamline flow needed for the flow of electric current.
There is similar effect that happens in semiconductor and the mobility of primary carrier
decreases with increase in temperature. This applies to holes equally as well as electrons.
But in semiconductors, when the supply voltage of a MOS transistor is reduced, and
interesting effect is observed. At lower voltages the delay through the MOS device
decreases with increasing temperature, rather than increasing. After all common wisdom is
that with increasing temperature the mobility decreases and hence one would have
expected reduced current and subsequently reduced delay. This effect is also referred to as
low voltage Inverted Temperature Dependence.
Lets first see, what does the delay of a MOS transistor depend upon, in a simplified model.
Delay = ( Cout * Vdd )/ Id [ approx ]

Where
Cout = Drain Cap
Vdd = Supply voltage
Id = Drain current.
Now lets see what drain current depends upon.
Id = (T) * (Vdd Vth(T))
Where
= mobility
Vth = threshold voltage
= positive constant ( small number )
One can see that Id is dependent upon both mobility and threshold voltage Vth. Let
examine the dependence of mobility and threshold voltage upon temperature.
(T) = (300) ( 300/T )m
Vth(T) = Vth(300) (T 300)
here 300 is room temperature in kelvin.
Mobility and threshold voltage both decreases with temperature. But decrease in mobility
means less drain current and slower device, whereas decrease in threshold voltage means
increase in drain current and faster device.
The final drain current is determined by which trend dominates the drain current at a given
voltage and temperature pair. At high voltage mobility determines the drain current where as
at lower voltages threshold voltage dominates the drain current.
This is the reason, at higher voltages device delay increase with temperature but at lower
voltages, device delay increases with temperature.[20]

NAND Vs NOR

NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is
normally three times that of holes compared to NOR and thus the NAND is a faster gate. Additionally, the

gate-leakage in NAND structures is much lower. If you consider t_phl and t_plh delays you will find that it
is more symmetric in case of NAND ( the delay profile), but for NOR, one delay is much higher than the
other(obviously t_plh is higher since the higher resistance p mos's are in series connection which again
increases the resistance).

Latch Up Effect
A latch-up is a type of short circuit which can occur in an integrated circuit (IC). More specifically it is the
inadvertent creation of a low-impedance path between the power supply rails of a MOSFET circuit,
triggering a parasitic structure which disrupts proper functioning of the part, possibly even leading to its
destruction due to overcurrent. A power cycle is required to correct this situation.
A single event latch-up is a latch-up caused by a single event upset, typically heavy ions or protons from
cosmic rays or solar flares.
The parasitic structure is usually equivalent to a thyristor (or SCR), a PNPN structure which acts as a
PNP and an NPN transistor stacked next to each other. During a latch-up when one of the transistors is
conducting, the other one begins conducting too. They both keep each other in saturation for as long as
the structure is forward-biased and some current flows through it - which usually means until a powerdown. The SCR parasitic structure is formed as a part of the totem-pole PMOS and NMOS transistor pair
on the output drivers of the gates.

How to Prevent Latch Up Effect

by adding tap wells, for example in an Inverter for NMOS add N+ tap in n-well and conncet it to

Vdd, and for PMOS add P+ tap in p-substrate and connect it to Vss.
an increase in substrate doping levels with a consequent drop in the value of Rs.
reducing Rp by control of fabrication parameters and by ensuring a low contact resistance to Vss.
By Providing Guard rings

Latch Vs Flipflop (Advantages and Disadvantages)

Advantages and Disadvantages

1. In synthesis of HDL codes inappropriate coding can infer latches instead of flip flops. Eg.:if and case
statements. This should be avoided sa latches are more prone to glitches.
2. Latch takes less area, Flip-flop takes more area ( as flip flop is made up of latches) .
3. Latch facilitate time borrowing or cycle stealing whereas flip flops allow synchronous logic.
4. Latches are not friendly with DFT tools. Minimize inferring of latches if your design has to be made
testable. Since enable signal to latch is not a regular clock that is fed to the rest of the logic. To ensure
testability, you need to use OR gate using enable and scan_enable signals as input and feed the
output to the enable port of the latch.
5. Most EDA software tools have difficulty with latches. Static timing analyzers typically make
assumptions about latch transparency. If one assumes the latch is transparent (i.e.triggered by the active
time of clock,not triggered by just clock edge), then the tool may find a false timing path through the input
data pin. If one assumes the latch is not transparent, then the tool may miss a critical path.
6. If target technology supports a latch cell then race condition problems are minimized. If target
technology does not support a latch then synthesis tool will infer it by basic gates which is prone to race
condition. Then you need to add redundant logic to overcome this problem. But while optimization
redundant logic can be removed by the synthesis tool ! This will create endless problems for the design
team.
7. Due to the transparency issue, latches are difficult to test. For scan testing, they are often replaced by
a latch-flip-flop compatible with the scan-test shift-register. Under these conditions, a flip-flop would
actually be less expensive than a latch.
8. Flip flops are friendly with DFT tools. Scan insertion for synchronous logic is hassle free.

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