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Principle of I2C Bus and its Application in IC design

Li Yifan, Mo Fei
Multimedia Communication lab, Beijing University of Posts and Telecommuncations,
Beijing (100083)
Abstract
Compared with the parallel bus,I2C bus do require less wiring, fewer IC connection pins, and the less
number of traces required on printed circuit boards. So there are many applications of I2C bus in IC
design. In this paper,the principle and the operation of I2C bus will be introduced. Also the design of
I2C slave in FPGA and I2C master in PC which is simulated by the parallel ports will be discussed.
Keywords: I2C bus, parallel port communication

1. Introduction
As we all know, in consumer electronics, telecommunications and industrial electronics
nowadays, there are often many similarities between seemingly unrelated designs. For example,
nearly every system includes:
Some intelligent control, usually a single-chip microcontroller
General-purpose circuits like LCD drivers, remote I/O ports, RAM, EEPROM, or data
converters
Application

oriented circuits such as digital tuning and signal processing circuits for radio and
video systems, or DTMF generators for telephones with tone dialing.
To exploit these similarities to the benefit of both systems designers and equipment
manufacturers, as well as to maximize hardware efficiency and circuit simplicity, Philips
developed a simple bi-directional 2-wire bus for efficient inter-IC control. This bus is called the
Inter IC or I2C bus.
At present, Philips IC range includes more than 150 CMOS and bipolar I2C bust compatible
types for performing functions in all three of the previously mentioned categories. All I2C bus
compatible devices incorporate an on-chip interface which allows them to communicate directly
with each other via the I2C bus. This design concept solves the many interfacing problems
encountered when designing digital control circuits. [1]
In our project, we use I2C bus as the connect port to communicate with peripheral equipment.
We design an I2C slave in FPGA and make a program in PC to simulate the I2C master such as
SCM or MCU which will really control the FPGA in the future.
So in this paper, the principle and the operation of I2C bus will be introduced. Also the design
of I2C slave in FPGA and I2C master in PC will be discussed.

2. Principle of I2C Bus

The I2C bus is a popular two-wired, serial bus used in a complete system usually consisting of
at least one microcontroller and other peripheral devices with an advantage of its low overhead.
Although serial buses do not have the throughput capability of parallel buses, they do require less
wiring, fewer IC connection pins, and the less number of traces required on printed circuit boards.
Each device connected to the bus is software addressable by a unique address with a simple
Master/Slave protocol. Fast devices are able to communicate with slow devices.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit
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is sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (see START and STOP signals).[2]

2.1 Protocol of I2C bus

Normally, a standard communication consists of four parts:
1) START signal generation
2) Slave address transfer
3) Data transfer
4) STOP signal generation

Figure 1 : Standard Communication of I2C bus

2.1.1 START signal

When the bus is free/idle, meaning no master device is engaging the bus (both SCL and SDA
lines are high), a master can initiate a transfer by sending a START signal. A START signal,
usually referred to as the S-bit, is defined as a high-to-low transition of SDA while SCL is high.
The START signal denotes the beginning of a new data transfer.
2.1.2 Slave Address Transfer
The first byte of data transferred by the master immediately after the START signal is the
slave address. This is a seven-bits calling address followed by a RW bit. The RW bit signals the
slave the data transfer direction. No two slaves in the system can have the same address. Only the
slave with an address that matches the one transmitted by the master will respond by returning an
acknowledge bit by pulling the SDA low at the 9th SCL clock cycle.
2.1.3 Data Transfer
Once successful slave addressing has been achieved, the data transfer can proceed on a
byte-by-byte basis in the direction specified by the RW bit sent by the master. Each transferred
byte is followed by an acknowledge bit on the 9th SCL clock cycle. If the slave signals a No
Acknowledge, the master can generate a STOP signal to abort the data transfer or generate a
Repeated START signal and start a new transfer cycle.
If the master, as the receiving device, does not acknowledge the slave, the slave releases the SDA
line for the master to generate a STOP or Repeated START signal.
2.1.4 STOP signal
The master can terminate the communication by generating a STOP signal. A STOP signal,
usually referred to as the P-bit, is defined as a low-to-high transition of SDA while SCL is at
logical 1. Following is the operation examples of I2C bus
Example 1
Write 1 byte of data to a slave.
Slave address = 0x51 (b1010001)
Data to write = 0xAC
I2C Sequence:
1) Generate start command
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2) Write slave address + write bit

3) Receive acknowledge from slave
4) Write data
5) Receive acknowledge from slave
6) Generate stop command

Figure 2 : Master Write Sequence of I2C Bus

Example 2
Read a byte of data from an I2C memory device.
Slave address = 0x4E
Memory location to read from = 0x20
I2C sequence:
1) Generate start signal
2) Write slave address + write bit
3) Receive acknowledge from slave
4) Write memory location
5) Receive acknowledge from slave
6) Generate start signal
7) Write slave address + read bit
8) Receive acknowledge from slave
9) Read byte from slave
10) Write no acknowledge (NACK) to slave, indicating end of transfer
11) Generate stop signal

Figure 3 : Master Read Sequence of I2C Bus

3. Design of I2C Slave Core in FPGA

In the design, the master will ask the slave to read or write the interior registers. So what the slave
core does is something like the transformation between serial and parallel. Also the slave core
should connect to all the registers. Following is the block diagram of I2C slave core:

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8 bits address
datain and dataout
SCL
I2C
Interface

Master

Registers for
Input Part

Input

Registers for
Process Part

Process

Registers for
Output Part

Output

SDA

Slave Core
Figure 4 : Block Diagram of I2C Slave Core:

In our design, only 8 bits data after the R/W signal will be regard as the memory address so that
master can read or write several registers from one input address.
Following is the operation sequence:
In the master writer case, the sequence is:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

Master generates a start signal.

Master sends a salve device address + write bit.
Slave sends an acknowledge signal.
Master sends a memory address which to be written.
Slave sends an acknowledge signal.
Master sends the data1 and slave sends an acknowledge signal.
Master sends the data2 and slave sends an acknowledge signal.
.
.
.
Master sends a stop signal.

And in the master read case, the sequence is:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

Master generates a start signal.

Master sends a salve device address + write bit.
Slave sends an acknowledge signal.
Master sends a memory address which to be read.
Slave sends an acknowledge signal.
Master generates a stop signal.
Master generates a start signal.
Master sends the salve device address + read bit.
Slave sends an acknowledge signal.
Master receives the data_1 and sends an acknowledge signal.
Master receives the data_2 and sends an acknowledge signal.
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12.
13.
14.
15.

.
.
Master receives the data_n and sends a stop signal.

From the sequence, we can know that:

Master can read and write several data from a serial address by only sending one address. The
serial address will add one automatically each time.
Master device must stop the existing operation and sent a start signal not only when changing the
read and write mode but also when changing the memory address.
Also we can see the operation from the flow chart

Output
serially

Idle
N

Receive 8 bits
And device address right ?

Send ACK

Read bit is
1?

Send 8 bits ?

Receive 8
bits ?

Prepare the data

of next address
register

Send ACK
Read bit is
1?

Receive ACK

Address + 1

Prepare the data

and output
serially
Read bit is
1?

Wait for
memory address
N

Sda output
1?

N
Y

Receive 8
bits ?

Idle
Y

Send ACK

Figure 5: Flow Chart of the I2C Slave Core Operation

To test if the slave core works, an I2C master module is coded in verilog. The master read or
writes four serial registers in four serial addresses once time. We use ncverilog to do the
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simulation, the master write the data to the register first and then read the data from the
corresponding register to see if the data is the same.
Following is the waveform after simulation:

Figure 6: Waveform of Writing and Reading the Same Address

We use the SimVision to see the waveform of the simulation.

In the figure, WRmemS is the write flag signal and the RDmemS is the read flag signal.
mem_AdrS is 8 bits Address to which the master do the operation.
wr_data is 8 bits data the master prepare to write to the register.
mem_data is 8 bits data the master read from the register.
From the waveform, we can see the master writer data 0x12, 0x34, 0x56 and 0x78 to address 0x05,
0x06, 0x07 and 0x08 separately first and read the same four addresses. The data read from the
addresses is the same as the data write into. The I2C slave core works well.

Figure 7: Waveform of Writing Address from 0x05 to 0x08

As we introduced above, the master should write a start address before writing and reading data.
The slave core receives the mem_AdrS first and receives the wr_data while the WRmemS occurs.
After that the address adds one automatically and waits the next WRmemS to receive the new
data.

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Figure 8: Waveform of Reading Address from 0x05 to 0x08

The slave core also receives the address first and prepares the data for master to read while the
RDmemS occurs. After that the address also adds one automatically and waits the next RDmemS
to prepare the new data.

4. Design of I2C master in PC

After RTL code design, we should download it to the FPGA and do the real R/W test.
We use the PC to simulate the I2C master and use the parallel port as the I2C bus. To transform the
parallel port to the simple 2-wire bus, a cable transform the DB25 interface in PC to interface of
FPGA board is necessary. Following is the cable which we use:

Figure 9: Cable Transform from DB25 to DB9

Also we design software to communicate with the FPGA in VC++.

The software can read and write any byte data from any address. Also it can read and write
specifically register.
Following is the software of I2C master:

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Figure 10: Software of I2C Master

The bottom Initialize will pull up all the sda and scl line to initialize the I2C bus.
The bottom Write or Read will write or read Byte Num data to the address from the Start
Address. Byte Num means how many bytes the master will write or read.
When Write, master will get the data which to be write from the specifically txt file and write
them to the registers in FPGA.
When Read, master will read the data from the registers in FPGA and save them into the
specifically txt file.
The bottom Set 0 or Set 1 will set zero or one to any Bit of the register whose address is Start
Address.
The bottom Read All will read all the registers and display their values on the edit block of each
address.
The bottom Write All will write the data which input into each edit block to corresponding
address.
Follow figure shows the Read All operation:

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Figure 11: Read All Register Values Using I2C Master Software

5. Conclusion
In the paper, the principle of I2C bus is introduced detailedly. Also the design both I2C slave and
master are presented. The I2C slave core is tested not only in software by the simulation but also
in hardware by really connect to the PC which works like an I2C master device. The whole
communication through I2C bus is very helpful to anyone want to use this simple 2-wire bus and
useful in IC design.

Reference
[1] Philips Semiconductors (2000) The I2C-Bus Specification
[2] Richard Herveille (2003) I2C Master Core Specification Open Cores
[3] Wenyu Xia (2003) Digital system Design Tutorial --- Verilog
[4] Zhi Liu, JIngyi Yang (2003) Development and Application of I2C Simulation Software Kit Based on Parallel
Ports
[5] Wen Zhang (2002) Test of Simulation I2C Bus by PC Parallel Ports
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