CHAPTER 1

OVERVIEW OF THESIS
1.1 INTRODUCTION
WIRELESS LAN (WLAN) in the multigigahertz bands, such as Hiper LAN II
and IEEE 802.11a/b/g, are recognized as leading standards for high-rate data
transmissions, and standards like IEEE 802.15.4 are recognized for low-rate data
transmissions. The demand for lower cost, lower power, and multiband RF circuits
increased in conjunction with need of higher level of integration. The frequency
synthesizer, usually implemented by a Phase-Locked Loop (PLL), is one of the powerhungry blocks in the RF front-end and the first-stage frequency divider consumes a large
portion of power in a frequency synthesizer. Dynamic latches are faster and consume less
power compared to static dividers. The frequency synthesizer reported in uses a prescaler
as the first-stage divider, but the divider consumes Power. Most IEEE 802.11a/b/g
frequency synthesizers employ SCL dividers as their first stage, while dynamic latches
are not yet adopted for multiband synthesizers. In this paper, a dynamic logic multiband
flexible integer-N divider based on pulse-swallow topology is proposed which uses a
low-power wideband 4/5 prescaler and a wideband multi modulus 64/65/79/80 prescaler.
The divider also uses an improved low-power loadable bit-cell for the Swallow S counter.
The frequency synthesizer is one of the basic building blocks in modern
communication systems. The operating frequency of the frequency synthesizer is limited
by the frequency divider and the Voltage-Controlled Oscillator. The function of channel
selection in the frequency synthesizer demands programmable division ratios for the
frequency divider. The integer-N frequency synthesizer is more practical, less costly and
of low spurious sideband performance as compared with the fractional-N frequency
synthesizer. It is usually formed by a prescaler, a Program Counter (P counter) and a
Swallow Counter(S counter). Such a topology can provide a programmable division ratio
of NP + S, where N, P and S are the division ratios of three blocks respectively. The
prescaler provides a dual-modulus of N=N +1.

The P counter provides a fixed division ratio according to the requirement of the
overall division ratio, while the continuous division ratios from 0 to 48 is achieved
through the S counter by periodically reloading the divide-by-2 stages, where n is the
number of stages of the S counter. The continuous division

ratio is used to select the

desired channels. Much research has been focused on the prescaler design for its highest
operating frequency. However, in the modern communication system, there is an
increasing demand for multi-standards applications. The requirement for wide band and
high resolution operations continue to be the problems. To satisfy these requirements,
different reference frequencies, and different arrangement for N, P and S counters are
selected for different applications. In this project, a new wide-band high resolution
programmable frequency divider is proposed. The wide band and high resolution are
obtained by using the all-stage programmable topology in both counters.
The high-speed frequency divider is a key block in frequency synthesis. The
prescaler is the most challenging part in the high-speed frequency-divider design because
it operates at the highest input frequency. A dual-modulus prescaler usually consists of a
divide-by-2/3 (or 4/5) unit followed by several asynchronous divide-by-2 units. The
operation of the divide-by-2/3 unit at the highest input frequency makes it the bottleneck
of the prescaler design. To achieve the two different division ratios, D Flip-Flops (DFFs)
and additional logic gates, which reduce the operating frequency by introducing an
additional propagation delay, are used in the unit. The power consumption of this divideby-2/3 unit, which is the greatest portion of the total power consumption in the prescaler,
significantly increases due to the power consumption of the additional components.

CHAPTER 2
LITERATURE SURVEY
2.1 A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency dividerLevantino, S.; Samori, C.; Lacaita, A.L.-Feb. 2004.
DESCRIPTION: The adoption of dynamic dividers in CMOS Phase-Locked Loops for
multigigahertz applications allows to reduce the power consumption substantially without
impairing the phase noise and the power supply sensitivity of the Phase-Locked Loop
(PLL). A 5-GHz frequency synthesizer integrated in a 0.25-m CMOS technology
demonstrates a total power consumption of 13.5 mW. The frequency divider combines
the conventional and the extended true-single-phase-clock logics. The oscillator employs
a rail-to-rail topology in order to ensure a proper divider function. This PLL intended for
wireless LAN applications can synthesize frequencies between 5.14 and 5.70 GHz in
steps of 20 MHz A low-power 5-GHz CMOS frequency synthesizer for wireless LAN
transceivers has been presented. The PLL integrated in a 0.25- m CMOS technology
consumes only 13.5 mW, thanks to a dynamic TSPC divider. This class of dividers is
demonstrated to be suitable for multigigahertz synthesizers, since it does not impair the
power supply rejection or the phase noise performance. WIRELESS LAN systems in the
56-GHz band, such as HiperLAN II and IEEE 802.11a, are recognized as the leading
standards for high-rate data transmissions. Being intended for mobile operations, the
radio transceiver has a limited power budget. The frequency synthesizer, usually
implemented by a Phase-Locked Loop (PLL), is one of the most critical blocks in terms
of average current dissipation since it operates extensively for both receiving and
transmitting. The best published integrated synthesizers around 5 GHz suitable for
wireless LAN receivers consume up to 25mWin both CMOS and bipolar realizations.
Other synthesizers embedded in 802.11a-compliant transceivers can consume up to 200
mW.

DISADVANTAGES OF EXISTING METHOD:

This high power consumption is mainly due to the first stages of the frequency
divider that often dissipates half of the total power. Due to the high input
frequency, the first stage of the divider cannot be implemented in conventional
static CMOS logic.

Instead, it is commonly realized in Source-Coupled Logic (SCL), which allows

higher operating frequency, but burns more power.

ADVANTAGES OF PROPOSED METHOD:

Dynamic latches are known to be faster and more compact than static ones. The
True-Single-Phase-Clock (TSPC) design allows to drive the dynamic latch with
a single clock phase, thus avoiding the skew problem.

The use of dynamic logic is not only possible up to 6 GHz, but also extremely
effective in reducing the synthesizer power dissipation.

2.2 Design and Optimization of the Extended True Single-Phase Clock-Based

Prescaler -Xiao Peng Yu; Manh Anh Do; Wei Meng Lim; Kiat Seng Yeo; JianGuo Ma- : Nov.2006
DESCRIPTION:

The power consumption and operating frequency of the Extended

True Single-Phase Clock (E-TSPC)-based frequency divider is investigated. The shortcircuit power and the switching power in the E-TSPC-based divider are calculated and
simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented
using a CMOS technology. Compared with the existing design, a 25% reduction of power
consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this
divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz
with low-power consumption. The prescaler is implemented in low-power highresolution frequency dividers for wireless local area network applications. The design and
optimization of a high-speed E-TSPC-based prescaler has been carried out by
investigation of the operating frequency and power consumption of the E-TSPC circuit. A
new divide-by-2/3 unit with low power consumption has been proposed. It is suitable for
4

the high-speed CMOS prescaler design. A divide-by-8/9 dual-modulus prescaler

implemented with the proposed unit has been implemented to achieve the ultra-lowpower consumption. The dual-modulus operation above 4 GHz in the TSPC-based
prescaler has first been achieved. The prescaler has been implemented in high-resolution
frequency dividers. It is suitable for the wireless communication system below 4 GHz.
The operation of this proposed prescaler and frequency divider have also been silicon
verified. The high-speed frequency divider is a key block in frequency synthesis. The
prescaler is the most challenging part in the high-speed frequency-divider design because
it operates at the highest input frequency. A dual-modulus prescaler usually consists of a
divide-by-2/3 (or 4/5) unit followed by several asynchronous divide-by-2 units. The
operation of the divide-by-2/3 unit at the highest input frequency makes it the bottleneck
of the prescaler design.
DISADVANTAGES OF EXISTING METHOD:

The Extended True Single-Phase Clock (E-TSPC) logic is proposed to increase

the operating frequency. However, this causes additional power consumption.

In modern wireless communication systems, the power consumption is a key

consideration for the longer battery life. The MOS Current Mode Logic
(MCML) circuit, which is of high power consumption, is commonly used to
achieve the high operating frequency, while a True Single-Phase Clock (TSPC)
dynamic circuit, which only consumes power during switching, has a lower
operating frequency.

ADVANTAGES OF PROPOSED METHOD:

In this paper, the power consumption and operating frequency in the E-TSPC
logic style is evaluated. The two major sources of power consumption, namely,
the short-circuit power and the switching power, in the E-TSPC divide- by-2 unit

is calculated and simulated.

Based on the analysis, a new divide-by-2/3 unit is proposed to achieve the low
power consumption by reducing the switching activities and the short-circuit
current in the DFFs of the unit, and a dual-modulus prescaler implemented with
the unit is proposed.
5

2.3 A Dynamic-Logic Frequency Divider for 5-GHz WLAN Frequency SynthesizerYue-Fang Kuo and Ro-Min Weng- National Dong Hwa University Hualien, Taiwan,
Republic of China.
DESCRIPTION:

A dynamic-logic frequency divider for fully integrated CMOS

frequency synthesizer is presented in this paper. The divider based on the dual-modulus
prescaler and dynamic logic circuit is designed to reduce the power consumption,
transistor-counts, and chip area. The simulation results show the proposed circuit
achieved the operating frequency band from 5.15GHz to 5.825GHz for wireless local
area network applications. A simple architecture of the dynamic-logic frequency divider
has been demonstrated in a standard 0.18m CMOS technology. The frequency divider is
designed without counters and the simulation results show the advantages in low power
consumption and less chip area. The proposed frequency divider achieves the operating
frequency bands form 5.15GHz and 5.825GHz in steps of 20MHz, which covers 15
channels in WLAN applications. IEEE 802.11a and HiperLAN are standards of wireless
data networks with frequency band operated from 5 to 6GHz which covers fifteen
channels with a channel spacing of 20MHz. The frequency synthesizers are widely used
to generate Local Oscillation (LO) signals in modern communication systems. In order to
cover the required carries and operate from input frequency of 5GHz, the division of the
divider has to be programmed from 257 to 294. The operating frequency of a frequency
synthesizer is limited by the frequency divider as well as the Voltage Controlled
Oscillator (VCO).
DISADVANTAGES IN EXISTING METHOD:

For WLAN standard, most common high-speed frequency are based on pulseswallow architecture. The architectures require two additional counters for
generation of a desired division ratio. It occupies many gate-counts, large chip

area, and consumes extra power.

The high power consumption is mainly due to the first stages of the frequency
divider that often consumes half of the total power. The first stage of the divider
cannot be implemented in dynamic TSPC circuit

ADVANTAGES OF PROPOSED METHOD:

This paper proposes a new frequency divider keeping the same function as a
conventional one without employing a sallower counter to consume takes extra
power and unnecessary chip area.

The proposed topology is based on the counter-less and dual-modulus counter

detector.

2.4

Design of a low power wideband high resolution programmable frequency

divider- X. P. Yu et al. - Sep. -2005

DESCRIPTION: The design of a high-speed wide-band high resolution programmable
frequency divider is investigated. A new reloadable D flip-flop for the high speed
programmable frequency divider is proposed. It is optimized in terms of propagation
delay and power consumption as compared with the existing designs. Measurement
results show that an all-stage programmable counter implemented with this D flip-flop
using the Chartered 0.18 m CMOS process is capable of operating up to 1.8 GHz for a
1.8 V supply voltage and 5.8-mW power consumption. By using this counter, an ultrawide range high resolution frequency divider is achieved with low power consumption
for 56-GHz wireless LAN applications. The design difficulties of the wide-band high
resolution programmable frequency divider for multi-standard application are
investigated. A high speed low power counter is successfully implemented for multistandard operations. Measurements results show the first GHz all-stage programmable
divider with low power consumption is achievable with the proposed bit cell.
DRAWBACKS OF EXISTING METHOD:

The frequency synthesizer is one of the basic building blocks in modern

communication systems. The operating frequency of the frequency synthesizer is
limited by the frequency divider and the voltage-controlled oscillator. The
function of channel selection in the frequency synthesizer demands programmable
division ratios for the frequency divider.

Much research has been focused on the prescaler design for its highest operating
frequency. However, in the modern communication system, there is an increasing
demand for multi-standards applications.
7

ADVANTAGES OF PROPOSED METHOD:

A new wide-band high resolution programmable frequency divider is proposed.

The wide band and high resolution are obtained by using the all-stage
programmable topology in both counters.

2.5 4.2 mW frequency synthesizer for 2.4 GHz Zigbee application with fast settling
Time performance- S. Shin et al.,- Jun. 2006 .
DESCRIPTION: A new frequency synthesizer with low-power and short settling time is
introduced. With two-point channel controls for an integer-N PLL, we have achieved a
near zero settling time for any frequency change in 2.4GHz Zigbee band. By utilizing a
vertical-NPN parasitic transistor for the VCO biasing, the close-in phase noise has been
improved by 5dB from the case of MOS biasing. A modified-TSPC topology is proposed
for low-voltage frequency divider circuits. Using the 1.2V supply voltage for 0.18mum
CMOS, the power consumption is only 4.2Mw. New frequency synthesizer architecture
with very low power and short frequency settling time was introduced. A two-point
channel control scheme was used for our proposed frequency synthesizer in which a
DAC with tunable gain and a linearized VCO are used to effectively compensate the gain
mismatch between the two control paths. Despite the use of an integer-N architecture
with narrow 20kHz bandwidth, we have achieved near zero frequency settling time
within the accuracy of the measurement equipment for the 75MHz frequency jumping
from 2.4GHz.The battery life for mobile applications is inversely proportional to the
energy consumption of mobile devices. Thus it is important to minimize the energy
consumption by minimizing both the active duty-cycle and the active power consumption
of a wireless terminal concurrently.

DISADVANTAGES OF EXISTING METHOD:

The frequency settling time of a PLL decreases as the loop-bandwidth increases.

However, it requires a high frequency fractional controller thus increases the
hardware complexity and active power consumption.
8

ADVANTAGES OF PROPOSED METHOD:

In this paper, a new frequency synthesizer with very short frequency settling time

and low active power consumption is introduced.

For short frequency settling time, a two-point channel control scheme composed
of a direct-VCO control (compensation-path) and a divider control (main-path) is
used.

CHAPTER 3
EXISTING SYSTEM
3.1 BLOCK DIAGRAM
9

Figure.3.1 Existing Dynamic logic multiband flexible divider

1.
2.
3.
4.

Wideband 2/3 prescaler

Multimodulus 32/33/47/48 prescaler
Swallow P-counter
Swallow S-counter

3.1.1 MODULE DESCRIPTION

3.1.1.1 WIDEBAND 2/3 PRESCALER
The E-TSPC 2/3 prescaler reported in consumes large short-circuit power and has
a higher frequency of operation than that of 2/3 prescaler. The wideband single-phase
clock 2/3 prescaler used in this design consists of two D-flip-flops and two NOR gates
embedded in the flip-flops as in Fig. 3.2. The first NOR gate is embedded in the last stage
of DFF1, and the second NOR gate is embedded in the first stage of DFF2. Here, the
transistors M2, M25, M4, and M8 in DFF1 helps to eliminate the short-circuit power
during the divide-by-2 operation. The switching of division ratios between 2 and 3 is
controlled by logic signal MC.

10

Fig. 3.2 Wideband Single-Phase Clock 2/3 Prescaler

When MC switches from 0 to 1 transistors M2, M4 and M8 in DFF1 turns off
and the nodes S1, S2 and S3 switch to logic 0. Since node S3 is 0 and the other input
to the NOR gate embedded in DFF2 is Qb, the wideband prescaler operates at the divideby-2 mode. During this mode, nodes S1, S2 and S3 switch to logic 0 and remain at 0
for the entire divide-by-2 operation, thus removing the switching power contribution of
DFF1. Since one of the transistors is always OFF in each stage of DFF1, the short-circuit
power in DFF1 and the first stage of DFF2 is negligible. The total power consumption of
the prescaler in the divide-by-2 mode is equal to the switching power in DFF2 and the
short-circuit power in second and third stages of DFF2.
n

Pwideband-divide-by-2=

fclkCLiVdd 2
i=1

+Psc1+psc2

Where CLi is the load capacitance at the output node of the ith stage of DFF2,
n=4 and Psc1 and Psc2 are the short-circuit power in the second and third stages of
DFF2. When logic signal MC switches from 1 to 0, the logic value at the input of
DFF1 is transferred to the input of DFF2 as one of the input of the NOR gate embedded
11

in DFF1 is 0 and the wideband prescaler operates at the divide-by-3 mode. During the
divide-by-2 operation, only DFF2 actively participates in the operation and contributes to
the total power consumption since all the switching activities are blocked in DFF1. Thus,
the wideband 2/3 prescaler has benefit of saving more than 50% of power during the
divide-by-2 operation.
3.1.1.2 MULTIMODULUS 32/33/47/48 PRESCALER
The proposed wideband multimodulus prescaler which can divide the input
frequency by 32, 33, 47, and 48 is shown in Fig 3.3. It is similar to the 32/33 prescaler
used in, but with an additional inverter and a multiplexer. The proposed prescaler
performs additional divisions (divide- by-47 and divide-by-48) without any extra flipflop, thus saving a considerable amount of power and also reducing the complexity of
multiband divider. The multimodulus prescaler consists of the wideband 2/3 (N1/
(N+1))prescaler four asynchronous TSPC divide-by-2 circuits ((AD)=16)

and

combinational logic circuits to achieve multiple division ratios. Beside the usual MOD
signal for controlling N (N+1) divisions, the additional control signal Sel is used to
switch the prescaler between 32/33 and 47/48 modes.

Fig. 3.3 Multimodulus 32/33/47/48 Prescaler

Case 1: Sel=0
12

When Sel=0 , the output from the NAND2 gate is directly transferred to the input
of 2/3 prescaler and the multimodulus prescaler operates as the normal 32/33 prescaler,
where the division ratio is controlled by the logic signal MOD. If MC=1, the 2/3
prescaler operates in the divide-by-2 mode and when MC=0, the 2/3 prescaler operates in
the divide-by-3 mode.
If MOD =1, the NAND2 gate output switches to logic 1 (MC=1)and the wideband
prescaler operates in the divide- by-2 mode for entire operation. The division ratio N
performed by the multimodulus prescaler is
N = (AD*N1) + (0*(N1+1)) = 32 4
Where N=2 and AD=16 is fixed for the entire design. If MOD=0 , for 30 input
clock cycles MC remains at logic 1, where wideband prescaler operates in divide-by-2
mode and, for three input clock cycles, MC remains at logic 0 where the wideband
prescaler operates in the divide-by-3 mode. The division ratio N+1 performed by the
multimodulus prescaler is
N + 1 = ((AD 1)*N1) + (1*(N1+1)) =33 5

Case 2: Sel = 1
When Sel = 1, the inverted output of the NAND2 gate is directly transferred to the
input of 2/3 prescaler and the multimodulus prescaler operates as a 47/48 prescaler,
where the division ratio is controlled by the logic signal MOD. If MC = 1, the 2/3
prescaler operates in divide-by-3 mode and when MC=0, the 2/3 prescaler operates in
divide-by-2 mode which is quite opposite to the operation performed when Sel=0.
If MOD = 1, the division ratio N+1 performed by the multi modulus prescaler is same as
except that the wideband prescaler operates in the divide-by-3 mode for the entire
operation
Given by
N + 1 = ((AD *(N1+1)) + (0*N1)) = 48 6
If MOD = 1, the division ratio N performed by the multi modulus prescaler is
13

N = ((AD - 1) * (N1+1)) + (1*N1) = 47 7

3.1.1.3 PROGRAM COUNTER
The program counter is responsible for counting P pulses of Slow CLK before
outputting a pulse to the phase/frequency detector and resetting itself and the swallow
counter. The implementation used in this project, using a 7-bit ripple counter, a 7-bit
comparator, and a zero-detector is shown in Figure3.4. The ripple counter is clocked by
SlowCLK, and increments its count by one each clock cycle. At each stage, the 7-bit
comparator compares each count bit to the corresponding bit in the control signal, and
outputs a 0 for each equal bit. When the zero-detector detects equivalence in all of the 7
bits, indicating that the desired count has been reached, Fout is driven high. On the next
clock cycle, the program counter is reset to zero and the count is restarted. In addition,
the output pulse on Fout is used to reset the count of the swallow counter, indicating the
end of one complete cycle of the frequency divider.

Fig.3.4.Block Diagram of a 7-Bit Program Counter

The ripple counter is implemented using 7 cascaded D-type flip-flops, each
arranged in a toggle configuration. The output of each flip-flop is used to clock the next
flip-flop. Since the output of each flip-flop inverts on every clock cycle, each flip-flop
14

essentially divides its clock by two, causing the next stage of the ripple counter to be
clocked at half the rate of the previous flip flop. Each flip-flop was designed to respond
to the falling edge of its clock, when the output of the previous stage changes from a 1 to
a 0. In this way, an incrementing binary count is achieved with the outputs of each flipflop forming the bits of the count. Since the program counter contains 7-bits, any count
between 0 and 127 can be set by the control signal. It is important to realize however that
in order to achieve a division ratio as specified in the equation DIV=NP+S, the control
signal must be set to P-1, since the zero-state is included in the count.
P-Counter Implementation
It is possible to see the three major components of the program counter
implemented using MCML logic gates. At the input of the counter, an array of 7 flip-flops
is used as the ripple counter. The outputs of the ripple counter, taken from the outputs of
each of the flip-flops, are fed into an array of 7 XNOR gates. The XNOR gates compare
each bit with the corresponding bit in the control signal, outputting a logical 1 when the
bits are equal. Although this logic is inverted compared to the description of the
comparator in the previous section, the zero-detector is implemented as a one-detector
using a tree of cascaded AND gates. In this way, the overall logic of the circuit is
unchanged, and the output pulse can be generated without any additional logic.
Another difference seen is a separate output, Swallow RST, and some simple
circuitry used to generate it. Swallow RST is used internally to reset the flip-flops of the
program counter, and externally to reset the flip-flops of the swallow counter. Since the
fan-out of the reset signal is high (7 flip-flops in the PC, and 6 in the SC), the reset signal
is broken into two paths and driven using separate MCML buffers. In early simulations,
these buffers were absent and the reset signal could not provide enough current to drive
the input capacitance associated with the flip-flops. Swallow RST was generated using
an approach that guarantees predictable timing of the reset signal. Fout is tapped and
fed to the input of a flip-flop clocked by Fin. On the clock cycle immediately following
Fout going high, the pulse is sampled by the flip-flop, generating Swallow RST and
resetting both the program counter and the swallow counter. To ensure that the reset

15

signal is removed before the next clock cycle, the reset signal is fed back to its generating
flip-flop through a delay chain comprised of three buffers.
3.1.1.4 SWALLOW COUNTER
The swallow counter, as indicated in Figure 3.5, is used to count S pulses of Slow
CLK before asserting the modulus control signal and changing the modulus of the DMP
to N. The similarities between the swallow counter and the program counter are apparent.
Once again, the count (6-bits in this case) is maintained using a ripple counter comprised
of cascaded flip-flops clocked with SlowCLK. In addition, a comparator compares each
count bit with its corresponding bit in the control signal, and a zero-detector asserts
modulus control when all bits are equal. However, the swallow counter does not reset
when the count is reached, but masks the input clock using an AND gate connected to the
inverse of modulus control. As a result, the ripple counter stops counting when the count
is reached, and the state of the circuit is maintained until a reset signal (SwallowRST) is
received from the program counter. Since the swallow counter contains 6 bits, it is
capable of any count from 0 to 64. Once again, the control signal must be set to S-1, since
the zero-state is included in the count.

Fig.3.5 Block Diagram of a 6-Bit Swallow Counter

16

The 6-bit ripple counter implemented as an array of flip-flops, and clocked with
the gated clock provided by the AND of Slow CLK and modulus control. In addition, the
comparator is implemented as an array of MCML XNOR gates, while the zero-detector is
actually implemented as a one-detector using a tree of cascaded AND gates. Unlike the
program counter however, no additional circuitry is necessary to generate the reset as the
reset is received from the program counter by means of the Swallow RST signal.

17

CHAPTER 4
POWER OPTIMISATION OF SINGLE-PHASE CLOCK
MULTIBAND FLEXIBLE DIVIDER
4.1 PROPOSED SYSTEM
The proposed wideband multimodulus prescaler which can divide the input
frequency by 64, 65, 79 and 80. It is similar to the 32/33/47/48 prescaler, but with an
additional inverter and a multiplexer. The proposed prescaler performs additional
divisions (divide- by-79 and divide-by-80) without any extra flip-flop, thus saving a
considerable amount of power and also reducing the complexity of multiband divider.
The multimodulus prescaler consists of the wideband 4/5 (N1/(N1+1)) prescaler, four
asynchronous TSPC divide-by-2 circuits (AD=16) and combinational logic circuits to
achieve multiple division ratios. Beside the usual MOD signal for controlling (N/N+1)
divisions, the additional control signal Sel is used to switch the prescaler between 64/65
and 79/80 modes. Advantages in proposed system are best performance on power
consumption, efficient architecture in silicon verification.
4.1.1 OBJECTIVE
A dynamic logic multiband flexible integer-N divider based on pulse-swallow
topology is proposed which uses a low-power wideband 4/5 prescaler and a wideband
multi modulus 64/65/79/80 prescaler. To achieve high-rate data transmissions and low
rate data transmissions.

4.1.2 DESIGN METHODOLOGIES

The key parameters of high-speed digital circuits are the propagation delay and
power consumption. The maximum operating frequency of a digital circuit is calculated.
Fmax = 1/(tp LH + tp HL ) . 1
where tp LH and tp HL are the propagation delays of the low-to-high and highto-low transitions of the gates, respectively. The total power consumption of the CMOS
18

digital circuits is determined by the switching and short circuit power. The switching
power is linearly proportional to the operating frequency and is given by the sum of
switching power at each output node as in
n

P switching=

fclkCLiVdd 2
i=1

where n is the number of switching nodes, Fclk is the clock frequency, CLi is the
load capacitance at the output node of the ith stage, and Vdd is the supply voltage.
Normally, the short-circuit power occurs in dynamic circuits when there exists direct
paths from the supply to ground which is given by
P sc = I sc * V dd 3
where Isc is the short-circuit current. The analysis shows that the short-circuit
power is much higher in E-TSPC logic circuits than n TSPC logic circuits. However,
TSPC logic circuits exhibit higher switching power compared to that of E-TSPC logic
circuits due to high load capacitance. For the E-TSPC logic circuit, the short-circuit
power is the major problem. The E-TSPC circuit has the merit of higher operating
frequency than that of the TSPC circuit due to the reduction in load capacitance, but it
consumes significantly more power than the TSPC circuit does for a given transistor size.
The following analysis s based on the latest design using the popular and low-cost 0.18microm CMOS process.
4.2 PROPOSED 4/5 PRESCALER:
The 4/5 prescaler reported in consumes large short circuit power and has a higher
frequency of operation than that of 2/3 prescaler. The wideband single-phase clock 4/5
prescaler used in this design, which consists of three D-flip-flops and two nand gates
embedded.
The Multi prescaler 4by5 consist of Four D-flip flop, two Nand gates, and two OR
gates one Not gate with main 4/5 prescaler circuit. The multi modulus prescaler operates
as the normal 64/65/79/80.

19

Fig 4.1 4/5 Prescaler

4.3 MULTIPRESCALER_4BY5:
The proposed wideband multimodulus prescaler which can divide the input
frequency by 64, 65, 79 and 80 is shown in Fig. 4.2 It is similar to the 32/33 prescaler
used in, but with an additional inverter and a multiplexer. The proposed prescaler
performs additional divisions (divide- by-79 and divide-by-80) without any extra flipflop, thus saving a considerable amount of power and also reducing the complexity of
multiband divider. The multimodulus prescaler consists of the wideband 2/3 (N1/
(N+1))prescaler , four asynchronous TSPC divide-by-2 circuits ((AD)=16)

and

combinational logic circuits to achieve multiple division ratios. Beside the usual MOD
signal for controlling N/(N+1) divisions, the additional control signal Sel is used to
switch the prescaler between 64/65 and 79/80 modes.

Fig.4.2 Multiprescaler_4by5
20

4.4 PROPOSED MULTIBAND FLEXIBLE DIVIDER

Fig 4.3 Proposed Multiband Flexible Divider

Our proposed multiband flexible divider is Combined by 2/3 Prescaler and 4/5
Prescaler in multi modulus Prescaler. By using Mux we can operate either 2/3 Prescaler
and 4/5 Prescaler. It will operate 32/33/47/48 or 64/65/79/80 bandwidth.
4.4.1 PROGRAM COUNTER
The program counter is responsible for counting P pulses of Slow CLK before
outputting a pulse to the phase/frequency detector and resetting itself and the swallow
counter. The implementation used in this project, using a 7-bit ripple counter, a 7-bit
comparator, and a zero-detector is shown in Figure4.4. The ripple counter is clocked by
SlowCLK, and increments its count by one each clock cycle. At each stage, the 7-bit
comparator compares each count bit to the corresponding bit in the control signal, and
outputs a 0 for each equal bit. When the zero-detector detects equivalence in all of the 7
bits, indicating that the desired count has been reached, Fout is driven high. On the next
clock cycle, the program counter is reset to zero and the count is restarted. In addition,
21

the output pulse on Fout is used to reset the count of the swallow counter, indicating the
end of one complete cycle of the frequency divider.

Fig.4.4 Block Diagram of a 7-Bit Program Counter

The ripple counter is implemented using 7 cascaded D-type flip-flops, each
arranged in a toggle configuration. The output of each flip-flop is used to clock the next
flip-flop. Since the output of each flip-flop inverts on every clock cycle, each flip-flop
essentially divides its clock by two, causing the next stage of the ripple counter to be
clocked at half the rate of the previous flip flop. Each flip-flop was designed to respond
to the falling edge of its clock, when the output of the previous stage changes from a 1 to
a 0. In this way, an incrementing binary count is achieved with the outputs of each flipflop forming the bits of the count. Since the program counter contains 7-bits, any count
between 0 and 127 can be set by the control signal. It is important to realize however that
in order to achieve a division ratio as specified in the equation DIV=NP+S, the control
signal must be set to P-1, since the zero-state is included in the count.

22

P-Counter Implementation
It is possible to see the three major components of the program counter
implemented using MCML logic gates. At the input of the counter, an array of 7 flip-flops
is used as the ripple counter. The outputs of the ripple counter, taken from the outputs of
each of the flip-flops, are fed into an array of 7 XNOR gates. The XNOR gates compare
each bit with the corresponding bit in the control signal, outputting a logical 1 when the
bits are equal. Although this logic is inverted compared to the description of the
comparator in the previous section, the zero-detector is implemented as a one-detector
using a tree of cascaded AND gates. In this way, the overall logic of the circuit is
unchanged, and the output pulse can be generated without any additional logic.
Another difference seen is a separate output, Swallow RST, and some simple
circuitry used to generate it. Swallow RST is used internally to reset the flip-flops of the
program counter, and externally to reset the flip-flops of the swallow counter. Since the
fan-out of the reset signal is high (7 flip-flops in the PC, and 6 in the SC), the reset signal
is broken into two paths and driven using separate MCML buffers. In early simulations,
these buffers were absent and the reset signal could not provide enough current to drive
the input capacitance associated with the flip-flops. Swallow RST was generated using
an approach that guarantees predictable timing of the reset signal. Fout is tapped and
fed to the input of a flip-flop clocked by Fin. On the clock cycle immediately following
Fout going high, the pulse is sampled by the flip-flop, generating Swallow RST and
resetting both the program counter and the swallow counter. To ensure that the reset
signal is removed before the next clock cycle, the reset signal is fed back to its generating
flip-flop through a delay chain comprised of three buffers.

23

4.4.2 SWALLOW COUNTER

The swallow counter, as indicated in Figure 4.5, is used to count S pulses of Slow
CLK before asserting the modulus control signal and changing the modulus of the DMP
to N. The similarities between the swallow counter and the program counter are apparent.
Once again, the count (6-bits in this case) is maintained using a ripple counter comprised
of cascaded flip-flops clocked with SlowCLK. In addition, a comparator compares each
count bit with its corresponding bit in the control signal, and a zero-detector asserts
modulus control when all bits are equal. However, the swallow counter does not reset
when the count is reached, but masks the input clock using an AND gate connected to the
inverse of modulus control. As a result, the ripple counter stops counting when the count
is reached, and the state of the circuit is maintained until a reset signal (SwallowRST) is
received from the program counter. Since the swallow counter contains 6 bits, it is
capable of any count from 0 to 64. Once again, the control signal must be set to S-1, since
the zero-state is included in the count.

Fig4.5. Block Diagram of a 6-Bit Swallow Counter

24

S-Counter Implementation
The 6-bit ripple counter implemented as an array of flip-flops, and clocked with
the gated clock provided by the AND of Slow CLK and modulus control. In addition, the
comparator is implemented as an array of MCML XNOR gates, while the zero-detector is
actually implemented as a one-detector using a tree of cascaded AND gates. Unlike the
program counter however, no additional circuitry is necessary to generate the reset as the
reset is received from the program counter by means of the Swallow RST signal.
4.4.3 COMPARISON BETWEEN MULTIMODULUS 2/3 AND 4/5 PRESCALER:

Case(1
)

MOD=

SEL=0

2/3

4/5

FREQUENC

PRESCALE

PRESCALE

Y DIVISION

RATIO

32

64
FD=NP+S

N=(AD*N1)+(0*N1+1)

MOD=

N+1=((AD-

1)*N1)+(1*(N1+1))

MOD=

N+1=(AD*(N+1)+(0*N

1)

33

65

48

80

Case(2
)
SEL=1

FD=(N+1)PS

MOD=

N=((AD-1)*(N1+1))

+(1*N1)

47

79

Table (1) Comparison between multimodulus 2/3 and 4/5 prescaler

25

CHAPTER 5
EXPERIMENTAL RESULTS
5.1 SIMULATION RESULTS
5.1.1. D FLIP FLOP:

Fig 5.1.1.Simulation Result of D Flip Flop

5.1.2. MUX:

Fig 5.1.2.Simulation Result of Mux

26

5.1.3. COMPARATOR S:

Fig 5.1.3 Simulation Result of Comparator S

5.1.4. COMPARATOR P:

Fig 5.1.4 Simulation Result of Comparator P

27

5.1.5. PROPOSED MULTIBAND FREQUENCY DIVIDER:

Fig 5.1.5.Simulation result of Proposed multiband frequency divider

5.2 SYNTHESIS RESULTS:

5.2.1 RTL DIAGRAM OF MULTIMODULUS PRESCALER:

28

Fig.5.2.1 RTL diagram of multimodulus prescaler

5.2.2 RTL DIAGRAM OF PROPOSED DYNAMIC LOGIC FLEXIBLE DIVIDER:

29

Fig 5.2.2 RTL diagram of proposed dynamic logic flexible divider

5.2.3 RTL DIAGRAM OF TOP MODULE :

Fig 5.2.3 RTL diagram of top module

5.2.4 Power Analysis:
30

Figure 5.2.4 Result for power analysis

5.3 COMPARISON OF RESULTS:

31

5.3.1 PERFORMANCE OF DIFFERENT DIVIDERS:

Design Parameters
Process(um)
Supply Voltage(v)
Max.Frequency(GHz)
Power(mW)

Existing System
0.18
1.8
5.14-5.7
0.225

Proposed System
0.18
1.8
2.4-2.484/5-5.825
0.171

Divide mode
Resolution

20

1,2,5,10,20

Table (2). Performance of different dividers

CHAPTER 6
ADVANTAGES, DISADVANTAGES AND APPLICATIONS
ADVANTAGES
32

The main advantages of the proposed method can be summarized as:

Dynamic latches are known to be faster and more compact than static ones.

The extended true-single-phase-clock (E-TSPC) design allows to drive the

dynamic latch with a single clock phase, thus avoiding the skew problem.

DISADVANTAGES

High power consumption is mainly due to the first stages of the frequency divider
that often dissipates half of the total power.

E-TSPC having high operating frequency, while a true single-phase clock (TSPC)
dynamic circuit, which only consumes power during switching, has a lower
operating frequency

APPLICATIONS

In real time applications are satellite transmitter and receiver.

Radio transmitter, Local communication transmitter (Mobile).

CHAPTER 7
CONCLUSION AND FUTURE WORK
A dynamic logic multiband flexible integer N divider is designed which uses the
wideband 4/5 prescaler, multimodulus 64/65/79/80 prescaler, and is silicon verified using
the 0.18m CMOS technology. Since the multimodulus 64/65/79/80 prescaler has
33

maximum operating frequency of 20 GHz, the values of P and S-counters can actually
be programmed to divide range of frequencies with finest resolution of 1 MHz and
variable channel spacing. However, since interest lies in the 2-2.4 and 55.825-GHz
bands of operation, the P- and S-counters are programmed accordingly. The proposed
multiband flexible divider also uses an improved loadable bit-cell for Swallow S-counter
and consumes a power of 0.171mW, and provides a solution to the low power PLL
synthesizers for Bluetooth, Zigbee, IEEE 802.15.4, and IEEE 802.11a/b/g WLAN
applications with variable channel spacing.
FUTURE WORK

This work can be extended to classify different range of frequencies. This can be

done by using different prescalers.

Based on the frequency we can improve the technology in Bluetooth, Zigbee,
IEEE 802.15.4, and IEEE 802.11a/b/g WLAN applications with variable channel
spacing.

34

ANNEXURE-A

35

SOFTWARE REQUIREMENT
XILINX

Xilinx, Inc. (NASDAQ: XLNX) is the world's largest supplier of programmable

logic devices, the inventor of the field programmable gate array (FPGA) and the first
semiconductor company with a fabless manufacturing model.
In the Xilinx software we can do simulation and synthesis .The entire processor will be
implemented using the Xilinx FPGAs so you won't have to spend time wiring up that part
of the circuit. You will, however, have to wire the switches and lights that are used to
control the processor, and have to wire the Xilinx part itself to the switches and lights, but
this shouldn't be too bad. You will also use the backplane bus in your lab kit so that the
Triscuit will be built on two boards: one for the Xilinx chip, and one for the switches and
lights.
The HDL Editor feature provides extensive edit and search capabilities with languagespecific color coding of keywords, as well as integrated on-line syntax checking to scan
VHDL code for errors. The Language Assistant feature speeds design entry by providing
a lookup list of typical language constructs and commonly used synthesis modules like
counters, accumulators, and adders.

36

VHDL

VHDL: VHSIC Hardware Description Language- IEEE standardized Language

BASIC COMPONENTS OFA VHDL MODEL
The purpose of VHDL descriptions is to provide a model for digital circuits and systems.
This abstract view of the real physical circuit is referred to as entity. An entity normally
consists of five basic elements, or design units.

Fig : Basic Model of VHDL

In VHDL one generally distinguishes between the external view of a module and its
internal description. The external view is reflected in the entity declaration, which
represents an interface description of a 'black box'. The important part of this interface
description consists of signals over which the individual modules communicate with each
other.
The internal view of a module and, therefore, its functionality is described in the
architecture body. This can be achieved in various ways. One possibility is given by
coding a behavioral description with a set of concurrent or sequential statements. Another
possibility is a structural description, which serves as a base for the hierarchically
designed circuit architectures. Naturally, these two kinds of architectures can also be
combined. The lowest hierarchy level, however, must consist of behavioral descriptions.
37

One of the major VHDL features is the capability to deal with multiple different
architectural bodies belonging to the same entity declaration. Being able to investigate
different architectural alternatives permits the development of systems to be done in an
efficient top-down manner. The ease of switching between different architectures has
another advantage, namely, quick testing. In this case, it is necessary to bind one
architecture to the entity in order to have a unique hierarchy for simulation or synthesis.
Which architecture should be used for simulation or synthesis in conjunction with a given
entity is specified in the configuration section. If the architecture body consists of a
structural description, then the binding of architectures and entities of the instantiated sub
modules, the so-called components, can also be fixed by the configuration statement.

The package is the last element mentioned here. It contains declarations of frequently
used data types, components, functions, and so on. The package consists of a package
declaration and a package body. The declaration is used, like the name implies, for
declaring the above-mentioned objects. This means, they become visible to other design
units. In the package body, the definition of these objects can be carried out, for example,
the definition of functions or the assignment of a value to a constant. The partitioning of a
package into its declaration and body provides advantages in compiling the model
descriptions.
Why VHDL?
A design engineer in electronic industry uses hardware description language to keep pace
with the productivity of the competitors. With VHDL we can quickly describe and
synthesize circuits of several thousand gates. In addition VHDL provides the capabilities
described as follows:

Power and flexibility

VHDL has powerful language constructs with which to write succinct code description of
complex control logic. It also has multiple levels of design description for controlling
38

design implementation. It supports design libraries and creation of reusable components.

It provides Design hierarchies to create modular designs. It is one language fort design
and simulation.
Device Independent design
VHDL permits to create a design without having to first choose a device for
implementation. With one design description, we can target many device architectures.
Without being familiar with it, we can optimize our design for resource or performance.
It permits multiple style of design description.
Portability
VHDL portability permits to simulate the same design description that we have
synthesized. Simulating a large design description before synthesizing can save
considerable time. As VHDL is a standard, design description can be taken from one
simulator to another, one synthesis tool to another; one platform to another-means
description can be used in multiple projects.
Benchmarking capabilities
Deviceindependent design and portability allows benchmarking a design using
different device architectures and different synthesis tool. We can take a complete design
description and synthesize it, create logic for it, evaluate the results and finally choose the
device-a CPLD or an FPGA that fits our requirements.
ASIC Migration
The efficiency that VHDL generates, allows our product to hit the market quickly
if it has been synthesized on a CPLD or FPGA. When production value reaches
appropriate levels, VHDL facilitates the development of application specific integrated
circuit (ASIC). Sometimes, the exact code used with the PLD can be used with the ASIC
and because VHDL is a well-defined language, we can be assured that out ASIC vendor
will deliver a device with expected functionality.
39

VHDL DESCRIPTION

In the search of a standard design and documentation for the Very High Speed Integrated
Circuits (VHSIC) program, the United States Department of Defense (DOD) n
1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole,
Massachusetts. In 1983, the DOD established requirements for a standard VHSIC
Hardware Description Language VHDL, its environment and its software was awarded to
IBM, Texas Instruments and Intermetrics corporations.
VHDL 2.0 was released only after the project was begun. The language was significantly
improved correcting the shortcoming of the earlier versions; VHDL 6.0 was released in
1984. VHDL 1078/1164 formally became the IEEE standard Hardware Description
Language in 1987.
A VHDL design is defined as an ENTITY declaration and as an associated
ARCHTECTURE body. The declaration specifies its interface and is used by
architecture bodies of design entities at upper levels of hierarchy. The architecture body
describes the operation of a design entity by specifying its interconnection with other
design entities STRUCTURAL description, by its behavior BEHAVIORAL
description, or by a mixture of both. The VHDL language groups, sub programs or
design entities by use of packages.
For customizing generic descriptions of design entities, CONFIGURATIONSare used.
VHDL also supports libraries and contains constructs for accessing packages, design
entities or configurations from various libraries.
ENTITIES and ARCHITECTURES
ENTITY Declaration:
The ENTITY declaration declares the name, direction and data type of each port of
component.
Syntax: entity name is
40

Port (

);

End name:
ARCHITECTURE Declaration:
The ARCHITECTURE portion of a VHDL description describes the behavior of the
component.
Syntax: architecture <architecture name > of <entity name> is
Begin
The BEGIN that follows the signal declaration marks the start of the
architecture body. The follows a process declaration, marked by the keyword PROCESS
and an ensuring BEGIN.
The END statement ending the architecture must be accompanies by the name of the
architecture which must match the name shown in the first of the architecture.
Sequential Processing
Sequential statements are statements that execute serially, one after other. In architecture
for an entity, all statement are concurrent, in VHDL, the process statements can exist in
the architecture where all statements are sequential.
Syntax:
[process-label:] process [(sensitivity list)]
Process-declarative-part;
Begin
Process-statement-part::=
Sequential statements};
End process [process-label];
A Process statement has a declaration section and a statement part in declaration
section types, variables, constants, subprograms, etc., can be declared. Statements part
contains only sequential statements which consist of CASE statements, IF THEN ELSE
statements, LOOP statements, etc.

41

Sensitivity list
This list defines the signals that will cause the statements inside the process statements to
execute whenever one or more elements of the list change value, i.e., list of signal that the
process is sensitive to. Changes in the values of these signals will cause to process to be
invoked.
Sequential Statements
Sequential statements exist inside the boundaries of a process statement, as well as in sub
programs. The sequential statements that are generally used are:
IF
CASE
LOOP
ASSERT
WAIT
IF statement
Syntax:

IF (condition) THEN

Sequence_of_statements;
[ELSE condition THEN
Sequence of_ statements ;}
[ELSE
Sequence_of_statements;]
END IF;
The IF statement start with the keyword IF and ends with the keywords END IF.
There are also two optional clauses: they are the ELSEIF clause and the ELSE clause.
The conditional construct in all cases is a Boolean expression. This is an expression that
42

evaluates to either true or false. Whenever the condition evaluates to a true value, the
sequence of statements following are executed. IF condition is true or false the sequence
of statements for the ELSE clause is executed, if one exits. The IF statement can have
multiple ELSE IF statements parts, only one ELSE statement part, between each
statement part can exist more than one sequential statement.
CASE Statement
The CASE statement is used whenever a single expression value can be used to select
between a numbers of actions.
Syntax:

CASE expression is

Case_statemant_alternative;
{Case_statemant_alternative ;}
END CASE;
Alternative:

WHEN choice=>
Sequence_of_statements;
Where

choice::=

simple_expression
discrete_range
element_simple _name
OTHERS
A CASE statement consists of the keyboard CASE followed by an expression and the
keyboard is. The expression will either return a value that matches one of the choices in a
WHEN statement part or a match an others clause. After these statements are executed,
control is transferred to the statements following the END CASE clause
The CASE statement will execute the proper statement depending on the value of input
instruction. If the value of instruction is one of the choices listed in the WHEN clause
is executed.

43

ANNEXURE-B

44

SOURCE CODE

BITCELL
entity bitcell is
Port ( clk,pi,sp,ldb,ld1 : in STD_LOGIC;
q,qb:inout std_logic:='0');
end bitcell;
architecture Behavioral of bitcell is
begin
process(clk)
begin
if clk'event and clk='1' then
if ldb='1' then
q<=pi;
qb<=not(pi);
end if;
end if;
end process;
end Behavioral;
CLKDIV2
entity clk_div is
port (
cout :out std_logic;
countb:out std_logic;
enable :in std_logic;
clk :in std_logic;
reset :in std_logic
);
end entity;
architecture rtl of clk_div is
signal clk_div :std_logic;
begin
process (clk, reset) begin
if (reset = '1') then
clk_div <= '0';
elsif (rising_edge(clk)) then
if (enable = '1') then
clk_div <= not clk_div;
end if;
end if;
end process;
45

cout <= clk_div;

countb<=not(clk_div);
end architecture;
CLKDIV3
ENTITY divide_by3 IS
PORT (
clk
: IN STD_LOGIC;
reset_n : IN STD_LOGIC;
o_clk_by3: OUT STD_LOGIC
);
END divide_by3;
ARCHITECTURE Arch OF divide_by3 IS
SIGNAL COUNTER : UNSIGNED(1 DOWNTO 0);
SIGNAL div_1 : STD_LOGIC;
SIGNAL div_2 : STD_LOGIC;
SIGNAL clk_low_cnt : STD_LOGIC;
SIGNAL clk_high_cnt : STD_LOGIC;
BEGIN
-- Counter generation
PROCESS(clk,reset_n)
BEGIN
IF (reset_n = '0') THEN
COUNTER <= "11";
ELSIF RISING_EDGE(clk) THEN
IF COUNTER = "10" THEN
COUNTER <= "00";
ELSE
COUNTER <= COUNTER + 1;
END IF;
END IF;
END PROCESS;
-- clk_r generation
PROCESS(clk,reset_n)
BEGIN
IF (reset_n = '0') THEN
clk_low_cnt <= '0';
clk_high_cnt <= '0';
ELSIF RISING_EDGE(clk) THEN
IF COUNTER = "00" THEN
clk_low_cnt <= '1';
ELSE
46

clk_low_cnt <= '0';

END IF;
IF COUNTER = "10" THEN
clk_high_cnt <= '1';
ELSE
clk_high_cnt <= '0';
END IF;
END IF;
END PROCESS;
-- div_1 generation
PROCESS(clk,reset_n)
BEGIN
IF (reset_n = '0') THEN
div_1 <= '0';
ELSIF RISING_EDGE(clk) THEN
IF clk_low_cnt = '1' THEN
div_1 <= NOT div_1;
END IF;
END IF;
END PROCESS;
-- clk_f generation
PROCESS(clk,reset_n)
BEGIN
IF (reset_n = '0') THEN
div_2 <= '0';
ELSIF FALLING_EDGE(clk) THEN
IF clk_high_cnt = '1' THEN
div_2 <= NOT div_2;
END IF;
END IF;
END PROCESS;
o_clk_by3 <= div_1 XOR div_2;
END Arch;
DLATCH
entity dlatch is
Port ( clk,d : in STD_LOGIC;
q,qbar:out std_logic);
end dlatch;
architecture Behavioral of dlatch is
47

component nandgate is
Port ( a,b : in STD_LOGIC;
c:inout std_logic);
end component;
component notgate is
Port ( a : in STD_LOGIC;
b:out std_logic);
end component;
signal nclk,m1,m2,m3,m4,s1,s2,s3,s4:std_logic :='0';
begin
u0:nandgate port map(d,clk,m1);
u1:nandgate port map(m1,clk,m2);
u2:nandgate port map(m1,m4,m3);
u3:nandgate port map(m3,m2,m4);
u4:notgate port map(clk,nclk);
u5:nandgate port map(m3,nclk,s1);
u6:nandgate port map(nclk,m4,s2);
u7:nandgate port map(s1,s4,s3);
u8:nandgate port map(s3,s2,s4);
q<=s3;
qbar<=s4;
end Behavioral;
NANDGATE
entity nandgate is
Port ( a,b : in STD_LOGIC;
c:inout std_logic);
end nandgate;
architecture Behavioral of nandgate is
begin
c<=a nand b;
end Behavioral;

PCOUNTER
entity pcounter is
Port ( clk : in STD_LOGIC;
op:out std_logic_vector(6 downto 0));
end pcounter;
architecture Behavioral of pcounter is
signal co:std_logic_vector(6 downto 0):="0000000";
48

begin
process(clk)
begin
if clk'event and clk='1' then
co<=co+"0000001";
op<=co;
end if;
end process;
end Behavioral;
COUNTERSP
entity countersp is
Port ( clk : in STD_LOGIC;
mods:inout std_logic);
end countersp;
architecture Behavioral of countersp is
component pcounter is
Port ( clk : in STD_LOGIC;
op:out std_logic_vector(6 downto 0));
end component;
component scounter is
Port (clk,s1,s2,s3,s4,s5,s6 : in STD_LOGIC;
mod1:inout std_logic);
end component;
signal coun:std_logic_vector(6 downto 0):="0000000";
begin
hh0:pcounter port map(clk,coun);
hh1:scounter port map(clk,coun(0),coun(1),coun(2),coun(3),coun(4),coun(5),mods);
end Behavioral;
MUX
entity mux21 is
Port ( a,b,sel : in STD_LOGIC;
o : out STD_LOGIC);
end mux21;
architecture Behavioral of mux21 is
begin
with sel select
o<=a when '0',
b when '1',
'0' when others;

49

end Behavioral;
PRESCALER
entity prescalar is
Port (clk,mc:in STD_LOGIC;
outf,qb2:inout std_logic:='0');
end prescalar;
architecture Behavioral of prescalar is
component dlatch is
Port ( clk,d : in STD_LOGIC;
q,qbar:out std_logic);
end component;
signal xnor2op,ints,q,qb:std_logic:='0';
begin
kk0:dlatch port map(clk,qb2,q,qb);
ints<=q xnor mc;
xnor2op<=ints xnor outf;
kk1:dlatch port map(clk,xnor2op,outf,qb2);
end Behavioral;
SCOUNTER
entity scounter is
Port (clk,s1,s2,s3,s4,s5,s6 : in STD_LOGIC;
mod1:inout std_logic);
end scounter;
architecture Behavioral of scounter is
component bitcell is
Port ( clk,pi,sp,ldb,ld1 : in STD_LOGIC;
q,qb:inout std_logic:='0');
end component;
signal
norop,norop1,nandop,nandop1,q1,q2,q3,q4,q5,q6,qb1,qb2,qb3,qb4,qb5,qb6:std_logic:='0'
;
signal ldb,ld1,mod1b:std_logic:='1';
begin
kkq0:bitcell port map(clk,s1,mod1,ldb,ld1,q1,qb1);
kkq1:bitcell port map(q1,s2,mod1,ldb,ld1,q2,qb2);
kkq2:bitcell port map(q2,s3,mod1,ldb,ld1,q3,qb3);
kkq3:bitcell port map(q3,s4,mod1,ldb,ld1,q4,qb4);
kkq4:bitcell port map(q4,s5,mod1,ldb,ld1,q5,qb5);
kkq5:bitcell port map(q5,s6,mod1,ldb,ld1,q6,qb6);
norop1<=q4 nor q5;
norop<=norop1 nor q6;

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nandop1<=norop nand qb3;

nandop<=nandop1 nand qb2;
kkq6:bitcell port map(clk,'0',ldb,ld1,mod1,mod1b);
end Behavioral;
TOPMODULE
entity topmod is
Port ( clk,rst,en1,sel : in STD_LOGIC;
q1,q2,q3,q4:inout std_logic:='0'
);
end topmod;
architecture Behavioral of topmod is
component proposedmultimod is
Port ( clk,rst,mods,en1,sel : in STD_LOGIC;
q1,q2,q3,q4:inout std_logic:='0');
end component;
component countersp is
Port (clk : in STD_LOGIC;
mods:inout std_logic);
end component;
signal mods:std_Logic:='1';
begin
oo0:countersp port map(clk,mods);
oo1:proposedmultimod port map(clk,rst,mods,en1,sel,q1,q2,q3,q4);
end Behavioral;

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