Fabrication and Characterization of Organic Solar Cell

CMOS Transistors
It took almost 20 years after the invention of the bipolar transistor
for MOS to make its appearance. Shockley (and many others) had thought
of this device first, it was (or should have been) much more simple: put a
plate close to the surface of silicon, connect it to a voltage and move the
carriers inside the silicon electro-statically.
The problem was the surface of silicon. Here the silicon atoms are
no longer neatly tied up with each other by sharing the outermost electrons.
They face an entirely different material, SiO2 (or worse, some covering
with unknown impurities mixed in). This material doesn't even have a
crystal structure, it is amorphous. In 1964 a startup, General Microelectronics, felt it had licked
the
problem with CMOS and brought out the first digital MOS integrated
circuit. It was one of the worst products ever to hit the market: a large
portion stopped working within days. The reason: there were elements with
the silicon-dioxide (chiefly sodium) that carried an electric charge and could
move. One day the MOS transistor was perfectly functional, the next day it
was permanently turned on.
It took another few years to gain an understanding of MOS surface
physics and make stable MOS transistors. Today the silicon surface is so
well understood that we can deliberately place a charge into the oxide layer
that stays there for years, probably even centuries. It is now the dominant
integrated device, being much smaller than the bipolar transistor. (The
number of MOS transistors produced every year has long surpassed the
number of ants in the world. At the time of writing this book,
semiconductor manufacturers produced some 500 million transistors for
every person in the world per year).
The figure
shows a cross-section
of the most often
used (n-well) process.
There are many
variations and
refinements; this is
only the basic one.
In the gate
area the insulating
layer (SiO2 or nitride,
or a combination) is
thinned down and silicon is grown on top of it. Since the insulator is
amorphous, the grown silicon is not single-crystal, it consists of many small
crystals which do not fit together very well (thus it is called poly-crystalline

silicon or simply poly).

Next the source and drain regions are implanted, using a mask. The
inside edges are masked by the gate, so they align perfectly to the gate (i.e.
they are self-aligning). The device is also self-insulating: as long as the
source and drain are at or above the substrate potential (usually ground), the
junctions to the substrate are reverse-biased and no bulky isolation diffusion
is necessary.
For the p-channel transistor the polarities for the source and drain
implants are reversed and these regions are placed inside an n-type
diffusion. In most applications one such n-well hosts many p-channel transistors and is simply
connected to the positive supply voltage; in this
way the devices are insulated from each other as long as each source and
drain is at or below the positive supply

Fig. 1-18: Cross-section of an N-well CMOS process.

.
In both the n-channel and p-channel transistors, sources and drains
are identical, i.e. you can arbitrarily call one the source and the other the
drain. Or one region can do double-duty, being the drain for one transistor
and the source for the next one, connected in series.
The p-channel transistor is always at a disadvantage, because holes
are more difficult to move than electrons. Thus it will have a lower gain
than an n-channel device (for the same gate oxide thickness) and be
somewhat slower. (MOS
transistors, by the way,
are called unipolar
devices, because they
employ only one type of
carrier, as opposed by the
bipolar transistor, in
which both electrons and
holes are important for
the operation).
Now let's look at
an (n-channel) MOS
transistor in more detail.
The basic idea is to create
a region (a channel)

between source and drain

which has the same
polarity (n-type), so that
there is direct conduction between
the two. This is done with a positive
voltage at the gate which pushes
holes away from the surface and the
device is called an enhancementmode
transistor (there are also
depletion-mode devices in which a
channel is implanted or diffused and
then cut off with a negative gate
voltage).
This is true only at zero or
very low drain voltage. As the drain
voltage is increased, a depletion region forms around it. Since there is now a voltage drop along
the
channel, with the drain side at a higher voltage than the source, the
depletion region along the channel gradually increases toward the drain,
cutting more and more into the channel. Thus the resistance of the channel
increases.

Fig. 1-19: As the drain voltage is increased, a

depletion region pinches off the channel.

Fig. 1-20: Drain current vs. drain voltage

with the gate voltage held constant.

The initial slope of the

drain voltage / drain current
curve is the resistance of the
channel without any depletion
layers. The final slope at the
highest drain voltage represents
its resistance with the depletion
layer almost pinching off the
channel. It is an unfortunate
fact that this region is called
the "saturation region", which
clashes badly with the earlier
definition for the bipolar
transistor.
Above a certain gate
potential, which has to be exceeded
to attract any carriers to the surface (the threshold voltage) an MOS
transistor is basically a square-law device: doubling the gate voltage results
in four times the drain current. The measure of gain is the
transconductance, drain current divided by gate voltage. So again, like the
bipolar transistor, this is a non-linear device:
Id k
W
L
Vgs VT 2

where Id = drain current

k = transconductance
W = channel width

L = channel length
Vgs = gate-to-source voltage
VT = threshold voltage
or Vgs - VT = gate voltage above the threshold
The region below the channel also influences the gain. It forms a
back-gate. In an n-well n-channel transistor this is the substrate, common
to all devices. You have no choice but to connect it to the lowest negative

Fig. 1-21: Drain current vs. gate voltage

with the drain voltage held constant.

voltage. But there is a choice for the p-channel transistor. If you place all
the p-channel transistors in a common n-well, you get the smallest total area
and therefore the lowest cost. But if the source of such a transistor is
operated below the positive supply, the back-gate (the n-well) pinches off
the channel further and you get a reduced gain (by perhaps 30%). You can
avoid this by placing this transistor in its own n-well.