Dynamic Test Data Transformations for

Average and Peak Power Reductions

Ozgur Sinanoglu, Ismet Bayraktaroglu and Alex Orailoglu
Computer Science and Engineering Department
University of California, San Diego
La Jolla, CA 92093

fozgur, ibayrakt, alexg@cs.ucsd.edu

Abstract
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by
average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan
chain, which in turn reflect into significant levels of circuit
switching unnecessarily. Judicious utilization of logic in the
scan chain can help reduce transitions while loading the test
vector needed. The transitions embedded in both test stimuli
and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as
well as inversion of capture paths with no performance degradation. To reduce average and peak power, we herein propose
computationally efficient schemes that identify the location and
the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the
proposed scheme.

1 Introduction
Testing in parallel the cores in a System-On-a-Chip (SOC)
helps reduce test application time; power dissipation imposes
strict limits to this parallelism as overheating the chip might
result in damaging the cores under test. Not only does average power dissipation during testing need to be reduced consequently to avoid overheating the chip, but furthermore particular attention has to be devoted to peak power dissipation issues
as exceeding power thresholds may result in burning the chip.
During test mode, filling in the scan chain with test data requires shifting the bits one by one into each chain, thus creating
increased switching activity in the flip-flops. The rippling effect in a scan chain reflects into the circuit, resulting in a large
number of unnecessary transitions at the circuit lines, unless
costly additional control is utilized.
In traditional approaches, the stimulus inserted to the scan
chain is one and the same as the test vector; similarly, the collected test response to be transmitted to the ATE is identical
to the circuit response captured in the scan cells. Modification of the scan chain through logic gate insertion between the
 The work of the first author is supported through a graduate fellowship by
IBM.

Proceedings of the Seventh IEEE European Test Workshop (ETW02)

1530-1877/02 $17.00 2002 IEEE

scan cells though shatters this equivalence. The modifications

necessitate the insertion of a transformed stimulus which in all
likelihood differs from the actual test vector; an analogous conclusion can be drawn for the test response as well. As the scan
chain transitions are strictly determined by the transitions embedded in the input stimulus (and not by the actual test vector
to be applied to the circuit under test) and the output response
collected through the scan-out pin, scan chain modifications
can be utilized to reduce the number of scan chain transitions.
An analysis of the original test data and their transition frequencies can be used to determine effectively the appropriate
scan chain modifications which yield the transformed stimuli
and responses with a reduced number of transitions.
The fundamental test data transformation techniques can be
enhanced through the inversion of certain test response bits
during the capture cycle. Although the test stimuli bits remain
intact by such modifications, the number of possible transformations for test responses can be effectively increased, leading
to improved test power results. The additional gate delay associated with the response inversion process during the capture
cycle solely is added to the test path, keeping intact the functional operation of the circuit timing-wise.
Even though test power during the capture cycles can be effectively ignored in computing the average test power, it might
create peak power violations; a strategy to reduce the transitions created due to overwriting the test stimulus with the test
response is necessitated, consequently. The aforementioned
test response inversion idea enables controlling capture power
as the correlation between the test stimulus-test response pair
that causes power violation can be increased through the inversion of particular response bits. Overwriting a test stimulus
vector with a highly correlated test response vector leads to
rippling in fewer scan cells during the capture cycle.

2 Previous Work
Numerous methodologies that aim at test power reduction
in a scan-based environment have been proposed recently. The
utilization of externally controlled gates [1] to mask out the
transitions originating from the scan chain have been shown to
reduce test power drastically; however performance degrada-

test
stimulus

cell 5

cell 4

cell 3 cell 2

cell 1

inserted
stimulus

00110
Transition1
Transition2

cell 5

cell 4

cell 3 cell 2

cell 1

cell 4

cell 3 cell 2

cell 1

00001
Transition

scan in

scan in
cell 5

test
1
response

cell 4

cell 3 cell 2

cell 5

cell 1

scan out
1

test
1
response

tion due to gate delays inserted on critical paths may be unacceptable. Several techniques have been employed during the
test application process; appropriate primary input assignment
during shift cycles [2] helps reduce transition propagation from
scan chain to the circuit under test. The effectiveness of such
techniques is limited, as typically circuits are controlled mostly
by scan chains rather than primary inputs.
Several techniques aim at reducing transitions in the scan
chain. In [3], the test cubes are compacted and padded so
as to minimize the number of scan chain transitions; even
though test power is reduced, test application time may suffer a bit of deterioration in comparison to the random padding
case as padding for minimum power typically results in a few
additional test vectors. To minimize the switching activity in
the scan chain, two techniques, test vector ordering and scanlatch ordering, are proposed in [4]; however, the computational complexity of these techniques limits their applicability. Whetsel proposes [5] a general scheme for partitioning the
scan chain into several smaller scan chains so as to have only
one of the small chains active at a time; rippling occurs in only
one small chain, thus reducing the test power dissipated. A
numerous set of variations [6, 7] on this basic scheme advocated by Whetsel in [5] is pursued by Bonhomme et al. The
instantiation of the general scheme advocated by Whetsel [5]
to partitioning into two scan chains specifically is illustrated in
[6, 7]. Bonhomme et al examine this particular instance in the
context of ATE controlled scan-based environments in [6] and
continue their efforts by focusing on the same bipartitioning
instance in the context of LFSR produced tests in [7].
In [8], scan chain modification through the insertion of logic
gates between the scan cells is proposed to reduce the scan
chain transitions associated with the test stimuli inserted. The
test vectors are analyzed to identify the location and the type of
logic to be inserted to the scan path. Even though considerable
scan-in test power reductions are achieved, scan-out test power
is not handled, limiting the effectiveness of the technique in
overall test power reduction. Furthermore, the technique delivers only average power reductions; peak power considerations
are overlooked.

3 Motivation
The rippling that originates from the scan chain reflects into
more transitions inside the circuit, causing increased power
dissipation unnecessarily. Scan chain flip-flops frequently tog-

Proceedings of the Seventh IEEE European Test Workshop (ETW02)

1530-1877/02 $17.00 2002 IEEE

observed
response
00000

Transition3

Figure 1. Rippling of the scan cells

scan out

Figure 2. Test data transformation through scan chain

modification for the example in figure 1

gle due to transitions embedded in the test data; figure 1 illustrates how the transitions between the test data bits flip the
scan cells. The transition between the two rightmost bits of
the test vector flips all but the rightmost scan cell, whereas the
other transition in the test stimulus vector flips the two leftmost
cells. The transition embedded in the test response on the other
hand flips the three rightmost cells.
The scan chain transitions during the shift of the test data
can be reduced through scan chain modifications. Appropriate
insertion of logic gates between scan cells enables the insertion
of a new stimulus and the observation of a new response with
fewer transitions embedded. For instance in figure 2, insertion
of an inverter between the third and the fourth scan cells helps
reduce the number of transitions from 9 down to 4 during the
shift cycles.
Through various scan chain modifications, numerous test
data transformations can be implemented, each having a certain impact on the test data transitions. These modifications
consist of logic gate insertion between scan cells as well as
inversion of capture paths; such modifications involve no gate
delay introduction to the critical paths of the circuit. It is essential to identify the relationship between a particular scan chain
modification and the transformation function implemented by
this modification; identification of this relationship in turn
helps pinpoint the optimal scan chain modification that would
lead to the transformed test data with the fewest possible transitions.

4 System Overview
In this section, the characteristics for possible scan chain
modifications are explored to enable the implementation of a
computationally efficient methodology; a divide and conquer
scheme is presented wherein various scan chain fragments can
be independently considered for possible modification. The
modifications allowed in the scan chain are judiciously selected so as to enable independence among various scan chain
fragments; the impact of the insertion of different gates on
test data transformation is analyzed. The variety of the scan
chain modifications is increased through insertion of inverters
in capture cycles; not only is the number of possible scan chain
modifications increased, but furthermore peak power violations during capture cycles can be effectively handled through
the appropriate capture path inversions.

cell i+2 cell i+1 cell i

cell i+1

cell i1

...

...

cell i

cell i1

...

scan out

scan in

...

scan out

scan in

Test vector bit i+2

bit i+1
Actual
ai+2
ai+1
Inserted ai+2 ai+1 ai+2 ai

bit i

bit i-1

ai 1
 ai+1  ai+2 ai 1  ai+1  ai+2
ai

Figure 3. Impact of XOR gates on the transitions between test data bits

4.1 Divide and Conquer Scheme

As distinct test vectors should be mapped to distinct stimuli (responses), functions with controlling values should not be
utilized in scan chain modifications; only X(N)ORs and inverters should be used as they preserve bijectivity. Even with the
restriction of the possible scan chain modifications to bijective
ones, still the cardinality of the candidate transformation set
can be exceedingly large. Computational efficiency dictates independent modifications in various scan chain fragments; the
optimal modification in each scan chain fragment should be
individually implemented by analyzing the corresponding bits
of the test vectors. Test vector data should therefore be decomposed into blocks, each block composed of a number of
consecutive bits. Decomposition into non-overlapping blocks
results in uncovered transitions between blocks; on the other
hand, blocks overlapping in multi-bit positions leads to ambiguity in handling the transitions falling within the intersection
of blocks, conflicting with the modification independence constraints. Consideration of every transition therefore necessitates a single bit overlap between any two consecutive blocks.

4.2 Transition-preserving Modifications

The necessary independence of modifications can be guaranteed through limiting their impact to a single test data block;
if the modification of a certain part of the scan chain affects
solely the transitions embedded in a single test data block, each
test data block can be analyzed and transformed independently.
Such a local modification impact can be achieved if the modification impacts solely the transitions between the bits to be
delivered into the scan cells involved in the modification, resulting in a transition-preserving modification for the test bits
that pass through the modified scan chain fragment. Alternative, non-transition-preserving modifications result in a computationally taxing block-ordering problem, otherwise.
An inverter, for example, between two scan cells necessitates transformation of the actual test data that passes through
this gate; the applied stimulus (observed response) bits which
are to pass through the inverter should equal the original test
data bits negated. The only transition that is affected by such a
modification is the one between the two bits, only one of which
is negated; all the other transitions remain intact. Therefore,
this modification is indeed a transition-preserving one as it has
a local impact on the transitions between the test data bits; con-

Test vector bit i+2 bit i+1

bit i
bit i-1 bit i-2
Actual
ai+2 ai+1
ai
ai 1 ai 2
Inserted ai+2 ai+1 ai ai+1 ai 1 ai 2

Figure 4. A function implemented in the scan chain

using XOR gates

tiguous scan chain bit pairs can thus be modified independently

of the remaining bits through the insertion of inverters.
Unfettered use of X(N)OR functions, on the other hand,
may impose cumulative effects. A modification for example
consisting of the insertion of a single X(N)OR gate is not
transition-preserving as it fails to keep intact the transitions
between the test bits that pass through this gate. Even the
modification through the insertion of two XOR gates shown
in Figure 3 imposes a non-transition preserving bahavior as all
the bits except the leftmost1 ones in the applied stimulus (observed response) have to be recomputed; a trivially analogous
case holds for XNORs. Utilization of the X(N)OR function in
a transition-preserving manner necessitates masking the effect
of an X(N)OR gate with another one in the subsequent bit location, as illustrated in figure 4, enabling the examination of test
data in small chunks of three bits. The overall impact of such
a modification is thus limited to two consecutive transitions either side of the middle cell. As the applied stimulus (observed
response) bits that are to pass through two X(N)OR gates in
consecutive locations either remain intact or are negated, such
a modification is a transition-preserving one. The local impact
of this modification enables the utilization of X(N)OR gates
together with inverters for modifying scan chain fragments.

4.3 Capture Path Inversion

Even though the aforementioned modifications can be used
to remedy the peak power violations during the shift of test
data, handling such a violation during a capture cycle necessitates the ability to transform the problematic test response vector into a new vector whose correlation with the corresponding
test stimulus is higher. Overwriting the test stimulus with the
transformed test response can help reduce scan chain transi1 The test vector bits with the lower numbered indices are shifted into the
scan chain prior to the ones with higher indices.

system
test
system test

capture/test
MUX

normal/test

MUX
normal/test

MUX

Figure 5. Scan capture path inversion

Proceedings of the Seventh IEEE European Test Workshop (ETW02)
1530-1877/02 $17.00 2002 IEEE

F1
F2
F3
F4
F5
F6
F7
F8

Gates
XOR,XOR
XNOR,XNOR
INV,INV
XOR,XNOR
XNOR,XOR
INV,-,INV
-,-

ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1

Test bit

ai
ai  ai+1
0
(ai  ai+1 )
0
ai
ai  ai+1
0
(ai  ai+1 )
0
ai
ai
ai

ai
ai
ai
ai
a0i
a0i
a0i
a0i
ai

1
1
1
1
1
1
1
1
1

000
00
--0-0
-0
000

001
00
-+
-+
0+
-0
-0
0+
00

010
00
++
++
0+
+0
+0
0+
00

Impact
011 100
00
++00
++0+0
+0
0+0
+0
0000
00

101
++
00
++
+0
0+
+0
0+
00

110
-+
00
-+
-0
0+
-0
0+
00

111
-00
--0
0-0
000

Table 1. The transition-preserving modifications and their impact on the transitions between test data bits

tions, in turn reducing peak power during capture cycles. The

appropriate transformation of the actual response vector can be
achieved only if the test response bits that differ from the stimulus bits in the same bit position can be negated. The design
of certain scan cells as in figure 5 provides this transformation
for the corresponding test response bits, yet keeps intact the
normal operation of the circuit. For the test response bits to be
flipped, an inverter is inserted on the capture path of the corresponding scan cell, whereas the other cells receive the system
output intact during the capture cycle. Capture path inversion
of certain response bits provides control over the power dissipated during capture cycles, enabling the reduction of peak
power in these cycles. No performance deterioration whatsoever is suffered during the functional operation as a result, as
inverter delays are introduced solely on test paths; no gate delay on critical paths is introduced.

5 Algorithmic Framework
In this section the possible scan chain modifications are presented. Average and peak power issues are considered separately; two different algorithms, both based on test data analysis, are provided.
Table 1 lists the transformations associated with various
scan chain modifications along with the impact on the test data
transitions. The second column denotes the gates to be inserted between the elements of the left pair and the gates to
be inserted between the elements of the right pair, in that order. The third column shows the test data that needs to be inserted to the scan chain to bring in the three actual test vector
bits into the scan cells. The information provided in the third
column constitutes the transformed test response data as well.
Notably, for all the entries in table 1, the rightmost test bit,
ai 1 , either remains intact or is simply negated, thus ensuring
the transition-preserving property for all such modifications.
The distinct local impact of every modification on the transitions within a block of test data is demonstrated in the same
table; for all eight combinations of three test data bits, the effect of implementing a modification on the transitions between
the first two and the last two bit positions in the block, respectively, is provided. A transition that is removed is denoted by
+, a transition created due to the modification of the scan
chain, by -; 0 denotes no impact. For instance, inserting 2
XOR gates results in removing both transitions when the test

Proceedings of the Seventh IEEE European Test Workshop (ETW02)

1530-1877/02 $17.00 2002 IEEE

data bits are 101, since 111 should be applied to bring in

101 to the modified scan chain.
An increased variety of scan chain modifications can be
achieved through the implementation of certain scan cells as
in figure 5. As the scan chain fragments consist of three scan
cells each, eight versions of each of the eight modifications
can be implemented, differentiated by whether an inverter is
introduced to each of the three capture paths. The inversion of
all or none of the bits during the capture cycle constitute identical cases as far as the transitions between the test response
bits are concerned; therefore, every version has a single equivalent one in terms of the impact on the transitions, yielding
only four distinct versions for every modification. While the
overall number of possible modifications for a scan chain fragment of three cells is thirtytwo, the number of distinct cases
remains eight in terms of impact on the transitions between
the test response bits. For instance, a modification consisting
of inserting two XOR gates with no capture paths inverted is
equivalent to another modification consisting of inserting two
XNOR gates with the capture path in the middle inverted; the
transformed test response bits are equivalent for both modifications. Since the inverters inserted on the capture paths have
no impact on the test stimulus bits, the modifications that are
equivalent for test responses have still distinct effects on the
transitions between the test stimulus bits. The total number of
possible modifications to be considered is therefore thirtytwo.
Table 2 groups the modifications that are equivalent in terms
of the impact on the transitions between the test response bits;
an N symbol inside the parenthesis denotes an inverter that
is introduced to the capture path, whereas - denotes no inversion. For instance, F4(- - N) denotes the modification wherein
an XOR and an XNOR gate is inserted to the left and the right
of the center scan cell in the scan chain fragment, respectively,
and the capture path of the rightmost scan cell is inverted.
As implementing these transition-preserving modifications
enables independent modifications in the scan chain, the test
data can be decomposed into blocks that can be individually
analyzed. Any one of these modifications might affect the transitions at two adjacent locations; three test bits are involved in
the decision making process in selecting the most appropriate
modification. Consequently, the test data blocks to be analyzed
consist of three consecutive bits of every test vector.

F1(- - -), F2(- N -), F4(- - N), F5(N - -)

F2(- - -), F1(- N -), F5(- - N), F4(N - -)
F3(- - -), F8(- N -), F6(- - N), F7(N - -)
F4(- - -), F5(- N -), F1(- - N), F2(N - -)
F5(- - -), F4(- N -), F2(- - N), F1(N - -)
F6(- - -), F7(- N -), F3(- - N), F8(N - -)
F7(- - -), F6(- N -), F8(- - N), F3(N - -)
F8(- - -), F3(- N -), F7(- - N), F6(N - -)

ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1
ai+1

Test bit

ai
ai  ai+1
0
(ai  ai+1 )
0
ai
ai  ai+1
0
(ai  ai+1 )
0
ai
ai
ai

ai
ai
ai
ai
a0i
a0i
a0i
a0i
ai

Table 2. Thirtytwo modifications grouped based on

the impact on the test response bits

6 Average Power Reduction

Reduction of the average test power necessitates decreasing
the total number of scan chain transitions during the shift of the
test data. As the modifications can be implemented independently in various scan chain fragments, decomposition of the
test data into blocks is enabled, allowing the analysis of individual blocks and yet achieving the overall minimum number
of transitions.
A straightforward algorithm of reduced complexity can
therefore be developed wherein for every block of test data
bits, the modification that will lead to the transformation with
the fewest transitions is selected among the thirtytwo possible
modifications in table 2 and is implemented in the corresponding part of the scan chain. A skew in the test data distribution within a block can be of benefit; for example, if 101
occurs more frequently in a block, F3 is implemented in the
corresponding part of the scan chain and both transitions are
removed.

7 Peak Power Reduction

Even though the methodology is still based on transformation of the test data, peak power is handled differently than
average power. In the case of peak power, the number of transitions during the test cycles wherein peak power violation occurs is reduced, instead of attempting to minimize the total
number of transitions. Instead of analyzing the whole test data
and hence minimizing the total number of transitions, only the
problematic test vectors should be taken into account for implementing the appropriate modifications in the scan chain.
The initial step consists of the identification of the test cycle(s) wherein the number of scan chain transitions exceeds
the desired peak power level. Depending on the power violation type, various actions may need to be taken. If the power
violation occurs during the capture cycle wherein the test stimulus vector is overwritten by the test response vector, the capture paths corresponding to the rippled scan cells should be inverted. If, on the other hand, the power threshold is exceeded
during the shifting of the test data, the associated test stimulus
and response vectors are decomposed into blocks for implementing the appropriate modifications in various scan chain
fragments; we refer the reader to table 1 for the possible modifications.

Proceedings of the Seventh IEEE European Test Workshop (ETW02)

1530-1877/02 $17.00 2002 IEEE

1
1
1
1
1
1
1
1
1

Circuit
s713
s953
s1423
s5378
s9234
s13207
s15850
s35932

Avg. power red.(%)

18.7
11.6
10.4
10.2
12.5
10.3
16.2
11.3

Area cost(%)
5.8
2.8
5.7
3.8
2.6
3.3
4.7
4.2

Table 3. Average test power reduction

Due to the modifications in the scan chain, the test vectors

that originally cause no power violations may themselves exhibit problematic behavior; in that case, the scan chain modifications performed in the previous step are undone and the test
vector that caused the violation in the current step is handled
together with the previous problematic test vectors. The complete process is repeated until no power violation occurs. As
the number of problematic test vectors handled at every step
can only decrease, the convergence of the algorithm is guaranteed; however, the algorithm may fail to attain the desired
peak power level. In that case, the algorithm is re-executed by
increasing the desired peak power level.

8 Experimental Results
The proposed average and peak test power reduction
schemes have been applied to several fully-scanned circuits in
ISCAS89 [9]. The test vectors that are used to compute the test
power reductions achieved by the proposed methodologies are
generated by ATALANTA [10].
Table 3 demonstrates the average test power reductions
based on test data transformations; the reduction in the total
number of transitions in the scan chain, and the increase in
area overhead are provided. Overall test power reductions of
10% to 20% are achieved with small area cost of typically less
than 5%.
Peak power reductions along with the associated area costs
are reported in table 4; every time the peak power reduction
algorithm is executed, a target peak power level is selected in
advance. Of course, no guarantees can be extended for achieving arbitrary peak power thresholds. From the experimental
data, it is seen that a 20% peak power reduction is attained for
only the circuit s713 whereas a 5% reduction is achieved for
all the circuits. The proposed methodology achieves 10% reduction in peak power for six of the eight benchmarks. As the
target peak power reduction is increased, the area cost becomes
larger; since the number of test cycles wherein power violation
occurs is increased, the number of modifications implemented
in the scan chain goes up, resulting in larger area overhead.
The considerable average power reductions attained by the
methodology we propose enable the application of manufacturing tests with no overheating of the chip. Furthermore, controlling the peak power below certain thresholds eliminates the
danger of burning the chip during test. Reliable test of circuits
is enabled by the average and peak power reduction method-

Circuit
s713
s953
s1423
s5378
s9234
s13207
s15850
s35932
Average

Target: 5%
Area
3.4
2.4
4.7
3.4
2.2
3.1
4.0
3.4
3.3

Target: 10%
Area
4.1
2.9
5.6
N/A
2.7
3.5
N/A
3.9
3.8

Target: 15%
Area
5.6
N/A
5.8
N/A
N/A
N/A
N/A
4.1
5.2

Target: 20%
Area
5.9
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5.9

Table 4. Peak test power reduction

ologies we propose, consequently.

Test power reduction schemes in the literature such as
[5, 4, 6], which aim at reducing the switching activity in the
scan chain, constitute orthogonal approaches that can be applied in conjunction with the methodology we propose. For
comparison purposes, we have implemented the technique in
[6] and shown that the proposed technique can furthermore be
utilized on top of other techniques such as [6]. Table 5 presents
the average test power reductions when the technique in [6] is
applied alone and in conjunction with the technique we propose, respectively. The application of the two techniques in
conjunction consists of the decomposition of the scan chain
into two partitions as advocated in [6], followed up by modifications based on the test data analysis we propose. It can be
seen that power reductions achieved by [6] can be significantly
improved through the utilization of the proposed scan chain
modifications as well. The improvements reported in the last
column of table 5 display similarity to the power reductions
achieved by the proposed methodology presented in the second column of table 3; these results hint that the benefits of the
method we propose remain undiminished even when applied
in conjunction with other previously proposed techniques.

9 Conclusion
To enable parallelism when testing cores in an SOC design, the average and peak test power associated with the cores
should be reduced. The proposed methodology achieves this
reduction by slightly modifying the scan chain based on the
analysis of the given test set. The suggested modifications in
the scan chain enable the decomposition of the test set into
blocks as a modification in a scan chain fragment impacts only
the transitions within a single block. Each test data block is
analyzed individually to identify the modification that leads
to the optimal transformation of the block; subsequently, the
modification is implemented for the corresponding scan chain
fragment. The consequent computationally efficient algorithm
achieves significant test power reductions.
The proposed methodology achieves test power reductions
through insertion of logic gates on the test paths. In addition
to logic gate insertions between scan cells which offer numerous transformations for both stimuli and responses, particular
capture paths are inverted, resulting in an increased number of

Proceedings of the Seventh IEEE European Test Workshop (ETW02)

1530-1877/02 $17.00 2002 IEEE

Circuit
s713
s953
s1423
s5378
s9234
s13207
s15850
s35932

[6] alone
45.5
40.3
51.9
38.0
42.6
39.1
53.9
47.9

[6] and proposed

53.7
47.9
57.2
44.5
50.5
43.7
60.4
53.2

Improvement
15.0
12.7
11.1
10.5
13.8
7.6
14.1
10.2

Table 5. Proposed scheme in conjunction with [6]

transformations for test responses. Since no gate delays are introduced to the critical paths, no interference with the normal
operation of the circuit exists.
To demonstrate the efficacy of the proposed approach, we
have applied it on several ISCAS85 and ISCAS89 benchmark
circuits. The experimental results indicate that significant average and peak test power reductions are achieved with slight
additional area cost. This area cost is negligible compared to
the test application time saved due to the increased parallelism
among core tests that the proposed methodology enables.

References
[1] H. J. Wunderlich and S. Gerstendorfer, Minimized power consumption for scan based BIST, in ITC, pp. 8594, 1999.
[2] T. Huang and K. Lee, An input control technique for power
reduction in scan circuits during test application, in ATS, pp.
315320, 1999.
[3] R. Sankaralingam, R. R. Oruganti and N. A. Touba, Adapting
scan architectures for low power operation, in VTS, pp. 3540,
2000.
[4] V. Dabholkar, S. Chakravarty, I. Pomeranz and S. M. Reddy,
Techniques for minimizing power dissipation in scan and
combinational circuits during test application, IEEE TCAD,
vol. 17, n. 12, pp. 13251333, 1998.
[5] L. Whetsel, Adapting scan architectures for low power operation, in ITC, pp. 863872, 2000.
[6] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault and
S. Pravossoudovitch, A gated clock scheme for low power
scan testing of logic ICs or embedded cores, in ATS, pp. 253
258, 2001.
[7] Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch and H.J. Wunderlich, A modified clock scheme for
a low power BIST test pattern generator, in VTS, pp. 306311,
2001.
[8] O. Sinanoglu, I. Bayraktaroglu and A. Orailoglu, Test Power
Reduction Through Minimization of Scan Chain Transitions,
in VTS, pp. 161169, 2002.
[9] F. Brglez, D. Bryan and K. Kozminski, Combinational Profiles
of Sequential Benchmark Circuits, IEEE ISCAS, vol. 14, n. 2,
pp. 19291934, May 1989.
[10] H. K. Lee and D. S. Ha, On the Generation of Test Patterns
for Combinational Circuits, Technical Report 12-93, Department of Electrical Eng., Virginia Polytechnic Institute and State
University.