Timing Diagram

Representation of Various Control signals generated during

Execution of an Instruction.
Following Buses and Control Signals must be shown in a
Timing Diagram:
Higher Order Address Bus.
Lower Address/Data bus
ALE
RD
WR
IO/M

Timing Diagram
Instruction:
A000h

MOV A,B

Corresponding Coding:
A000h

78

Timing Diagram
Instruction:
A000h

MOV A,B

Corresponding Coding:
A000h

78

OFC

8085

Memory

Timing Diagram
Instruction:
A000h

T1

MOV A,B

Corresponding Coding:
A000h

T2

T3

T4

A0h

A15- A8 (Higher Order Address bus)

00h

78h

78
ALE
RD

WR

OFC

8085

Memory

IO/M

Op-code fetch Cycle

Timing Diagram
Instruction:
A000h

MVI A,45h

Corresponding Coding:
A000h

3E

A001h

45

Timing Diagram
Instruction:
A000h

MVI A,45h

Corresponding Coding:
A000h

3E

A001h

45

OFC
MEMR

8085

Memory

Timing Diagram
T1

T2

T3

T4

T5

T6

A0h

T7

A0h

A15- A8 (Higher Order Address bus)

00h

3Eh

01h

45h

DA7-DA0 (Lower order address/data Bus)

Instruction:
A000h MVI A,45h
Corresponding Coding:
A000h

3E

A001h

45

ALE
RD

WR

IO/M

Op-Code Fetch Cycle

Memory Read Cycle

Timing Diagram
Instruction:
A000h

LXI A,FO45h

Corresponding Coding:
A000h

21

A001h

45

A002h

F0

Timing Diagram
Instruction:
A000h

LXI A,FO45h

Corresponding Coding:

OFC

A000h

MEMR

21

A001h

45

A002h

F0

MEMR

8085

Memory

Timing Diagram

T1

T2

T3

Memory Read Cycle

Memory Read Cycle

Op-Code Fetch Cycle

T4

T5

A0h

T6

T7

T8

A0h

T9

T10

A0h

A15- A8 (Higher Order Address bus)

00h

21h

DA7-DA0 (Lower order address/data Bus)

ALE
RD

WR

IO/M

01h

45h

02h

F0h

Timing Diagram
Instruction:
A000h

MOV A,M

Corresponding Coding:
A000h

7E

Timing Diagram
Instruction:
A000h

MOV A,M
OFC

Corresponding Coding:
A000h

MEMR

7E
8085

Memory

Timing Diagram
T1

T2

T3

T4

A0h

T5

T6

T7

Content Of Reg H

A15- A8 (Higher Order Address bus)

00h

Instruction:

7Eh

L Reg

Content Of M

DA7-DA0 (Lower order address/data Bus)

A000h MOV A,M

Corresponding Coding:
A000h

7E

ALE
RD

WR

IO/M

Op-Code Fetch Cycle

Memory Read Cycle

Timing Diagram
Instruction:
A000h

MOV M,A

Corresponding Coding:
A000h

77

Timing Diagram
Instruction:
A000h

MOV M,A
OFC

Corresponding Coding:
A000h

MEMW

77
8085

Memory

Timing Diagram
T1

T2

T3

T4

A0h

T5

T6

T7

Content Of Reg H

A15- A8 (Higher Order Address bus)

00h

Instruction:

7Eh

L Reg

Content of Reg A

DA7-DA0 (Lower order address/data Bus)

A000h MOV M,A

Corresponding Coding:
A000h

77

ALE
RD

WR

IO/M

Op-Code Fetch Cycle

Memory Write Cycle