Design of a Temperature-Compensated

CMOS Relaxation Oscillator

Orazio Aiello
Microelectronics EMC Group, Eln. Dept., Politecnico di Torino
Corso Duca degli Abruzzi, 24, I-10129 Torino, Italy
Email: orazio.aiello@polito.it

VDD

AbstractThis paper deal with a square-wave relaxation

oscillator with a high temperature-steadiness of the oscillation
frequency. A conventional relaxation oscillator is first considered.
Then, a modified version with a reduced temperature coefficient
of its oscillation frequency is proposed. A temperature stability of
the oscillation frequency below the 5% in the range [40125] C
is discussed and evaluated by means of time domain simulations.

ICHARGE

Comparator
Switch

I. I NTRODUCTION
Clock reference is a needful part of any synchronous digital
circuit. In order to achieve an excellent frequency stability
with temperature (below 1ppm
C ), variation in supply voltage
and process, quartz crystal oscillators are usually employed as
clock reference. Nevertheless, the inability to include quartz
oscillator in standard CMOS process increases the overall size
and the cost of the system. The problem of achieving an
oscillation frequency that does not depend on the temperature
has raised especially for low-cost applications. For a general
purpose clock reference, a temperature-independent oscillation
frequency usually means a maximum frequency variation less
than 5% in a temperature range [40 125] C. BiCMOS
multi-vibrator offer excellent temperature stability [1], [2] but
cannot be included in standard CMOS. A very precise clock
reference based on a ring oscillator and a relaxation oscillator
for low-power application have been performed for a specific
oscillation frequency [3], [4].
In relaxation oscillators the stability with the temperature
is usually achieved using a dual comparator architecture [5].
Anyhow, these circuits include latches and need external
voltage and current reference whose temperature coefficients
concur to the overall frequency steadiness of the relaxation
oscillator [6] - [8]. In this paper, a relaxation oscillator with
a percentage variation of the frequency oscillation due to
the temperature below 5% has been designed by means of a
modulation of the temperature-dependance of the bias current.
The present paper details the design of a temperature
compensated, fully trimmable on-chip IC relaxation oscillator
in 0.35m CMOS technology process. This paper is organized
as follows. In section II a common method to design a clock
my means of a relaxation oscillator is described. On the
basis of the oscillator operation, a temperature-compensated
design is considered in Section III. Finally, in Section IV some
concluding remarks are drawn.

VOUT

VTRIANGLE

C
IDISCHARGE

Fig. 1.

VTH

Relaxation oscillator scheme

charging

discharging

Vhyst
VTL

Fig. 2. Capacitor voltage waveform VTRIANGLE and output square-wave

voltage of the relaxation oscillator VOUT .

II. O N - CHIP R ELAXATION O SCILLATOR

A subclass of relaxation oscillator family where current
sources are used to charge and discharge the timing capacitor
is sketched in Fig. 1 [5]. The capacitor C is charged until
the voltage across its terminals VTRIANGLE exceeds the upper
threshold voltage of the comparator VTH . It implies the switch-

VDD
S

M12

M16

M3

M18

Switch

M7

M4

M8

VDD/2

M1

M2

M19

M22

VDD/2

M6

M9

ICHARGE

Current
reference

IB

VOUT

M20

IDISCHARGE

M5

M17

M10

M21

Fig. 3.

IB (T )
fosc (T ) =
2 C Vhyst (T )

(1)

where IBIAS is the current that provided the charging/discharging of the capacitor C. The charge and discharge
currents are set to be equal (ICHARGE = IDISCHARGE = IB )
for a duty cycle equal to 0.5). Vhyst = VTH VTL is the
amplitude of the hysteresis window of the comparator. Eq. 1
highlights that the temperature-dependent terms that concur to
the steadiness of the oscillation frequency are the bias current
IBIAS and hysteresis voltage Vhyst .
A schematic of a relaxation oscillator where the timing capacitor is charged/discharged by a current reference is reported
in Fig. 3. The bias current IB is usually provided by a current
reference and its value is considered to be constant during the
oscillator design. Since the same current is mirrored to supply
several circuits in the same chip, the bias current dependance
to the temperature is usually minimized.
Even through, the bias current IB does not strongly depend
on the temperature, the comparator hysteresis Vhyst changes
with the temperature due to a respective drift of the process
parameter Kn as can be highlighted in eq. (2).

Vhyst (T ) = 2

M11

Comparator

Schematic A: Relaxation oscillator with a fixed bias current

ing of the output voltage VOUT of the threshold comparator

that, in turn, enables the discharging of the capacitor C. Such a
discharging continues until the voltage VTRIANGLE falls below
the lower threshold of the comparator VTL . Then, the entire
cycle repeats. The voltage across the capacitor VTRIANGLE
and the square waveform provided by the relaxation oscillator
VOUT are represent in Fig. 2. Neglecting the switching delay,
the oscillation frequency can be written as

IB_c

VTRIANGLE

M23

W
L 6,7

IB c
( ) ( )
W
Kn (T ) W
L 1,2
L

( )
W

+
6,7

(W )
L

3,4

3,4

(2)
For the relaxation oscillator described in Fig. 3, several contributes find out the overall temperature coefficient of the oscil-

1
fTosc . Such a coefficient depends
lation frequency T Cf = fosc
on the stability of internal charge and discharge currents with
temperature; stability of the hysteresis comparator thresholds
across the temperature range; comparator bias and leakage
current deviations due to temperature changes. In order to
reduce T Cf , the temperature variation of the aforementioned
contributes have been considered in the following Section.

III. T EMPERATURE -C OMPENSATED R ELAXATION

O SCILLATOR D ESIGN
Eq. (1) shows that the oscillator frequency is inversely
proportional to the hysteresis voltage Vhyst . It means that for a
temperature-independent bias current IB , any temperature drift
of Vhyst results in an equal amount of relative frequency drift.
Any junction leakage current or comparator input bias current
at the timing terminal will add or subtract from the oscillator
charge and discharge current and will cause a frequency error.
Normally, junction leakage currents are in the nanoampere
range. Thus, their effects on frequency accuracy and frequency
drift are negligible. Therefore, the main contributes to the
frequency drift are given by only two effect: the drift of the
charge and discharge bias current and the drift of the total
hysteresis voltage Vhyst . A positive temperature coefficient
of Vhyst results in a negative contribution to temperature
coefficient of the oscillation frequency. Therefore, designing
a bias current circuitry with a positive temperature coefficient
it is possible to compensate the drift of the hysteresis window Vhyst , minimizing the overall variation of the oscillation
frequency due to the temperature changes. In fact using a
constant external current reference IB (Schematic A: Fig. 3),
it was observed a variation of frequency (above 10%) in the
temperature range of 40 to 125 C due to the comparator
hysteresis drift (see the upper dashed lines in Fig. 5).
In order to minimize the frequency variation due to the
temperature, a modulation of the bias current IB has been
considered. The temperature variation of the current IB is
provided by the temperature drift of a resistance R and the

VDD
S

M12

M16

Current
T-dependent

Switch

M6

M7

M4

M8

M9
S

VDD/2

M1

M2

M19

M22

VDD/2

M3

M18
ICHARGE

IB

VOUT

M20

R
IDISCHARGE

M13

IB_c

VTRIANGLE

M23
C

M21

M17

Fig. 4.

M11

M5
M10

Comparator

Schematic B: Relaxation oscillator with a temperature-dependent bias current

process temperature-dependant parameters of the transistors

in the bias current branch (red dashed line in Fig. 4).
With reference to the circuit in Fig. 4, the Kirchoffs voltage
law (KVL) equation
g = VDD VSG12 IB R VGS13 = 0

(3)

can be written as

IB R +

(
IB

1
+
Kp ( W
L )12

1
Kn ( W
L )13

)
+

VDD + Vtn + |Vtp | = 0

(4)
To minimize the temperature dependence of the frequency,
the frequency temperature coefficient T Cf has been pointed
out.
T Cf =

1
fosc

fosc IB
f Vhyst

IB T
Vhyst T

Fig. 5. Temperature vs Frequency percentage error of the schematic in Fig.

3 (upper lines) and in Fig. 4 (lower lines)

)
.

(5)

It depends on the temperature variation of the bias current

and that of the hysteresis voltage reported respectively in eq.
(6) and eq. (7). On the basis of such equations, the temperature
coefficient of the oscillation frequency has been found out
in eq. (8). Properly choosing the size of the transistor M13
and the value of the resistor R, the temperature coefficient
of the frequency T Cf can be strongly reduced. Once the
temperature coefficient of the frequency T Cf has been minimized, the value of the temperature-independent oscillation
frequency fosc can be modified by means of a variation of
the timing capacitor C. In fact C influences the frequency but
not its temperature coefficient T Cf . Furthermore, as can be
highlighted from eq. (8), T Cf does depend on the size of the
transistors M3-M4 and M6-M7 that define the amplitude of
the hysteresis voltage Vhyst .

According to the aforementioned equations, a 5MHz

temperature-compensated relaxation oscillator has been designed with a bias current at room temperature equal to 40A
and a timing capacitor equal to C = 10pF . A comparison
between the temperature behavior of oscillator with constant
bias current (Schematic A: Fig. 3) and the presented oscillator
with a bias current modulation (Schematic B: Fig. 4) has been
reported in Fig. 5. The relaxation oscillator with constant
external bias current has frequency variations above 10%
(upper black dashed line in Fig. 5) in the temperature range
[40 125] C. This is due to Vhyst drift. The proposed
solution aimed to minimize the overall temperature coefficient
of the oscillation frequency shows a frequency drift below 5%
(lower black dashed line in Fig. 5).
In Fig. 6, the maximum and minimum variations of the
oscillation frequency in Montecarlo simulations considering
all the process variations of the simulations parameters are


IB
=
T

IB
Kp ( W
L )12

Kp
T

Vhyst
T

Kp
IB
T
Kp ( W
L )12

Vtn
n
|Vtp | + K (IBW ) K
T + T Vtn
n
L 13
(
)
VDD +Vtn +|Vtp |
1
2 R+
IB
(
)
1
1 IB
1 Kn
= Vhyst

2
IB T
Kn T
|Vtp |
T

R
T

IB R
(6)

(7)

(
)
1
fosc
1 IB
IB Kn
T Cf =

= IB

=
f
T
2 T
Kn T
osc
|V |
Kn
Vtn
R
B
+ Ttp |Vtp | + K IW
T + T Vtn T IB R
n( L )
1 Kn
13

1
Kn T
2 (R IB + VDD + Vtn + |Vtp |)
(8)

V. APPENDIX
The first-order temperature coefficient of the reference current is obtained from the total differential of eq. (3), which
implicitly defines the reference current as a function of technology and design parameters [9]. This differential is evaluated
assuming the current IB and the absolute temperature T as
independent variables and taking into account that the only
temperature-dependent quantities that appear in eq. (3) are n,
p, Vtn , Vtp ed R.
g(IB )
g(n, p, Vtn , Vtp , R)
dIB +
dT = 0
IB
T

(9)

This differential, on the basis of eq. (3), can be written as

eq. (6).
R EFERENCES
Fig. 6. Temperature vs Frequency percentage error of the Schematic B.
Minimum and maximum variations of the process parameter (Montecarlo
analysis)

reported. Such a simulations show that in the worst case, the

frequency temperature drift is lower than 6%. The presented
circuits shows a low process dependence of temperature frequency steadiness (eventually adjustable though a trimming on
the resistance R or the timing capacitor C).

IV. C ONCLUSIONS
A temperature-independent relaxation oscillator that can be
employed as on-chip clock reference has been designed. An
oscillation frequency independent by the temperature changes
has been achieved considering a compensation among the
temperature-dependent terms that define the itself oscillation
frequency. Furthermore, changing the value of the timing capacitor, is possible to achieve a different oscillation frequency
with the same minimized temperature coefficient.

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