Digital Electronics Lab-I: Laboratory Manual (EEC-352)

Digital Electronics Lab-I
LABORATORY MANUAL
[For Specific Focus to Laboratory Work]
[EEC-352 ]
Compiled By:
Sneihil Gopal
Lecturer, Electronics & Communication Department
Department of Electronics & Communication Engineering
PSAT Pranveer Singh Institute of Technology

Bhauti, Kalpi Road, Kanpur
List of Content
S.No. Content Page No.

1. Introduction
2. Syllabus
3. Index of Experiments
4. Manuals of all Experiments
5. Quizzes

INTRODUCTION
Here are some guidelines to help you perform the experiments and to submit the
reports:
1. Read all instructions carefully and carry them all out.

2. Ask a demonstrator if you are unsure of anything.
3. Record actual results (comment on them if they are unexpected!)
4. Write up full and suitable conclusions for each experiment.
5. If you have any doubt about the safety of any procedure, contact the
demonstrator beforehand.
6. THINK about what you are doing!

The Breadboard
The breadboard consists of two terminal strips and two bus strips (often broken
in the centre). Each bus strip has two rows of contacts. Each of the two rows of
contacts are a node. That is, each contact along a row on a bus strip is connected
together (inside the breadboard). Bus strips are used primarily for power supply
connections, but are also used for any node requiring a large number of
connections. Each terminal strip has 60 rows and 5 columns of contacts on each
side of the centre gap. Each row of 5 contacts is a node.
You will build your circuits on the terminal strips by inserting the leads of
circuit components into the contact receptacles and making connections with
22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab.
It is a good practice to wire +5V and 0V power supply connections to separate
bus strips.

Fig 1. The breadboard. The lines indicate connected holes.

The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of power
to the ICs could result in them exploding or becoming very hot - with the
possible serious injury occurring to the people working on the experiment!
Ensure that the power supply polarity and all components and connections
are correct before switching on power .
Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The
steps for wiring a circuit should be completed in the order described below:
1. Turn the power (Trainer Kit) off before you build anything!
2. Make sure the power is off before you build anything!
3. Connect the +5V and ground (GND) leads of the power supply to the
power and ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the
chips in the same direction with pin 1 at the upper-left corner. (Pin 1 is
often identified by a dot or a notch next to it on the chip package)
5. Connect +5V and GND pins of each chip to the power and ground bus
strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up
wire between corresponding pins of the chips on your breadboard. It is
better to make the short connections before the longer ones. Mark
each connection on your schematic as you go, so as not to try to make
the same connection again at a later stage.
7. Get one of your group members to check the connections, before you
turn the power on.
8. If an error is made and is not spotted before you turn the power on.
Turn the power off immediately before you begin to rewire the circuit.
9. At the end of the laboratory session, collect you hook-up wires, chips
and all equipment and return them to the demonstrator.
10.Tidy the area that you were working in and leave it in the same
condition as it was before you started.

Common Causes of Problems
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the
circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
In all experiments, you will be expected to obtain all instruments, leads,

components at the start of the experiment and return them to their proper place
after you have finished the experiment. Please inform the demonstrator or
technician if you locate faulty equipment. If you damage a chip, inform a
demonstrator, don't put it back in the box of chips for somebody else to use.
Example Implementation of a Logic Circuit
Build a circuit to implement the Boolean function F = ( Á . B́ ).

Quad 2 Input 7400 Hex 7404 Inverter

Fig 2. The complete designed and connected circuit
Sometimes the chip manufacturer may denote the first pin by a small indented
circle above the first pin of the chip. Place your chips in the same direction, to
save confusion at a later stage. Remember that you must connect power to the
chips to get them to work.

Useful IC Pin details
7400(NAND)
7402(NOR)

7404(NOT)
7408(AND)
7411(3-i/p AND)

7432(OR)
7486(EX-OR)

7410(3-i/p NAND)

7420(4-i/p NAND)

SYLLABUS
EEC-352 : Digital Electronics Lab-I
Objective: To understand the digital logic and create various systems by using
these logics.
1. Introduction to digital electronics lab- nomenclature of digital ICs,
specifications, study of the data sheet, concept of V cc and ground, verification
of the truth tables of logic gates using TTL ICs.
2. Implementation of the given Boolean function using logic gates in both SOP
and POS forms.
3. Verification of state tables of RS, JK, T and D flip-flops using NAND &
NOR gates.
4. Implementation and verification of Decoder/De-multiplexer and Encoder
using logic gates.
5. Implementation of 4x1 multiplexer using logic gates.
6. Implementation of 4-bit parallel adder using 7483 IC.
7. Design, and verify the 4-bit synchronous counter.
8. Design, and verify the 4-bit asynchronous counter.
9. Mini Project.

INDEX
Roll No…………………
S. No. Name of Experiment Page Date Signature Remarks

No.
1. Introduction to digital
electronics lab-
nomenclature of digital ICs,
specifications, study of the
data sheet, concept of Vcc
and ground, verification of
the truth tables of logic gates
using TTL ICs.
2. Implementation of the given
Boolean function using logic
gates in both SOP and POS
forms.
3. Verification of state tables
of RS, JK, T and D flip-
flops using NAND & NOR
gates.
4. Implementation and
verification of Decoder/De-
multiplexer and Encoder
using logic gates.
5. Implementation of 4x1
multiplexer using logic gates
6. Implementation of 4-bit
parallel adder using 7483
IC.
7. Design, and verify the 4-bit
synchronous counter.
8. Design, and verify the 4-bit
asynchronous counter.
9. Mini Project.

EXPERIMENT NO-1
Date of Experiment Grade Faculty’s Signature Date
OBJECTIVE:.
Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the
data sheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL
ICs.
APPARATUS REQUIRED:
Sr.No. Name of Apparatus Specifications Qty.

1 7400 TTL NAND gate 01
2 7408 TTL AND gate 01
3 7432 TTL OR gate 01
4 7402 TTL NOR gate 01
5 7404 TTL NOT gate 01
6 7486 TTL X-OR gate 01
7 Digital Trainer kit With Bread board& 5V dc Supply 01
8 Patch cords As required
THEORY:
IC Faimaly summary:- Various families of lofic Ics exist on the market however the
families. Mainly used in digital electronics lab are the TTL and the high speed CMOS
families.
Nomenclature of digital IC’s :-
MM74XXXNNNRP
MM - Manufacturer

74/54 - Temparature range
XXX - Technology tipe
NNN - Logic function
R - Revision
RP - Package type
Manufacturer ----- MM
SN - Taxas Instrument, Motorola
DM - National semioconductor
Temparature Range -74 or 54

74 ----- standard (commercial) 0 to 700C
54 ----- Military -55 to 1250c
Technology type XXX

LS --- Low power shottky
ALS-- Advanced low power schottky
Fv --- Fast TTL
HC --- high speed CMOS
C --- Low speed CMOS
Vcc :- It is supply voltage which operate any instrument without damaged. Vcc terminal is
always Red.
Ground :- It is zero potential point, GND terminal is always Black.
PROCEDURE:
1. OR gate
 Place the 2 input OR gate IC 7432 in the bread board.
 Connect pin No.14 to Vcc(+5V) and pin 7 to ground.
 Make the connection for gate 1 connect among pin 1,2 and 3
 Verify the truth table for various combinations of inputs.
2. AND gate
 Place two input IC AND gate IC7408 on the bread board.
 Repeat step 2 to 4 as given for OR gate.
3. NOT gate
 Place NOT gate IC 7404 on the Bread board.
 Connect pin No.14 to Vcc(+5V) and pin 7 to ground.
 Let us consider the first gate connected between the pin 1 and 2.
 Verify the truth table for different inputs.

4. NAND gate
 Place two input NAND gate IC 7400 on the bread board.
5. NOR gate
 Place two input IC NOR gate IC7402 on the bread board.
 Connect the output to pin no.3
6. X-OR gate
 Place two input IC X-OR gate IC7486 on the bread board.
 Repeat step 2 to 4 as given for OR gate

Logic Diagrams and Truth table of various logic gates:

A B Output Q
0 0 0
0 1 1
1 Gate 0 Description1 Truth Table
1 AND Gate 1 0
The AND gate is a logic Outpu
gate that gives an output A B
tQ
of '1' only when all of its 0 0 0
inputs are '1'. Thus, its 0 1 0
output is '0' whenever at
1 0 0
least one of its inputs is
1 1 1
'0'. Mathematically, Q =
A · B.
OR Gate The OR gate is a logic Outpu
gate that gives an output A B
tQ
of '0' only when all of its 0 0 0
inputs are '0'. Thus, its 0 1 1
output is '1' whenever at
1 0 1
least one of its inputs is
1 1 1
'1'. Mathematically, Q =
A + B.
NOT Gate The NOT gate is a logic Output
gate that gives an output A
Q
that is opposite the state 0 1
of its 1 0
input. Mathematically, Q
= A.
NAND Gate The NAND gate is an Outpu
AND gate with a NOT A B
tQ
gate at its end. Thus, for 0 0 1
the same combination of 0 1 1
inputs, the output of a
1 0 1
NAND gate will be
1 1 0
opposite that of an AND
gate. Mathematically, Q
= A · B.
NOR Gate The NOR gate is an OR Outpu
gate with a NOT gate at A B
tQ
its end. Thus, for the same 0 0 1
combination of inputs, the 0 1 0
output of a NOR gate will
1 0 0
be opposite that of an OR
gate.Mathematically, Q 1 1 0
= A + B.
PSAT The EXOR
Pranveer Singh Institute
EXOR Gate
gate (for
of Technology
'EXclusive OR' gate) is a
logic gate that gives an
output of '1' when only one
of its inputs is '1'.
RESULT:
Introduction to digital electronics lab –nomenclature of digital Ics, specifications studuy of

data sheet, concept of Vcc and ground ,Verification of truth tables of logic gates using TTL
Ics.
PRECAUTIONS:
 All the IC should be checked before use the apparatus.

 All LEDs should be checked.
 All connection should be tight.
 Always connect GND first and then connect Vcc.
 Used suitable type Patch cords.
 The circuit should be off before change the connections
After completed experiment switched off the supply of the apparatus
EXPERIMENT NO-2
OBJECTIVE:
Implementation of the given Boolean function using logic gates in both SOP and POS forms.
APPARATUS REQUIRED:
S.No. Name of apparatus Specification Quantity

1 SOP & POS kit Using 7404,7408, 7432. 01
2 Patch cords ------------------------ As required
THEORY:
Logical functions are generally expressed in terms of logical variables. Values taken on by
the logical functions and logical variables are in the binary form. An arbitrary logic function
can be expressed in the following forms:
(i) Sum of Products (SOP)
(ii) Product of Sums (POS)
Sum of Products (SOP):

The logic sum of two or more logical product terms is called a Sum of Products expression. It
is basically an OR operation of AND operated variable such as:
Y = AB + BC + AC
Y = AB + Á C + BC
In this approach we simplified the given Boolean expression using basic Boolean lows and
theorem. In this approach we assign 1 value to normal variable and 0 to its complements.
Also considered the values to find the expression from any arithmetic or logic calculation.
Sum of Product solution logic diagram
Product of Sum(POS)
Product of Sums (POS):

A product of sums expression is a logical product of two or more logical sum terms. It is
basically an AND operation of OR operated variables such as:
(i) Y = (A+B) (B+C)(C+ Á )
(ii) Y = (A+B+C)(A+Ć )
In POS form we simplified the given Boolean expression using basic Boolean lows and
theorem. In this approach we assign 0 values to normal variable and 1 to its complements.
Also considered the values to find the expression from any arithmetic or logic calculation.

The POS solution logic diagram
Procedure:-
 Connect the circuit as per circuit diagram.
 Switch ON the experimental board.
 Give the inputs to A & B through switches.
 Observed the output y on the kit through LEDs
 For different combination of inputs observe the output and match them with
respective truth table and verify the equations SOP & POS.
Truth Table for SOP Truth Table for POS

INPUT OUTPUT INPUT OUTPUT
A B Y= Á B+ A B́ A B Y=( Á+ B ) ( A+ B́)
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0
RESULT:
Study of Boolean function and both equations SOP&POS are verified.
PRECAUTIONS:
 All the ICs should be checked before starting the experiment.
 All the connection should be tight.
 Always connect ground 1st and then connect Vcc.
 Suitable type wire should be used for different types of circuit.
 The kit should be Off before change the connections.
 After completed the experiment switched off the supply of the apparatus.
EXPERIMENT NO-3
OBJECTIVE:
Verification of state tables of R-S, J-K ,T & D flip-flop using NAND and NOR Gates.
APPARATUS REQUIRED:
Sr.No. Name of Apparatus Specifications Qty.

1 Flip-flop trainer kit Using 7404,7400,7476 IC 01
2 Patch cards ----- As required
THEORY :

Flip-flop:-The basic one bit digital memory circuit is known as flip-flop. It can have store
0or 1state. Flip –flops are classified according to the number of inputs.
R-S Flip-flop:- This circuit is similar to SR latch except enable signal is replaced by clock
pulse.
Logic Diagram
CLOCK S R Qn Qn+1 State

0 0 0 0 Qn
0 0 1 1 (No Change)
0 1 0 0 Reset
0 0 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Prohibited
1 1 1 X state
D Flip-flop

The modified clocked SR flip-flop is known as D flp-flop . From the truth table SR flip-flop
we see that the output of the SR flip-flop is in unpredictable state when the inputs are same.
In many practical applications, these input conditions are not required. These input conditions
can be avoided by making then complement of each other.
Logic diagram:
Output Qn+1 = CLK . D + CLK Qn
Truth Table
CLK D Qn Qn+1 State

1 0 X 0 Reset
1 1 X 1 Set
0 X X Qn N.C.
J-K Flip-flop:
In a RS flip-flop the input R=S= 1 lead to an indeterminate output. The RS flip-flop circuit
may be rejoined so that if both inputs are 1 then also the output are complements of one
another.
Logic diagram:
Truth table:

CLOCK J K Qn Qn+1 State
0 0 0 0 Qn
0 0 1 1 (No Change)
0 1 0 0 Reset
0 1 1 0
1 0 0 1 Set
1 0 1 1
1 1 0 X Qn
1 1 1 X (Toggle)
T FLIP-FLOP:
T flip-flop is also known as Toggle flip-flop. The T flip-flop is a modification of the J-K flip-
flop. Both the J K inputs of the JK flip flop are held at logic 1 and the clock signal continuous
to change the outputs will simply change state with each rising edge of the clop signal.
Logic diagram:
Truth table:
CLOCK T Qn Qn+1 State

0 0 0
0 1 1 NC
1 0 1
1 1 0 Toggle
PROCEDURE:
 Connections are made as per circuit diagram.
 Verify truth table for various combinations of inputs
RESULT:
 Study and verified truth of various flip-flops.
Precautions:
 All the IC should be checked before use the apparatus.
 All LEDs should be checked.
 All connection should be tight.
 Always connect GND first and then connect Vcc.
 Used suitable type Patch cords.
 The circuit should be off before change the connections
 After completed experiment switched off the supply of the apparatus.
EXPERIMENT NO-4
OBJECTIVE:
Implementation & verification of Decoder/Demultiplexer and Encoder using logic gates.
APPARATUS REQUIRED:
Sr.No. Name of apparatus Specification Quantity

1 Encoder/decoder kit Using logic gates 01

THEORY:
Decoder:
A Decoder is a multiple –input and multiple output combinational logic circuits which
converts coded inputs into coded outputs, where the input and output coded are different.
Logic diagram of 2 to 4 Decoder
Procedure:
 Connect the supply from the trainer kit through patch cords, also connect circuit
diagram as per circuit diagram.
 Give the input to A, B and EN through switches.
 Observe the output Yo to Y3 on the trainer kit through LEDs.
 For different combinations of inputs observe the outputs and match them with truth
table.
Truth Table
Inputs Outputs
EN A B Y3 Y2 Y1 Yo
1 X X 0 0 0 0
0 0 0 0 0 0 1
0 0 1 0 0 1 0
PSAT Pranveer
0 Singh
1 Institute
0 0of Technology
1 0 0
0 1 1 1 0 0 0
Encoder:
An encoder is a combinations logic circuit. It is the reverse of a decoder function. It has 2 n
input lines and n output lines. An encoder accepts an active level on one of its inputs
representing a digit such as a decimal/octal digit and it convert to coded output.
EXPERIMENT NO-5
OBJECT:
Implementation of 4x1 Multiplexer using logic gates.
APPARATUS REQUIRED:

1 MUX kit Using 7404,7411,7432 01
THEORY:
Multiplexer:
A multiplexer (MUX) is a device that accepts data from one of many input sources for
transmission over a common shared line. To achieve this MUX has several data lines and a
single output along with data-select inputs, which permit digital data on any one of the inputs
to be switched to the output line. The logic symbol for a 1-of-4 data selector/multiplexer is
shown in Figure:
Figure: - Logic symbol for 1-of-4 multiplexer
The selection lines decide the number of inputs lines of particular multiplexer. If the number
of n inputs lines is equal to 2m , then m select lines are required to select one of the n input
line .
Note that if a binary zero appears on the data-select lines then data on input line D 0 will
appear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0
Similarly, the data output is equal to D1, D2 and D3 for , and

, respectively. Thus the total multiplexer logic expression, formed from ORing
terms is

The implementation of this equation is as shown in Figure
Figure: - Logic circuit for 1-of-4 multiplexer
PROCEDURE:
 Connections are made as per circuit diagram.

 Verify the truth table.
 Also connect Vcc and Ground the perform experiment.
TRUTH TABLE :
Data Select Inputs Input Selected
S1 S0
0 0 D0
0 1 D1
1 0 D2
1 1 D3

RESULT:
Study of 4x1 multiplexer and verified its truth table.
PRECAUTIONS:

 The kit should be OFF before change the connections.
EXPERIMENT NO-6
OBJECT:
Implementation of 4- bit parallel adder using 7483 IC.
APPARATUS REQUIRED:-

1 Encoder/decoder kit Using logic gates 01
THEORY:
Adder: An adder is a logic circuit which adds two or three bits at a time and give sum and
carry as the result.
Parallel Adder:
A n –bit parallel adder can be constructed using number of full adders circuit connected in
parallel the carry output of each is connected to the carry input of the next higher –order
adder.
Since all the bits of the augends and addend are fed into the adder circuits simultaneously and
the additions in each position are known as parallel adder.
A3 A2 A1 A0 Augends bits
B3 B2 B1 B0 Addend bits
S3 S2 S1 S0 Sum bits
Logic diagram of BCD Adder & sub tractor

Where A0, A1, A2, A3 &B0, B1, B2, B3 are BCD inputs
S0, S1, S2, S3 Are sum outputs, M is control inputs
Pin diagram of 7483 IC
PROCEDURE:
 Connect ground and Vcc to 7483 IC from trainer kit through patch cords.
 Connect inputs A1, A2, A3, A4 and B1, B2, B3, B4 to logic input switches.
 Connect carry in CY1 to ground so that carry input will be in logic state 0.
 Connect SUM1, SUM2, SUM3, SUM4 and carry out CYo to the ouput display.
 Verify the truth table for different combinations of inputs.
Truth Table of 4-bit parallel adder

Outputs
Inputs CYO=L
CYI=L
A1 B1 A2 B2 S1 S2 C1
A3 B3 A4 B4 S3 S4 Co
L L L L L L L
H L L L H L L
L H L L H L L
H H L L L H L
L L H L L H L
H L H L H H L
L H H L H H L
H H H L L H L
L L L H L H L
H L L H H H L
L H L H H H L
H H L H L L H
L L H H L L H
H L H H H L H
L H H H H L H
H H H H L H H
RESULT:
Study of parallel adder using 7483IC and verified the truth table.
PRECAUTIONS:
 The kit should be OFF before change the connections.

EXPERIMENT NO-7
OBJECT :
Design and verified 4-bit synchronous counter.
APPARATUS REQUIRED:-

1 4-bit Synch. Counter kit Using 74193 IC 01
THEORY:-
Synchronous counter:-
Synchronous counter is one in which all the flip-flops are triggered simultaneously by the
clock pulse. So they are also called parallel counters. In synchronous counter clock pulse is
applied common to all the flip-flops.
A 4-bit synchronous counter can be made by using IC 74193. Here D0, D1, D2, D3 are the
data inputs. CLKU and CLKD is the pin specified for required operation of the chip(as UP
counter or as DOWN counter). We got the data on Qo, Q1, Q2, Q3
Logic Diagram of 4-bit asynchronous counter
PROCEDURE:-
 Connect all the data inputs and clock to the CLKU (pin no. 5) or CLKD (pin no. 4) for
UO and DOWN counter respectively.
 For the counter porpuse CLR (pin no.14) and S (pin no.11) should be low and high
respectively.

 For UP counting CLKU connected to Clock and CLKD should be high vice –versa.
 Output can be observed from Qo, Q1, Q2, Q3 on LEDs.
 To Reset counter make CLR input should be high.
Mode selection table:-
CLKU CLKD CLR S FUNCTION
H L H Count UP
H L H Count Down
X X H X Reset
X X L L Load input
Pin Diagram of 74193 IC Truth Table as UP counter
RESULT:
Study of 4- bit Synchronous counter using 74193IC and mode selection, truth table is
verified.
PRECAUTIONS:

EXPERIMENT NO-8
OBJECT :
Design and verify 4-bit Asynchronous Counter.
APPARATUS REQUIRED:

1 4-bit Asynch. Counter kit Using 7493 IC 01
THEORY:
Asynchronous Counter:
In asynchronous counter, the flip-flop is clocked by the External clock pulse and each
successive flip-flop is clocked from the previous flip-flop output. Design a ripple counter, the
number of flip-flops required depend upon of the number of states. The maximum number of
the output state of a counter is 2n Where n is a number of flip-flop of the counter.
A ripple counter can be constructed by use of clocked J-K flip-flops.
The A flip-flop must be change state before it can trigged the B flip-flop, and B flip-flop has
to change state before it can trigger C flip flop. And flip- flop has to change state before it can
be trigger the D lip-flop.
7493 Four-Bit asynchronous Counter:

The 7493A is presented as an example of a specific integrated circuit asynchronous counter.
This device actually consists of a single flip-flop ‘A’ and a three-bit asynchronous counter
( B, C & D ). This arrangement is for flexibility. It can be used as devide-by-2 device if only
the single flip-flop is used, or it can be used as a modulus-8 counter if only the three-bit
counter portion is used.
This device also provides gated reset inputs, R0(1) and R0(2). When both of these inputs are
HIGH, the counter is RESET to the 0000 by the CLR .
In addition, the 7493 can be used as a four-bit modulus-16 counter (counts 0 through 15) by
connecting the QA output to the CLK(B) input.
It can also configured as a decade counter (counts 0 through 9) with asynchronous recycling
by using the gated reset inputs for partial decoding of count ten. This will be done by connect
QB with R0(1) and QD with R0(2).

Logic diagram of 4-bit asynchronous counter:-
PROCEDURE:
 Connect the circuit as per circuit diagram.

 Verify the given mode selection and truth table.

Mode select table
RESET INPUTS OUTPUTS
Mr1 Mr2 Q3 Q2 Q1 Q0
H H L L L L
L H COUNT
H L COUNT
L L COUNT
RESULT:
Study of 4- bit asynchronous counter using 7493IC and mode selection, truth table is
verified.
PRECAUTIONS:



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Digital Electronics Lab-I

Department of Electronics & Communication Engineering

PSAT Pranveer Singh Institute of Technology

S.No. Content Page No.

4. Manuals of all Experiments

PSAT Pranveer Singh Institute of Technology

1. Read all instructions carefully and carry them all out.

PSAT Pranveer Singh Institute of Technology

Fig 1. The breadboard. The lines indicate connected holes.

PSAT Pranveer Singh Institute of Technology

Building the Circuit

PSAT Pranveer Singh Institute of Technology

In all experiments, you will be expected to obtain all instruments, leads,

Example Implementation of a Logic Circuit

Build a circuit to implement the Boolean function F = ( Á . B́ ).

Quad 2 Input 7400 Hex 7404 Inverter

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

EEC-352 : Digital Electronics Lab-I

PSAT Pranveer Singh Institute of Technology

S. No. Name of Experiment Page Date Signature Remarks

PSAT Pranveer Singh Institute of Technology

Date of Experiment Grade Faculty’s Signature Date

Sr.No. Name of Apparatus Specifications Qty.

Nomenclature of digital IC’s :-

PSAT Pranveer Singh Institute of Technology

Temparature Range -74 or 54

Technology type XXX

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

PSAT Pranveer Singh Institute of Technology

Introduction to digital electronics lab –nomenclature of digital Ics, specifications studuy of

 All the IC should be checked before use the apparatus.

After completed experiment switched off the supply of the apparatus

Date of Experiment Grade Faculty’s Signature Date

S.No. Name of apparatus Specification Quantity

PSAT Pranveer Singh Institute of Technology

Sum of Products (SOP):

Sum of Product solution logic diagram

Product of Sums (POS):

PSAT Pranveer Singh Institute of Technology

Truth Table for SOP Truth Table for POS

Date of Experiment Grade Faculty’s Signature Date

Sr.No. Name of Apparatus Specifications Qty.

PSAT Pranveer Singh Institute of Technology

CLOCK S R Qn Qn+1 State

PSAT Pranveer Singh Institute of Technology

CLK D Qn Qn+1 State

PSAT Pranveer Singh Institute of Technology

CLOCK T Qn Qn+1 State

PSAT Pranveer Singh Institute of Technology

Date of Experiment Grade Faculty’s Signature Date

Sr.No. Name of apparatus Specification Quantity

PSAT Pranveer Singh Institute of Technology

Logic diagram of 2 to 4 Decoder

Date of Experiment Grade Faculty’s Signature Date

Sr.No. Name of apparatus Specification Quantity

PSAT Pranveer Singh Institute of Technology