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-- Company: DKH LABS

-- Engineer: Deekshith Allamaneni
--
-- Create Date: 20:45:29 10/21/2010
-- Design Name: IC 7485 Cascading Four Bit Comparator
-- Module Name: Comp7485_bh - Behavioral
-- Project Name: 7485 Four bit comparator
-- Target Devices:
-- Tool versions:
-- Description: ECAD LAB; Deekshith Allamaneni; NMREC; 08B61A0421;
--Contact: http://www.adeekshith.blogspot.com/
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Comp7485_bh is
Port ( n1 : in STD_LOGIC_VECTOR (03 downto 0);
n2 : in STD_LOGIC_VECTOR (03 downto 0);
gip : in STD_LOGIC;
eip : in STD_LOGIC;
lip : in STD_LOGIC;
gop : out STD_LOGIC;
eop : out STD_LOGIC;
lop : out STD_LOGIC);
end Comp7485_bh;

architecture Behavioral of Comp7485_bh is

begin
process(n1,n2,gip,eip,lip)
begin
if(gip<='0' and eip<='1' and lip <='0') then
if(n1(3) > n2(3)) then
gop<='1'; eop<='0'; lop<='0';
elsif(n1(3) < n2(3)) then
gop<='0'; eop<='0'; lop<='1';
else
if(n1(2) > n2(2)) then
gop<='1'; eop<='0'; lop<='0';
elsif(n1(2) < n2(2)) then
gop<='0'; eop<='0'; lop<='1';
else
if(n1(1) > n2(1)) then
gop<='1'; eop<='0'; lop<='0';
elsif(n1(1) < n2(1)) then
gop<='0'; eop<='0'; lop<='1';
else
if(n1(0) > n2(0)) then
gop<='1'; eop<='0'; lop<='0';
elsif(n1(0) < n2(0)) then
gop<='0'; eop<='0'; lop<='1';
else
gop<='0'; eop<='1'; lop<='0';
end if;
end if;
end if;
end if;
elsif(gip<='1' and eip<='0' and lip<='0') then
gop<='1'; eop<='0'; lop<='0';
elsif(gip<='0' and eip<='0' and lip<='1') then
gop<='0'; eop<='0'; lop<='1';
else
gop<='1'; eop<='1'; lop<='1';
end if;
end process;
end Behavioral;