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Q549.2E
LA
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©
Copyright 2009 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by ER/EL 0965 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18311
2009-May-08
EN 2 1. Q549.2E LA Revision List
1. Revision List
Manual xxxx xxx xxxx.0
• First release.
Notes:
• Figures can deviate due to the different set executions.
• Specifications are indicative (subject to change).
For on-line product support please use the links in Table 2-1.
Here is product information available, as well as getting started,
user manuals, frequently asked questions and software &
drivers.
2009-May-08
Technical Specifications and, Connections Q549.2E LA 2. EN 3
2.3 Connections
4 3 2 1
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2009-May-08
EN 4 2. Q549.2E LA Technical Specifications and, Connections
Note: The following connector colour abbreviations are used Cinch: S/PDIF - Out
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq
Grey, Rd= Red, Wh= White, Ye= Yellow.
Cinch: Audio - Out
2.3.1 Side Connections Rd - Audio - R 0.5 VRMS / 10 kohm kq
Wh - Audio - L 0.5 VRMS / 10 kohm kq
Head phone (Output)
Bk - Head phone 32 - 600 ohm / 10 mW ot EXT3: Cinch: Video YPbPr - In, Audio - In
Gn - Video Y 1 VPP / 75 ohm jq
Cinch: Video CVBS - In, Audio - In Bu - Video Pb 0.7 VPP / 75 ohm jq
Rd - Audio R 0.5 VRMS / 10 kohm jq Rd - Video Pr 0.7 VPP / 75 ohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq Rd - Audio - R 0.5 VRMS / 10 kohm jq
Ye - Video CVBS 1 VPP / 75 ohm jq Wh - Audio - L 0.5 VRMS / 10 kohm jq
S-Video (Hosiden): Video Y/C - In EXT1 & 2: Video RGB - In, CVBS - In/Out, Audio - In/Out
1 - Ground Y Gnd H
20 2
2 - Ground C Gnd H
3 - Video Y 1 VPP / 75 ohm j
4 - Video C 0.3 VPP / 75 ohm j 21 1
10000_001_090121.eps
090121
USB2.0
Figure 2-4 SCART connector
11
6
15
RJ45: Ethernet (if present)
10000_002_090121.eps
090127
12345678
E_06532_025.eps
1 - Video Red 0.7 VPP / 75 ohm j 210905
2 - Video Green 0.7 VPP / 75 ohm j
3 - Video Blue 0.7 VPP / 75 ohm j
4 - n.c. Figure 2-5 Ethernet connector
5 - Ground Gnd H
6 - Ground Red Gnd H 1 - TD+ Transmit signal k
7 - Ground Green Gnd H 2 - TD- Transmit signal k
8 - Ground Blue Gnd H 3 - RD+ Receive signal j
9 - +5VDC +5 V j 4 - CT Centre Tap: DC level fixation
10 - Ground Sync Gnd H 5 - CT Centre Tap: DC level fixation
11 - n.c. 6 - RD- Receive signal j
12 - DDC_SDA DDC data j 7 - GND Gnd H
13 - H-sync 0-5V j 8 - GND Gnd H
14 - V-sync 0-5V j
15 - DDC_SCL DDC clock j
2009-May-08
Technical Specifications and, Connections Q549.2E LA 2. EN 5
2009-May-08
EN 6 3. Q549.2E LA Precautions, Notes, and Abbreviation List
• All ICs and many other semiconductors are susceptible to Due to lead-free technology some rules have to be respected
electrostatic discharges (ESD w). Careless handling by the workshop during a repair:
during repair can reduce life drastically. Make sure that, • Use only lead-free soldering tin. If lead-free solder paste is
during repair, you are connected with the same potential as required, please contact the manufacturer of your soldering
the mass of the set by a wristband with resistance. Keep equipment. In general, use of solder paste within
components and tools also at this same potential. workshops should be avoided because paste is not easy to
• Be careful during measurements in the high voltage store and to handle.
section. • Use only adequate solder tools applicable for lead-free
• Never replace modules or other components while the unit soldering tin. The solder tool must be able:
is switched “on”. – To reach a solder-tip temperature of at least 400°C.
• When you align the set, use plastic rather than metal tools. – To stabilize the adjusted temperature at the solder-tip.
This will prevent any short circuits and the danger of a – To exchange solder-tips for different applications.
circuit becoming unstable. • Adjust your solder tool so that a temperature of around
360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
3.3 Notes Avoid temperatures above 400°C, otherwise wear-out of
tips will increase drastically and flux-fluid will be destroyed.
3.3.1 General To avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Measure the voltages and waveforms with regard to the • Mix of lead-free soldering tin/parts with leaded soldering
chassis (= tuner) ground (H), or hot ground (I), depending tin/parts is possible but PHILIPS recommends strongly to
on the tested area of circuitry. The voltages and waveforms avoid mixed regimes. If this cannot be avoided, carefully
shown in the diagrams are indicative. Measure them in the clear the solder-joint from old tin and re-solder with new tin.
Service Default Mode with a colour bar signal and stereo
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
2009-May-08
Precautions, Notes, and Abbreviation List Q549.2E LA 3. EN 7
It should be noted that on the European Service website, 0/6/12 SCART switch control signal on A/V
“Alternative BOM” is referred to as “Design variant”. board. 0 = loop through (AUX to TV),
6 = play 16 : 9 format, 12 = play 4 : 3
The third digit in the serial number (example: format
AG2B0335000001) indicates the number of the alternative AARA Automatic Aspect Ratio Adaptation:
B.O.M. (Bill Of Materials) that has been used for producing the algorithm that adapts aspect ratio to
specific TV set. In general, it is possible that the same TV remove horizontal black bars; keeps
model on the market is produced with e.g. two different types the original aspect ratio
of displays, coming from two different suppliers. This will then ACI Automatic Channel Installation:
result in sets which have the same CTN (Commercial Type algorithm that installs TV channels
Number; e.g. 28PW9515/12) but which have a different B.O.M. directly from a cable network by
number. means of a predefined TXT page
By looking at the third digit of the serial number, one can ADC Analogue to Digital Converter
identify which B.O.M. is used for the TV set he is working with. AFC Automatic Frequency Control: control
If the third digit of the serial number contains the number “1” signal used to tune to the correct
(example: AG1B033500001), then the TV set has been frequency
manufactured according to B.O.M. number 1. If the third digit is AGC Automatic Gain Control: algorithm that
a “2” (example: AG2B0335000001), then the set has been controls the video input of the feature
produced according to B.O.M. no. 2. This is important for box
ordering the correct spare parts! AM Amplitude Modulation
For the third digit, the numbers 1...9 and the characters A...Z AP Asia Pacific
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be AR Aspect Ratio: 4 by 3 or 16 by 9
indicated by the third digit of the serial number. ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black
Identification: The bottom line of a type plate gives a 14-digit bars without discarding video
serial number. Digits 1 and 2 refer to the production centre (e.g. information
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers ATSC Advanced Television Systems
to the Service version change code, digits 5 and 6 refer to the Committee, the digital TV standard in
production year, and digits 7 and 8 refer to production week (in the USA
example below it is 2006 week 17). The 6 last digits contain the ATV See Auto TV
serial number. Auto TV A hardware and software control
system that measures picture content,
MADE IN BELGIUM and adapts image parameters in a
MODEL : 32PF9968/10
220-240V ~ 50/60Hz dynamic way
128W AV External Audio Video
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF AVC Audio Video Controller
S BJ3.0E LA AVIP
B/G
Audio Video Input Processor
Monochrome TV system. Sound
10000_024_090121.eps carrier distance is 5.5 MHz
090121
BLR Board-Level Repair
BTSC Broadcast Television Standard
Figure 3-1 Serial number (example) Committee. Multiplex FM stereo sound
system, originating from the USA and
3.3.7 Board Level Repair (BLR) or Component Level Repair used e.g. in LATAM and AP-NTSC
(CLR) countries
B-TXT Blue TeleteXT
If a board is defective, consult your repair procedure to decide C Centre channel (audio)
if the board has to be exchanged or if it should be repaired on CEC Consumer Electronics Control bus:
component level. remote control bus on HDMI
If your repair procedure says the board should be exchanged connections
completely, do not solder on the defective board. Otherwise, it CL Constant Level: audio output to
cannot be returned to the O.E.M. supplier for back charging! connect with an external amplifier
CLR Component Level Repair
3.3.8 Practical Service Precautions ComPair Computer aided rePair
CP Connected Planet / Copy Protection
CSM Customer Service Mode
• It makes sense to avoid exposure to electrical shock.
CTI Color Transient Improvement:
While some sources are expected to have a possible
manipulates steepness of chroma
dangerous impact, others of quite high potential are of
transients
limited current and are sometimes held in less regard.
CVBS Composite Video Blanking and
• Always respect voltages. While some may not be
Synchronization
dangerous in themselves, they can cause unexpected
DAC Digital to Analogue Converter
reactions that are best avoided. Before reaching into a
DBE Dynamic Bass Enhancement: extra
powered TV set, it is best to test the high voltage insulation.
low frequency amplification
It is easy to do, and is a good service precaution.
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
DFU Directions For Use: owner's manual
DMR Digital Media Reader: card reader
DMSD Digital Multi Standard Decoding
DNM Digital Natural Motion
2009-May-08
EN 8 3. Q549.2E LA Precautions, Notes, and Abbreviation List
DNR Digital Noise Reduction: noise uses 8 bit or 10 bit data words, and has
reduction feature of the set a maximum data rate of 270 Mbit/s,
DRAM Dynamic RAM with a minimum bandwidth of 135
DRM Digital Rights Management MHz.
DSP Digital Signal Processing ITV Institutional TeleVision; TV sets for
DST Dealer Service Tool: special remote hotels, hospitals etc.
control designed for service LS Last Status; The settings last chosen
technicians by the customer and read and stored
DTCP Digital Transmission Content in RAM or in the NVM. They are called
Protection; A protocol for protecting at start-up of the set to configure it
digital audio/video content that is according to the customer's
traversing a high speed serial bus, preferences
such as IEEE-1394 LATAM Latin America
DVB-C Digital Video Broadcast - Cable LCD Liquid Crystal Display
DVB-T Digital Video Broadcast - Terrestrial LED Light Emitting Diode
DVD Digital Versatile Disc L/L' Monochrome TV system. Sound
DVI(-d) Digital Visual Interface (d= digital only) carrier distance is 6.5 MHz. L' is Band
E-DDC Enhanced Display Data Channel I, L is all bands except for Band I
(VESA standard for communication LPL LG.Philips LCD (supplier)
channel and display). Using E-DDC, LS Loudspeaker
the video source can read the EDID LVDS Low Voltage Differential Signalling
information form the display. Mbps Mega bits per second
EDID Extended Display Identification Data M/N Monochrome TV system. Sound
(VESA standard) carrier distance is 4.5 MHz
EEPROM Electrically Erasable and MIPS Microprocessor without Interlocked
Programmable Read Only Memory Pipeline-Stages; A RISC-based
EMI Electro Magnetic Interference microprocessor
EPLD Erasable Programmable Logic Device MOP Matrix Output Processor
EU Europe MOSFET Metal Oxide Silicon Field Effect
EXT EXTernal (source), entering the set by Transistor, switching device
SCART or by cinches (jacks) MPEG Motion Pictures Experts Group
FDS Full Dual Screen (same as FDW) MPIF Multi Platform InterFace
FDW Full Dual Window (same as FDS) MUTE MUTE Line
FLASH FLASH memory NC Not Connected
FM Field Memory or Frequency NICAM Near Instantaneous Compounded
Modulation Audio Multiplexing. This is a digital
FPGA Field-Programmable Gate Array sound system, mainly used in Europe.
FTV Flat TeleVision NTC Negative Temperature Coefficient,
Gb/s Giga bits per second non-linear resistor
G-TXT Green TeleteXT NTSC National Television Standard
H H_sync to the module Committee. Color system mainly used
HD High Definition in North America and Japan. Color
HDD Hard Disk Drive carrier NTSC M/N= 3.579545 MHz,
HDCP High-bandwidth Digital Content NTSC 4.43= 4.433619 MHz (this is a
Protection: A “key” encoded into the VCR norm, it is not transmitted off-air)
HDMI/DVI signal that prevents video NVM Non-Volatile Memory: IC containing
data piracy. If a source is HDCP coded TV related data such as alignments
and connected via HDMI/DVI without O/C Open Circuit
the proper HDCP decoding, the OSD On Screen Display
picture is put into a “snow vision” mode OTC On screen display Teletext and
or changed to a low resolution. For Control; also called Artistic (SAA5800)
normal content distribution the source P50 Project 50: communication protocol
and the display device must be between TV and peripherals
enabled for HDCP “software key” PAL Phase Alternating Line. Color system
decoding. mainly used in West Europe (color
HDMI High Definition Multimedia Interface carrier= 4.433619 MHz) and South
HP HeadPhone America (color carrier PAL M=
I Monochrome TV system. Sound 3.575612 MHz and PAL N= 3.582056
carrier distance is 6.0 MHz MHz)
I2 C Inter IC bus PCB Printed Circuit Board (same as “PWB”)
I2 D Inter IC Data bus PCM Pulse Code Modulation
I2 S Inter IC Sound bus PDP Plasma Display Panel
IF Intermediate Frequency PFC Power Factor Corrector (or Pre-
IR Infra Red conditioner)
IRQ Interrupt Request PIP Picture In Picture
ITU-656 The ITU Radio communication Sector PLL Phase Locked Loop. Used for e.g.
(ITU-R) is a standards body FST tuning systems. The customer
subcommittee of the International can give directly the desired frequency
Telecommunication Union relating to POD Point Of Deployment: a removable
radio communication. ITU-656 (a.k.a. CAM module, implementing the CA
SDI), is a digitized video format used system for a host (e.g. a TV-set)
for broadcast grade video. POR Power On Reset, signal to reset the uP
Uncompressed digital component or PTC Positive Temperature Coefficient,
digital composite signals can be used. non-linear resistor
The SDI signal is self-synchronizing, PWB Printed Wiring Board (same as “PCB”)
2009-May-08
Precautions, Notes, and Abbreviation List Q549.2E LA 3. EN 9
2009-May-08
EN 10 4. Q549.2E LA Mechanical Instructions
4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing and Taping • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal
4.4 Set Re-assembly
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Mechanical Instructions Q549.2E LA 4. EN 11
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2009-May-08
EN 12 4. Q549.2E LA Mechanical Instructions
For easy servicing of this set, there are a few possibilities Each Ambi Light unit is mounted on a subframe. Refer to
created: Figure 4-5 for details.
• The buffers from the packaging.
• Foam bars (created for Service).
E_06532_018.eps
171106
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Figure 4-4 Foam bars 090319
4.3.2 Speakers 1
2009-May-08
EN 14 4. Q549.2E LA Mechanical Instructions
4
1
1
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Follow the instructions for LCD Panel until “remove plastic rim”.
After removal of this rim, you gain access to the Wi-Fi
antennas.
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 15
18310_219_090318.eps
Purpose 090319
• To create a pre-defined setting, to get the same
measurement results as given in this manual. Figure 5-1 Service mode pad
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
After activating this mode, “SDM” will appear in the upper right
protection (a sort of automatic stepwise start-up). See
corner of the screen (when a picture is available).
section “5.3 Stepwise Start-up”.
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”). How to Navigate
When the “MENU” (or HOME) button is pressed on the RC
transmitter, the TV set will toggle between the SDM and the
Specifications
normal user menu.
2009-May-08
EN 16 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
• To view operation hours. TV will go to the Stand-by mode. If the NVM was corrupted or
• To display (or clear) the error code buffer. empty before this action, it will be initialized first (loaded with
default values). This initializing can take up to 20 seconds.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” button. After activating SAM
with this method a service warning will appear on the screen,
Display Option
continue by pressing the “OK” button on the RC. Code
27mm
MODEL:
32PF9968/10
main software (example: Q5492-1.2.3.4 = PROD.SERIAL NO:
AG 1A0620 000001
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Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 17
• With the “OK” key, it is possible to activate the selected NVM. ComPair will foresee in a possibility to do this. This
action. identification number is the 12nc number of the SSB.
• 12NC display. Shows the 12NC of the display.
How to Exit SAM • 12NC supply. Shows the 12NC of the supply.
Use one of the following methods: • 12NC “fan board”. Shows the 12NC of the “fan board”-
• Switch the TV set to STAND-BY via the RC-transmitter. module (for sets with LED backlight)
• Via a standard RC-transmitter, key in “00” sequence, or • 12NC “LED Dimming Panel”. Shows the 12NC of the
select the “BACK” key. LED dimming Panel (for sets with LED backlight).
General
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee in a possibility to do this.
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee a in possibility to
do this.
• Installed date. Indicates the date of the first installation of
the TV. This date is acquired via time extraction.
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
• 12NC SSB. Gives an identification of the SSB as stored in
NVM. Note that if an NVM is replaced or is initialized after
corruption, this identification number has to be re-written to
2009-May-08
EN 18 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
5.3 Stepwise Start-up mode with a faulty FET 7U08 is done, you can destroy all IC’s
supplied by the +3V3, due to overvoltage (12V on 3V3-line). It
When the TV is in a protection state due to an error detected by is recommended to measure first the FET 7U08 or others
FET’s on shortcircuit before activating SDM via the service
stand-by software (error blinking is displayed) and SDM is
pads.
activated via shortcutting the pins on the SSB, the TV starts up
until it reaches the situation just before protection. So, this is a
kind of automatic stepwise start-up. In combination with the
The abbreviations “SP” and “MP” in the figures stand for:
start-up diagrams below, you can see which supplies are
present at a certain moment. Important to know is, that if e.g. • SP: protection or error detected by the Stand-by
Processor.
the 3V3 detection fails and thus error layer 2 = 18 is blinking
• MP: protection or error detected by the MIPS Main
while the TV is restarted via SDM, the Stand-by Processor will
enable the 3V3, but the TV set will not go to protection now. Processor.
The TV will stay in this situation until it is reset (Mains/AC
Power supply interrupted). Caution: in case the start-up in this
Mains
off Mains
on
St by
- No data Acquisition
required
Semi Active
- tact SW pushed
- last status is hibernate St by - St by requested
after mains ON - tact SW pushed
- Tact switch Pushed
- last status is hibernate
after mains ON
Tact switch
pushed WakeUp
requested
(SDM)
GoToProtection
Hibernate
GoToProtection
Protection
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Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 19
Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available .
st-by µP resets
Initialise I/O pins of the st-by µP: If the protection state was left by short circuiting the
- Switch reset-AVC LOW (reset state) SDM pins, detection of a protection condition during
- Switch WP-NandFlash LOW (protected) startup will stall the startup. Protection conditions in a
- Switch reset-system LOW (reset state) playing set will be ignored. The protection mode will
- Switch reset-5100 LOW (reset state) not be entered.
- Switch reset-Ethernet LOW (reset state)
- Switch reset-ST7100 LOW (reset state)
- keep reset-NVM high, Audio-reset and Audio-Mute-Up HIGH
Yes
Enter protection
The supply-fault line is a
1V2 DCDC or class D error:
Supply-fault I/O combination of the DCDC
No Layer1: 2
High? converters and the audio
Layer2: 19
protection line.
Yes
Enter protection
This enables the +3V3 and
+5V converter. As a result,
Enable the DCDC converter for +3V3 and
also +5V-tuner, +2V5, +1V8-
+5V. (ENABLE-3V3)
PNX8541 and +1V8-PNX5100
become available.
Wait 50ms Delay of 50ms needed because of the latency of the detect-1 circuit.
This delay is also needed for the PNX5100. The reset of the
PNX5100 should only be released 10ms after powering the IC.
yes
Enter protection
Detect-1 I/O line Detect-2 I/O line Disable 3V3, switch standby
No No
High? High? line high and wait 4 seconds
No Release Reset-PNX5100.
PNX5100 will start booting.
EJTAG probe
Yes
connected ?
No
No Cold boot?
Yes
Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism
I_17660_125a.eps
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EN 20 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
Reset-system is switched HIGH by the Reset-system is switched HIGH by the Release reset MPEG4 module:
AVC at the end of the bootscript AVC at the end of the bootscript BOLT-ON-IO: High
Reset-system is connected to USB -reset,
4to1HDMI Mux and channel decoder.
AVC releases Reset-Ethernet when the AVC releases Reset-Ethernet when the MPEG4 module will start booting
end of the AVC boot-script is detected end of the AVC boot-script is detected autonomously.
This cannot be done through the bootscript,
the I/O is on the standby µP
Reset-Audio and Audio-Mute-Up are Reset-Audio and Audio-Mute-Up are Wait 3000 ms
switched by MIPS code later on in the switched by MIPS code later on in the
Timing need to be updated if startup process startup process
more mature info is available.
Log SW event:
Bootscript ready POR polling positive ? No
No STi7100PorFailure
in 1250 ms?
No
Yes Wait 200 ms
yes
Set I²C slave address
of Standby µP to (60h)
Initialize audio
Wait 5ms
Switch Standby
3-th try?
I/O line high.
Yes
Download firmware into the channel
No
decoder
Blink Code as
error code
Downloaded
Third try? No
Enter protection successfully ?
Yes Yes
initialize AutoTV
Semi-Standby I_17660_125b.eps
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Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 21
autonomous action
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON -> SEMI -> ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON-> SEMI-
>STBY -> SEMI -> ON can be made in less than 2s, Wait until previous on-state is left more than 2
the semi -> stby transition has to be delayed seconds ago. (to prevent LCD display problems)
until the requirement is met.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Active I_17660_126.eps
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EN 22 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON->SEMI ->ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON -> SEMI-
->STBY -> SEMI -> ON can be made in less than 2s, Wait until previous on-state is left more than 2
the semi -> stby transition has to be delayed seconds ago. (to prevent LCD display problems)
until the requirement is met.
Wait until valid and stable audio and video , corresponding to the requested
output is delivered by the AVC
AND
[the backlight PWM has been on for 1s (internal inverter LPL displays
OR the backlight PWM has been on for 2s (external inverter LPL displays)] .
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Active I_17660_127.eps
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2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 23
Semi Standby
The assumption here is that a fast toggle (<2s)
can only happen during ON -> SEMI -> ON. In
these states, the AVC is still active and can
provide the 2s delay. If the transition ON -> SEMI-
>STBY->SEMI->ON can be made in less than 2s, Wait until previous on-state is left more than 2
the semi -> stby transition has to be delayed seconds ago. (to prevent LCD display problems)
until the requirement is met.
Release audio mute and wait 100ms before any other audio
handling is done (e.g. volume change)
Active I_17660_128.eps
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2009-May-08
EN 24 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
autonomous action
Wait 100ms
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Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 25
autonomous action
Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing , the lights will
switch off abruptly when the supply is cut.
Wait 10ms
Wait 5ms
Important remark:
release reset audio 10 sec after
entering standby to save power
I_17660_130.eps
Stand by 140308
2009-May-08
EN 26 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
Wait 10ms
Wait 5ms
I_17660_131.eps
Protection 140308
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 27
5.4.1 ComPair With this tool you can test the memory of the PNX8543, as well
if the PNX5100 is enabled and audio-testing.
Introduction
ComPair (Computer Aided Repair) is a Service tool for Philips What is needed?
Consumer Electronics products. and offers the following: – An USB-stick
1. ComPair helps to quickly get an understanding on how to – “TESTSCRIPT Q549”. Downloadable from the Philips
repair the chassis in a short and effective way. Service website from the section “Software for Service
2. ComPair allows very detailed diagnostics and is therefore only”
capable of accurately indicating problem areas. No – A ComPair/service cable (3138 188 75051).
knowledge on I2C or UART commands is necessary,
because ComPair takes care of this. Procedure
3. ComPair speeds up the repair time since it can Create a directory “JETTFILES” under the root of the USB-stick
automatically communicate with the chassis (when the uP – Place “MemTestTV543.bin” and “autojett.bin” (available in
is working) and all repair information is directly available. “TESTSCRIPT Q549”) under the directory “JETTFILES”
4. ComPair features TV software up possibilities. – Install the computer program “BOARDTESTLOGGER”
(available in “TESTSCRIPT Q549”) on the PC
Specifications – Connect a “ComPair/service”-cable from the service-
ComPair consists of a Windows based fault finding program connector in the set, into the “multi function” jack at the
and an interface box between PC and the (defective) product. front of the ComPair II box :
The ComPair II interface box is connected to the PC via an Required settings in ComPair :
USB cable. For the TV chassis, the ComPair interface box and - start up the ComPair application.
the TV communicate via a bi-directional cable via the service - Select the correct database (open file “Q549.2E LA”, this
connector(s). will set the ComPair interface in the appropriate mode).
The ComPair fault finding program is able to determine the - Close ComPair
problem of the defective television, by a combination of – Start up the program “BOARDTESTLOGGER” and select
automatic diagnostics and an interactive question/answer “COMx”
procedure. – Put the USB stick into the TV and start up the TV while
pressing the “i+”-button on a Philips DVD RC6 remote
control (it’s also possible to use a TV remote in “DVD”-
How to Connect
mode)
This is described in the chassis fault finding database in
ComPair. – On the PC the memory test is shown now. This is also
visible on the TV screen.
TO TV – In “BOARDTESTLOGGER” an option “Send extra UART
TO
UART SERVICE
TO
I2C SERVICE
TO
UART SERVICE
command” can be found where you can select “AUD1”.
CONNECTOR CONNECTOR CONNECTOR
This command generates hear test tones of 200, 400,
1000, 2000, 3000, 5000, 8000 and 12500Hz.
ComPair II
Multi
RC in function
RC out
5.5.1 Introduction
PC
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
ComPair II Developed by Philips Brugge
shift one position to the right.
Optional power
When an error occurs, it is added to the list of errors, provided
HDMI
I2C only
5V DC
the list is not full. When an error occurs and the error buffer is
E_06532_036.eps
full, then the new error is not added, and the error buffer stays
150208
intact (history is maintained).
To prevent that an occasional error stays in the list forever, the
Figure 5-12 ComPair II interface connection
error is removed from the list after more than 50 hrs. of
operation.
Caution: It is compulsory to connect the TV to the PC as When multiple errors occur (errors occurred within a short time
shown in the picture above (with the ComPair interface in span), there is a high probability that there is some relation
between), as the ComPair interface acts as a level shifter. If between them.
one connects the TV directly to the PC (via UART), ICs will be
blown! New in this chassis is the way errors can be displayed:
How to Order • There is a simple blinking LED procedure for board level
ComPair II order codes: repair (home repair) so called LAYER 1 errors next to the
• ComPair II interface: 3122 785 91020. existing errors which are LAYER 2 errors (see Table 5-2).
• Software is available via the Philips Service web portal. – LAYER 1 errors are one digit errors.
• ComPair UART interface cable for Q54x.x. – LAYER 2 errors are 2 digit errors.
(using 3.5 mm Mini Jack connector): 3138 188 75051. • In protection mode.
– From consumer mode: LAYER 1.
Note: While encounting problems, contact the local support – From SDM mode: LAYER 2.
desk. • Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
– From SDM mode: LAYER 2.
Important remark:
2009-May-08
EN 28 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
For all errors detected by MIPS which are fatal => • Via polling on I/O pins going to the stand-by processor.
rebooting of the TV set (reboot starts after LAYER 1 • Via sensing of analog values on the stand-by processor or
error blinking), one should short the solder paths the PNX8543.
(SDM) at start-up from the power OFF state by mains • Via a “not acknowledge” of an I2C communication.
interruption and not via the power button to trigger the
SDM via the hardware pins. Take notice that some errors need several minutes before they
• In CSM mode start blinking or before they will be logged. So in case of
– When entering CSM: error LAYER 1 will be displayed problems wait 2 minutes from start-up onwards, and then
by blinking LED. Only the latest error is shown. check if the front LED is blinking or if an error is logged.
• In SDM mode
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
• In the ON state
– In “Display error mode”, set with the RC commands
“mute_06250X _OK” LAYER 2 errors are displayed via
blinking LED.
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 29
2009-May-08
EN 30 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
logged and displayed via the blinking LED procedure when • Activate the CSM. The blinking front LED will show only
SDM is switched on. the latest layer 1 error, this works in “normal operation”
• Error 42 (Temp sensor). Only applicable for TV sets with mode or automatically when the error/protection is
an I2C controlled screen. monitored by the standby processor.
• Main NVM. When there is no I2C communication towards In case no picture is shown and there is no LED blinking,
the main NVM, LAYER 1 error = 2 will be displayed via the read the logging to detect whether “error devices” are
blinking LED procedure. In SDM, LAYER 2 error will be mentioned. (see section “5.8 Fault Finding and Repair
blinked as “15”. Errors here can not be logged due to Tips, 5.8.6 Logging”).
inaccessibility of the NVM device. • Activate the SDM. The blinking front LED will show the
• Error 53. This error will indicate that the PNX8543 has entire content of the LAYER 2 error buffer, this works in
read his bootscript (when this would have failed, error 15 “normal operation” mode or when SDM (via hardware pins)
would blink) but initialization was never completed because is activated when the tv set is in protection.
of hardware problems (NAND flash, ...) or software Important remark:
initialization problems. Possible cause could be that there For all errors detected by MIPS which are fatal =>
is no valid software loaded (try to upgrade to the latest main rebooting of the TV set (reboot starts after LAYER 1 error
software version). Note that it can take a few minutes blinking), one should short the solder paths at start-up from
before the TV starts blinking LAYER 1 error = 2 or in SDM, the power OFF state by mains interruption and not via the
LAYER 2 error = 53. power button to trigger the SDM via the hardware pins.
• Error 64. Only applicable for TV sets with an I2C controlled • Transmit the commands “MUTE” - “062500” - “OK”
screen . with a normal RC. The complete error buffer is shown.
Take notice that it takes some seconds before the blinking
LED starts.
5.6 The Blinking LED Procedure • Transmit the commands “MUTE” - “06250x” - “OK”
with a normal RC (where “x” is a number between 1
5.6.1 Introduction and 5). When x = 1 the last detected error is shown, x = 2
the second last error, etc.... Take notice that it takes some
The blinking LED procedure can be split up into two situations: seconds before the blinking LED starts.
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
This will be only one digit error, namely the one that is
5.7 Protections
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This 5.7.1 Software Protections
approach will especially be used for home repair and call
centres. The aim here is to have service diagnosis from a Most of the protections and errors use either the stand-by
distance. microprocessor or the MIPS controller as detection device.
• Blinking LED procedure LAYER 2 error. Via this procedure, Since in these cases, checking of observers, polling of ADCs,
the contents of the error buffer can be made visible via the and filtering of input values are all heavily software based,
front LED. In this case the error contains 2 digits (see table these protections are referred to as software protections.
“5-2 Error code overview”) and will be displayed when SDM There are several types of software related protections, solving
(hardware pins) is activated. This is especially useful for a variety of fault conditions:
fault finding and gives more details regarding the failure of • Protections related to supplies: check of the 12V, +5V,
the defective board. +3V3 and 1V2.
• Protections related to breakdown of the safety check
Important remark: mechanism. E.g. since the protection detections are done
For all errors detected by MIPS which are fatal => rebooting of by means of software, failing of the software will have to
the TV set (reboot starts after LAYER 1 error blinking), one initiate a protection mode since safety cannot be
should short the solder paths at start-up from the power OFF guaranteed any more.
state by mains interruption and not via the power button to
trigger the SDM via the hardware pins. Remark on the Supply Errors
The detection of a supply dip or supply loss during the normal
When one of the blinking LED procedures is activated, the front playing of the set does not lead to a protection, but to a cold
LED will show (blink) the contents of the error buffer. Error reboot of the set. If the supply is still missing after the reboot,
codes greater then 10 are shown as follows: the TV will go to protection.
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit
2. A pause of 1.5 s Protections during Start-up
3. “n” short blinks (where “n”= 1 to 9) During TV start-up, some voltages and IC observers are
4. A pause of approximately 3 s, actively monitored to be able to optimise the start-up speed,
5. When all the error codes are displayed, the sequence and to assure good operation of all components. If these
finishes with a LED blink of 3 s monitors do not respond in a defined way, this indicates a
6. The sequence starts again. malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
Example: Error 12 8 6 0 0. the start-up flow in detail (see section “5.3 Stepwise Start-up”).
After activation of the SDM, the front LED will show:
1. One long blink of 750 ms (which is an indication of the 5.7.2 Hardware Protections
decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
The only real hardware protection in this chassis appears in
3. Eight short blinks followed by a pause of 3 s
case of an audio problem e.g. DC voltage on the speakers. This
4. Six short blinks followed by a pause of 3 s protection will only affect the Class D (7D10) and puts the
5. One long blink of 3 s to finish the sequence
amplifier in a continuous burst mode (cyclus approximately 2
6. The sequence starts again.
seconds).
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 31
loudspeakers will move slowly in one or the other direction started immediately when +12V incoming voltage is available
until the initial failure shuts the amplifier down, this cyclus (+12V is enabled by STANDBY signal, active low). Supply
starts over and over again. voltages +3V3, 2V5, +1V8-PNX5100, +1V8-PNX85XX, +5V
and +5V-TUN are switched-on directly by signal ENABLE-3V3
5.7.3 Important remark regarding the blinking LED indication (active low), provided that +12V (detected via 7U40 &7U41) is
available. +12V is considered OK (=> DETECT -12V signal
becomes high and 12V/3V3 and 12V/5V DC-DC converter can
As for the blinking LED indication, the blinking led of LAYER 1
be started up) if it rises above 10V5 (typical) and doesn’t drop
error displaying can be switched off by pushing the power
button on the keyboard. below 10V (typical).
This condition is not valid after the set was unpowered (via
mains interruption). The blinking LED starts again and can only Debugging
be switched off by unplugging the mains connection. The best way to find a failure in the DC/DC converters is to
This can be explained by the fact that the MIPS can not load check their start-up sequence at power-on via the mains cord,
the keyboard functionality from software during the start-up and presuming that the standby microprocessor and the external
doesn’t recognizes the keyboard commands at this time. supply are operational. Take STANDBY signal high-to-low
transition as time reference.
When +12V becomes available (maximum 1 second after
5.8 Fault Finding and Repair Tips STANDBY signal goes low) then +1V2-PNX85XX and +1V2-
PNX5100 are started immediately. Then, after ENABLE-3V3
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra goes low, all the other supply voltages should rise within 2ms.
Info”.
Tips
5.8.1 Ambilight • When an output supply voltage is short-circuited to GND
the corresponding DC-DC converter is not making any
Due to degeneration process of the AmbiLights, there can be a audible noise, the converter switches-off immediately and
difference in the colour and/or light output of the spare will attempt a re-start only after +12V drops and rises
ambilight module in comparison with the originals ones again.
contained in the TV set. Via ComPair the light output can be • Check the integrity (at least no short-circuit between drain
adjusted. and source) of power MOS-FETs, especially the high-side
ones: 7U05, 7U08, 7U0D-1 and 7U0H-1 before starting the
platform in SDM mode, otherwise it can be easily
5.8.2 Audio Amplifier
damaged.
• Switching frequency of DC-DC converters should be
The Class D-IC 7D10 has a powerpad for cooling. When the IC around 290KHz for 12V to 1V2 DC-DC converters and
is replaced it must be ensured that the powerpad is very well around 370KHz for 12V to 3V3 and 12V to 5V DC-DC
pushed to the PWB while the solder is still liquid. This is needed converters.
to insure that the cooling is guaranteed, otherwise the Class D-
IC could break down in short time.
5.8.5 Exit “Factory Mode”
5.8.3 CSM
When an “F” is displayed in the screen’s right corner, this
means the set is in “Factory” mode, and it normally
When CSM is activated and there is a USB stick connected to happens after a new SSB is mounted. To exit this mode, push
the TV, the software will dump the complete CSM content to the the “VOLUME minus” button on the TV’s local keyboard for 10
USB stick. The file (Csm.txt) will be saved in the root of the USB seconds (this disables the continuous mode).
stick. If this mechanism works it can be concluded that a large Then push the “SOURCE” button for 10 seconds until the “F”
part of the operating system is already working (MIPS, USB...) disappears from the screen.
2009-May-08
EN 32 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
5.8.7 Loudspeakers
5.8.10 PCI bus To prevent damage on the coax wires, especially the female
core of the coax wires (can be bend over during dis- and
The splash screen image is not distributed via the regular YUV reconnecting), this should be carried out by use of pliers.
signal path from the PNX8543 to the PNX51XX, but loaded one
time via the PCI bus.Once the splash screen image is loaded
into the PNX51XX, it will be continuously generated by the
PNX51XX until the first incoming video disables the splash
screen.So when teletext and/or general UI is available, but no
splash screen (option “ON”) is visible during start-up, check the
PCI bus as possible root cause.
The EDID MUX device (including all HDMI NVM except the 4th)
is upgradeable via USB, see ComPair for further instructions. It
should be noted that in case a new spare EDID MUX device is
used for repair, the initial default address must be changed
from “C0” to “CE”, to be done via ComPair.
The EDID for VGA connector or the 4th HDMI can only be
upgraded via external I2C. To upgrade the EDID for the VGA
connector or 4th HDMI, pin 7 of the EDID NVM has to be short
circuited to ground. Therefore a test point is foreseen (see
Figure 5-13). For the VGA EDID NVM it’s most suitable to
connect pin 7 to ground on the NVM device itself. See ComPair
for further instructions.
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 33
START
Set is still
Set is going into protection after operating?
replacing the SSB
(blinking LED, error 2). No
Create “repair” directory on USB stick and
Take care that speakers are connected! connect USB stick to TV-set
In some sets, the speakers are in the rear Go to SAM mode (062596 i+) and
cover, and when the set is switched “on” save the TV settings via “Upload to USB”.
without speakers, it is possible that the Audio
protection is triggered.
- Replace SSB board by a Service SSB.
Advise: remount rear cover before switching - Make the SSB fit mechanically to the set.
“on” (see also SCC_71772).
Start-up set.
Set behaviour?
Set is starting up but no display. Set is starting up & display is OK. Set is starting up in “Factory” mode.
After entering “Display Option” code, set is Unplug the mainscord to verify the correct
going to Standby (= validation of code). disabling of the factory-mode.
Saved settings
No After entering “Display Option” code, set is going
on USB stick?
to Standby (= validation of code).
2009-May-08
EN 34 5. Q549.2E LA Service Modes, Error Codes, and Fault Finding
5.9 Software Upgrading 5. The renamed “upg” file will be visible and selectable in the
upgrade application.
5.9.1 Introduction
Back-up Software Upgrade Application
If the default software upgrade application does not start (could
The set software and security keys are stored in a NAND-
be due to a corrupted boot 2 sector) via the above described
Flash, which is connected to the PNX8543 via the PCI bus.
method, try activating the “back-up software upgrade
application”.
It is possible for the user to upgrade the main software via the
How to start the “back-up software upgrade application”
USB port. This allows replacement of a software image in a
manually:
stand alone set, without the need of an E-JTAG debugger. A 1. Disconnect the TV from the Mains/AC Power.
description on how to upgrade the main software can be found
2. Press the “INFO”-button on a Philips remote control or
in the DFU.
“CURSOR DOWN” button on a Philips DVD RC-6 remote
control (it is also possible to use a TV remote in “DVD”
Important: When the NAND-Flash must be replaced, a new mode). Keep the “INFO”-button (or “cursor down” button)
SSB must be ordered, due to the presence of the security keys! pressed while reconnecting the TV to the Mains/AC Power.
(copy protection keys, MAC address, ...). 3. The software upgrade application will start.
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
5.9.3 Stand-by Software Upgrade via USB
2. Update the TV software => see the eUM (electronic User
Manual) for instructions.
3. Perform the alignments as described in chapter 6 (section In this chassis it is possible to upgrade the Stand-by software
via a USB stick. The method is similar to upgrading the main
6.5 Reset of Repaired SSB).
software via USB.
4. Check in CSM if the HDMI key, MAC address.. are valid.
For the correct order number of a new SSB, always refer to the Use the following steps:
1. Create a directory “UPGRADES” on the USB stick.
Spare Parts list!
2. Copy the Stand-by software (part of the one-zip file, e.g.
StandbySW_CFT72_88.0.0.0.upg) into this directory.
5.9.2 Main Software Upgrade 3. Insert the USB stick into the TV.
4. Start the download application manually (see section “
• The “UpgradeAll.upg” file is only used in the factory. Manual Software Upgrade”.
• The “FlashUtils.upg” file is only used by service centra 5. Select the appropriate file and press the “OK” button to
which are allowed to do component level repair on the upgrade.
SSB.
5.9.4 Content and Usage of the One-Zip Software File
Automatic Software Upgrade
In “normal” conditions, so when there is no major problem with
Below the content of the One-Zip file is explained, and
the TV, the main software and the default software upgrade instructions on how and when to use it.
application can be upgraded with the “AUTORUN.UPG”
(FUS part of the one-zip file: e.g. 3104 337 05661 _FUS
• BootProm_PNX5120_Q5492_x.x.x.x.zip. A programmed
_Q5492_ 1.26.15.0_commercial.zip). This can also be done by
the consumers themselves, but they will have to get their device can be ordered via the regional Service
organization.
software from the commercial Philips website or via the
• Ceisp2padll_P2PAD_x.x.x.x.zip. Not to be used by
Software Update Assistant in the user menu (see eUM). The
“autorun.upg” file must be placed in the root of the USB stick. Service technicians. For ComPair development only.
• DDC_Q5492_x.x.x.x.zip. Contains the content of the VGA
How to upgrade:
NVM. See ComPair for further instruction.
1. Copy “AUTORUN.UPG” to the root of the USB stick.
2. Insert USB stick in the set while the set is in ON MODE. • EDID_Q5492_x.x.x.x.zip. Contains the EDID content of
the different EDID NVM’s. See ComPair for further
The set will restart and the upgrading will start
instructions.
automatically. As soon as the programming is finished, a
message is shown to remove the USB stick and restart the • EJTAGDownload_Q5492_x.x.x.x.zip. Only used by
service centra which are allowed to do component level
set.
repair.
• FUS_Q5492_x.x.x.x_commercial.zip. Contains the
Manual Software Upgrade “autorun.upg” which is needed to upgrade the TV main
In case that the software upgrade application does not start
software and the software download application.
automatically, it can also be started manually.
• Factory_Q5492_x.x.x.x_commercial.zip. Only for
How to start the software upgrade application manually: production purposes, not to be used by Service
1. Disconnect the TV from the Mains/AC Power.
technicians.
2. Press the “OK” button on a Philips TV remote control or a
• FlashUtils_Q5492_x.x.x.x_commercial.zip. Not to be
Philips DVD RC-6 remote control (it is also possible to use used by Service technicians.
a TV remote in “DVD” mode). Keep the “OK” button
• MOP_RAC3_x.x.x.x.zip. Contains the MOP local contrast
pressed while reconnecting the TV to the Mains/AC Power.
software and is upgradeable via USB (UPG). This SW is
3. The software upgrade application will start. not part of the FUS autorun.upg!
• OAD_Q5492_x.x.x.x.zip. Not to be used by Service
Attention! Technicians.
In case the download application has been started manually, • OpenSourceFile_Q5492_x.x.x.x.zip. Not to be used by
the “autorun.upg” will maybe not be recognized. Service technicians.
What to do in this case: • PQPrivate_Q5492_x.x.x.x.zip. Not to be used by Service
1. Create a directory “UPGRADES” on the USB stick. technicians.
2. Rename the “autorun.upg” to something else, e.g. to • StandbySW_CFTxx_x.x.x.x_commercial.zip. Contains
“software.upg”. Do not use long or complicated names, the Stand-by software in “upg” and “hex” format.
keep it simple. Make sure that “AUTORUN.UPG” is no – The “StandbySW_xxxxx_prod.upg” file can be used to
longer present in the root of the USB stick. upgrade the Stand-by software via USB.
3. Copy the renamed “upg” file into this directory. – The “StandbySW_xxxxx.hex” file can be used to
4. Insert USB stick into the TV. upgrade the Stand-by software via ComPair.
2009-May-08
Service Modes, Error Codes, and Fault Finding Q549.2E LA 5. EN 35
• MOP_AMBILIGHT_V1-2_UPG_jettsigned.zip. Contains
the MOP ambientlight software (ARM processor on the
DC-DC AL interface board) and is upgradeable via USB
(UPG). This SW is not part of the FUS autorun.upg! and is
not available in the One-Zip software file but provided
separately via the commercial Philips website (software for
servicers only). Instructions for upgrading are included in
the zip file.
5.9.6 UART logging 2K9 (see section “5.8 Fault Finding and
Repair Tips, 5.8.6 Logging)
2009-May-08
EN 36 6. Q549.2E LA Alignments
6. Alignments
Index of this chapter: • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 475.25 MHz
6.2 Hardware Alignments • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.3 Software Alignments signal strength of at least 1 mV and a frequency of 61.25
6.4 Option Settings MHz (channel 3).
6.5 Reset of Repaired SSB • LATAM models: an NTSC M TV-signal with a signal
6.7 Total Overview SAM modes strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
2009-May-08
Alignments Q549.2E LA 6. EN 37
• Set the RED, GREEN and BLUE default values according The first line (group 1) indicates hardware options 1 to 4, the
to the values in Table 6-2. second line (group 2) indicate software options 5 to 8.
• When finished press OK on the RC, then press STORE (in Every 5-digit number represents 16 bits (so the maximum value
the SAM root menu) to store the aligned values to the NVM. will be 65536 if all options are set).
• Restore the initial picture settings after the alignments. When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
Table 6-2 White tone default setting See Table 6-3 Option and display code overview for the
options.
White Tone 32" 37" Black level
offset Diversity
Colour Temp R G B R G B R G Not all sets with the same Commercial Type Number (CTN)
Normal 127 95 97 127 121 106 8 8 necessarily have the same option code!
Cool 127 100 112 124 127 119 8 8 Use of Alternative BOM => an alternative BOM number usually
Warm 127 89 52 127 111 64 8 8 indicates the use of an alternative display or power supply. This
results in another display code thus in another Option code. For
White Tone 56" Black level the power supply there is no difference. Refer to Chapter 2.
offset
Technical Specifications and, Connections.
Colour Temp R G B R G
Normal 127 117 111 8 8
6.4.5 Option Code Overview
Cool 124 124 125 8 8
Warm 127 95 65 8 8
Table 6-3 Option and display code overview
For dealer options, in SAM select “Dealer options”. New here in this chassis is the “Net TV” functionality. Therefore
See Table 6-4 SAM mode overview. the CTN (“set type” item in CSM1) must be filled into the spare
SSB to ensure access to the Net TV portals.
6.4.3 (Service) Options The loading of the CTN can be done via ComPair (Model
number programming).
Select the sub menu's to set the initialisation codes (options) of The reset item (Clear NET TV memory) can be selected via
the model number via text menus. MENU (or HOME) => Setup => Installation => Clear NET TV
See Table 6-4 SAM mode overview. memory (customer preferences stored at provider side will be
reset now).
6.4.4 Opt. No. (Option numbers)
2009-May-08
EN 38 6. Q549.2E LA Alignments
6.5.1 SSB identification 3. Create a folder "upgrades" in the root of a USB stick (size
> 50 MB) and save the "autorun.upg" file in this "upgrades"
Whenever ordering a new SSB, it should be noted that the folder. Note: it is possible to rename this file, e.g.
correct ordering number (12nc) of a SSB is located on a sticker "Q549_SW_version.upg", this in case there are more than
on the SSB. The format is <12nc SSB><serial number>. The one "autorun.upg" files on your USB stick
ordering number of a “Service” SSB is the same as the ordering 4. Plug the prepared USB stick into the TV set, and select the
number of an initial “factory” SSB. "autorun" file in the displayed browser on the screen
5. Now the main TV software will be loaded automatically,
supported by a progress bar
6. Set the correct "display code" via "062598-HOME-xxx",
where "xxx" is the 3-digit display panel code (see sticker on
the side/bottom of the cabinet).
2009-May-08
Alignments Q549.2E LA 6. EN 39
2009-May-08
EN 40 6. Q549.2E LA Alignments
2009-May-08
Alignments Q549.2E LA 6. EN 41
2009-May-08
EN 42 7. Q549.2E LA Circuit Descriptions
7. Circuit Descriptions
Index of this chapter: Main difference with the previous platform is the introduction of
7.1 Introduction “Net TV” and “CI+”.
7.2 Power Architecture
7.3 Front-End 7.1.1 Implementation
7.4 HDMI
7.5 Video and Audio Processing - PNX8543
Key components of this chassis are:
7.6 Common Interface CI+
• PNX8543 Digital Colour Decoder
7.7 Net TV • EP3C25F324C7N FPGA (“Local Contrast”)
7.8 Ambi Light
• HD1816AF Hybrid Tuner
• DRX3926K Demodulator
Notes: • TDA9996 HDMI Switch
• Only new circuits (circuits that are not published recently) • TPA3123D2PWP Class D Power Amplifier
are described. • DP83816AVNG PCI ethernet media access controller and
• Figures can deviate slightly from the actual situation, due physical layer (MacPhyter-II).
to different set executions.
• For a good understanding of the following circuit
7.1.2 TV543 Architecture Overview
descriptions, please use the wiring, block (see chapter
9. Block Diagrams) and circuit diagrams (see chapter
10. Circuit Diagrams and PWB Layouts).Where necessary, • For details about the chassis block diagrams refer to
chapter 9. Block Diagrams. An overview of the TV543
you will find a separate drawing for clarification.
architecture can be found in Figure 7-1.
7.1 Introduction
DDR
16
8 PCI
FLASH Ethernet
Spartan SPI
XC3S250E
LVDS
hdmi
Mini Led Dimming
PCI (Wifi)
TDA9996
hdmi
MUX
18310_200_090317.eps
090317
2009-May-08
Circuit Descriptions Q549.2E LA 7. EN 43
1M71 1M59
H
1M01
1
0
1
1F02
1R12
1CJ0
1HP0
DDR2
DDR2
Y Pb
1R08
Xilinx
1G50
1E51
Scart / YPbPr
Scart / YPbPr
GPI
DDR2 1E50
1M36
O
SPO Lo Pr
lvds-rx
1R07
lvds-tx
1HE0
40x40
5100
1.27
CY3 DDR
ambi
Ro L
uart C40
PCI/
XIO
Head
vdi
1G51
I
²
pci/xio
C
R
Right
G
A
Left
T
DDR2
Audio In
USB
LVDS 2
LVDS 1
Audio
J
Out
10048
E
TDA
STBY
CVBS
DDR PNX8542/3 GPIO
Tuner
98XX
TDA
Video
In
10023
TDA
Wifi Y/C
HDMI A
HDMI B
DV in
Video
TS in
Out
DDR2 CA
PCI
USB
2.0
HD
R
HDMI
L
RJ45 MI
MUX
1.3
1M20
Ethernet
DC/DC
FLASH 1P00
1M95
I I I I
M M M M
D D D D
H H H H CA
Class-D
1M99
M
H
D
I
1
7
3
5
18310_201_090317.eps
090317
2009-May-08
EN 44 7. Q549.2E LA Circuit Descriptions
F use
12VD isp V display
PSU P la tfo rm LC D
P ow er
SSB Power-on
Standby
F use
+12V +1V2 +1V2-PNX85XX
D ual
D C/D C Display
Fuse
Enable-3V3
+3V3 +3V3
12V
U ndervoltage Sw itches off +2V5 +2V5 +2V5 (loc.Contr.FPGA)
detect +3V3 and
+5V +3V3F +1V8 +1V8 +1V8-PNX85XX
2.5V 1%
D etect 2
(12V sense) voltage ref +1V8 +1V8-PNX5100
Boost conv
.
+33V +33V-TUN(analog)
(opt)
AN D
Stby P
D etect1
Audio proc
+ C lass D
24V
18310_202_090317.eps
090317
All power supplies are a black box for Service. When defective, Below find an overview of the different PSUs that are used:
a new board must be ordered and the defective one must be
returned, unless the main fuse of the board is broken. Always Table 7-1 Supply diversity
replace a defective fuse with one with the correct
specifications! This part is available in the regular market. Supplier PSU Model Input Voltage Range
Consult the Service website for the order codes of the boards. LGIT PLHL-T826A 32" High Mains (198- 265 Vac)
Delta DPS-298CP A 37" High Mains (198- 265 Vac)
In the TV543 Elite Core platform, for sets up to and including Delta DPS-411AP-3 A 56" High Mains (198- 265 Vac)
47", the Integrated Power Board (IPB) - incl. inverter is used.
For sets of 52 " and 56", a conventional PSU (with additional
inverters) is used.
2009-May-08
Circuit Descriptions Q549.2E LA 7. EN 45
7.3 Front-End
P la tfo rm w ith e m b e d d e d E D ID
The Front-End consist of the following key components:
• Tuner HD1816AF
E D ID: 2 5 3B IIC
• SAW filter 36M125 CPU
• IF demodulator DRX3926K TDA9996
• AGC amplifier UPC3221GV. 3B 3B 3B 3B
2 5 3 co m m o nB yte s
Below find a block diagram of the front-end application.
+ 1B su ba d d re s o f
S o u rceP h ysica l A d d re ss
+3B fo r inp u t A
I2C-SSB +3B fo r inp u t B
NXP Hybrid SAW
CVBS 4 × HDMI +3B fo r inp u t C
IF Amplifier DRX3926K 2nd SIF PNX8543
Tuner Filter
TS
inputs +3B fo r inp u t D
IF-AGC 18440_214_090227.eps
I2C-TUNER 090227
18440_211_090227.eps
090227 Figure 7-6 EDID control (embedded EDID)
H D M IB-R X
Some more delta’s compared to the previous PNX85xx are:
1P 05
DRX
H D M IA-R X
Out
D • 2 HDMI inputs (A & B)
• HDMI deep colour RGB/YCbCr 4:4:1 10/12 bit detection.
H D M I Side
C
TDA9996 (optional)
CRX
The PNX8543 handles the digital and analogue audio- and
A
AR X
E d id B
video decoding and processing. The processor is a MIPS32
BR X
general purpose CPU and a 8051-based TV controller for
power management and user event handling.
HDMI 4
1P06
1P04
1P03
1P02
(optional)
18440_213_090227.eps
090227
2009-May-08
EN 46 7. Q549.2E LA Circuit Descriptions
PNX8543x
MEMORY
CONTROLLER
TS in from
channel decoder MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single or dual
OUTPUT channel)
DV-ITU-656 DV INPUT
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT
AUDIO DSP
Dual SPDIF I2S
AUDIO IN AUDIO OUT
I2S SPDIF
300 MHz
AV-DSP
HDMI
Dual HDMI
RECEIVER DRAWING
ENGINE
I 2C PWM GPIO IR ADC SPI UART I2C GPIO Flash USB 2.0 CA PCI 2.2
x 22 x 10
18440_202_090226.eps
090226
Refer to Figure 7-8 for the main video interfaces for the
PNX8543 and the video signal flow between blocks and
memory.
2009-May-08
Circuit Descriptions Q549.2E LA 7. EN 47
DDR2-SDRAM
PNX8543x
MCU-DDR
VCP/PC 2D_DE
VCP_
UIP
LOW IF VCP_RX GFX1
CVBS VCP_ LCD panel
WIFD GFX2
RGB AFE CPIPE_ LVDS_BUF FPD-LVDS1
(ADC) PIP L2QTV LVDS_TX
YPbPr LCD panel
PC_
VGA PC_RX FPD-LVDS2
UIP
DMA BUS main
HDMI
MBVP_
L2QTV
Dual HDMI HDMI_ HDMI_UIP
RX
MBVP_
L2VO1
monitor
CVBS/Y DAC
CPIPE_ CVBS1/Y
MBVP_ DENC
L2VO C
DV (including L2VO2
VIP
ITU-656) (ITU-656)
monitor
MUX DAC CVBS2/C
A
TS
TSI
PCMCIA
CAI MSVD
TSDO
TSDI VMSP
CMD
18440_203_090226.eps
090226
Refer to Figure 7-9 for the main audio interfaces for the
PNX8543 and the audio signal flow between blocks and
memory.
2009-May-08
EN 48 7. Q549.2E LA Circuit Descriptions
DDR2-SDRAM
PNX8543x
MCU
TM2270
TS-IN CAI VMSP (MPEG, AC-3, MP3
DECODER)
XB4
XB1
fast SPDIF
I2S-IN-SD1
I2S-IN-SD2
XB2
I2S-IN-SD3
I2S-IN-SD4
AI AO
I2S-IN-WS
I2S-IN-SCK
I2S-IN-OSC
4 × I2S
SPDIF
4 × I2S
HDMI HDMI_RX XB3
4
I2S
4 × I2S
I2S-OUT-SD1
4 I2S-OUT-SD2
IF ADC I2S-OUT-SD3
SSIF ASDEC APP - AUDIO DSP I2S-OUT-SD4
DigIF (DEMODULATION (POST PROCESSING)
from AND DECODING)
SPDIF I2S-OUT-WS
XB4 I2S-OUT-SCK
I2S-OUT-OSC
L, R ADC
2 Main L, R
DAC
2
HP L, R
DAC
2
SCART2 L, R
DAC
2
SCART1 L, R
DAC
18440_204_090226.eps
090226
2009-May-08
Circuit Descriptions Q549.2E LA 7. EN 49
DDR2-SDRAM
PNX8543x
MCU_DDR
I2C-1 IIC4_DMA
I2C-3 IIC3_DMA
AVDSP
DMA BUS
UART-1 UART1
PCI_XIO
PCI/XIO
UART-2 UART2
CAI
CI/CA
USB USB2.0
I2C-MC
SYSTEM UART-3
CONTROLLER
JTAG_MMIO 80C51 PWMs
EJTAG
GPIOs
18440_205_090226.eps
090226
The Connectivity Subsystem consists of: keys in the components, unauthorised exchange of these
• PCI/XIO interface components will always result in a defective board.
• USB2.0 interface
• Three 2-wire UARTs
• Four Master/Slave I2C interfaces
• Common Interface/Conditional Access Interface.
2009-May-08
EN 50 7. Q549.2E LA Circuit Descriptions
7.6 Common Interface CI+ Access Module (CAM) and the Integrated Digital Television
(IDTV). The security mechanisms in CI+ are derived/copied
Together with this platform, an extention to the Common from POD (with the exception of Out Of Band (OOB) used in
US CA systems). For more information about conventional CA
Interface (CI) Conditional Access system is added, called CI+.
systems using a CI module, refer to the BJ3.0E L/PA or BL2.xU
Service Manual.
CI+ or Common Interface Plus is a specification that extends
the Common Interface (DVB-CI) as described in the digital
The CI+ standard is downwards compatible with the existing CI
broadcasting standard DVB.
standard.
P N X 8543
T ransport stream C om m and
C A-C TR L
C A-M D I
C A-M D O
P C I/X IO
interface interface
MHEG MMI
ap p licatio n
scram b ler
C A clien t
D E S /AE S
Tran sp o rt S tream s
C A-C o n tro l
CAM P ro p rietary C A
scram b ling
18440_221_090227.eps
090227
7.7 Net TV
In this chassis, a feature that enables access to dedicated called “Net TV”, is introduced. A separate Wi-Fi module
internet pages from a limited group of information suppliers, enables wireless communication with a local network.
The Ambi Light architecture in this platform has been entirely The use of the DC/DC board is optional. In case no DC/DC
renewed. The characteristics are: board is implemented, the ARM processor is located on one of
• Additional DC/DC board generating 12/16/24 V (optional) the AL boards.
• ARM processor (on DC/DC panel or AL board)
• Low-power LEDs Refer to Figure 7-12 for the Ambi Light architecture.
• SPI interface from ARM to LED drivers
• I2C upgradeable via USB
• Each AL module has a temperature sensor.
2009-May-08
Circuit Descriptions Q549.2E LA 7. EN 51
18310_203_090317.eps
090317
7.8.1 ARM controller The SPI bus is a synchronous serial data link standard that
operates in full duplex mode.
Refer to Figure 7-13 below for signal interfacing to and from the
ARM controller. The ARM controller is located on the DC/DC For debugging purposes, the working principle is given below:
board (item no. 7302) or AL panel (item no. 7102). • At startup the controller will read-out matrix data from the
EEPROM devices (via SPI DATA RETURN)
• Before operation, the driver current is set via SPI, with
driver in DC mode
SD A SPI C LO C K
S da1 Sck • During normal operation the controller receives RGB-,
SC L
S c l1
P 0. 7
SPI LATC H configuration-, operation mode- and topology data via I2C
S E L1
t bd
SPI LATC H 2
(only on dc/dc for aurea)
• The controller converts the I2C RGB data via the matrixes
P 0. 8
S E L2
t bd
to SPI LED data
M OSI
SPI D ATA O U T • Via data return the controller receives error data (if
PW M C LO C K
applicable).
M A T0.0
Also PWM clock and BLANK signals are generated by the
AR M M ISO
SPI D ATA R ETU R N controller. The controller can be reprogrammed via I2C (via
BLAN K
USB). The controller can receive matrix values via I2C, which
M A T1.0
will be stored in the EEPROM of each AL module via the SPI
PR O G
t bd bus. The temperature sensor in each AL module controls the
Tx D
Tx d0
t bd
C S EEPR O M TEMP line; in case of a too high temperature the controller will
RxD
R x d0
P 0. 10
TEM P reduce the overall brightness.
o ut16
o ut16
S o ut S in S o ut S in S o ut
LED LED LED
D R IV E R D R IV E R D R IV E R
1 2 N
S P I d ata in
18310_205_090318.eps
090318
2009-May-08
EN 52 7. Q549.2E LA Circuit Descriptions
Figure 7-14 SPI communication between ARM controller and LED drivers
ARM
18310_206_090318.eps
090318
2009-May-08
IC Data Sheets Q549.2E LA 8. EN 53
8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).
Block Diagram
Pin Configuration
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC
TPS53124
6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2
18250_300_090319.eps
090319
2009-May-08
EN 54 8. Q549.2E LA IC Data Sheets
Block Diagram
RF AGC MPEG-2
DVB-T/QAM TS
IF AGC FEC
SAW
Main
IF AMP ADC CVBS
Tuner
DVB-T/QAM/ATV DAC
Demodulator
Stereo Decoder
Integrated Tuner SIF
DAC
I2S Audio
Presaw
Sense
I2C
I2 C
System Controller
GPIO
Pin Configuration
VSSAH_CVBS INP
VDDAH_CVBS INN
CVBS VSSAH_AFE1
SIF VDDAH_AFE1
VSSAL_AFE2 VDDAL_AFE1
VDDAL_AFE2 VSSAL_AFE1
PDP IF_AGC
PDN RF_AGC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XI 49 32 RSTN
XO 50 31 SAW_SW
VSSAH_OSC 51 30 GPIO2
VDDAH_OSC 52 29 VSYNC
VDDH 53 28 VSSL
VSSH 54 27 VDDL
VSSL 55 26 VDDH
VDDL 56 25 VSSH
TDO 57
DRXK 24 I2C_SDA1
TMS 58 23 I2C_SCL1
TCK 59 22 MD7
TDI 60 21 MD6
I2C_SDA2 61 20 MD5
I2C_SCL2 62 19 MD4
I2S_CL 63 18 VDDH
I2S_DA 64 17 VSSH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
I2S_WS VDDL
VDDL VSSL
VSSL MD3
GPIO1 MD2
MSTRT MD1
MERR MD0
VSSH MVAL
18440_300_090303.eps
VDDH MCLK 090303
2009-May-08
IC Data Sheets Q549.2E LA 8. EN 55
Block Diagram
PNX8543x
MEMORY
CONTROLLER
TS in from
channel decoder MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single or dual
OUTPUT channel)
DV-ITU-656 DV INPUT
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT
AUDIO DSP
Dual SPDIF I2S
AUDIO IN AUDIO OUT
I2S SPDIF
300 MHz
AV-DSP
HDMI
Dual HDMI
RECEIVER DRAWING
ENGINE
I2C PWM GPIO IR ADC SPI UART I2C GPIO Flash USB 2.0 CA PCI 2.2
x 22 x 10
Pin Configuration
ball A1
index area 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
A
B
C
D
E
F
G
H
J
K PNX8543xEH
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
Transparent top view
18440_301_090303.eps
090303
2009-May-08
EN 56 8. Q549.2E LA IC Data Sheets
Block Diagram
PNX51xx
MEMORY
CONTROLLER
TM327x 1
LVDS RX 1 GIC 1
Video
UIP L3K7
TM327x 2
GIC 2
LVDS RX 2
TM327x 3
GIC 3
PCI/XIO
LVDS TX 1
I2C Video
LVDS TX 2
I2C-DMA
CPIPE L3K7
I2C
GFX LVDS TX 3
LVDS TX 4
UART UART
16 X GPIO
EJTAG
CLOCK CAB
AUDIO IN
AUDIO OUT
Pin Configuration
ball A1
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H PNX51xx
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
2009-May-08
IC Data Sheets Q549.2E LA 8. EN 57
RXDV/MA11
RXER/MA10
MA4/EECLK
TXD3/MA15
TXD2/MA14
TXD1/MA13
TXD0/MA12
RXD3/MA9
RXD2/MA8
RXD1/MA7
RXD0/MA6
COL/MA16
MA3/EEDI
AUXVDD
AUXVDD
AUXVDD
AUXVDD
RXCLK
TXCLK
RXOE
TXEN
MDIO
M DC
C RS
M A5
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
C1
X2
X1
TPRDP/M TPTDP/M
3V DSP Physical Layer
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
NC 37 144 MA2/LED100N
38 143 MA1/LED10N
VSS
39 142 MA0/LEDACTN
IAUXVDD
VREF 40 141 MD7
Test data out RESERVED 41 Pin1 140 MD6
MII Mgt
139 MD5
MII RX
42
MII TX
Identification
Test data in
NC
NC 43 138 MD4/EEDO
VSS 44 137 AUXVDD
25 MHz Clk TPRDM 45 136 VSS
TPRDP 46 135 MD3
SRAM IAUXVDD 47 134 MD2
48 133 MD1/CFGDISN
RX-2 KB REGEN
132 MD0
VSS 49
RAM MII RX RESERVED
VSS
50
51
131
130
MWRN
MRDN
SRAM MII TX 129 MCSN
RXFilter BIST Interface MII Mgt
VSS
TPTDM
52
53 128 EESEL
.5 KB
SRAM
TX-2 KB
Logic Logic BIOS ROM Cntl
BIOS ROM Data
EEPROM/LEDs
TPTDP
VSS
AUXVDD
VSS
AUXVDD
54
55
56
57
58
DP83816 127
126
125
124
123
RESERVED
NC
NC
NC
PWRGOOD
PMEN/CLKRUNN 59 122 3VAUX
PCICLK 60 121 AD0
INTAN 120 AD1
Rx rd data
61
Tx rd data
BROM/EE
AD2
Rx wr data
119
Tx wr data
RSTN 62
MII Mgt
R x A ddr
MII RX
Tx Addr
MII TX
100
101
102
103
104
105
106
107
108
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
PCI AD
PCIVDD
VSS
VSS
PCIVDD
AD25
AD24
CBEN3
IDSEL
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
CBEN2
IRDYN
CBEN1
AD15
AD14
AD13
AD12
AD11
AD10
DEVSELN
FRAMEN
TRDYN
STOPN
PERRN
SERRN
PAR
PCIVDD
VSS
NC
NC
DP83816
F_15710_167.eps
230905
2009-May-08
EN 58 8. Q549.2E LA IC Data Sheets
Block Diagram
1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR
PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP
Shutdown
SD 1 F
Control
MUTE
GAIN0
GAIN1
} Control
Pin Configuration
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR
TERMINAL
24-PIN I/O/P DESCRIPTION
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to properly
Thermal pad Die pad P
secure device to printed wiring board.
18440_302_090303.eps
090303
2009-May-08
Block Diagrams Q549.2E LA 9. EN 59
9. Block Diagrams
Wiring Diagram 32" (Elite Core)
WIRING DIAGRAM 32" (ELITE CORE)
8150
3. SPI-DATA-RETURN
11. VLED1 BACKLIGHT 2. SPI-DATA-OUT
12. GND 8159 1. SPI-CLOCK-BUF
13. VLED2
14. GND
1G50 (B05C)
SDA-AMBI-3V3
SCL-AMBI-3V3
41. N.C
1M59 (B06A)
40. TXDAT-
39.TXDAT
+3V3
...
GND
GND
GND
GND
...
...
1.
2.
3.
4.
5.
6.
7.
3. TX2E+
2. SCL-DISP
8151 1. SDA-DISP
8159
1G51 (B05C)
51. N.C.
50. SDA-DISP
49. SCL-DISP
...
...
2. N.C.
1. HV1
3. HV1
2. N.C.
1. HV2
3. HV2
5. +24V
3. +24V
1. +24V
6. GND
4. GND
2. GND
...
CN7
1316
1319
3. +VDISP1
2. +VDISP1
1. +VDISP1
B SSB
WIFI (1011)
MODULE
ON 1A01
1A01
124P
(1042)
KEYBOARD CONTROL
CN4
11. NC 1M20 (B01B)
10. GND_SND 8. +5V
MAIN POWER SUPPLY 9. +VSND
8. +12V
7.
6.
KEYBOARD
LED1
7. +12V 5. +3V3-STANDBY
IPB 32 PLHL-T826A 6. +12V
5. GND1
4.
3.
LED2
RC
(1050) 4. GND1 2. GND
AMBI-LIGHT MODULE
AMBI-LIGHT MODULE
3. GND1 1. LIGHT-SENSOR
2. STANDBY
8395
(1127)
1. 3V3_ST
1M95 (B01B)
11. N.C
10. GND
CN5 9. +AUDIO-POWER
12. NC 8. +12V
11. NC 7. +12V
10. NC 6. +12V
5/5 (1074)
5/5 (1076)
9. INV_OK 5. GND
8. A/P_DIM 4. GND
7. BOOST 3. GND
1M01
6. DIM 2. STANDBY
5. BL_ON_OFF 1. +3V3-STANDBY
4. GND1
3P
3. GND1
8399
2. +12V
AL
AL
1. +12V
1M99 (B01B)
12. GND
11. SDA-SET
10. SCL-SET
9. POWER-OK
8. BACKLIGHT-PWM...
RIGHT-SPEAKER
LEFT-SPEAKER
7. BACKLIGHT-BOOST
6. BACKLIGHT-OUT
GND-AUDIO
GND-AUDIO
1735 (B10A)
5. LAMP-ON-OUT
4. GND
CN1 3. GND
1. N
2. L
2. +12VD 1M83 (AL1)
1. +12VD 14. GND
4.
3.
2.
1.
13. VLED2
12. GND
11. VLED1
10. PROG
9. TEMP-SENSOR
8. EEPROM-CS
7. GND
6. +3V3
8735 5. CONTROL-2
4. CONTROL-1
8735
3. SDA
2. GND
1. SCL
8408
- + - +
INLET
8120
RIGHT SPEAKER LEFT SPEAKER
(5214) (5213)
8101
Board Level Repair
IR LED PANEL
(1112) 1M01 1M20
3P 8P
Component Level Repair
Only For Authorized Workshop
18310_400_090305.eps
090421
2009-May-08
Block Diagrams Q549.2E LA 9. EN 60
8802 8802
TO TO
8319
BACKLIGHT BACKLIGHT
8159
AMBI-LIGHT MODULE
AMBI-LIGHT MODULE
1G50 (B05C)
SDA-AMBI-3V3
SCL-AMBI-3V3
41. N.C
8316
1M59 (B06A)
40. TXDAT-
39.TXDAT
8150
+3V3
...
GND
GND
GND
GND
...
...
1.
2.
3.
4.
5.
6.
7.
3. TX2E+
2. SCL-DISP
8590 1. SDA-DISP
3/3 (1074)
3/3 (1075)
1G51 (B05C)
51. N.C.
50. SDA-DISP
49. SCL-DISP
8151 ...
AL
AL
...
2. N.C.
1. HV1
3. HV1
2. N.C.
1. HV2
3. HV2
5. +24V
3. +24V
1. +24V
6. GND
4. GND
2. GND
...
CN7
1316
1319
3. +VDISP1
2. +VDISP1
1. +VDISP1
1M84 (AL1)
B SSB 1M83 (AL1)
5. CONTROL2
4. CONTROL1
1M90 (AB1)
1M59 (AB1)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
WIFI (1150) 14. GND
13. VLED2
MODULE
7. GND
5. +24V
3. +24V
1. +24V
6. +3V3
6. GND
4. GND
2. GND
2. GND
3. SPI-DATA-RETURN 12. GND
3. SDA
1. SCL
4. SPI-LATCH 11. VLED1
ON 1A01
1A01
5. PWM-CLOCK-BUF 10. PROG
124P
6. +3V3 (1042) 9. TEMP-SENSOR
7. BLANK-BU
DC-DC 8. EEPROM-CS
8. EEPROM-CS
9. TEMP-SENSOR AB INTERFACE
7. GND
6. +3V3
10. PROG 5. CONTROL-2
(1028)
KEYBOARD CONTROL
8584
5. GND1 9. TEMP-SENSOR
(1050) 4. GND1 8. EEPROM-CS 2. GND
3. GND1 7. BLANK-BUF 1. LIGHT-SENSOR
2. STANDBY 6. +3V3
1. 3V3_ST 5. PWM-CLOCK-BUF
(1114)
4. RIGHT-SPEAKER
1. LEFT-SPEAKER
7. BACKLIGHT-BOOST
8399 6. BACKLIGHT-OUT
3. GND-AUDIO
2. GND-AUDIO
1735 (B10A)
5. LAMP-ON-OUT
FUSE 4. GND
CN1
3. GND
1. N
2. L
2. +12VD
1. +12VD
AMBI-LIGHT MODULE
AMBI-LIGHT MODULE
8408 8585
8735
8735
3/3 (1073)
3/3 (1076)
INLET
-+ -+ -+ -+
AL
AL
8120
1M84 (AL1)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT
3. SPI-DATA-RETURN
4. SPI-LATCH
RIGHT SPEAKER
(5214)
LEFT SPEAKER
(5213)
1M83 (AL1)
14. GND
13. VLED2
5. PWM-CLOCK-BUF 12. GND
6. +3V3 11. VLED1
7. BLANK-BU 10. PROG
8. EEPROM-CS 9. TEMP-SENSOR
9. TEMP-SENSOR 8. EEPROM-CS
10. PROG 7. GND
11. VLED1 6. +3V3
12. GND 5. CONTROL-2
13. VLED2 4. CONTROL-1
14. GND 3. SDA
2. GND
1. SCL
8101
18310_401_090305.eps
090420
2009-May-08
Block Diagrams Q549.2E LA 9. EN 61
3. SPI-DATA-RETURN
3. SPI-DATA-RETURN
3. SPI-DATA-RETURN
3. SPI-DATA-RETURN
3. SPI-DATA-RETURN
5. PWM-CLOCK-BUF
5. PWM-CLOCK-BUF
5. PWM-CLOCK-BUF
5. PWM-CLOCK-BUF
5. PWM-CLOCK-BUF
1. SPI-CLOCK-BUF
1. SPI-CLOCK-BUF
1. SPI-CLOCK-BUF
1. SPI-CLOCK-BUF
1. SPI-CLOCK-BUF
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
9. TEMP-SENSOR
2. SPI-DATA-OUT
2. SPI-DATA-OUT
2. SPI-DATA-OUT
2. SPI-DATA-OUT
2. SPI-DATA-OUT
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
5. CONTROL-2
4. CONTROL-1
5. CONTROL-2
4. CONTROL-1
5. CONTROL-2
4. CONTROL-1
5. CONTROL-2
4. CONTROL-1
5. CONTROL-2
4. CONTROL-1
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
8. EEPROM-CS
1M83 (AL1)
1M83 (AL1)
1M83 (AL1)
1M83 (AL1)
1M83 (AL1)
4. SPI-LATCH
4. SPI-LATCH
4. SPI-LATCH
4. SPI-LATCH
4. SPI-LATCH
7. BLANK-BU
7. BLANK-BU
7. BLANK-BU
7. BLANK-BU
7. BLANK-BU
AMBI-LIGHT MOD. AMBI-LIGHT MOD. AMBI-LIGHT MOD. AMBI-LIGHT MOD. AMBI-LIGHT MOD.
1M85 (AL4)
1M84 (AL1)
1M84 (AL1)
1M84 (AL1)
1M85 (AL4)
AL AL AL AL AL 1M85 (AL4)
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
1M83 (AL1)
10. PROG
10. PROG
10. PROG
10. PROG
10. PROG
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
13. VLED2
11. VLED1
10. PROG
10. PROG
10. PROG
10. PROG
10. PROG
4/4 (1073) 3/3 (1080) 3/3 (1076) 3/3 (1074) 4/4 (1072)
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
6. +3V3
6. +3V3
6. +3V3
6. +3V3
6. +3V3
7. GND
2. GND
7. GND
2. GND
7. GND
2. GND
7. GND
2. GND
7. GND
2. GND
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
14. GND
12. GND
14. GND
6. +3V3
6. +3V3
6. +3V3
6. +3V3
6. +3V3
3. SDA
3. SDA
3. SDA
3. SDA
3. SDA
1. SCL
1. SCL
1. SCL
1. SCL
1. SCL
1. SCL
2. GND 13. VLED2
3. SDA 12. GND
4. CONTROL-1 11. VLED1
5. CONTROL-2 10. PROG
6. +3V3 9. TEMP-SENSOR
7. GND 8. EEPROM-CS
8. EEPROM-CS 8583 8586 8587 8588 8589 8590 7. BLANK-BU
9. TEMP-SENSOR 6. +3V3
10. PROG 5. PWM-CLOCK-BUF
11. VLED1 8802 8801 4. SPI-LATCH
12. GND Board Level Repair 3. SPI-DATA-RETURN
13. VLED2 2. SPI-DATA-OUT
14. GND 1. SPI-CLOCK-BUF
TO
8319
BACKLIGHT
TO 8303
AMBI-LIGHT MODULE
AMBI-LIGHT MODULE
BACKLIGHT
8159
1G50 (B05C)
SDA-AMBI-3V3
SCL-AMBI-3V3
41. N.C
1M59 (B06A)
40. TXDAT-
4/4 (1070)
39.TXDAT
4/4(1075)
8150
+3V3
...
GND
GND
GND
GND
...
8316
...
1.
2.
3.
4.
5.
6.
7.
3. TX2E+
2. SCL-DISP
8690 1. SDA-DISP
AL
AL
1G51 (B05C)
51. N.C.
50. SDA-DISP
CN2 / 1319
6. GND1
4. GND1
2. GND1
5. +24V
3. +24V
1. +24V
49. SCL-DISP
CN7
14. PDIM_Select 8151 ...
13. PWM
... 1M83 (AL1)
1M85 (AL4) 12. On/Off
...
1. SPI-CLOCK-BUF 11. Vbri 14. GND
3. +VDISP1 13. VLED2
2. SPI-DATA-OUT 10. GND3
2. +VDISP1 12. GND
3. SPI-DATA-RETURN 9. GND3
1. +VDISP1 11. VLED1
4. SPI-LATCH 8. GND3
5. PWM-CLOCK-BUF
6. +3V3
7. GND3
6. GND3
MAIN POWER SUPPLY
CN9
B SSB 10. PROG
9. TEMP-SENSOR
5. CONTROL2
4. CONTROL1
1M90 (AB1)
1M59 (AB1)
7. BLANK-BU 5. 24Vinv 5. GND1 8. EEPROM-CS
8. EEPROM-CS 4. 24Vinv 4. GND1 WIFI (1011)
7. GND
3. N.C.
PSU DPS-411AP3A B MODULE 6. +3V3
7. GND
3. 24Vinv
5. +24V
3. +24V
1. +24V
6. +3V3
9. TEMP-SENSOR
6. GND
4. GND
2. GND
2. GND
3. SDA
1. SCL
10. PROG 2. 24Vinv 2. +12V 5. CONTROL-2
ON 1A01
1A01
11. VLED1 1. 24Vinv 1. +12V 4. CONTROL-1
(1050)
124P
12. GND 3. SDA
13. VLED2
(1042) 2. GND
DC-DC
8584
CN3 / 1316
14. GND
12. N.C.
11. N.C.
CN4
11. NC
AB INTERFACE
1. SCL
9. GND3 9. +VSND
8. GND3 8. +12V
8683
7. GND3 7. +12V 1M84 (AB1) 1M20 (B01B)
6. GND3 6. +12V 14. GND 8. +5V
5. 24Vinv 5. GND1 13. VLED2 7. KEYBOARD
4. 24Vinv 4. GND1 12. GND 6. LED1
3. 24Vinv 3. GND1 11. VLED1 5. +3V3-STANDBY
2. 24Vinv 2. STANDBY 10. PROG 4. LED2
1M83 (AL1) 1. 24Vinv 1. 3V3_ST 9. TEMP-SENSOR 3. RC
1. SCL 8. EEPROM-CS 2. GND 1M84 (AL1)
2. GND 7. BLANK-BUF 1. LIGHT-SENSOR 14. GND
3. SDA 6. +3V3 13. VLED2
CN5
(1127)
8120
3P
1M99 (B01B)
12. GND
11. SDA-SET
10. SCL-SET
9. POWER-OK
8. BACKLIGHT-PWM...
4. RIGHT-SPEAKER
1. LEFT-SPEAKER
7. BACKLIGHT-BOOST
8399 6. BACKLIGHT-OUT
3. GND-AUDIO
2. GND-AUDIO
1735 (B10A)
5. LAMP-ON-OUT
FUSE 4. GND
CN1
3. GND
1. N
2. L
2. +12VD
AMBI-LIGHT MODULE
AMBI-LIGHT MODULE
1. +12VD
8408 8585
8735
3/3 (1071)
3/3 (1082)
8735
AL
AL
-+ -+ -+ -+
INLET
1M84 (AL1)
1. SPI-CLOCK-BUF
2. SPI-DATA-OUT 1M83 (AL1)
3. SPI-DATA-RETURN 14. GND
4. SPI-LATCH 13. VLED2
5. PWM-CLOCK-BUF
6. +3V3
7. BLANK-BU
RIGHT SPEAKER LEFT SPEAKER 12. GND
11. VLED1
10. PROG
8. EEPROM-CS (5214) (5213)
9. TEMP-SENSOR
9. TEMP-SENSOR 8109 8. EEPROM-CS
10. PROG 7. GND
11. VLED1 6. +3V3
12. GND 5. CONTROL-2
13. VLED2
14. GND 1M09
4P
1M20
3P
1M01
8P TWEETER LIGHT STRIP
TWEETER 4. CONTROL-1
3. SDA
2. GND
(5215)
IR LED PANEL (1047)
(5216) 1P09
4P
L (1046)
1. SCL
8101
18310_407_090420.eps
090508
2009-May-08
Block Diagrams Q549.2E LA 9. EN 62
68P
PCMCIA AL18 TX851B+ K17 K2 TXF1B+ RX51001B+ AC20 TO DISPLAY
B_P TX2
CA-MDI(0-7) CA_MDI AK18 TX851B- K18 K1 TXF1B- RX51001B- AD20 1080p 50/60Hz
B_N
17 AP19 TX851C+ L17 M2 TXF1CLK+ RX51001CLK+ AC19 37
PCMCIA-VCC-VPP C_P
CONDITIONAL
ACCESS
18
33
C_N
D_P
AN19
AP20
TX851C-
TX851D+
M17
L13
FPGA M1
L2
TXF1CLK-
TXF1C+
RX51001CLK-
RX51001C+
AD19
AE19
38
39
AN20 TX851D- M14 L1 TXF1C- RX51001C- AF19
51
52
D_N
E_P
AM20
AL20
TX851E+
TX851E-
P17
P18
WOW P2
P1
TXF1D+
TXF1D-
RX51001D+
RX51001D-
AE18
AF18
PNX5120 N.C.
40
41
E_N
TX851CLK+
B02B DEMODULATOR CLK_P
AM19 N17 T3 TXF1E+ RX51001E+ AC18
AL19 TX851CLK- N18 R3 TXF1E- RX51001E- AD18
7T50 CLK_N QUAD LVDS
1T11
HD1816AF/BHXP
DRX3926K
AP22 TX852A+ U17
LOCAL U2 TXF2A+ RX51002A+ AE17
HD-NM 1920x1080
1G51
51
LOUT2_A_P
11 TUN-P11 9T11 B-IF-_N-IF- 2T19 PDP 3T53 47
PD_P FE-DATA(0-7) LOUT2_A_N AN22 TX852A- V17 CONTRAST V3 TXF2A- RX51002A- AF17
FHD 100Hz 100/120HZ 50
IF-OUT2 MD TNR_TSDI AL22 TX852B+ U15 U4 TXF2B+ RX51002B+ AC17 I2C 49
5T12
LOUT2_B_P
9T21 2T20 3T55 AK22 TX852B- V15 V4 TXF2B- RX51002B- AD17 TX3
10 TUN-P10 B-IF+_N-IF+ PDN 48 LOUT2_B_N 40
IF-OUT1 PD_N B04K ANALOGUE AV AP23 TX852C+ U14 U6 TXF2CLK+ RX51002CLK+ AC16
LOUT2_C_P
7T10 3T70 AN23 TX852C- V14 V6 TXF2CLK- RX5100CCLK- AD16
44 IF-P F2 LOUT2_C_N
UPC3221GV SIF AI51 AP24 TX852D+ U13 U5 TXF2C+ RX51002C+ AE16
+5V-TUN LOUT2_D_P TX4
DEMODULATOR 7T52 TX852D- V5 TXF2C- RX51002C- AF16 TO DISPLAY
AN24 V14
1 AGC AMPLIFIER 43 3T70 9T61 CVBS4 H3 LOUT2_D_N
TXF2D+ RX51002D+ 11 1080p 100/120Hz
MAIN HYBRID VCC CVBS AI44 AM24 TX852E+ U11 U7 AE15
LOUT2_E_P
AL24 TX852E- V11 V7 TXF2D- RX51002D- AF15 5
TUNER 1
1T25
5 2T15 2 7 IF- 3000 39 9T63 CVBS-TER-OUT LOUT2_E_N
AM23 TX852CLK+ U10 U8 TXF2E+ RX51002E+ AC15 4
LOUT2_CLK_P
AL23 TX852CLK- V10 V8 TXF2E- RX51002E- AD15 3
3T50 LOUT2_CLK_N
2 4 3 6 IF+ 40
8,18,26,53 AK19 2
IN OUT VDDH +3V3 IREF_LVDS VDDA-LVDS
SAW 36M125 2,16,27,56 B05E 1
4 49 VDDL +1V2 B06F FPGA WOW - DDR +VDISP1
AGC CONTROL XI 37 AB20
1 TUN-P1 9T18 VDDAH_AFE1 +3V3A SUPPLY +3V3
DC_POWER
XTAL_OUT
9 TUN-P9 9T23
ANTENNA-SUPPLY
+5V-TUN-PIN
+5V-TUN
1T50
27M
50
XO
VDDAH_CVBS
VDDAH_OSC
42
52
36,46
+3V3E
+3V3D
PNX8543 7FL0
AA5
L16
P22
+1V2-PNX5100
+1V8-PNX5100
3T98
VDDAL_AFE +1V2A EDD1216AJTA +1V2-PNX5100-DDR-PLL1
3T22 AB18
IF-AGC 34 +3V3-PNX5100-LVDS-IN
+5V-TUN IF_AGC J5
MM1-D(0-15) DDR +1V2-PNX-TRI-PLL1
3 TUN-P3 9T20 33 SDRAM L5
RF-AGC +1V2-PNX-TRI-PLL2
RF-AGC RF_AGC
H264 MM1-A(0-12)
8Mx16
1
+2V5-DDR1
T5
M22
+1V2-PNX-TRI-PLL3
+1V2-PNX5100-DLL
49 AE25
B08A ANALOGUE EXTERNALS A
7E02
B08B ANALOGUE EXTERNALS B USB 2.0 VREF-DDR1
E15
+3V3-PNX5100-DDR-PLL0
+1V2-PNX5100-LVDS-PLL
74HC4053PW B15
+3V3-PNX5100-LVDS-PLL
16 AE14
MDX +5V +1V2-PNX5100-CLOCK
1P05 AD14 +3V3-PNX5100-CLOCK
5 CVBS-TER-OUT
1 DRX2+ 14
7E16-7E06
3 DRX2- 1E01
7E05
1 Y_CVBS-MON-OUT-SC Y-CVBS-MON-OUT A3
CVBS1Y_P
B06D FPGA LOCAL CONTRAST B05A DDR2 B05A PNX5100: SDRAM
1
4
2
DRX1+
19 - LVDS IN/OUT
6 DRX1- 9,10,11 P24
VREF PNX5100-DDR2-VREF-CTRL
7 DRX0+ REGIMBEAU_CVBS-SWITCH
B04A 7C01
9 DRX0- CONTROL EDE5116AJBG-8E-E
18
1
8
19
21
4 CRX1+ 7 AV1-B 9EA1 AV1-PB L2
2
AI22 7C02
6 CRX1- AV1-G
11 9EA2 AV1-Y N2 EDE5116AJBG-8E-E
7 CRX0+ AI12
*JUMPERS IN CASE OF NO FPGA
9 CRX0- 20 AV1-CVBS 9EA7 AV1-Y_CVBS G4 DDR2
18
AI41 PNX5100-DDR2-A(0-12)
19
VDDA_HDMI_3V3_BIAS RREF-PNX85XX
2
4 BRX1+ 11 AV3-Y N3
11 AI13 AC6
6 BRX1- EXT 2 VDD_3V3_SBPER +3V3-STANDBY
20 AV2-Y_CVBS H1
7 BRX0+ 15 AI42
16
7E14 AJ12
9 BRX0- VDD_1V2_CORE +1V2-PNX85XX
18
16 AV2-BLK
19
20
10 21 B04A AF5
BRXC+ VDD_1V2_SBCORE 1V2-STANDBY
HDMI 2 12 8 AV2-STATUS CONTROL
BRXC- AJ21
CONNECTOR B04A VDD_3V3_PER +3V3-PER
SCART2 CONTROL
1P04 AG30
VDD_1V8_DDR 1V8-PMNX85XX
1 ARX2+
B08B ANALOGUE EXTERNALS B
1E05
3 ARX2-
1 R-VGA K4 B07C USB CONNECTOR
1
4 ARX1+ PC3_AI3
2
6
15
ARX1- PC1_AI3
5
3 B-VGA M4
7 ARX0+ PC2_AI3
3P59
13 H-SYNC-VGA T1
9 ARX0- HSYNCIN
1
1P07
6
18
11
14 V-SYNC-VGA T2
19
+T
10 ARXC+ VSYNCIN AL16 USB-OC 1
USB_FAULT USB 2.0
1
12 ARXC- AN16 2 CONNECTOR SIDE
HDMI 3 VGA USB20-DM
3 2
USB_DM SW UPLOAD
CONNECTOR CONNECTOR AP16 USB20-DP 3
USB_DP JPEG
4
4
1E03
3H37 MP3
AM17
AV4-PR K1 USB_RPU +3V3-PER
PR PC3_AI1
AN17 3H45
7P02 +3V3-PER
USB_VBUS
TDA9996 AV4-PB M1
PB PC1_AI1
CRX2+ 72 90 DRX2+ EXT 3
CRX2- 71 89 DRX2- 1E04 B07F PNX8543: FLASH
CRX1+ 69 87 DRX1+ AV4-Y P1 B04F CONTROL
Y PC2_AI1 7P10
CRX1- 68 86 DRX1- NAND01GW3B2BN6F
CRX0+ 66 HDMI 84 DRX0+
B08C ANALOGUE EXTERNALS C NAND
CRX0- 65 SWITCH 83 DRX0-
1E11 FLASH
CRXC+ 63 81 DRXC+ PCI_AD PCI-AD24<->NAND-AD
CRXC- 62 80 DRXC- 1G
FRONT-Y_CVBS H2
BRX2+ 42 CVBS AI43
BRX2- 41 8,45,91,24, 12,37
SIDE FRONT-C G1 AI54 VCC +3V3-NAND
BRX1+ 39 75,95 1E14
VDDx_1V8 +1V8-PNX85XX I/O 1
BRX1- 39 4 3
VDDO_3V3 +3V3
BRX0+ 36 46,55 SVHS IN 5
VDDx_3V3 +3V3
BRX0- 35 15,21,34,40, 2
4 B04G PNX8543: SDRAM
BRXC+ 33 64,70,85,88
VDDH_3V3 REF-3V3 B04H DIGITAL VIDEO IN B04G SDRAM
BRXC- 32
B07E HDMI SWITCH
AA31 3HJ5
M_IREF +1V8-PNX85XX
ARX2+ 23 2 HDMIB-RXC+ A14 AB32
C_+ HDMI_RXC_B_N M_VREF DDR2-VREF-CTRL
ARX2- 22 3 HDMIB-RXC- A15
C_- HDMI_RXC_B_P 7HG0
ARX1+ 20 99 HDMIB-RX0+ B13
D0_+ HDMI_RX0_B_N EDE1116AEBG
ARX1- 19 100 HDMIB-RX0- B14
17 D0_- HDMI_RX0_B_P
ARX0+ 96 HDMIB-RX1+ A12
D1_+ HDMI_RX1_B_N DDR2
ARX0- 16 97 HDMIB-RX1- A13 (0-12)
D1_- HDMI_RX1_B_P SDRAM
ARXC+ 14 93 HDMIB-RX2+ B11
D2_+ HDMI_RX2_B_N
ARXC- 13 94 HDMIB-RX2- B12 J1
D2_- HDMI_RX2_B_P DQ DDR2-D(0-15) VDDL +1V8-PNX85XX
3HK0 J2
C16 VREF DDR2-VREF-DDR
RREF-PNX85XX HDMI_RREF
B07E HDMI SWITCH 7HG1
1P06 EDE1116AEBG
1 HDMIA-RX2+ B15
HDMI_RX2_A_N
3 HDMIA-RX2- B16 DDR2-A(0-12)
DDR2
HDMI_RX2_A_P A
SDRAM
1
4 HDMIA-RX1+ A16
2
HDMI_RX1_A_N
6 HDMIA-RX1- A17
HDMI_RX1_A_P (16-31) J1
7 HDMIA-RX0+ B17 VDDL +1V8-PNX85XX
HDMI_RX0_A_N J2
9 HDMIA-RX0- B18 VREF DDR2-VREF-DDR
HDMI_RX0_A_P
18
19
10 HDMIA-RXC+ A18
HDMI_RXC_A_N
12 HDMIA-RXC- A19
HDMI 4 HDMI_RXC_A_P
CONNECTOR 18310_402_090305.eps
090324
2009-May-08
Block Diagrams Q549.2E LA 9. EN 63
68P
PCMCIA VREF_POS
CA-MDI(0-7) CA_MDI AK9 5D07
VDDA_3V3_DAC VDDA-DAC 1,3
17 PVCC_L +AUDIO-POWER
PCMCIA-VCC-VPP 10,12 5D08
CONDITIONAL 18 PVCC_R
7HM2-1 1735
ACCESS 33 22 LEFT-SPEAKER 1
AN14 ADAC(1) EF +AUDIO-L 5 OUT-L
51 ADAC1 IN-L
52 CLASS D 2
POWER
SPEAKER-L
B02B DEMODULATOR 7HM2-2 AMPLIFIER
EF 3
AP13 ADAC(2) -AUDIO-R 6
7T50 ADAC2 IN-R
1T11 DRX3926K 15 RIGHT-SPEAKER 4
HD1816AF/BHXP OUT-R
9T11 2T19 3T53 A-STBY 2 SPEAKER-R
11 TUN-P11 B-IF-_N-IF- PDP 47 B04A STANDBY SD
IF-OUT2 PD_P MD FE-DATA(0-7) CONTROLLER
5T12
10 TUN-P10 9T21 B-IF+_N-IF+ 2T20 PDN 3T55 48 AC5 AUDIO-MUTE 4
IF-OUT1 PD_N PO_7 MUTE
B04K ANALOGUE AV
7T10 44 3T70 F2
IF-P 7D03
UPC3221GV SIF AI51
+5V-TUN 7T52 A-STBY STANDBY &
AGC AMPLIFIER DEMODULATOR 3T70 3T56
1 43 CVBS4 H3 PROTECTION
MAIN HYBRID VCC CVBS AI44
TUNER 1T25 2T15 2 7 3052 39
1 5 IF- B04M PNX8543: AUDIO B08C ANALOGUE EXTERNALS C
2 4 2T17 3 6 IF+ 3T50 40 8,18,26,53
VDDH +3V3 7HVA-1 7HVA-2
SAW 36M125 IN OUT 2,16,27,56 AD1 A-PLOP B08A
VDDL +1V2 RESET-AUDIO
4 49 37 PO_6
AGC CONTROL XI VDDAH_AFE1 +3V3A B08B
1 TUN-P1 9T18 42
DC_POWER ANTENNA-SUPPLY 1T50 VDDAH_CVBS +3V3E
+5V-TUN 27M 52
VDDAH_OSC +3V3D
+5V
9 TUN-P9 9T23
+5V-TUN-PIN
50
XO VDDAL_AFE
36,46
+1V2A
PNX8543 7HV0
3T98
TPA6111A2DGN
3T22 IF-AGC
+5V-TUN 34
IF_AGC
HEADPHONE
3 TUN-P3 9T20 RF-AGC 33 AMPLIFIER
RF-AGC RF_AGC
RESET-AUDIO 5 1
SHUTDOWN 1E15
8
1 Headphone
3 DRX2- ADAC4 IN-2 VDD +3V3 Out 3.5mm
AUDIO IN
1
4
2
DRX1+
VGA 1P0B
6 DRX1- DVI -> HDMI 2 AUDIO-IN4-R AM5
7 DRX0+ AIN_4_R
9 DRX0-
B07C USB CONNECTOR
18
19
10 DRXC+
HDMI SIDE 12 DRXC- B08A ANALOGUE EXTERNALS A B04I PNX8543: AUDIO
CONNECTOR 1E01 +5V
3 AP-SCART-OUT-L 3EA7 7HM1
1P02 AUDIO-CL-L 1 3 ADAC(7) AL9 ADAC7
1
3P59
1 CRX2+
3EA8 B04E CONTROL 1P07
3 1 AP-SCART-OUT-R AUDIO-CL-R 7 5 ADAC(8) AL8 ADAC8
CRX2-
+T
7
AL16 USB-OC 1
1
1
EXT 1 9EA4 2
11
6 AV1-AUDIO-L AUDIO-IN1-L AN7 AIN_1_L AN16 USB20-DM CONNECTOR SIDE
6 CRX1-
3 2
USB_DM
15 AP16 USB20-DP 3 SW UPLOAD
7 CRX0+ 16 USB_DP
9EA4 4 JPEG
4
9 CRX0- 2 AV1-AUDIO-R AUDIO-IN1-R AP7 AIN_1_R
MP3
18
20
19
21
10 CRXC+ AM17 3H37
12 SCART1 USB_RPU +3V3-PER
HDMI 1 CRXC-
CONNECTOR
1E02 AN17 3H45
USB_VBUS +3V3-PER
3 AP-SCART-OUT-L 7E01
1P03 1
A-PLOP
A-PLOP B04M
1 BRX2+
7 1 AP-SCART-OUT-R
3 BRX2-
B07F PNX8543: FLASH
1
EXT 2
2
4 BRX1+ 11
6 AUDIO-IN2-L AK6 AIN_2_L
6 BRX1- 15
16
7 BRX0+
2 AUDIO-IN2-R AL6 AIN_2_R
9 BRX0- 20
18
21
19
4 ARX1+
2
AUDIO OUT
6 ARX1- L+R 12,37
6 AUDIO-OUT-R 14 12 ADAC(6) AP10 ADAC6 VCC +3V3-NAND
7 ARX0+
9 ARX0- 7E10
18
19
4 HDMIA-RX1+ A16
2
HDMI_RX1_A_N AJ21
6 HDMIA-RX1- A17 VDD_3V3_PER +3V3-PER
HDMI_RX1_A_P
7 HDMIA-RX0+ B17 AG30
HDMI_RX0_A_N VDD_1V8_DDR 1V8-PMNX85XX
9 HDMIA-RX0- B18
HDMI_RX0_A_P
18
19
10 HDMIA-RXC+ A18
HDMI_RXC_A_N
12 HDMIA-RXC- A19
HDMI 4 HDMI_RXC_A_P
CONNECTOR
18310_403_090305.eps
090313
2009-May-08
Block Diagrams Q549.2E LA 9. EN 64
7H00
PNX85439EH/M2 7303
DRX3926K-XK-A3
B04N TUN_CA
7N04 49
1N00 1P00
DP83816AVNGNOPB TNR_TSDI FE-DATA(0-7)
1304
27M
1 CA-MICLK DEMODULATOR
H32
17 CA_MICLK
50
B10 FE-CLK 9
1N02
CA-MDI(0-7) CA_MDI TNR_MICLK
25M
MAC C10 FE-VALID 10
PHYTER II 7P15-7P16 A34 TNR_MIVAL
FE-SOP
ETHERNET 18 CA_VSN_0 TNR_MISTRT B9 5
32
10/100 Mb/S MOCLKA CA-MOCLK_VS2 H31 RESET-SYSTEM
CONNECTOR CA_MOCLK PNX8543 B03G
COMMON INTERFACE
B04F B04O LVDS
RESET-ETHERNET 62 PCI-AD(0-31) AL23 TX852CLK-
B04A LOUT2_CLK_N B06G
B07H BUFFERING LOUT2_CLK_P
AM23 TX852CLK+
B06G
AL19 TX851CLK-
PCMCIA CLK_N B06G
7N13 TX851CLK+
CA-DATADIR D31
CA_DATA_DIR CLK_P AM19 B06G
61 IRQ-PCI CA-DATAEN A31
CA_DATA_EN
CONDITIONAL B04G MEMORY
ACCESS PCMCIA-D(0-7) PCI-AD(24-31) B04G PNX8543: SDRAM
7HG0
7N11 EDE1116AEBG
B09A MINI PCI CONNECTOR 7N12 7HG1
CA-ADDEN B31 M_DQ DDR2-D(0-31)
CA_ADD_EN EDE1116AEBG
PCMCIA-A(0-14) PCI-AD(0-14)
9H25
M_A DDR2-A(0-12)
1A01 IRQ-CA J34 CA_RDY
DDR2-CLK_P
SDRAM
1 AB34 J8
M_CLK_P
RESET-mPCI IRQ-PCI
MINI PCI CONNECTOR
68 AB33 DDR2-CLK_N K8
M_CLK_N
AN28 RESET-SYSTEM
B05A DDR2 RESET_SYS B02B B04A B04B
B05A PNX5100: SDRAM B07C USB CONNECTOR B08D ANALOGUE EXTERNAL D
7C01 1P07
EDE5116AJBG 1 USB-OC AL16 1E06
USB_FAULT
PNX5120
1
1 CONNECTOR
DDR2-A(0-12)
B04A STANDBY
AD2 1E50
PNX5100-DDR2-CLK_P
SDRAM P0_5 9E05 9E41
P26 J8 AG1 RXD-UP 3
UA_RX_0 UP
P25 PNX5100-DDR2-CLK_N K8 B04B PNX8543: DEBUG AH5 TXD-UP 9E03 9E40 3 STANDBY
2H07 SDM AG2 UA_TX_1
P1_7 RES
SDM RES
B04A PNX8543: STANDBY CONTROLLER B01B DC / DC
2H06
B05F CONTROL SPI-PROG AK2 P6_4 1M20
AF24 RESET-PNX5100 AN2 LIGHT-SENSOR 1
B04A SPI-PROG CADC_1
AE13
2
1CD0
27M
EP3C25F324C7N
POWER-OK 9
P2_6 AE5
B06G I/O BANK E18 BACKLIGHT-CONTROL-FPGA-IN OUTP 1 RESET-STBY AF3
RESET_IN
2 RESET-PNX5100 8
INP AB3 BACKLIGHT-PWM-ANA-DISP
F18 CLK-OUT-PNX5100 P0_2 B05F B05H
1M95
B06F FPGA WOW - DDR 3 TO
GND AD5 STANDBY 2 POWER
7FL0 P2_3
7HC3 SUPPLY
EDD1216AJTA
M24C64-WDW6P
7HC4
B07D HDMI
FPGA MM1-D(0-15)-->DQ1(0-15)
7P32
P0_1 AC1
RESET-NVM 8
CEC-HDMI AG4 EEPROM
WOW DDDR CONTROL P1_2
MM1-A(0-11) (8Kx8)
SDRAM TO PIN:
7P02 XTAL_I
W1
8Mx16 TDA9996
A2 MM1-CLK+ 45 1P04-13 B04H HDMI_DV
1HF0
27M
1P03-13 PCEC-HDMI 57
1P02-13
1
MM1-CLK-
2
A1 46 HDMI
1P05-13
7H02
SWITCH XTAL_O
W2
M25P05-AVMN6P
B06E FPGA WOW - POWER & COTROL ARX-DDC-SCL 12 HDMIB-RX HDMI_RX
1P04-15
18
BRX-DDC-SCL 31
19
2009-May-08
Block Diagrams Q549.2E LA 9. EN 65
3HPM
3HPK
G32 SDA3 3HPJ SDA-SSB
SDA 3
D33 SCL3 3HPH SCL-SSB
SCL 3
+5V-DDC
3CDD
3CDC
3FNG
3CD8
3CD7
3FNF
3P77
3P76
3T58
3T57
3F23
3F22
ERR 7FH0 7F01
13 9T16
49 50 24 23 K1 K2 5 6 G17 G18 54 53
3P61
3P58
1P04 M25P16 M25P20
+3V3
PNX8543 ARX-DDC-SDA 16 9T15
11 TUNER BUS
7P02 7T50 RES 7C00 7CD0 7FN0 7F00 1HP0
B04G PNX8543: SDRAM HDMI 400 kHz 16M 2M 3U67
TDA9996 DRX3926K PNX5120EH M24C08 EP3C25F324C7N XC3S250E
3T61
3T59
12 ARX-DDC-SCL 15 CONNECTOR 3 FLASH FLASH 3
B04G 7HG0 SDA
+5V-DDC 61 9T71 TUN-SDA 3T16 TUN-P7
EDE1116AEBG HDMI DEMODULATOR PNX5120 BOOT FPGA SPARTAN-3 3U66 1
MEMORY MUX MICRONAS FHD 120Hz EEPROM LOCAL FPGA SCL
7HG1 62 9T70 TUN-SCL 3T15 TUN-P6
DDR2-D CONTRAST 9FNA
3P64
3P63
M_DQ EDE1116AEBG 1P03 B06F FPGA WOW - DDR D18
ERR BRX-DDC-SDA 16 ERR ERR ERR ERR ERR
M_A 23 30 27 15 21 25 7FL0 29 9FN9
DDR2-A SDRAM C18
HDMI 7 6 EDD1216AJTA
31 BRX-DDC-SCL 15 CONNECTOR 2
DDR MM1-D RESERVED
+5V-DDC 1T11
HD1816AF SDRAM
8Mx16 MM1-A
3P68
3P67
1P02 MAIN +3V3
60 CRX-DDC-SDA 16 TUNER
AMBILIGHT BUS
HDMI
3FAA
3FAB
61 CRX-DDC-SCL 15 30 kHz 1M59
CONNECTOR 1
ERR 3CDA 9F22 3FA6
34 L1 SDA-AMBI-3V3 3
+5V-DDC
L2 3CD9 SCL-AMBI-3V3 9F21 3FA5 1
B04H
TO
3P66
3P65
1P05 3
+3V3 AMBI-LIGHT
D15 DDC-SDA 6 78 DRX-DDC-SDA 16 HDMI 4 MODULE
DDC_SDA_B
CONNECTOR 5
C15 DDC-SCL 5 79 DRX-DDC-SCL 15
DDC_SCL_B SIDE 7
B07E HDMI SWITCH B08B ANALOGUE EXTERNALS B B05A PNX5100: SDRAM B04N PNX8543: VIDEO STREAMS B07F PNX8543: FLASH
HDMI_DV
+5V-DDC
7C01
3P29
3P28
1P06 EDE5116AJBG
+5VDCOUT
E19 DDCA-SDA 9P19 ERX-DDC-SDA 16 7E18 7C02
DDC_SDA_A HDMI M24C02 PNX5100-DDR2-D(0-31)(0-31) EDE5116AJBG
C18 DDCA-SCL 9P20 ERX-DDC-SCL 15 CONNECTOR 4
3E70
3E47
DDC_SCL_A 1E05
10
PNX5100-DDR2-A(0-12) SDRAM 1M97
15
12 DATA-SDA EEPROM
3P30
3P31
5
3HB2 I2C-SDA 15
B07F PNX5100: SDRAM
5 6 15 CLK-SCL 6 256x8
3HB1
6
I2C-SCL 14
11
7P10 1M96
B04F NAND01GW3B2BN 7P07
9P29-4 5 VGA
M24C02
CONNECTOR
FLASH
9P29-3 6
PCI-AD 1G EEPROM
256x8
PCI
RES
B01B DC/DC B06C TEMPERATURE & FAN CONTROL B06A FPGA BACKLIGHT - LVDS & I2C - MUX B06D FPGA LOCAL CONTRAST
LVDS IN/OUT
+3V3-PER +3V3
SET BUS
100 kHz
3HPV
3HPT
3F39
3F38
1R08
B33 SDA2 3HPU SDA-SET 9F20 SDA-BOLT-ON 3E83 6
SDA 2
TO BOLT-ON
D32 SCL2 3HPS SCL-SET 9F19 SCL-BOLT-ON 3E84 5
SCL 2 MODULE
9FA2
9FA1
1F53
3F61
3F62
3F67
3F66
9F18 9F16 +3V3
ERR +3V3-PER 3F17 2
14 DISPLAY BUS
1 2 7 6 2 1 9F17 9F14
STANDBY BUS 3F18 3 100 kHz
3F37
3F36
1F51
400 kHz
3H50
3H49
RESERVED RESERVED
B04A
3H53
3H53
3H52
+3V3-PER
STANDBY QUAD 9E41
BILATERAL 2 RXD-UP
3HC2-2
5 6
7HC4 6 SWITCHES 9E40
9 TXD-UP
AC1 RESET-NVM 3HC2-1 EF 8 7HC3
PO_1 UART-SWITCH 13
M24C64 B04A 7E17
1R12 1G50
UART-SWITCHn 5 ST3232C
3E08
3H60
3HPL
L32 RXD-MIPS 9
GPIO_4 R2-OUT
L31 TXD-MIPS 10
GPIO_5 T2-IN
3HPP
1R20 1E06
AL27 5FC7 3 9E35 RXD 3E41
RXD-MIPS2 3
UA2_RX
9E36 3E91 UART
AK27 TXD-MIPS2 5FC5 1 TXD 2
UA2_TX SERVICE
1 CONNECTOR
RES
18310_405_090305.eps
090316
2009-May-08
Block Diagrams Q549.2E LA 9. EN 66
VDDA-DAC
1C02 5CG2 +VDISP1 7A02
LCD-PWR-ON
+1V8-PNX85XX B04g,p,
B05e
7CG2 B07D HDMI
POWER SUPPLY B04p
LCD-PWR-ON T3A
B06e,B07d
+1V8-PNX85XX +1V8-PNX85XX 7A00-2
1C01 B09b
CN4 1M95 5CG0 +VDISP2
1 1 +3V3-STANDBY B02A FRONT-END B05e
+3V3 +3V3
LCD-PWR-ON
3.3V_ST
7U50
B04a,p B04M PNX8543: AUDIO T3A RES B01a +12V +12V
B07d,B08d B01b
+1V2-STANDBY 5P11 REF-3V3 3A07 +V-LM833
IN OUT B01a,B04p
COM +3V3 +3V3 7P01 7A07
+3V3A +3V3A B01a 3A26
B02b 1V8-HDMI +2V5-REF
+AUDIO-POWER +AUDIO-POWER IN OUT VOLT.
7U0M B07h
+5V-TUN +5V-TUN B01b B05I PNX5100: DEBUG COM REG.
7U0N AUDIO-VDD ADIO-VDD
5T11 RES
VOLT. +5V-TUN-PIN B04i +3V3 +3V3
REG. B01a +3V3-STANDBY +3V3-STANDBY
+33VTUN +33VTUN B01b
RESERVED
B01b
3T10 +5V +5V B10A AUDIO
B01c
2 2 STANDBY B06A
STANDBY B04A 3T11 3T12 +VTUN
B04N PNX8543: VIDEO STREAMS FPGA BACKLIGHT-LVDS & I2C-MUX 3P47 +5V-EDID
3 3 1M59 B07e +AUDIO-POWER +AUDIO-POWER
CONTROL 1F50 1P04
+3V3-PER +3V3-PER 5F05 6 HDMI 3 B01b
GND1 ANTENNA-SUPPLY ANTENNA-SUPPLY TO 1M59 18 AIN-5V
4 4 B02b B04p AB1 CONNECTOR
T1A
GND1 +3V3 +3V3 +3V3 +3V3 DC-DC
5 5 B01a
B01a OR
GND1 5F04 +3V3M AMBI-LIGHT HDMI 2
1P03
BIN-5V
AB1 INTERFACE + SINGLE DC-DC
MODULE 18
CONNECTOR
7F07 1M90
6 6
1U01 +12V B01c,B02b, B02B DEMODULATOR +1V2M +24V
+12V B06c,B07b,h, B04O PNX8543: DIGITAL VIDEO OUT / LVDS IN OUT TO CN7
1
7 7 T3A B08b,B09b COM 1P05
7F06 HDMI SIDE DIN-5V SUPPLY
+12V 18 1101 5102
3U42 5U08 6U0B +33VTUN +1V2-PNX85XX +1V2-PNX85XX +2V5M CONNECTOR +24VF
8 8 AB2
+12V B01a VDDA-LVDS VDDA-LVDS IN OUT
1M59
B02a 9T64 COM T3A
7U0P B04p 1P02
HDMI 1 TO 1M59 6 +3V3
18 CIN-5V AB3
9T62 +1V2 CONNECTOR B06A
VSW SSB +12V +12V
5T51 +1V2A +1V2-PNX85XX +1V2-PNX85XX AB2
7T54
RESERVED B04P PNX8543: POWER B01a
+2V5 +2V5 c001 VLED1
IN OUT B09b
COM
1U03 +12VF +1V2-PNX85XX +1V2-PNX85XX +5V +5V +16V +16V
RES B01a AB2
B01a +3V3 +3V3 B01c
9 9 T3A +AUDIO-POWER B01a B01b
+1V2-STANDBY +1V2-STANDBY RES B07E HDMI SWITCH c002 VLED2
1M84
+VSND B04i,m,B10a 5T54 +3V3A
B02a +1V8-PNX85XX +1V8-PNX85XX +5V-EDID +5V-EDID 6
10 10 5U20 B07d TO
GND_SND 5T53 +3V3D B09b 11
5U21 B01b
+3V3-STANDBY +3V3-STANDBY B06B U-WAND 6P06 AMBI-LIGHT
2K9 SUPPLIES 5T52 +3V3E 13 MODULE
+3V3 +3V3
11 11 5U06 +5V-TUN +5V-TUN B01a 1P06
B07h +12V HDMI SIDE EIN-5V
N.C. +3V3 +3V3 +12V 18 OPTIONAL
B01a B01b CONNECTOR
5U17 5T55 +5V-TUN-CVBS
2K8 SUPPLIES 5HVH +3V3-PER
+5V-DDC
B04a,b,e,f,n 1M96
7T56 3T69 ANTENNA-SUPPLY 5HV8 RREF-PNX85xx 3
AB2 DUAL DC-DC
B02a
5HVD VDDA-LVDS
B04h B06C TEMPERATURE & FAN CONTROL
RES +24VF +24VF
B04o +3V3 +3V3 AB1
+12V RES B01a
CN7 VDDA-AUDIO VDDA-AUDIO 7200
+12V +12V
1 B04l TPS54283PWP
24Vb +12V +12V 5HY4 VDDA-DAC B01b
2 +3V3 +3V3 14
GND1
3
TO B01a B01b
5HY7 AUDIO-ADC
B04l B07F PNX8543: FLASH
NON (VLED1)
24Vb DC-DC INTERFAC +5V +5V 12 5201 +12V
SYNCHRONOUS AB1
4 (OPTIONAL) B01c +3V3 +3V3
GND1 B06D FPGA WOW - LVDS IN / OUT B01a CONVERTER
(VLED2)
5 1M20 5200 +16V
24Vb 5P09 +3V3-NAND 3 AB1
6 +3V3-STANDBY 5 +VDISP 5FH4 +VDISP
TO B05A PNX5100: SDRAM B05h
GND1 1F51
IR/LED
8 5FG1 41 OPTIONAL
PANEL +1V8-PNX5100 +1V8-PNX5100
B04A PNX8543: STANDBY CONTROLLER
B06e 5FG2
1316 3C20 PNX5100-DDR2-VREF-CTRL B07G ETHERNET
AB3 MICROCONTROLLER BLOCK
1
HVR
2 +1V2-PNX85XX +1V2-PNX85XX 3C22 PNX5100-DDR2-VREF-DDR +3V3 +3V3
HVR TO DISPLAY B01a
3 B01a
HVR B01c
+1V2-PNX5100 +1V2-PNX5100 B06E FPGA WOW - POWER & CONTROL 5N06 +3V3-ET-DIG B01b
+3V3 +3V3
7301
+3V3-STANDBY +3V3-STANDBY 5N07 +3V3-ET-ANA +1V8
B01b IN OUT
1319 +3V3 +1V2-PNX85XX +1V2-PNX85XX COM
+3V3
B01a
HVL
1 B01a
+3V3-PER +3V3-PER
B05B PNX5100: VIDEO-IN CFH0 +1V2-FPGA
B06g
2 B04p OPTIONAL
HVL TO DISPLAY
+3V3 +3V3 5FH0 +1V2-PLL
HVL
3
B01c
+5V +5V B01a B06g B07H BUFFERING
+1V8-PNX85XX +1V8-PNX85XX
B09b +3V3 +3V3
B01a
CFH1 +1V8-PNX5100
B05a,c +5V5-TUN +5V5-TUN
B01c
B05C PNX5100: POWER +2V5 +2V5
B01A DC/DC
B04B PNX8543: DEBUG B09b 7P11 +5V-TUN
B02a,b
5FH2 +2V5out-FPGA
B06g
+1V2-PNX5100 +1V2-PNX5100 7P13
B01c 5FH3 +2V5in-FPGA
+3V3-PER +3V3-PER B06g VOLT.
1V2-STANDBY 1V2-STANDBY B04p 5C60 +1V2-PNX5100-CLOCK REG.
B01b 5FH4 +2V5-PLL
B06g
5C61 +1V2-PNX5100-TRI-PLL1 +12V +12V
+12VF +3V3 +3V3 B01b
+12VF
B01b 5C62 +1V2-PNX5100-TRI-PLL2 B01a
5FH1 +3V3-FPGA
5U33 +12VF1 B04E PNX8543: CONTROL
5C63 +1V2-PNX5100-TRI-PLL3
B06g
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 67
A 1 2 3 4 5 6 7 8 9 1100 A6 F123 E2 A
1101 A7 F124 E2
1M59 C2 F125 B3
1M84 A2 F126 A2
1M85 A2 I100 A6
1M90 D2 I101 C6
INTERFACE + SINGLE DC-DC 5107 RES
2100 A6
2101 B5
I102 C6
I103 C6
30R 2102 C6 I104 D9
B 5108 RES
+24VF +16V
2103 D6 I105 D5 B
2104 D5 I106 D7
A A
5100 RES
5101 RES
30R 2105 D9 I108 D6
2106 D9 I109 A8
30R
30R
1100 I100 5102
F126 +24V 2107 E9 c001 E2
SPI-LATCH2CONN T 3.0A 32V 10u
F107
1101 * I109 2108 D3 c002 E2
* 2109 E3
2100
220n
1M85 1M84
2.0A T 63V 3100 B5
1 1
F101 SPI-CLOCK-BUF
* * 3101 C5
5103
5104
30R
30R
F102 SPI-DATA-OUT
C 2
3
2
3
F103
F104
SPI-DATA-RETURN
SPI-LATCH1CONN
3102 D6 C
4 4 3103 D9
F105 PWM-CLOCK-BUF +12V
5 5 3104 D6
is prohibited without the written consent of the copyright
6 6 F106 +3V3
All rights reserved. Reproduction in whole or in parts
3100 3105 D5
B 7 7
F108 BLANK-BUF
* * B 3106 D5
5105
5106
F109
30R
30R
8 8 EEPROM-CS 0R1
F110 TEMP-SENSOR RES 3107 D5
9 9
10 10 F111 PROG 3108 E9
F112 VLED1 +16V
11 11 3109 D2
100R
2101
3112
10n
12 12 7100
F113 F114 NCP3163BMNR2G 3110 D3
3
D 13
14
13
14
F125
VLED2
VCC
Φ
3111 E8 D
15 16 15 16 3112 B6
4 15 5100 A8
LPK_SENSE LVI_OUT
502382-1470 502382-1470 5101 A8
5 10 VSW
3101 I101 DRV_COL 5102 A7
11
SPI-LATCH1 47R
6 SWI_EMIT 12 5103 B8
9101 SPI-LATCH1CONN 7 13 5104 B8
C 9102 (RES) 8 SWI_COL
C 5105 B8
owner.
9 20
5106 B8
SS24
6100
9103(RES)
E 9104 SPI-LATCH2CONN
2102 I103
14
BOOT_IN
21
22 5107 A6 E
SPI-LATCH2 23 5108 A6
2n2
1M59 17 24 6100 C8
1
F115 SCL I102 16 VFB 25 7100 B7
1 2
+16V I108 VIA 26
2
1 27
9101 C3
3 F116 SDA TIM_CAP 9102 C3
3103
3109 RES 28
3K3
4 F117 CONTROL1
F118 100R 3110 RES CONTROL2 2 29 9103 C3
5 NC
2104
100n
2103
220p
3102
100R 30 9104 C3
15K
6 F119 +3V3
330R
3104
F120 31 F101 B3
7 I104
F D D F102 B3 F
2108
100p
RES
2105
100n
2106
100n
18
19
1%
F104 B3
3105
3106
3107
1M0
F105 B3
33K
12K
F106 B3
1M90 I106 F107 A7
F121 F108 B3
1 +24V
F109 B3
1%
F122
2
3
F123 +24V F110 B3
G G
100K
2109
100p
3111
3108
2107
100n
3K3
RES
F124 F111 B3
4
5 +24V F112 B3
6 F113 B3
1735446-6 F114 B5
E E F115 C2
F116 D2
F117 D2
c001 F118 D2
+12V VLED1
F119 D2
H c002
F120 D2 H
+16V VLED2 F121 E2
F122 E2
1 2 3 4 5 6 7 8 9
CLASS_NO 1 08-06-19
3104 328 58341 in in in out 24V 16V DC-DC INTERFACE 2 08-08-06
J 3104 328 58351 out out out in 12V 12V 08-06-19 1 3 08-09-18 J
3104 313 6325
3104 328 58361 out out out in 16V 16V 08-08-06 2 AMBI 2K9 4 08-10-23
3104 328 58371 out out out out 12V 16V 08-10-23 3 5 08-12-06
CT MGr CHECK ******** DATE 08-06-06 C ROYAL PHILIPS ELECTRONICS N.V. 2008
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_600_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 68
A A
2200 A4 I213 D5
1 2 3 4 5 6 7 8 2201 A4 I214 D4
2202 A5 I215 D3
2203 A5 I216 B5
2204 B3 I217 B4
DUAL DC-DC 2205 B6
+24VF 2206 B1
B 2207 B2
2208 B7
B
A A 2209 B7
2210 B8
100u 35V
100u 35V
2211 C3
2200
2201
220n
2202
220n
2203
2212 C4
RES RES
2213 C6
3200 I200 I201 3201 2214 C3
VSW 2215 C6
C 6R8
** 2204 7200 2205
6R8
2216 C2 C
3202
** * 3203
*
14
TPS54283PWP 2217 C7
1
PVDD1 PVDD2
**5200 6R8 47n F204 Φ F203 47n 6R8 (VLED1) 2218 D1
is prohibited without the written consent of the copyright
3 12 +12V
+16V SW1 SW2 2220 D7
B **
10u
5
EN1 EN2
6
10u B 2221 D3
7 8
* * RES RES
*
100u 35V
220u 25V
** ** ** FB1 FB2
SS24
SS24
2206
2207
6200
3204
3205
6201
2208
2209
2210
2222 D5
10R
10R
I206
4u7
22u
22u
I217 9 16 I216 2223 D8
ILIM2
10 17
I208 SEQ
* 2224 D8
9201
11 18
D BP
19
I209 3200 A3
3201 A6
D
**
20
*
2211
2213
21 3202 B3
**
1n0
1n0
9202
VIA2 22 3203 B6
23
24
3204 B3
I211 I210 3205 B6
F207 25
3206 D3
C ** 26
* C
2214
2215
GND GND_HS 3207 D2
1n0
1n0
owner.
2212
15
4u7
3208 D7
E 3209 D5
3210 D3
E
3211 D3
RES
2216 RES I212 2217 F201 3212 D6
+16V +12V 3213 D6
RES
22n 22n 5200 B2
RES 3206
3207
** 3208
* 5201 B7
3K3
3K3
3209
2218 RES
6200 B2
2219 RES
68K 47K
** ** *
*
*
1% 1% 1% 6201 B7
F F
3210
3211
3212
3213
2220
3K9
33K
3K3
33K
4u7
4u7
10u
I214 I213 7200 B4
D D
1%
9201 B5
2222 RES
RES 2221
9202 C4
22n
22n
VLED1
F200 B2
I215
F201 C7
* *
2223
2224
10u
10u
F202 D3
F202 F203 B5
F204 B4
F207 C4
7200 : TPS54383 in case of 16V or dual dc-dc converter
G I200 A3
I201 A6
G
The components marked with one star (*) belong to the 12V versions (3104 328 58351, 3104 328 58371). I204 B2
I205 B6
E The components marked with two stars (**) belong to the 16V versions E I206 B6
I208 B3
(3104 328 58331, 3104 328 58341, 3104 328 58361, 3104 328 58371). I209 B6
I210 C6
I211 C3
H I212 C3 H
1 2 3 4 5 6 7 8
I I
CHN SETNAME
CLASS_NO 1 08-06-19
J 08-06-19 1
3104 313 6325 3 08-09-18 J
08-08-06 2 AMBI 2K9 4 08-10-23
08-10-23 3 5 08-12-06
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_601_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 69
A A
1300 E2 9303 F3
1 2 3 4 5 6 7 8 9 10 11 1301 H5 9305 G1
1302 C4 9307 H4
B 2300 A3
2301 A4
C300 B8
F300 A5
B
2302 A5 F301 A8
MICROCONTROLLER 3310 2303 A4 F302 A10
2304 B8 F303 B11
7301
LD2985BM18R
RES +3V3 +3V3
100K RES 2305 B10 F304 C4
2306 B9 F305 C4
A F300
+3V3
A 2307 B10 F306 D4
1%
1%
1 5 +1V8
+3V3 IN OUT 2308 D4 F307 F3
3311
C C
3312
I303 7300-2
1K5
1K5
3
INH BP
4 LM393PT 2309 D5 F308 F3
2300
2301
100n
2302
4u7
1u0
F301 2310 F6 F309 G6
8
COM 5
2311 F7 F310 G6
2303
7
10n
F302 2312 F7 F311 G8
6
2
2313 F7 F312 G8
RES
4
2304
3314
2314 F7 F313 G8
-T 10K
10n
3313
2315 F7 F314 G5
10K
+3V3
F303 2316 F8 F315 H4
D 2305 2318 G2 F316 C9 D
B B 2319 G6 F317 F1
C300
10n RES
2320 H5 F320 E9
1K5 1%
3315
2306
100n
2307
+3V3
3316
10n
2321 H4 I300 E9
47K RES 2322 H4 I302 F9
7300-1
2323 H4 I303 A4
1K5 1%
LM393PT
2324 H4 I304 C10
RES
3317
8
3 3300-2 D5 I305 E6
E F316
2
1
I304 3318
3300-3 D7 I306 E7 E
+3V3 +3V3 10K RES 3300-4 D7 I307 G6
4
3301-1 D6 I308 G2
1K8 1%
3319
+3V3 3301-2 E5 I309 G5
RES
3301-3 E6 I310 D5
C C
3320
10K
10K
3321
3301-4 D7 I311 E7
3302-1 D7 I312 E7
RES
1302
F304 3302-2 D6 I313 E7
10K
10K
10K
3302-3 E6 I314 F7
10K
10K
F F
10K
10K
10K
10K
10K
1
5
2 F305 3302-4 D6 I315 F7
3 3303-1 E6 I316 F8
4 5 3303-2 D6 I317 F6
3302-2
3302-4
3301-1
3303-2
3304-1
3301-4
F306
3300-3
3304-2
3304-4
2
4
3303-3 E6 I318 F7
10K
10K
B3B-PH-SM4-TBT(LF)
RES
3304-1 D6 I319 F5
7
100R
100R
3322
3323
3324
3304-2 D7 I320 F8
3304-3 D7 I321 F6
7 3300-2
10K 3325
3304-4 D7 I322 G5
2
G D D 3305-1 E7 G
3305-2 G8
RES
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
I310
8
2308
100p
2309
100p
3305-3 G9
3305-4 G8
3306-1 E8
3302-1
3300-4
3304-3
3305-1
3326
3327
3302-3
3301-2 2
1
3301-3
3306-2 E8
3303-1
3303-3
3306-3 E8
3328
7302
19
43
31
3329
LPC2103FBD48 3306-4 E8
7
H VSS Φ VSSA 3307-1 E8
H
I305
11 13
10K
X1 P0.0|TXD0|MAT3.1 3307-2 F8
MICRO- P0.1|RXD0|MAT3.2
14
I306 3307-4 F8
16M9
I300
12 CTRL 18 3306-3 3 6 CONTROL1
X2 P0.2|SCL0|CAP0.0
E E 3308-1 F8
1300
6 46 100R
RST P0.16|EINT0|MAT0.2 I317 I318 I302
F 47 I319 3309-4 5 4
F
All rights reserved. Reproduction in whole or in parts
2314 RES
J 1 100R
J
1K0
2
10K
2310
100p
2311
100n
2312
100p
2313
100p
100p
2315
100p
2316
100p
NCP303LSN10T1 3
P0.21|SSEL1|MAT3.0
2
IN P0.22|AD0.0
32 3321 C5
1 33 3322 D5
F317 RST P0.23|AD0.1
3 34
GND P0.24|AD0.2 3323 D5
9305 RES
38
I308 P0.25|AD0.6 I307 3324 D7
5 4 39 UD-MD
CD NC P0.26|AD0.7 I322 3325 D6
8 F309
P0.27|TRST|CAP2.0
P0.28|TMS|CAP2.1
9 3326 D6
F310
2318
100n
K P0.29|TCK|CAP2.2
P0.30|TDI|MAT3.3
10
15
F311
F312
4
3305-4
5
10K 3 6
3327 D6
3328 E5
K
G P0.31|TDO
16
22R
3334 F313 2
3305-2
7
10K
3305-3 10K +3V3 G 3329 E5
VDD_1V8 VDD_3V3 VDDA 3330 E8
owner.
3331 E8
5
17
40
42
3335 F314
I309 3332 E3
100R 3333 F2
1
2
2319
100p
3336
10K
10K
3337
3334 G5
2320
100n
SKHUBHE010
3335 G5
L 9307
L
1301
3336 G6
RES
H H 7300-1 B9
2321
100n
2322
100n
2323
100n
2324
100n
7300-2 A10
7301 A4
7302 E3
M 7303 F2 M
9300 E3
9301 F3
9302 F3
1 2 3 4 5 6 7 8 9 10 11
N N
O O
CHN SETNAME
CLASS_NO 1 08-06-19
08-06-19 1 3 08-09-18
P 3104 313 6325
08-08-06 2 AMBI 2K9 4 08-10-23
08-10-23 3 5 08-12-06 P
NAME Peter Van Hove SUPERS. 3 130 3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_602_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 70
1M59
1302 5201 2208 1M85
2209
3338
6201
2220
2300
9104
2203 2210
3331
2310
7301
2322
2315
9103
7200
2301
9102
3307 9101
2202 2302 3306
2303
2321
2316
3308
2311
2201
2218 2323
3309
2319
3324
2200 2206
9201 3326
1101
2312
1301
9202
2219
1M90
6200
2223
2224
5102
1100
5200 2207
1M84
F115
F103
F106 F109
c001
I302 F116
F101 F113
F105
F110 F111
I300
F122
3109 F117
F307
F126
3110
5106 5103
9302
3332
9300
F118
F112 F304
9303
c002
3330
5105 5104
3321
3320
3205
3304 F312
I305 2308 2309 2212 I209
I306
F313
I312
3209
F305 I213
2318
F311
F207
3201
3203
I317
2222
1300
6100
I313
I303 2205
3212
I206
I217
F310 3208
F308
7302
I310
3337 2217
F309
3336
3204
3207
F300
3333
3339
9305
F317
9301 F200 2216
3303
I105
3210
I216
I321
2106
2104
3105 3200
I314
I204
3211
I315
3106 3202
I102
I104
I318
I320 2313 2105 3206 F123
I212
2102
3104
3103
3325 2221
F320
I307
3329
2107 I103
5107
F202
I208
C300
2304
3314
3311
2214 2211
F301
5100
2307 3312
F302
F303
7100 I109
3310
3318
3316
3315
2305
I304
3102
2103
F124
2306
I100
I108
3317 3112
3100
F316
I101
F104
F121
3319 I215 2101
3101
10000_012_090121.eps
090121
31043136325.5 18310_550_090309.eps
090309
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 71
A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101
1%
1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT
3135
3136
F121 9111 SPI-DATA-IN SPI-DATA-RETURN 9108 SDA +1V8
2 7116-2 2111 G4 C140 B10
1K5
1K5
2101
2102
100n
2103
C RES 3 4
C
4u7
F122
1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116
8
2113 H7 F102 F5
2104
F124 9110 COM 5
10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5
2
7
RES
F127 RES EEPROM-CS
4
8 2116 F9 F105 D7
2105
3137
-T 10K
F128
10n
TEMP-SENSOR
3111
9 2117 F9 F106 B12
F129 PROG
10
10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D
C140
9112
9114
2125
33p
14 1105 10n RES 2121 H6 F112 G8
1K5 1%
10u 35V
10u 35V
15 16 VLED1 VLED1-F 3138 2122 F9 F116 A10
2127
2128
2129
2107
100n
2108
+3V3
3139
1u0
10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11
1K5 1%
LM393PT 2125 B3 F120 A1
RES
3140
2126 F10 F121 A1
8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E
4
2
1K8 1%
3 SDA 2130 F2 F125 B1
3123
+3V3
C C
RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1
3107
10K
10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1
10K
10K
10K
10K
10K
10K
10K
10K
10K
PROG
10 3102-2 D9 F131 B1
5
F 11 VLED1 F105
3102-3 E9 F132 B1 F
10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1
3105-2 2
3106-2 2
3104-1 1
3102-1 1
3104-4 4
3101-3 3
4
14
10K
RES
10K
15 16 3103-2 G10 F135 E1
3102-2
3102-4
7
100R
100R
3109
3110
3105-4
3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1
10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G
10K
3104-3 E8 I110 G8
10K
RES
10K
10K
10K
10K
10K
10K
10K
10K
10K
3104-4 D9 I111 G8
8
5
2109
100p
2110
100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10
1
3114
3115
3104-2 2
3104-3 3
3
4
3116
3103-1
3105-4 D8 I124 E11
3102-3
3101-4
3105-1
3105-3
3106-1
3106-3
7102 3106-1 E8 I125 E11
19
43
31
3117
LPC2103FBD48
7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H
10K
X1 P0.0|TXD0|MAT3.1
E 16M9
12
X2
MICRO-
CTRL
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
14
18 3124-4 4 5 I124 CONTROL-1
E 3107 C7
3108 C7
1101
47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts
3119
2122 RES
2124 RES
1 100R
2114 RES
3124-1 E11
10K
1u0
14 P0.19|MAT1.2|MISO1
3120
J 2
J
10K
100p
2115
100p
2116
100p
2117
100p
100p
2123
100p
100p
2126
100p
2131
100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES
38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111
100n
17
40
42
BLANK-BUF
owner.
7 3131 F112
2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R
100p
3132
3131 G7
10K
10K
3133
10 PROG
2112
100n
9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119
100n
2120
100n
2121
100n
2113
100n
3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
1X03
REF EMC HOLE
O O
CHN SETNAME
1
CLASS_NO 1 2008-06-10
3 2008-10-27
P 8204 000 8857
2008-08-08 2 2K9
2008-10-27 3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_610_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 72
2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
B +3V3 +3V3 +3V3
2218 C12
2219 D12
B
7201-1 2220 E9
14
2214
100n
74HCT125PW 3121 D9
2 3203 B5
3219
3213
3210
3
10K
10K
3207 3204 B7
1
+3V3 EN 100R 3205 C5
2201
2217
100p
1K0 RES
33p
7212 3207 B9
7
PDTC144EU 3209 C9
C 7209
PDTC144EU
9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
1 5
D Φ Q
2 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3
2209
3203
74HCT125PW
10K
33p
3215 H6
14
1
S 3204 3216 H6
7 +3V3 12
HOLD 3220 3217 H6
D 3
W M95010-WDW6 10K
+3V3
3209
13
EN
11
27R
3218 H6 D
2202
2218
100p
GND 1K0 RES 3219 B11
33p
7
4 3220 C11
3221 H11
3222 I8
C 9212 RES
C 3223 C11
3224 H11
6216 I8
E 7201-1 A10 E
3223 7201-2 C10
F207
7201-3 D10
+3V3 EN 100R
2219
100p
7201-4 B10
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES
D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9
14
74HCT125PW
9 9210 B10
3121 9211 C9
8 F208 3212
100R EN
10 9212 C10
2220 RES
100R 9213 D9
7
9214 D10
100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9
F F
I I
2216 2215
1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
7215
28
TLC5946PWP
J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7
0
8
1
25 9 F211
GSCLK 2
10
3
2 11 F212
BLANK 4
12
5
K 3217
100R F204
6
MODE 6
7
13
14
F213
K
27 15 +3V3 +3V3
3215 IREF OUT 8
16
9
1K2 3 17
owner.
XLAT 10
18
11
H H
3224
3221
4 19
3K3
3K3
SCLK 12
5 20 F209
SIN 13
3216 24 21
SOUT 14
100R 22
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS
470R
2211
3222
1
29
30
31
32
33
33p
SML-310
6216
M I I M
+3V3
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
O O
1
CHECK DATE C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_611_090305.eps
090410
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 73
3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7
8
3328 G4 9325 F10
D D
9309-2
9310-2
9310-4
9310-1
9312-4
9312-3
9313-1
3330 I4 9326 G10
3331 F4 9327 H10
9301
3332 F4 F302 G5
1
7000 7001 7002 7003 7004
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 GREEN 3 4 GREEN 3 3 9303-3 6 GREEN 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5
E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 RED 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 5 9318-4 4 6 1
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7
7
3341 D1 F328 G9
3342 E2 F329 H10
3343 D1 F330 H10
3344 D1 F340 D1
3345 D12 F341 D1
B R G
F 3346 E1
3347 D1
F342 D1
F343 D2
F
3348 E12 F344 D12
D 3341
3336
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12
9320-1 8
9320-4 5
9320-2 7
8
1K5 390R 3335 3354
3340 3344 3352 E1 F348 G13
9306-4
9306-1
9319-1
390R 560R 3353 E1 F349 G13
560R 1K5 3345 3311 3357 3354 D13
G 3339
3355 E1 G
1
390R 1K5 560R
390R 2 9304-2 7 3348 3312 3358 3356 E1
3342 3357 D13
3346
390R 1K5 560R 3358 E13
560R 390R
3359 E13
3349 3353
E 560R 1K5 3360
E 3360 E13
3361 E13
3362 E13
H 3315
560R 3363 F13
3364 F13
H
3384
1K5 3365 F13
1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 F307 F325
1K5 560R 3370 F1
3331
3301
I 3371 F1
I
10K
10K
560R 7317 3364
F 3387 BC847BW
560R
F 3372 F1
3334 F308 F326 3373 F1
1K5
3374 G1
3388 1K0
3384 E1
3303
3385 F1
10K
1K5 3320 3366
is prohibited without the written consent of the copyright
3389 3386 F1
All rights reserved. Reproduction in whole or in parts
3304
10K
10K
7315 1K5
if VLED < 17V BC847BW 7003 C6
F303 F328 7004 C8
9326
K F348 7005 C11
7305 G4
K
7306 H5
3326
3306
10K
10K
7307 F4
owner.
7315 G9
8
7316 H10
9311-4
9311-3
9311-1
VLED1-F 7317 F9
H H 9301 C1
L F329 9302 C1
L
1
9303-1 C10
7316 9303-3 C10
BC847BW
9303-4 C10
3308 F330
9304-1 E10
9327
1K0 9304-2 E10
9304-4 E10
3309
10K
9305-1 C6
9305-2 C6
M 9305-4 C6 M
9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N
1 2 3 4 5 6 7 8 9 10 11 12 13
O O
CHN SETNAME
CLASS_NO 1 2008-06-10
3 2008-10-27
P 8204 000 8857
2008-08-08 2 2K9
2008-10-27 3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_612_090305.eps
090305
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 74
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108
3107
9313
2129 2128
9113
9109
9112
9111
2125
3110
3120
1M83 1M84
3128
3317
3316
3315
3313
3312
3311
3310
3335
3345
3348
3351
3119
3129 9315
2101 9121
3132
6216
3314
3320
3319
3318
3323
3322
3321
3221
3224
2103
2102
2211
3216
3133
9102
3117
3114
3113
3138 3136
7101
3111
C140
3106 3127
2106 3139
7215
2105
3137
I110
2111
3222
7110 2209 2108
2104
2119
1101 2117
9110
2130
9114
7212 7210
7209
9107
2202
9302
2127
I113
3342 3103 I111 2116
2107
7000
7001
7002
7003
7004
7005
3339 3115
9106
3131
3140 3135
7116
3126
1105
I114
3306
3305
3304
3303
3302
3301
3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116
3332
7307 3334
3331
3343 3373 3356 3391 2203
9325
9327
3220 3212
9326
2120 9119 2214
7315
7317
7316
2113
7102
9308
3211
3204
3123
9317
3210
3333
3327
3330
2218
3349 3371 3347 3387
2210
7201
2123
7214
3326
3328
3325
3104
9307 2124 3134
2122
3352 3370 3344 3388
9208
3219
3102
2216 2121 3141
3355 3341 3353
9213
3142
3207
7306
3214 2215 2131
9301
3217
9311
3337
7305
9211
9316
2217 9209
9312
9303
9319
9304
3203 3205
3218
3215
9305
9309
9320
9318
9310
9103
3118
9101
2114
9314
9306
9108
2201
3336
2220
2115
3112
2118
9104
3223 2219 3101 3125 3105
1M2A 1M1A
F139 F122
F126
I126
F345
F116
F106
F101
F109
F213 F137
F128
F131
F129
F124
F121
F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205
F341
F117 F307
F204 F342
F304 F302
18310_551_090309
3104 313 6313.3 090309
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 75
A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER BLOCK LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101
1%
1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT
3135
3136
F121 9111 SPI-DATA-IN SPI-DATA-RETURN 9108 SDA +1V8
2 7116-2 2111 G4 C140 B10
1K5
1K5
2101
2102
100n
2103
C RES 3 4
C
4u7
F122
1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116
8
2113 H7 F102 F5
2104
F124 9110 COM 5
10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5
2
7
RES
F127 RES EEPROM-CS
4
8 2116 F9 F105 D7
2105
3137
-T 10K
F128
10n
TEMP-SENSOR
3111
9 2117 F9 F106 B12
F129 PROG
10
10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D
C140
9112
9114
2125
33p
14 1105 10n RES 2121 H6 F112 G8
1K5 1%
10u 35V
10u 35V
2128
2129
2107
100n
2108
+3V3
3139
1u0
10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11
1K5 1%
LM393PT 2125 B3 F120 A1
RES
3140
2126 F10 F121 A1
8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E
4
2
1K8 1%
3 SDA 2130 F2 F125 B1
3123
+3V3
C C
RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1
3107
10K
10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1
10K
10K
10K
10K
10K
10K
10K
10K
10K
PROG
10 3102-2 D9 F131 B1
5
F 11 VLED1 F105
3102-3 E9 F132 B1 F
10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1
3105-2 2
3106-2 2
3104-1 1
3102-1 1
3104-4 4
3101-3 3
4
14
10K
RES
10K
15 16 3103-2 G10 F135 E1
3102-2
3102-4
7
100R
100R
3109
3110
3105-4
3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1
10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G
10K
3104-3 E8 I110 G8
10K
RES
10K
10K
10K
10K
10K
10K
10K
10K
10K
3104-4 D9 I111 G8
8
5
2109
100p
2110
100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10
1
3114
3115
3104-2 2
3104-3 3
3
4
3116
3103-1
3105-4 D8 I124 E11
3102-3
3101-4
3105-1
3105-3
3106-1
3106-3
7102 3106-1 E8 I125 E11
19
43
31
3117
LPC2103FBD48
7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H
10K
X1 P0.0|TXD0|MAT3.1
E MICRO- P0.1|RXD0|MAT3.2
14
E 3107 C7
16M9
12 18 3124-4 4 5 I124
X2 CTRL P0.2|SCL0|CAP0.0 CONTROL-1 3108 C7
1101
3119
2122 RES
2124 RES
1 100R
2114 RES
3124-1 E11
10K
1u0
14 P0.19|MAT1.2|MISO1
3120
J 2
J
10K
100p
2115
100p
2116
100p
2117
100p
100p
2123
100p
100p
2126
100p
2131
100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES
38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111
100n
17
40
42
2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R
100p
3132
3131 G7
10K
10K
3133
10 PROG
2112
100n
9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119
100n
2120
100n
2121
100n
2113
100n
3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
1X03
REF EMC HOLE
O O
CHN SETNAME
1
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
3104 313 6314.3 NAME Peter Van Hove SUPERS. 3 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_650_090508.eps
090507
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 76
2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER BLOCK LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B +3V3 +3V3
9208 RES
+3V3
2218 C12
2219 D12
B
7201-1 2220 E9
14
2214
100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219
3213
3210
3 PWM-CLOCK-BUF
10K
10K
3207 F205 3204 B7
1
+3V3 EN 100R 3205 C5
2201
2217
100p
1K0 RES
33p
7212 3207 B9
7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3
2209
3203
74HCT125PW
10K
33p
3215 H6
14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D
2202
2218
100p
GND 1K0 RES 3219 B11
33p
7210
7
3220 C11
10K RES
PDTC144EU 4
3 9211
3221 H11
3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E
14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R
2203
2219
100p
1K0 RES 7201-4 B10
33p
7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9
14
74HCT125PW
9 9210 B10
3121 9211 C9
SPI-DATA-RETURN 8 F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10
2220 RES
100R 9213 D9
7
9214 D10
100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9
F F
I +3V3
I
2216 2215
1u0 100n
7215
28
TLC5946PWP
J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
XLAT 10
18 F215
11
H H
3224
3221
4 19
3K3
SPI-CLOCK-BUF PWM-B2
3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS
470R
2211
3222
1
29
30
31
32
33
33p
SML-310
6216
M I I M
+3V3
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
O O
CHN SETNAME
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3104 313 6314.3 3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_651_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 77
3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5
9307
9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7
5
3328 G4 9325 F10
D D
9309-2
9309-1
9309-4
9310-2
9310-4
9310-1
9312-4
9312-3
9312-1
9313-1
9313-2
9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301
9302
3332 F4 F302 G5
4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5
E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7
7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12
9320-1 8
9320-4 5
9320-2 7
6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13
9306-4
9306-1
9306-3
9319-1
9319-4
9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G
3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3342 3357 D13
3346 3350
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331
3301
I 7307 3371 F1
I
10K
10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317
9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332
3303
3385 F1
10K
10K
560R 1K5 3320 3366
3373 3389 3386 F1
1K5 560R 3387 F1
560R 1K5 3321 3367 3388 F1
J 3374 3390 PWM-B1 PWM-B2
Place jumper 9325, 9326, 9327
1K5 560R 3389 F1 J
560R 1K5 if VLED < 17V 3322 3368 3390 G1
VLED1-F VLED1-F
3391 3391 G1
1K5 560R 7000 C2
G 1K5 F302 F327
RED-2
3323 G 7001 C3
Place jumper 9314, 9316, 9317 7002 C4
3325
3304
7305
10K
10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314
9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326
3306
10K
10K
7307 F4
7315 G9
8
7316 H10
PWM-R1 PWM-R2
9311-4
9311-3
9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L
1
GREEN-2 9303-1 C10
3327
3307
7306
10K
10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316
9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330
3309
10K
10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N
1 2 3 4 5 6 7 8 9 10 11 12 13
O O
CHN SETNAME
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3104 313 6314.3 3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_652_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 78
A A
1M3A E2
1 2 3 4 5 6 7 8 9 10 1M85 D2
3536 E9
B 3537 E9
3538 E7
B
3539 E9
3540 E7
LED DRIVE 3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
C 3547 E8 C
A A 3549 F7
3550 E8
3552 F7
3553 F8
3555 F7
7006 7007 3556 F8
LTW-E500T-PH1 LTW-E500T-PH1
3569 F7
D GREEN-1 4 GREEN 3 4 GREEN 3
3570 F7
3571 G7
D
RED-1 5 RED 2 5 RED 2 3572 G7
3573 G7
BLUE-1 6 BLUE 1 6 BLUE 1 3574 G7
B GND_HS GND_HS B 3584 F8
3585 F8
7
3586 F8
E 3587 G8 E
3588 G8
3589 G8
3590 G8
3591 G8
7006 A5
7007 A7
F C C F
1M85
1 SPI-CLOCK-BUF
2 SPI-DATA-OUT
G 3
4
SPI-DATA-RETURN
SPI-LATCH G
5 PWM-CLOCK-BUF GREEN-2
6 +3V3
D 7
8
BLANK-BUF
EEPROM-CS
RED-2
D
9 TEMP-SENSOR BLUE-2
10 PROG
11 VLED1
12
H 13
14
VLED2
H
15 16
3536
3538 3541
560R 1K5
3570 3586
K 560R
3571
1K5
3587
K
560R 1K5
3572 3588
G 560R
3573
1K5
3589
G
560R 1K5
L 3574 3590
L
560R 1K5
3591
1K5
M M
1 2 3 4 5 6 7 8 9 10
1X04
REF EMC HOLE
N N
O O
CHN SETNAME
CLASS_NO 1 2008-05-23
2008-05-23 1 3 0
P 8204 000 8874
3104 313 6314.3 2008-08-08 2 2K9
2008-10-31 3 P
NAME Peter Van Hove SUPERS. 1 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_653_090508.eps
090508
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 79
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108
3107
9313
2129 2128
9113
9109
9112
9111
2125
1M83 1M84 1M85
3110
3120
3128
3317
3316
3315
3313
3312
3311
3310
3335
3345
3348
3351
3119
3129 9315
2101 9121
3132
6216
3314
3320
3319
3318
3323
3322
3321
3221
3224
2103
2102
7215
2211
3216
3133
9102
3117
3114
3113
3138 3136
7101
3111
C140
3106 3127
2106 3139
2105
3137
I110
2111
3222
7110 2209 2108
2104
2119
1101 2117
9110
2130
9114
7212 7210
7209
9107
2202
9302
2127
I113
3103
7000
7001
7002
7003
7004
7005
7006
7007
3342 2116
1X03 1X04
I111
9106
3131
3140 3135
7116
3126
1105
I114
3306
3305
3304
3303
3302
3301
3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116
3332
7307 3334
3331
3343 3373 3356 3391 2203
9325
9327
3220 3212
9326
2120 9119 2214
7315
7317
7316
2113
7102
9212 9308
3211
3204
3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
3123
9317
3210
3333
3327
3330
2218
3349 3371 3347 3387
2210
7201
2123
7214
3326
3328
3325
3104
9307 2124 3134
2122
3352 3370 3344 3388
3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
9208
3219
3102
2216 2121 3141
3355 3341 3353
9213
3142
3207
7306
3214 2215 2131
9301
3217
9311
3337
7305
9211
9316
2217 9209
9312
9303
9319
9304
3536
3537
3539
3542
3203 3205
3218
3215
9305
9309
9320
9318
9310
9103
3118
9101
2114
9314
9306
9108
2201
3336
2220
2115
3112
2118
9104
3223 2219 3101 3125 3105
I126
F345
F116
F106
F344 F209 F104 I124 F212
F101
F109
F213 F137
F128
F131
F129
F124
F121
F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205
F341
F117 F307
F204 F342
F304 F302
18490_550_090326.eps
31043136314.3 090326
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 80
A 1 2 3 4 5 6 7 8 9 10 11 12 13 1101 E4
1105 B5
7116-2 A12
9101 E5
A
1M1A C1 9102 F5
1M2A G1 9103 F5
1M83 A1 9104 F5
MICROCONTROLLER BLOCK LITEON 1M84 E1 9106 H8
2101 A6 9107 A5
2102 A7 9108 A5
2103 A8 9109 A5
B 2104 B7 9110 B5 B
2105 B10 9111 A3
3134
2106 B13 9112 B2
2107 B11 9113 B3
A IN 7101
LD2985BM18R
+3V3 +3V3
100K RES A 2108 B12 9114 B2
1M83 +3V3 2109 D7 9119 H6
F101
1%
1%
F120 SCL SCL 9107 SPI-CLOCK 1 5 2110 D7 9121 G4
1 +3V3 IN OUT
3135
3136
F121 9111 SPI-DATA-IN SPI-DATA-RETURN 9108 SDA +1V8
2 7116-2 2111 G4 C140 B10
1K5
1K5
2101
2102
100n
2103
C RES 3 4
C
4u7
F122
1u0
3 SDA INH BP LM393PT
F123 CONTROL-1 CONTROL-1 9109 SPI-LATCH 2112 H7 F101 A8
4 F116
8
2113 H7 F102 F5
2104
F124 9110 COM 5
10n
5 CONTROL-2 CONTROL-2 PWM-CLOCK
F125 +3V3 7 2114 F9 F103 H7
6 F106
F126 9113 BLANK 6 2115 F9 F104 F5
2
7
RES
F127 RES EEPROM-CS
4
8 2116 F9 F105 D7
2105
3137
-T 10K
F128
10n
TEMP-SENSOR
3111
9 2117 F9 F106 B12
F129 PROG
10
10K
F130 VLED1 +3V3
F117
2118 H8 F107 C7
11
B 12
F131
2106 B 2119 H6 F108 D7
D 13
F132 VLED2 2120 H6 F109 G3 D
C140
9112
9114
2125
33p
14 1105 10n RES 2121 H6 F112 G8
1K5 1%
10u 35V
10u 35V
15 16 VLED1 VLED1-F 3138 2122 F9 F116 A10
2127
2128
2129
2107
100n
2108
+3V3
3139
1u0
10n
1.5A T
47K
2123 F10 F117 B13
RES
7116-1 2124 F10 F118 C11
1K5 1%
LM393PT 2125 B3 F120 A1
RES
3140
2126 F10 F121 A1
8
3
1M1A 1 3141 2127 B1 F122 A1
E 1 SCL
+3V3 +3V3
F118
2
10K RES
2128 B1
2129 B2
F123 A1
F124 B1
E
4
2
1K8 1%
3 SDA 2130 F2 F125 B1
3123
+3V3
C C
RES
CONTROL-1
4 2131 F10 F126 B1
5 CONTROL-2
3101-2 D7 F127 B1
3107
10K
10K
3108
6 +3V3
3101-3 D9 F128 B1
7
8 EEPROM-CS
F107
3101-4 E9 F129 B1
9 TEMP-SENSOR 3102-1 D9 F130 B1
10K
10K
10K
10K
10K
10K
10K
10K
10K
PROG
10 3102-2 D9 F131 B1
5
F 11 VLED1 F105
3102-3 E9 F132 B1 F
10K
12
VLED2 3102-4 D9 F133 E1
13
F108 3103-1 E9 F134 F1
3105-2 2
3106-2 2
3104-1 1
3102-1 1
3104-4 4
3101-3 3
4
14
10K
RES
10K
15 16 3103-2 G10 F135 E1
3102-2
3102-4
7
100R
100R
3109
3110
3105-4
3112
3103-3 G11 F136 F1
3103-4 G10 F137 F1
D D 3104-1 D8 F138 F1
10K 3113
2
7 3101-2
3104-2 E8 F139 F1
G G
10K
3104-3 E8 I110 G8
10K
RES
10K
10K
10K
10K
10K
10K
10K
10K
10K
3104-4 D9 I111 G8
8
5
2109
100p
2110
100p
3105-1 E9 I113 G10
3105-2 D8 I114 G10
3105-3 E8 I115 G10
1
3114
3115
3104-2 2
3104-3 3
3
4
3116
3103-1
3105-4 D8 I124 E11
3102-3
3101-4
3105-1
3105-3
3106-1
3106-3
7102 3106-1 E8 I125 E11
19
43
31
3117
LPC2103FBD48
7
3106-2 D8 I126 F11
VSS Φ VSSA
3106-3 E8
H 11 13
H
10K
X1 P0.0|TXD0|MAT3.1
E 16M9
12
X2
MICRO-
CTRL
P0.1|RXD0|MAT3.2
P0.2|SCL0|CAP0.0
14
18 3124-4 4 5 I124 CONTROL-1
E 3107 C7
3108 C7
1101
47 3127-1 1 8 SCL
12 P0.17|CAP1.2|SCL1
48 3127-4 4 5 100R 3123 C11
All rights reserved. Reproduction in whole or in parts
3119
2122 RES
2124 RES
1 100R
2114 RES
3124-1 E11
10K
1u0
14 P0.19|MAT1.2|MISO1
3120
J 2
J
10K
100p
2115
100p
2116
100p
2117
100p
100p
2123
100p
100p
2126
100p
2131
100p
NCP303LSN10T1 3
2
P0.21|SSEL1|MAT3.0
32
3124-3 E11
IN P0.22|AD0.0 3124-4 E11
1 33
F109 RST P0.23|AD0.1
3 34 3125-1 F11
GND P0.24|AD0.2
9121 RES
38 3125-2 F11
P0.25|AD0.6
5 4 39 UD-MD 3125-4 F11
CD NC P0.26|AD0.7
1M2A 8 I111
P0.27|TRST|CAP2.0
9
3126-1 F11
1 SPI-CLOCK-BUF P0.28|TMS|CAP2.1 3126-2 F11
G I110
G
2111
100n
17
40
42
BLANK-BUF
owner.
7 3131 F112
2118 RES
EEPROM-CS 3129 E11
8
TEMP-SENSOR 3130 G8
9 100R
100p
3132
3131 G7
10K
10K
3133
10 PROG
2112
100n
9106
RES
11 VLED1 3132 H8
9119
12 3133 H8
L 13
14
VLED2
+3V3 F103
3134 A13 L
15 16 +1V8 3135 A11
H H 3136 A12
3137 B11
2119
100n
2120
100n
2121
100n
2113
100n
3138 B13
3139 B12
3140 C11
3141 C13
M 3142 F11
7101 A7
M
7102 E6
7110 F4
7116-1 B11
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
1X03
REF EMC HOLE
O O
CHN SETNAME
1
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_630_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 81
2201 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 2202 C8
A 2203 D8 A
2209 B2
2210 G6
2211 I6
MICROCONTROLLER BLOCK LITEON 2214 A6
INPUT BUFFER 2215 F7
A A 2216 F7
2217 B12
+3V3
B +3V3 +3V3
9208 RES
+3V3
2218 C12
2219 D12
B
7201-1 2220 E9
14
2214
100n
74HCT125PW 3121 D9
PWM-CLOCK 2 3203 B5
3219
3213
3210
3 PWM-CLOCK-BUF
10K
10K
3207 F205 3204 B7
1
+3V3 EN 100R 3205 C5
2201
2217
100p
1K0 RES
33p
7212 3207 B9
7
PDTC144EU 3209 C9
C 7209
PDTC144EU
SPI-CS SPI-CS SPI-DATA-IN 9209
3210 B3 C
B 3 F202
+3V3
7214 8
VCC
B 3211 C9
EEPROM-CS 1 5
D Φ Q
2 SPI-DATA-RETURN 9210 RES 3212 D11
3213 B3
2 6
(64K) 7201-4 3214 H6
C +3V3
2209
3203
74HCT125PW
10K
33p
3215 H6
14
1
S 3204 3216 H6
7 +3V3 SPI-CLOCK 12
HOLD 3220 3217 H6
D F203
3
W M95010-WDW6 10K
+3V3
3209 F206
13
EN
11
27R
SPI-CLOCK-BUF
3218 H6 D
2202
2218
100p
GND 1K0 RES 3219 B11
33p
7210
7
3220 C11
10K RES
PDTC144EU 4
3 9211
3221 H11
3205
3222 I8
C EEPROM-CS-LOCAL 1 SPI-CLOCK-BUF 9212 RES
C 3223 C11
2 3224 H11
+3V3
7201-2 6216 I8
E E
14
74HCT125PW
7201-1 A10
BLANK 5
6 3223 BLANK-BUF 7201-2 C10
3211 F207
4 7201-3 D10
+3V3 EN 100R
2203
2219
100p
1K0 RES 7201-4 B10
33p
7
7209 B2
9213
7210 C2
7212 B3
7214 B6
F D 9214 RES SPI-DATA-OUT-FIL D 7215 G7
9208 A10 F
7201-3 +3V3
9209 B9
14
74HCT125PW
9 9210 B10
3121 9211 C9
SPI-DATA-RETURN 8 F208 3212
100R EN
10 DATA-RETURN-SWITCH 9212 C10
2220 RES
100R 9213 D9
7
9214 D10
100p
F202 B3
G F203 C5 G
F204 H6
F205 B10
E E F206 C10
F207 C10
F208 D10
F209 H11
F210 G9
H F211 G9
F212 G9
H
F213 H9
F214 H9
F215 H9
F F
I +3V3
I
2216 2215
1u0 100n
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
7215
28
TLC5946PWP
J VCC
Φ J
LED DRIVER
G PWM CONTROL F210
G
7 PWM-R1
0
8
1
PWM-CLOCK-BUF 25 9 F211
GSCLK 2
BLANK-BUF 10 PWM-G1
3
2210 2 11 F212
BLANK 4
33p 12 PWM-B1
5
K PROG 3217
100R F204
6
MODE 6
7
13
14
F213
PWM-R2 K
3218 RES 27 15 +3V3 +3V3
3215 IREF OUT 8
1K2 16 F214
9
SPI-LATCH 1K2 3 17 PWM-G2
owner.
XLAT 10
18 F215
11
H H
3224
3221
4 19
3K3
SPI-CLOCK-BUF PWM-B2
3K3
SCLK 12
SPI-DATA-IN 5 20 F209
SIN 13
SPI-DATA-OUT 3216 24 21 EEPROM-CS-LOCAL EEPROM-CS-LOCAL
SOUT 14
SPI-DATA-OUT-FIL 100R 22 DATA-RETURN-SWITCH DATA-RETURN-SWITCH
15
L +3V3
3214
26
XHALF XERR
23 L
10K VIA
GND GND_HS
470R
2211
3222
1
29
30
31
32
33
33p
SML-310
6216
M I I M
+3V3
1 2 3 4 5 6 7 8 9 10 11 12 13
N N
O O
CHN SETNAME
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 2 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_631_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 82
3301 F9 9310-2 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 3302 F9 9310-4 B8
A 3303 F9 9311-1 H13 A
3304 G9 9311-3 H13
3305 G9 9311-4 H12
LED LITEON 3306 H9 9312-1 B10
3307 H9 9312-3 B10
3308 H9 9312-4 B10
3309 I9 9313-1 B12
3310 D12 9313-2 B12
B A A 3311 D12
3312 E12
9313-4 B12
9314 G5
B
VLED1-F VLED2 3313 E12 9315-1 C12
3314 E12 9315-2 C12
3315 E12 9315-4 C12
3316 E12 9316 H5
9307
9308
3317 F12 9317 F5
3318 F12 9318-1 C8
C 3319 F12
3320 F12
9318-3 C8
9318-4 C8
C
3321 G12 9319-1 D9
3322 G12 9319-3 D9
B B 3323 G12
3325 G4
9319-4 D9
9320-1 D7
3326 H4 9320-2 D7
VLED1-F VLED2 3327 H4 9320-4 D7
5
3328 G4 9325 F10
D D
9309-2
9309-1
9309-4
9310-2
9310-4
9310-1
9312-4
9312-3
9312-1
9313-1
9313-2
9313-4
3330 I4 9326 G10
3331 F4 9327 H10
9301
9302
3332 F4 F302 G5
4
7000 7001 7002 7003 7004 7005
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 G 3333 H4 F303 G4
B R
3334 F4 F304 H5
4 GREEN 3 4 GREEN 3 4 GREEN 3 2 9305-2 7 4 GREEN 3 6 9318-3 3 4 GREEN 3 3 9303-3 6 4 GREEN 3 2 9315-2 7 3335 D12 F305 H5
3336 D2 F307 F5
E C 5 RED 2 5 RED 2 5 RED 2 4 9305-4 5 5 RED 2 8 9318-1 1 5 RED 2 4 9303-4 5 5 RED 2 4 9315-4 5
C 3337 D2 F308 F4
E
6 1 6 1 6 1 1 9305-1 8 6 1 5 9318-4 4 6 1 1 9303-1 8 6 1 1 9315-1 8
3338 D1 F325 F10
BLUE BLUE BLUE BLUE BLUE BLUE
3339 D2 F326 F9
GND_HS GND_HS GND_HS GND_HS GND_HS GND_HS 3340 D1 F327 G10
G R B
7
7
3341 D1 F328 G9
3342 E2 F329 H10
F344 F345 F346 3343 D1 F330 H10
F340 F341 F342 F343 3344 D1 F340 D1
3345 D12 F341 D1
B R G
F RED-1 3346 E1
3347 D1
F342 D1
F343 D2
F
GREEN-1
3348 E12 F344 D12
D 3338 3341
3336 BLUE-1
D 3349 E1 F345 D12
3350 E1 F346 D13
3351 E12 F347 G12
9320-1 8
9320-4 5
9320-2 7
6
560R 1K5 390R 3335 3310 3354
3340 3344 3337 3352 E1 F348 G13
9306-4
9306-1
9306-3
9319-1
9319-4
9319-3
390R 1K5 560R 3353 E1 F349 G13
560R 1K5 390R 3345 3311 3357 3354 D13
G 3343 3347 3339
3355 E1 G
3
390R 1K5 560R
560R 1K5 390R GREEN6 GREEN6 2 9304-2 7 3356 E1
3348 3312 3358
3342 3357 D13
3346 3350
RED6 RED6 1 9304-1 8 390R 1K5 560R 3358 E13
560R 1K5 390R 3351 3313 3359
BLUE6 BLUE6 4 9304-4 5 3359 E13
3349 3353
E 560R 1K5
390R 1K5
3314
560R
3360
E 3360 E13
3361 E13
3352 3356 3362 E13
H 560R 1K5
1K5
3315
560R
3361
3363 F13
3364 F13
H
3355 3384
1K5 560R 3365 F13
560R 1K5 3316 3362 3366 F13
3369 3385 3367 G13
VLED1-F VLED1-F 1K5 560R 3368 G13
560R 1K5 3317 3363 3369 F1
3370 3386 F307 F325
BLUE-2 1K5 560R 3370 F1
3331
3301
I 7307 3371 F1
I
10K
10K
560R 1K5 7317 3318 3364
F 3371 3387
BC847BW BC847BW
1K5 560R
F 3372 F1
3334 F308 3302 F326 3373 F1
9317
9325
560R 1K5 3319 3365 3374 G1
3372 3388 1K0 1K0
1K5 560R 3384 E1
3332
3303
3385 F1
10K
10K
560R 1K5 3320 3366
is prohibited without the written consent of the copyright
3304
7305
10K
10K
7315 1K5
BC847BW if VLED < 17V BC847BW 7003 C6
3328 F303 3305 F328 7004 C8
9314
9326
K 1K0 1K0
F347 F348 F349 7005 C11
7305 G4
K
7306 H5
3326
3306
10K
10K
7307 F4
owner.
7315 G9
8
7316 H10
PWM-R1 PWM-R2
9311-4
9311-3
9311-1
VLED1-F VLED1-F 7317 F9
H H 9301 C1
L F304 F329 9302 C1
L
1
GREEN-2 9303-1 C10
3327
3307
7306
10K
10K
7316 9303-3 C10
BC847BW BC847BW
9303-4 C10
3333 F305 3308 F330
9304-1 E10
9316
9327
1K0 1K0 9304-2 E10
GREEN-2 9304-4 E10
3330
3309
10K
10K
9305-1 C6
RED-2
9305-2 C6
M BLUE-2 9305-4 C6 M
PWM-G1 PWM-G2 9306-1 D5
I I 9306-3 D5
9306-4 D5
9307 A6
9308 A6
9309-1 B6
9309-2 B6
N 9309-4 B6
9310-1 B8
N
1 2 3 4 5 6 7 8 9 10 11 12 13
O O
CHN SETNAME
CLASS_NO 1 2008-06-10
3 ??
P 8204 000 8857
2008-08-08 2 2K9
3 P
NAME Peter Van Hove SUPERS. 3 130 3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_632_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 83
A A
1M3A E2
1 2 3 4 5 6 7 8 9 10 1M85 D2
3536 E9
3537 E9
B 3538 E7 B
LED DRIVE 3539 E9
3540 E7
3541 E8
3542 E9
3543 E7
3544 E8
3546 E7
C 3547 E8
3549 F7
C
A A 3550 E8
3552 F7
3553 F8
3555 F7
3556 F8
7006 2 7007 7008 7009
LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 LTW-E500T-PH1 3569 F7
3570 F7
D GREEN-1 4 GREEN 3 4 GREEN 3 4 GREEN 3 4 GREEN 3 3571 G7 D
3572 G7
RED-1 5 RED 5 RED 5 RED 5 RED
3573 G7
6 1 6 1 6 1 6 1
3574 G7
BLUE-1 BLUE BLUE BLUE BLUE
B GND_HS GND_HS GND_HS GND_HS B 3584 F8
3585 F8
7
3586 F8
3587 G8
E 3588 G8 E
3589 G8
3590 G8
2 2 2 3591 G8
7006 A2
7007 A4
7008 A5
7009 A6
F C C F
1M85
1 SPI-CLOCK-BUF
2 SPI-DATA-OUT
G 3
4
SPI-DATA-RETURN
SPI-LATCH G
5 PWM-CLOCK-BUF GREEN-2
6 +3V3
D 7 BLANK-BUF
EEPROM-CS
RED-2 D
8
9 TEMP-SENSOR BLUE-2
10 PROG
11 VLED1
12
H 13
14
VLED2
H
15 16
3536
3538 3541
8 EEPROM-CS
All rights reserved. Reproduction in whole or in parts
560R 1K5
3570 3586
K 560R
3571
1K5
3587
K
560R 1K5
owner.
3572 3588
560R 1K5
G 3573 3589
G
560R 1K5
L 3574 3590
L
560R 1K5
3591
1K5
M M
1 2 3 4 5 6 7 8 9 10
N 1X04
N
REF EMC HOLE
O O
CHN SETNAME
CLASS_NO 1 2008-08-14
3 2008-10-31
P 8204 000 8897
2008-08-14 2 LITEON 2K9
2008-10-31 3 P
NAME Peter Van Hove SUPERS. 1 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_633_090306.eps
090306
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 84
3364
3365
3366
3367
3363
3368
3354
3357
3358
3359
3360
3361
3362
2110 2109
3109
3108
3107
9313
2129 2128
9113
9109
9112
9111
2125
1M83 1M84 1M85
3110
3120
3128
3317
3316
3315
3313
3312
3311
3310
3335
3345
3348
3351
3119
3129 9315
2101 9121
3132
6216
3314
3320
3319
3318
3323
3322
3321
3221
3224
2103
2102
7215
2211
3216
3133
9102
3117
3114
3113
3138 3136
7101
3111
C140
3106 3127
2106 3139
2105
3137
I110
2111
3222
7110 2209 2108
2104
2119
1101 2117
9110
2130
9114
7212 7210
7209
9107
2202
9302
2127
I113
3103
7000
7001
7002
7003
7004
7005
7006
7007
7008
7009
3342 2116
1X03 1X04
I111
9106
3131
3140 3135
7116
3126
1105
I114
3306
3305
3304
3303
3302
3301
3309
3308
3307
3338 3374 3385 3389 I115 2126
2112 3213
3340 3369 3384 3390 3124 3130
3121 3116
3332
7307 3334
3331
3343 3373 3356 3391 2203
9325
9327
3220 3212
9326
2120 9119 2214
7315
7317
7316
2113
7102
9212
3552 3555
3549 3570
3546 3571
3543 3572
3540 3573
3538 3569
3574
9308
3211
3204
3123
9317
3210
3333
3327
3330
2218
3349 3371 3347 3387
2210
7201
2123
7214
3326
3328
3325
3104
9307 2124 3134
3541 3553
3544 3588
3547 3587
3550 3586
3556 3591
3584 3590
3585 3589
2122
3352 3370 3344 3388
9208
3219
3102
2216 2121 3141
3355 3341 3353
9213
3142
3207
7306
3214 2215 2131
9301
3217
9311
3536
3537
3539
3542
3337
7305
9211
9316
2217 9209
9312
9303
9319
9304
3203 3205
3218
3215
9305
9309
9320
9318
9310
9103
3118
9101
2114
9314
9306
9108
2201
3336
2220
2115
3112
2118
9104
3223 2219 3101 3125 3105
I126
F345
F116
F106
F344 F209 F104 I124 F212
F101
F109
F213 F137
F128
F131
F129
F124
F121
F308
F134 F210
F330 F326 F328
F202 F203 I125 F138
F206
F103 F207
F133 F112 F305 F211 F340 F343
F118 F136 F208
F329 F325 F327 F303 F125
F102 F205
F341
F117 F307
F204 F342
F304 F302
18310_553_090309
3104 313 6315.2 090309
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 85
SSB: DC/DC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
2U06 B10 2U0F A5 2U0R G10 2U0V E12 2U10 C14 2U15 B13 2U1B E14 2U55 D4 2U59 E2 2U63 F6 3U09 H9 3U0J B9 3U16 C5 3U1D F6 3U20 D5 3U24 F7 3U74 E9 5U01 B9 5U33 B13 7U03 D3 7U09 E1 FU06 F5 FU0B E14 IU07 E9 IU0P B6 IU11 B6 IU1D G10 IU1T A13 IU56 D3 IU60 E3
2U07 E11 2U0H C9 2U0S F1 2U0W A5 2U11 C14 2U16 E13 2U39 B6 2U56 D4 2U60 E6 2U64 G9 3U0A H10 3U0K E9 3U17 D3 3U1J G14 3U21 E2 3U25 F8 3U75 G10 5U02 A13 6U02 E2 7U05 C8 CU77 G2 FU07 B9 FU0C B14 IU08 B9 IU0S G5 IU12 D7 IU1E F9 IU30 E6 IU57 D3 IU61 D5
A 2U0B H9
2U0D H6
2U0J E9
2U0K F9
2U0T E11
2U0U E12
2U0Y A12
2U0Z B10
2U12 C9
2U14 A12
2U17 E13
2U19 A13
2U50 D7
2U54 C2
2U57 D2
2U58 D3
2U61 E4
2U62 F2
2U65 G8
3U06 B6
3U0F H5
3U0G H6
3U13 C7
3U15 C5
3U18 D5
3U19 D5
3U1M B9
3U1V F1
3U22 E3
3U23 F2
3U30 E6
3U31 G8
3U76 E11
5U00 E9
5U03 C13
5U32 A13
6U03 D5
7U02 B6
7U06 D8
7U08 A6
FU04 E2
FU05 A8
FU08 G14
FU0A E8
FU0E C14
IU06 G9
IU0K D7
IU0N C7
IU0T G9
IU0U E1
IU19 H9
IU1B C9
IU1P B6
IU1R F1
IU31 G9
IU55 C4
IU58 E3
IU59 E3
IU62 F6
IU63 D5
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B B
DC / DC
C A +12VF1
A C
FU05 5U02 RES IU1T
+12VF
10u
RES 22u
5U32 RES
2U0W
2U0Y
2U0F
2U14
2U19
22u
RES 22u
22u
1u0
7U08
5 6 7 8 30R
IU1P 5U33
SI4800BDY
4
1 2 3 12V/3V3 CONVERSION
D VSW
30R D
3U06
3R3
2U39
FU07 5U01 FU0C
B IU11 1n0
10u
+3V3
B
3U1M
2U0Z
2U06
3U0J
22R
22R
22u
22u
220u 25V
2U15
7U02
E 5 6 7 8
E
IU0P
4 SI4800BDY IU08
1 2 3
2U0H
1n0
5U03 FU0E
IU1B +3V3F
10u
RES 100u 4V
RES 100u 4V
C 7U05
C
2U12
2U10
2U11
F F
1n0
3U15 5 6 7 8
IU55 IU0N
4 SI4800BDY
10R
3U16 1 2 3
2U54
3U13
3R3
2u2
10R
2U50
3U18
3U19
G G
3R3
10R
10R
GND-SIG 100n
BAT54 COL
RES 2U56
3U20
RES 6U03
100n
3R3
IU57 7U03
D TPS53124PW D
23
7U06
Φ VIN IU63
2U57
2U58
100n
100n
5 6 78
RES
28
DRVH1
26 4
DRVL1 1 2 3
1
VBST1
15
IU0K
SI4800BDY 12V/1V2 CONVERSION
DRVH2
H 3U21 IU58
3
EN1 DRVL2
17
5U00 FU0B
H
24 27 +1V2-PNX85XX
GND-SIG TRIP1 LL1
16
2U0V
2U0T
14
2U0U
2U07
VBST2
2U16
2U17
4
6U02 RES VO1 +1V2-PNX85XX
3U0K
2U1B
3U74
3U76
12 5
22R
22R
10R
RES
ENABLE-3V3-5V EN2 VFB1
E E
22u
RES 22u
RES 22u
22u
3U22 IU60
2U59
RES
19 11
1n0
2U60
IU07
1n0
FU04
IU0U 8 2
1
2U0J
20 TEST 6
4u7
1n0
7U09 GND-SIG 2 NC 2U61
BC847BW 3 9
RES 3U23
2U62
13
10R
1u0
2U63 3U24
GND
2
All rights reserved. Reproduction in whole or in parts
2U0S FU06
2U0K
1n0
1% 3K3
J F 100n
RES
GND-SIG
3U1D F J
3U1V
3K3
RES
GND-SIG
3U25
10K
IU0S IU06 2U64
K CU77
3n3 K
2U0R
2U65
+1V2-STANDBY
1n0
1u0
owner.
3U31
3U75
1% 470R
4K7
L IU0T L
3U09
RES 2U0B
3U0A
100p
1% 1K0
3U0G
2U0D
3U0F
RES 100p
1% 1K0
47K
22K
IU19
H H
M GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG M
N N
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
O 1X08
REF EMC HOLE
O
CHN SETNAME
CLASS_NO 2 2008-11-21
DC/DC
P 8204 000 8932
TV543 R2 LDIPNX
2008-10-10 3 P
NAME Maelegheer Ingrid SUPERS. 3 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_500_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 86
SSB: DC/DC
1 2 3 4 5 6 7 8 9 10 11 12 13
1M20 A1 5U13 A1
1 2 3 4 5 6 7 8 9 1M95 E1 5U14 A1
1M99 C1 5U15 B1
1U01 E2 5U16 B1
A 2U41 1U03 E2 5U17 F2 A
DC / DC 100p 3U90 IU48 3U37 +3V3
2U21 B1
2U22 D2
5U20 F2
5U21 F2
LIGHT-SENSOR LIGHT-SENSOR 2U23 D2 6U0B E8
2U42 100R 100K RESERVED 2U24 A7 6U0C E8
2U25 B8 6U40 E3
TO 100p 3U91 IU49 2U26 B9 7U0M A9
RC
A LED PANEL
1M20
2U43 100R +3V3 +3V3-STANDBY
+3V3-STANDBY
A 2U27 F7
2U28 F8
7U0N B7
7U0P E7
FU32 5U07 2U29 E8 7U0Q E9
3U3W
3U46
4K7
1 5U10 100p IU51 2U2A E8 7U10 B4
B 3U92
B
2U24
68K
FU30 30R 3
1u0
2
FU31 2U2B E8 7U11 B3
5U11 30R
3 100R 2U2C B1 7U40-1 E3
3U96
3U97
30R 5U12 1
10K
10K
FU33 +3V3-STANDBY RES 7U0M
4 +5V +3V3-STANDBY RES BC847BW 2U30 D2 7U40-2 E4
FU34 5U13 30R 9U06 IU34
5 5U14 2U31 D3 7U41-1 F4
FU35 30R 2U44 IU50 2 +1V2-STANDBY
6
5U15 30R 9U08 2U32 E1 7U41-2 F5
FU36 IU3C
7 30R 3U4A 2U25 FU1F 2U33 F1 7U50 C7
5U16 IU52
8 100p 3U93 7U10 2U34 F1 9U06 A2
3U94
3U95
10K
10K
FU38 30R +5V RES 1K0
RES RES RES 22n 2U35 F1 9U07 B3
2U45 100R IU20 3U41 3U59 2U36 F1 9U08 B5
2U2C
2U26
100n
LED2
1u0
IU53 LED2 3 1
9U07 2U37 C1 CU70 D1
7U0N
C B 2U21 RES
100p
RES
10K 10K
TS431AILT
B
2U40 F3
2U41 A2
CU71 D1
FU10 F1 C
NC
BC847BW IU35
4
1K0 2U42 A2 FU11 F1
REF
is prohibited without the written consent of the copyright
NC
LED1
2U46
100p
A
7U11 LED1
BC847BW 2U45 B2 FU14 C1
10K 10K 2U46 B2 FU15 C2
5 2
2U47 D8 FU16 C1
+12VD
2U48 D8 FU17 C2
3U98 2U49 D7 FU18 C2
1M99 KEYBOARD
FU13 2U37 2U51 D1 FU19 C1
D 1
2
FU19
FU14 1u0
10R FU1H 2U52 D1
2U53 C1
FU1A E1
FU1B E1
D
3 3U35 B6 FU1C E1
4 3U37 A6 FU1D F1
FU16 LAMP-ON-OUT
C 5
6
FU18
FU17 100R 3U55 7U50
LD3985M122
C 3U3V B8
3U3W A8
FU1F B9
FU1G E9
7 BACKLIGHT-OUT
100R 3U56 3U3Y E6 FU1H C4
8 1K0 3U3Z F6 FU20 E1
FU24 BACKLIGHT-BOOST +3V3-STANDBY 1 5 +1V2-STANDBY
9 IN OUT 3U40 E8 FU21 E1
3U64 100R 3U57 IU3T
10 FU15 BACKLIGHT-PWM-ANA-DISP
owner.
3 4 3U41 B5 FU22 E1
11 INH BP 3U42 E9 FU23 E1
2U53
3U65
100p
RES
E 100R
E
1K0
3U58
12
2U52
3U43 E8 FU24 C1
100p
1n0
10n
10n
10n
COM
2U51
3U44 E9 FU25 D1
100p
1-1735446-2
2U47
3U45 E9 FU26 D1
100n
1u0
1u0
2
2U23
2U30
2U31
2U22
BZX384-C27
GND-AUDIO BAS316
RES 220n
3U64 C2 IU35 B8
RES 33K
RES 33K
7U40-2
6U0C
2U2B
3U80
5U08
2U29
3U44
3U45
220u
220n
3U65 C2 IU36 F7
10K
BC847BPN(COL)
2U32
4 3U66 D1 IU37 F8
IU41
VSW 3U67 D2 IU38 E7
10n 1U03 +12VF
1M95 5 3U80 E3 IU39 F9
G E 1
FU1A
+3V3-STANDBY
3.0A T 32V
3
3U60 FU39
E 3U81 E3 IU3B E8 G
3U81
FU1B
10K
2 IU42 ENABLE-3V3-5V
IU3B 3U42
3U82 E4 IU3C B8
FU20 3U83 E4 IU3T C8
BZX384-C8V2
3 22K +12V
3U61
RES
10K
FU23 3U84 F2 IU40 E3
10K RES
4 IU38 2K2
6U40
3U82
3U83
FU1C
6K8
2U2A
7U0P
3U43
100K
FU22
1u0
6 2N7002 3U86 F4 IU42 E4
6
3U3Y
3U40
3U47
68R
68R
1K0
7 FU21 3.0A T 32V 7U40-1 7U0Q 3U88 F3 IU43 E3
IU40 FU40
3
8 FU1D BC847BPN(COL) DETECT-12V BC847BW 3U89 F3 IU44 F3
FU10 +AUDIO-POWER 2
9 3U90 A3 IU45 F4
3U84
3U85
3U86
FU11 1 1 IU37
1K0
10K
3K3
10 3U91 A3 IU47 F3
2U27
1u0 RES
FU12 3
33p
IU36 3U92 A3 IU48 A4
2
H 11 IU44
H
2U40
3U3Z
2U28
220p
1-1735446-1 +1V2-STANDBY 5
10K
7U41-2 3U94 B3 IU50 A5
* 5U06 BC847BS(COL)
22K 3U95 B3 IU51 A3
2U33 RES
IU45
2U34 RES
2U36
3U63
RES
100p
100p
*
10K
7U41-1
10n
10n
3U98 C3 IU54 F5
30R BC847BS(COL) 2
5U20 5U06 F2
* 1 5U07 A1
30R 5U08 E7
2K9 supplies
5U21 5U10 A1
*
I 30R
5U11 A1
5U12 A1 I
1 2 3 4 5 6 7 8 9
CHN SETNAME
CLASS_NO 2 2008-11-21
DC/DC
J 8204 000 8932 J
TV543 R2 LDIPNX
2008-10-10 3
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_501_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 87
SSB: DC/DC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A 2U00 A12 2U04 D3 2U13 E3 2U66 B6 2U83 G7 2U8E A10 2U8K D10 2U8T H6 2U90 A12 3U03 C5 3U08 D3 3U14 B6 3U2C H6 3U2H D9 3U3F E11 5U04 D9 5U19 C11 6U01 D2 7U0D-2 C7 FU00 E2 FU87 D8 FU90 E5 IU03 C3 IU10 D3 IU16 C7 IU2A B6 IU2V C9 IU33 F8 A
2U01 A4 2U05 D2 2U18 E6 2U67 C7 2U8A A5 2U8F B12 2U8M D10 2U8U C8 3U00 C5 3U04 C3 3U10 E2 3U26 G9 3U2D H6 3U32 E6 3U3G F11 5U05 B9 5U30 A11 6U09 B11 7U0H-1 A6 FU0D F13 FU8B A14 IU00 C4 IU04 D5 IU13 D3 IU25 D6 IU2C E5 IU2Y F9 IU82 C9
2U02 C4 2U08 E6 2U20 F8 2U80 C4 2U8C B10 2U8G D10 2U8Q E9 2U8V C8 3U01 C5 3U05 C5 3U11 E7 3U27 G10 3U2F F10 3U33 F8 3U3J B9 5U09 A11 5U31 A11 7U01 C3 7U0H-2 B6 FU80 B14 FU8C B8 IU01 C3 IU05 D3 IU14 B6 IU28 C7 IU2D D5 IU2Z E9 IU85 E9
2U03 D2 2U09 E4 2U38 F8 2U81 C2 2U8D B10 2U8H D10 2U8R E9 2U8Y F9 3U02 C6 3U07 D2 3U12 E8 3U28 C6 3U2G B8 3U3A B12 3U3N D9 5U18 B11 6U00 C5 7U0D-1 B7 CU25 G2 FU85 D14 FU8D B14 IU02 C5 IU09 E8 IU15 E6 IU29 B6 IU2T G7 IU32 D6
B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 B
DC / DC FU8B
+12VF2
C A 5U09 RES
+12V A C
10u
5U30 RES
220u 25V
2U90
2U00
RES
1u0
30R
2U8A
2U8E
22u
22u
220u 25V
7U0H-1 5U31
2U01
RES
7 8
IU2A 30R
2 SI4936BDY
D 12V/5V CONVERSION D
1
FU8D
3U14
3R3
+5V5-TUN
2U66
B IU14 1n0
7U0H-2
FU8C 5U05 SS36 FU80
+5V B
5 6 10u 6U09
220u 25V
3U2G
2U8C
2U8D
2U8F
3U3J
1%
4 SI4936BDY
22R
22R
RES
22u
22u
5U18 RES
3
E E
3U3A
2K7
IU29 7U0D-1 30R
7 8
3U00 5U19
IU82
IU00 IU28
2 SI4936BDY
10R 30R RES
2U8V
1
1n0
3U01
3U28
3R3
2U81
2u2
10R 2U67
IU2V
C IU01 2U02 IU02
IU16 1n0
7U0D-2 5 6 C
2U8U
F F
1n0
3U04
3U02
3U03
3R3
10R
10R
GND-SIG1 100n
BAT54 COL
4 SI4936BDY
RES 2U80
3U05
RES 6U00
100n
3R3
3
IU03 7U01
TPS53124PW
23
Φ VIN
IU04
RES 2U03
2U04
100n
100n
28
DRVH1
26
IU25
12V/1V2 CONVERSION
DRVL1
1
VBST1
G 3
EN1
DRVH2
DRVL2
15
17 G
D GND-SIG1
3U07 IU05
24
TRIP1 LL1
27
16
FU87 5U04
FU85
+1V2-PNX5100
D
20K BAT54 COL IU10 LL2 10u
14
VBST2
3U2H
3U3N
4
22R
22R
6U01 RES VO1 +1V2-PNX5100
ENABLE-3V3-5V 12 5 IU2D
EN2 VFB1
2U8M
2U8H
2U8K
2U8G
3U08 IU13
10R RES
2U05
RES
19 11
1n0
3U3F
H GND-SIG1 18K
21
VFB2
10
22
IU2C IU85
H
RES 22u
22u
22u
RES 22u
V5FILT VREG5 4K7
2U8Q
2U08
1n0
1n0
FU00
8 2
1
2U09
20 TEST 6
4u7
GND-SIG1 2
NC 9 IU2Z
3U10
2U13
13
10R
1u0
E 2U18 3U11
E
GND
3U12
10K
PGND +5V5-TUN
2U8R
1n0
GND-SIG1 GND-SIG1 3n3 IU15 22K
RES
25
18
FU90
I GND-SIG1
I
IU09
2U20
GND-SIG1
3n3
2U8Y
1u0
2U38
is prohibited without the written consent of the copyright
1n0
All rights reserved. Reproduction in whole or in parts
3U3G FU0D
IU2Y SENSE+1V2-PNX5100
J F IU33 120R 1%
F J
3U2F
1% 470R
3U33
4K7
3U26
CU25
RES 2U83
3U27
100p
6K8
1% 1K0
K K
IU2T
GND-SIG1
owner.
L L
3U2C
3U2D
2U8T
1% 470R
100K
RES 100p
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
N N
O O
CHN SETNAME
CLASS_NO 2 2008-11-21
DC/DC
P 8204 000 8932
TV543 R2 LDIPNX
2008-10-10 3 P
NAME Maelegheer Ingrid SUPERS. 3 130 3 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_502_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 88
1T01 A5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A 1T11 C5
1T21 E5
A
1T25 C10
FRONT-END 1T01
UV1316E 16 17
2T10 B3
TUNER 2T11 B3
18 19 2T12 C2
RF-IN 2T13 C12
+33V_TUN
14 13 2T14 C2
MT MT 2T15 C10
AGC
ADC
SDA
B B
SCL
+5V
15 12
NC
IF2
IF1
TU
AS
A A 2T16 C13
2T17 C10
10
11
2T18 C13
1
2
3
4
5
6
7
8
9
TUN-P1 TUN-P11
2T19 F10
TUN-P2 TUN-P10
TUN-P3 TUN-P9 2T20 G10
TUN-P4 TUN-P8 2T21 E11
TUN-P5 TUN-P7 2T22 B7
TUN-P6 2T23 D5
C RESERVED
RF-AGC 9T10
IT03
IT11 9T11
AT10
B-IF-_N-IF-
2T25 B7
2T26 E5
C
TUN-P1 TUN-P11
5T10 IT12 2T27 D7
3T10 IT09
TUN-P3 9T12 +VTUN TUN-P9 2T28 E5
100R 3T13 IT04 2T35 30R 2T29 E7
FT23 FT22 TUN-SCL
B +33VTUN
3T11 3T12
+VTUN
TUN-P4
47R 18p
2T25
B 2T35 B5
2T36 B5
100R 100R
BZX384-C33
BZX384-C33
IT05 220n
IT10 IT13 2T37 C7
3T14 2T36
6T10
6T11
2T10
2T11
220n
220n
D TUN-SDA
47R 18p
+5V-TUN-PIN 9T13 TUN-P7 2T39 H9
3T10 B2
D
TUN-P5 9T40 TUN-P10
3T11 B2
2T22 IT0D IT16 IT17
TUN-P8 9T14 3T12 B2
RES
3T13 B5
4n7
2T37 2T13 3T14 B5
TUN-P6 +5V-TUN 3T15 E5
IT08 5T11 1T11 4n7 10n 3T16 E5
HD1816AF/BHXP
E +5V-TUN 3T17 E11 E
RES
9T43
9T31
RES
TUNER
C 30R
2T12 FT17 C 3T18 E11
1
+5V-TUN-PIN RF-IN 7T10 3T19 E11
XTAL_OUT
UPC3221GV-E1
DC_PWR
14 13 3T22 G9
IF_OUT1
IF_OUT2
RF_AGC
22u
VCC
2T14 MT MT IT19 2T15 IT20 IT21 2T16 3T98 E11
IT22
SDA
NC1
NC2
1T25 2 INPUT1 OUTPUT1 7
SCL
+5V
15 12 IF-
AS
B-IF-_N-IF- 1 5 5T10 B7
100n I O1 10n 10n
B-IF+_N-IF+ 2 4 IT23 IT24 5T11 C2
IGND O2 2T17 2T18 IT25
10
11
3 INPUT2 OUTPUT2 6 IF+ 5T12 F11
1
2
3
4
5
6
7
8
9
TUN-P1 TUN-P11 3 IT26
GND 10n 10n 6T10 B2
F TUN-P2 TUN-P10
F
GND1
GND2
OFWX6966M 4 VAGC
6T11 B2
TUN-P3 TUN-P9 AGC CONTROL
TUN-P4 TUN-P8 36M125 7T10 C11
9T10 B5
9T44
RES
TUN-P5 TUN-P7
TUN-P6 9T11 B7
5
D IT30
D
RES
9T32
TUN-P1 9T18 ANTENNA-SUPPLY 9T12 B5
AT11
IT28 9T21 B-IF+_N-IF+
2T23 9T13 B7
TUN-P10
9T14 C10
4n7
+5V-TUN-PIN 9T23 TUN-P9 IT32 9T18 D5
G RF-AGC
TUN-P3
9T20
2T27
TUN-P2
9T22
RES
9T20 D5
9T21 D7
G
3T15 IT14 2T26 4n7 9T22 D10
9T24
RES
TUN-SCL
9T41 TUN-P5 9T23 D7
47R 18p
TUN-P6 9T24 E9
3T98
3T16 2T28 2T29 +5V-TUN
9T25 F5
TUN-SDA TUN-P4 10K 9T27 G5
47R
E TUN-P7
18p 4n7
3T17 RES E 9T29 G7
9T30 G5
H IF 1T11 IS USED THEN 2T25 AND 9T11 ARE ALSO STUFFED
IF-AGC
6K8
+3V3A
9T31 C13 H
1T21 9T32 D13
220K
2T21
3T18
3T19
HD1816AF/BHXP
22K
22n
9T33 F11
TUNER 9T34 G11
9T40 B7
RF-IN
XTAL_OUT
9T41 E7
DC_PWR
14 13
IF_OUT1
IF_OUT2
RF_AGC
MT MT
9T43 C10
SDA
NC1
NC2
SCL
+5V
15 12 9T44 D10
AS
I B-IF-_N-IF-
2T19 IT34
PDP
9T45 G7
AT10 B7
I
10
11
1
2
3
4
5
6
7
8
9
F TUN-P1 TUN-P11
10n
F AT11 D7
RES
9T33
TUN-P2 TUN-P10 FT17 C2
TUN-P3 TUN-P9 FT18 G5
5T12
820n
TUN-P4 TUN-P8
FT21 H9
is prohibited without the written consent of the copyright
TUN-P5 TUN-P7
FT22 B3
All rights reserved. Reproduction in whole or in parts
IT15 TUN-P6
RF-AGC 9T25 FT23 B2
J TUN-P2 9T45
9T29
PDN
TUN-P8 B-IF+_N-IF+
2T20
PDN
IT03 B5
IT04 B5
J
TUN-P3 9T27 ANTENNA-SUPPLY IT36
10n IT05 B1
FT18 IT08 C1
RES
9T34
IF-AGC 9T30
TUN-P9 IT09 B5
IT0D B7
G IF 1T21 IS USED THEN 2T23,2T25,3T14, 3T15, 9T13, 9T11 AND 9T21 ARE ALSO STUFFED +5V-TUN
G IT10 B5
IT11 B7
IT12 B7
K IT13 B7 K
3T22
IT14 E5
6K8
IT15 F5
owner.
IT16 B9
RF-AGC FT21 IT17 B11
IT19 C10
2T39
IT20 C11
22n
IT21 C12
L H H IT22 C13
IT23 C11
L
IT24 C12
IT25 C13
IT26 D10
IT28 D7
IT30 D9
IT32 D11
M IT34 F11
IT36 G11
M
I I
N N
1 2 3 4 5 6 7 8 9 10 11 12 13 14
O O
CHN SETNAME
CLASS_NO 2 2008-11-21
FRONT-END
P 8204 000 8929
TV543 R2 LDIPNX
2008-10-10 3 P
NAME Randal De Keyzer SUPERS. 3 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_503_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 89
SSB: Demodulator
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
1T50 A5 AT50 A4
A 1 2 3 4 5 6 7 8 9 10 11 12 13 2T24 G5 AT51 B4 A
2T50 A4 FT20 E6
2T51 A4 FT24 C5
2T52 A4 FT25 C3
DEMODULATOR 2T53 B3 FT50 B8
2T54 B4 FT51 C3
2T55 B3 FT52 C3
2T50 IT50 2T56 B4 FT53 C3
B 12p
+3V3E +1V2A
2T57 B3
2T58 B4
FT54 C3
FT55 F7
B
A A
27M
2T59 B3 FT56 G8
1T50
+3V3A +3V3D +3V3 +1V2 +3V3
2T60 C8 FT57 G6
2T51 2T61 E10 FT58 H7
IT51
AT50 2T62 D12 FT59 I7
2T52 12p 7T50
3T50 2T63 D9 FT60 C10
37
42
52
36
46
18
26
53
16
27
56
3T80
3T81
3T82
DRX3926K-XK-A2
RES 10K
RES 10K
RES 10K
8
2
IF+
3T51 2T64 F6 FT61 D11
VDDAH_AFE1
VDDAH_CVBS
VDDAH_OSC
VDDAL_AFE1
VDDAL_AFE2
220R 100p IT53 VDDH VDDL
5T50
2T59
2T53
680n
C 2T65 G6 FT62 E11
C
2p2
22p
10K
AT51 49
3T52 2T54 IT55 XI 2T66 G6 FT63 I6
IF- 5 FE-SOP
50
MSTRT
6
2T67 G7 IT50 A5
220R 100p XO MERR FT50 2T68 G7 IT51 A5
3T53 IT56 2T55 IT57 Φ MCLK
9 FE-CLK
PDP 40 DEMODULATOR 10 FE-VALID 2T69 G7 IT53 B5
MVAL
B 560R 10n
2T56 RES 39
0
11 FE-DATA0
B 2T70 G7 IT55 B4
470R
3T54
12 IT58 FE-DATA1
100n 1 2T71 G8 IT56 B3
IT60 47 13 IT59 FE-DATA2
3T55 2T57
48
P
PD
2
14
2T72 G8 IT57 B4
PDN N 3 FE-DATA3
2T73 H6 IT58 B10
D RESET-SYSTEM
560R IT61 10n
2T58 RES
100n 32
RSTN
MD
4
5
19
20 IT62
FE-DATA4
FE-DATA5 2T74 H7 IT59 B9 D
21 IT63 FE-DATA6 2T75 H6 IT60 B4
6
31 22 FE-DATA7 2T76 H7 IT61 B3
SAW_SW 7
IT65 3T57 IT66 2T77 I6 IT62 B9
SCL-SSB SCL-SSB 23 33 RF-AGC
IT67 SCL1 RF_AGC 2T78 I6 IT63 B9
SDA-SSB SDA-SSB 100R 3T58 24 I2C 34 IF-AGC
SDA1 IF_AGC
IT68 100R +3V3 3T59 IT69 2T79 I6 IT65 C3
FT24
9T15 RES TUN-SCL TUN-SCL 9T70 4K7 62 44 2T60 IT70 3T60 2T80 I7 IT66 C4
SCL2 SIF +5V-TUN-CVBS
9T16 RES TUN-SDA TUN-SDA 9T71 61 I2C 100n 2T81 I7 IT67 C4
E C
SDA2 18K
E
470R
C
3T62
FT25 +3V3 3T61 43
FT51 4K7 59
CVBS
4
2T82 I7 IT68 C3
JTAG-TCK-DRXK TCK IT73 2T83 E4 IT69 C8
FT52 60 64
JTAG-TDI-DRXK TDI DA 7T51-2
FT53 57 63 5
BC847BPN(COL)
2T84 E3 IT70 C9
JTAG-TDO-DRXK TDO I2S CL 3T63
FT54 58 1 7T51-1 RES 2T85 E2 IT73 C9
JTAG-TMS-DRXK TMS WS
BC847BPN(COL) 3
10K RES 3T50 A2 IT75 D9
3 3T66-3 6
4 3T66-4 5
7
4 29
3T51 A10 IT76 D8
3T66-1
3T66-2
GPIO1 VSYNC 3T64 3T65 FT60
30
RES 10K
RES 10K
RES 10K
RES 10K
GPIO2 IF-P
3T52 B2 IT77 D9
150R IT75 150R
66 84 3T53 B2 IT79 D3
2T62
F 67 85 3T54 B3 IT80 E9
F
3p3
68 86 RESERVED 3T55 B2 IT81 E10
+3V3 +3V3 +3V3 +3V3 69 87
70 88
3T56 D11 IT83 E9
ANTENNA-CTRL
3T70 3T57 C3 IT84 E2
D +3V3
3T67
71
72
89
90
100R
D 3T58 C4 IT85 E3
73 91 FT61 3T59 C4 IT86 F6
4K7 3T56
74 92 CVBS4 3T60 C9 IT88 F6
VIA VIA +5V-TUN-CVBS
75 93
IT79 ANTENNA-SUPPLY 68R 3T61 C4 IT89 F3
BZX384-C6V8 76 94 IT76 IT77
+5V-TUN 2T63 3T71 3T62 C9 IT90 F3
G 77 95
3T63 C9 IT91 F4 G
6T50
2T83
100n
78 96
22u 18K
470R
3T72
79 97 IT96 1 3T64 C9 IT93 G2
3T73
150R
2T61
3T74
80 98 4 7T53-1
22u
3T65 C9 IT94 G3
VSSAH_CVBS
IT80
VSSAH_AFE1
VSSAL_AFE1
VSSAL_AFE2
VSSAH_OSC
81 99 6 7T52-2 2 RES
100R 3T66-1 D4 IT95 G3
2T84
100n
GND_HS
83 101 3T75 2 6 3T66-2 D4 IT96 E11
7T52-1
10K
BC847BPN(COL) 3 3T66-3 D3 IT97 E11
IT98 VSSH VSSL
E +5V-TUN 3T76
1
3T77 IT81 FT62
+5V-TUN-CVBS
E 3T66-4 D4 IT98 E5
2
4
38
41
51
35
45
7
17
25
54
3
15
28
55
65
9T63 CVBS-TER-OUT 3T67 D4
FT20
H +12V
3T68 IT84
1 7T56
150R IT83 180R
3T95 3T78 IT97 4
3T68 E2
3T69 E3
H
150R
3T79
BCP56 7T53-2
4K7 3T69 3T70 D9
100K
3T83
5 RES
3
IT85 3T71 D9
22n
2R2
9T64 3 3T72 E9
6T51 3T84 FT55
IT86
9T62 +5V-TUN-CVBS
3T73 E11
BAS316 2R2 +1V2-PNX85XX 3T74 E12
7T54
+12V RESERVED 3T75 E9
220R
220R
3T86
3T87
LD1117DT12
I 7T55-1 +3V3
IT88
3
IN OUT
2 +1V2
3T76 E9
3T77 E9
I
8
F IT89 3 LM393PT
1 3T88 COM F 3T78 E11
3T79 E12
RES 100n
2T64
IT90 2 IT91 RES
10K
3T80 A9
4
1
3T81 A9
3T89
3T90
3T91
is prohibited without the written consent of the copyright
27K
27K
6K8
3T82 A9
All rights reserved. Reproduction in whole or in parts
3T83 E3
3T84 F3
J +1V2
5T51
FT56
+1V2A 3T86 F3 J
600R 3T87 F3
3T88 F5
100u 4V
2T65
2T66
2T67
2T68
2T69
2T70
2T71
2T72
100n
100n
100n
100n
100n
100n
2u2
+12V 3T89 F3
3T90 F3
G G
2T24
2u2
7T55-2 3T91 F5
IT93 3T92 IT94
8
2K7 3T95 E9
30R
5T50 B3
3T94
4K7
2T73
2T74
100n
5T51 G7
2u2
owner.
RESERVED 5T52 G6
5T53 H6
5T54 I7
5T53
5T55 I6
FT58
L H +3V3
30R
+3V3D
H 6T50 E3
6T51 F2
L
7T50 A6
2T75
2T76
100n
2u2
7T51-1 C9
7T51-2 C10
7T52-1 E9
7T52-2 E10
FT59
5T54 7T53-1 E11
+3V3 +3V3A
7T53-2 E11
M 600R
7T54 F7 M
2T77
2T78
2T79
2T80
2T81
2T82
100n
100n
100n
7T55-1 F4
2u2
2u2
2u2
7T55-2 G4
I I 7T56 E3
9T15 C1
9T16 C1
5T55 FT63 9T62 F6
+5V-TUN +5V-TUN-CVBS 9T63 E11
N 30R 9T64 F6
9T70 C2
N
9T71 C2
1 2 3 4 5 6 7 8 9 10 11 12 13
O O
SETNAME
CLASS_NO 2 2008-11-21
FRONT-END
P 8204 000 8929
TV543 R2 LDIPNX
2008-10-10 3 P
NAME Randal De Keyzer SUPERS. 3 130 2 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_504_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 90
27M
2HF0
1HF0
7H00-6
22p
PNX85439EH/M2/24182 3H04 B11 IH16 F5
STANDBY 3H05 B11 IH17 G5
W1 3H06 C11 IH18 I4
I
2HF1
C C
22p
XTAL 3H07 C11 IH19 F4
W2 AJ1 SPI-CLK
O CLK 3H08 C11 IH20 F7
AK3 SPI-CSB
CSB 3H32 3H10 B2 IH21 I12
W3 SPI AK1 SPI-SDI SPI-SDI +3V3-STANDBY
VSS_XTAL SDI
AJ4 SPI-SDO 3H12 C12 IH26 H4
B 3H13
3H10
RES
10K
BOLT-ON-TS-ENn
RESET-NVM
BOLT-ON-TS-ENn
RESET-NVM
IHW1
IHW3
AC2
AC1
0
SDO
AL5 3H65 100R SCL-UP-MIPS SCL-UP-MIPS
10K
3H02 RES B 3H13 B1 IH32 C10
3H14 RES
1 SCL
3H66 100R
3H14 B2 IH33 H7
10K RESET-PNX5100 RESET-PNX5100 IHW4 AB3 MC AK5 SDA-UP-MIPS SDA-UP-MIPS 4K7 3H03 RES
+3V3-STANDBY 2 SDA 3H15 B1 IH34 G8
3H15 RES 10K RESET-ETHERNET RESET-ETHERNET IHW5 AB2
3 LED1 RES 3H04 4K7 3H16 B2 IH35 H7
10K 3H16 UART-SWITCH UART-SWITCH IHW2 AB1 P0 AJ3 3H67 100R LED1
4 0
3H17 3H68 100R 3H17 B1 IH36 H7
D RES
10K 3H19
10K WP-NANDFLASH
RESET-AUDIO
WP-NANDFLASH
RESET-AUDIO
IHW6
IHW9
AD2
AD1
5
6
PWM
1
AJ2 LED2 LED2 10K
10K
3H05
3H19 B2 IH37 C10 D
3H20 4K7 AUDIO-MUTE AUDIO-MUTE IHWA AC5
7 3H69 IH15 3H06 3H20 C1 IH91 H4
10K 2H00 AE2 PSEN PSEN
3H39 FHC3 PSEN 3H21 C2 IH92 F9
+3V3-STANDBY 1n0 RC-UP RC-UP AF2 IH32
0 3H54 100R ALE 10K 3H07
3H42 RES 10K REGIMBEAU_CVBS-SWITCH REGIMBEAU_CVBS-SWITCH AF1 AE3 ALE 3H22 C13 IHC1 H12
3H46 1 ALE +5V +3V3-PER +3V3-PER
10K CEC-HDMI CEC-HDMI AG4
2 P1 100R 3H56 IH37 3H08 10K 3H23 C1 IHC2 G12
3H48 27K SUPPLY-FAULT SUPPLY-FAULT AG3 AF4 EA EA 3H24 C2 IHD0 F12
3 EA
10K 3H51 SDM SDM AG2
3H25 C13 IHW1 B4
E C 3H21 10K
7
RESET_IN
AF3
100R
RESET-STBY
10K
C 3H26 C1 IHW2 B4
E
3H25
RES IHWB AC4
10K
MHP-SWITCH MHP-SWITCH 0
3H23 10K EJTAG-DETECT EJTAG-DETECT IHWC AC3 3H27 C2 IHW3 B4
+3V3-STANDBY 3H24 RES 1 +3V3-STANDBY
10K LAMP-ON LAMP-ON IHWD AE1
2
3H28 C1 IHW4 B4
4K7 RES
3H26 10K STANDBY STANDBY IHWF AD5 IH09 3H30 D2 IHW5 B5
3
3H12
3H22
10K RES 3H27 DETECT1 DETECT1 IHWG AD4 P2
3H31 D1 IHW6 B4
4
1
4K7
3H28 RES 10K DETECT2 DETECT2 IHWH AD3 7H03
5 BC847BW 3H32 B11 IHW9 B4
10K 3H30 POWER-OK POWER-OK IHWM AE5
6 3H36 D2 IHWA C5
100n
2H10
3H31 10K IHWN AE4
RES
ENABLE-3V3 ENABLE-3V3 7
10K 3H39 C2 IHWB C4
3H58
2
+3V3-STANDBY RXD-UP RXD-UP AG1 3H41 H6 IHWC C4
0 UA_RX FHD2
3H60
F 10K TXD-UP TXD-UP AH5
1 UA_TX 3H42 C1 IHWD C4 F
8
10K BOLT-ON-IO AH4 7H02 9H05 LAMP-ON
3H36 RES 2 3H43 H7 IHWF C5
BOLT-ON-IO AH3 P3 M25P05-AVMN6 RES
D IH02 AH2
3
IH00 VCC IH01 LAMP-ON-OUT D 3H44 I4 IHWG C4
Φ
10K 4
AH1
5 SPI-SDO 5
D Q
2 SPI-SDI 3H46 C2 IHWH C4
3H64 RES
RESET-SYSTEM AN3
IH03
6
512K 3H48 C1 IHWM D4
RESET-SYSTEM 0 SPI-CLK C FLASH 3H51 C2 IHWN D5
AV2-BLK AN2 IH06
10K 1 3H52 I13
AV1-BLK AP2 CADC SPI-CSB 1
2 S 3H53 I13
KEYBOARD AP1 IH07
3H70 KEYBOARD 3
3H54 C7
G 100K 2H01
LIGHT-SENSOR
AV1-STATUS AK2
4
SPI-WP 3
W
3H56 C7 G
AV2-STATUS AK4 P6 7
5 HOLD 3H58 D2
3H00 100n 3H60 D1
SPI-PROG SPI-PROG +3V3-STANDBY VSS
3H01 10K SPI-WP SPI-WP 3H64 D2
3H65 B7
4
E 10K
+3V3-STANDBY
+3V3-STANDBY +3V3-STANDBY E 3H66 B7
3H67 B7
9H25 RC
3H68 B7
H RC-UP
3H69 C7 H
3HD4
2
1
9H26
10K
* HOTEL TV * RC
3H78-2
3H78-1
9H14
3H70 E2
10K
10K
RC-OUT FHD0
9H27 * RC-UP 7HD0 RESET-STBY 3H72 G7
RC-IN NCP303LSN30
3H78-1 E6
7
8
IH92 FHD1 2
IH20 INP 3H78-2 E5
3 DETECT1 DETECT2 1 IHD0 1
OUTP 3H78-3 H4
5
IH14 CD
6 1 7H14 NC GND 3H78-4 H4
PDTC114EU 3H86-1 F4
+3V3 3H86-4 3H86-3 3H86-2 IH19
I 4 5 6 3 2 7 2 7H16-1 2
3H86-2 F4 I
3
F F
2HD0
1 3H86-1 8
9H15
100n
BC847BS(COL)
RES
10K 10K 10K 3H86-3 F3
1
10K
3H86-4 F2
3H87-1 I2
BAS316
6HW2
1u0 3H87-4 I4
All rights reserved. Reproduction in whole or in parts
3 3H92-1 G4
3H92-2 G4
J +1V2-PNX85XX
6
3H92-3
3
IH04
5 7H16-2 3H92-3 G3 J
7 3H92-2 2
BC847BS(COL)
10K
4 RES 3H92-4 H3
10K
3H72
4K7
IH17 3HC2-4 H13
10K
2 3HC2-2 7
K 9H13
6HW2 F5 K
10K
9H28
RES
7H00-6 A5
6 7H11 FH09 7H02 D10
RESET-NVM FHC6
NCP303LSN30 8 3HC2-1 1 BC857BW
owner.
BC847BS(COL) 1
10K 10K 6H10 IH35 OUTP
1 5 7H14 F6
10K
CD 2HC0 RES
4 3HC2-4 5
NC GND 7H16-1 F5
H +3V3-PER IHC1
H
10K
100n 7H16-2 G5
L 7HC3
7H93-1 H5 L
4
3
M24C64
8
IH91 IH08 7H93-2 I5
3 3HC2-3 6
2H12
3H43
2H11
100n
100n
Φ
3K3
7HC3 H12
5 3H78-4 4
10K
(8Kx8) 7 7HC4 H12
10K
WC
EEPROM 3H52 FHC1 7HD0 E12
1 6 SCL-UP-MIPS
7H93-2 IH21 0 SCL 9H05 D13
2 100R 3H53
BC847BS(COL) 1 ADR FHC2 9H13 G8
3 3 5 SDA-UP-MIPS
2 SDA 9H14 E11
+5V 3H87-1 10K 10K 10K 100R
IH18 9H15 F11
M M
4
1 8 5
7 3H87-2 2 3 3H87-3 6 5 3H87-4 4 9H25 E3
10K
4
9H26 E3
I FHC7
I 9H27 E3
3H44
10K
9H28 H13
MAIN NVM FH09 H12
FHC1 H13
FHC2 I14
FHC3 C5
N FHC6 H11 N
1 2 3 4 5 6 7 8 9 10 11 12 13 14
O 1X03
EMC HOLE
O
CHN SETNAME
CLASS_NO 2 2008-11-21
STANDBY CONTROLLER
P 8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10 3 P
NAME Randal De Keyzer SUPERS. 16 130 1 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_505_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 91
A A
B
1H11 C2 2H06 C3 2H07 D3 3HF3 A3 6HF0 B3 7HF2 B3 FH00 C2 FH01 D2 FH08 D3 IH93 C2 IH94 C3 IH95 D2
B
1 2 3 4
C C
PNX8543 : DEBUG
is prohibited without the written consent of the copyright
All rights reserved. Reproduction in whole or in parts
A +3V3-PER
A
D D
3HF3
330R
SML-310
6HF0
owner.
E B RESET-SYSTEM 7HF2
BE
PDTC114EU
TSTPOINT
FOR DEBUG
SKHUBHE010
SPI-PROG
1H11
IH94
GND TSTPOINT
G
FOR DEBUG
G
4
H H
1 2 3 4
I I
CHN SETNAME
CLASS_NO 2 2008-11-21
18310_506_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 92
3H09 C6
1 2 3 4 5 6 7 8 9 3H11 C1
A 3H33 C6
3H37 D4
A
PNX8543 : CONTROL 3H38 D5
3H45 D4
3H49 E4
3H50 E4
A +3V3-PER
A 3HF9 A3
3HFY C1
3HP2 C4
B 3HP3 B1 B
3HF9
3HP4 B1
10K
3HP6 B1
3HP8 C1
3HPA C1
3HPB C1
7H00-8 3HPC C1
PNX85439EH/M2/24182
3HPD E2
CONTROL 3HPE E2
C B IHF4 AP27
BL_PWM SCL 1
SDA 1
F33
H33
SCL1
SDA1
B 3HPF E2 C
IHFB 3HPG E2
RESET-SYSTEM AN28
RESET_SYS
+3V3-PER D32 SCL2 3HPH E2
SCL 2
is prohibited without the written consent of the copyright
3H33
10K 3H11 U4
15K
IRQ-PCI IRQ-PCI GPIO_2
10K 3HP8 IRQ-CA IRQ-CA IHF7 L34 3HPT F4
+3V3-PER GPIO_3
C 10K
10K
3HPC
3HPL
RXD-MIPS
TXD-MIPS
RXD-MIPS
TXD-MIPS
L32
L31
GPIO_4
GPIO_5
DM
DP
AN16
AP16
USB20-DM
USB20-DP
USB20-DP
C 3HPU F2
3HPV F4
IHF6 V2 AL16 USB-OC 3HPW B3
GPIO_6 USB FAULT
IHF8 V3 AK16
GPIO_7 PWR_EN 3HP2 FH03 7H00-8 B3
3H09
IHF9 V4 AM16
15K
GPIO_8 RREF 9H17 D3
IHFA V5
GPIO_9 12K 1%
+3V3-PER
FH03 C5
owner.
3HPD 3H49
SCL1 SCL-UP-MIPS SCL-UP-MIPS +3V3-PER
3HPE 100R 4K7 3H50
E SDA1
100R
SDA-UP-MIPS SDA-UP-MIPS
4K7
E
G SCL2
3HPF RES
100R
SCL-UP-MIPS G
RES 3HPG
SDA2 SDA-UP-MIPS
100R 3HPH FH04 3HPK
SCL3 SCL-SSB SCL-SSB +3V3-PER
3HPJ 100R FH05 1K5 3HPM
SDA3 SDA-SSB SDA-SSB
100R 1K5
3HPS FH11 3HPT
SCL2 SCL-SET SCL-SET +3V3-PER
H SDA2
3HPU 100R
SDA-SET SDA-SET
FH12 4K7 3HPV
H
F 100R 4K7 F
I 1 2 3 4 5 6 7 8 9 I
CH N SETNAME
CLASS_NO 2 2008-11-21
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_507_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 93
A A
2HF5 D7
1 2 3 4 5 6 7 8 2HF6 D7
2HF7 D7
3HES-1 C5
3HES-2 B5
D 10n
2HF6
D
7HF1 100n
G CY2305S
G
6
PCI-CLK-OUT
3HFG
PCI-CLK-ETHERNET
Φ VDD
ZERO 3
2HF7
10R 1
DELAY
10p 3HFK
BUFFER 2
2 PCI-CLK-PNX8535
3HFH PCI-CLK-PNX5100 3HFR
PCI-CLK-OUT 1
IHF0 REF CLK 3HFP 33R
IHF5 5 PCI-CLK-ETHERNET
10R 33R 3
3HF2 33R
PCI-CLK-PNX8535 7
4
H E 10R
8
E H
3HF4 * PCI-CLK-MINI GND
CLKOUT 3HFM
PCI-CLK-PNX5100
4
10R 33R 3HFN
PCI-CLK-MINI
33R
I I
1 2 3 4 5 6 7 8
CHN SETNAME
CLASS_NO 2 2008-11-21
CONTROL
J 8204 000 8927 J
2008-10-03 2 PNX8543 TV543 R2 LDIPNX
NAME Maelegheer Ingrid SUPERS. 16 130 6 A3
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_508_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 94
2HG0 E3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2HG1 E3
A 2HG2 E3 A
2HG3 E3
PNX 8543 : SDRAM 2HG4 E3
2HG5 E4
7H00-2
PNX85439EH/M2/24182 2HG6 E4
MEMORY 2HG7 E4
DDR2-A0 AA34 AH34 DDR2-D0 2HG8 E4
0 0 +1V8-PNX85XX +1V8-PNX85XX
DDR2-A1 AE33 AK33 DDR2-D1
1 1 2HG9 E6
B DDR2-A2 AA33
AD31
2 2
AH33
AL34
DDR2-D3
DDR2-D2 2HGA E7 B
A DDR2-A3
DDR2-A4 Y34
3
4
3
4
AL33 DDR2-D6 A 2HGB E7
DDR2-A5 AD32 AE34 DDR2-D5 2HGC E7
5 5
330u 6.3V
W33 M_A AK34
1K0 1%
1K0 1%
DDR2-A6 6 6 DDR2-D4 2HGD E7
2HHB
3HJ1
3HJ3
DDR2-A7 AC32 AF34 DDR2-D7
W34
7 7
AG32
2HGE E7
DDR2-A8 8 8 DDR2-D8
DDR2-A9 Y31 AK31 DDR2-D9 2HGF E8
9 9
DDR2-A10 AD34 AJ32 DDR2-D10 FH07 FH06
2HGG E8
10 10
DDR2-A11 V33 AL32 DDR2-D11 2HGH E9
11 11 DDR2-VREF-CTRL DDR2-VREF-DDR
C DDR2-A12 Y32
12 12
13
AL31
AF31
DDR2-D12
DDR2-D13
2HGJ E9
2HGK E9
C
AC34 AK32
1K0 1%
1K0 1%
DDR2-BA0 0 14 DDR2-D14
2HGM E9
3HJ2
3HJ4
DDR2-BA1 AD33 AF32 DDR2-D15
1 M_BA 15
DDR2-BA2 AA32 M_DQ P34 DDR2-D16 2HGN E10
2 16
T34 DDR2-D17 2HGP E10
17
DDR2-CAS W32 R33 DDR2-D19 2HGR E10
B DDR2-CKE AE31
M_CASB 18
19
U34
V34
DDR2-D18
DDR2-D22
B 2HGS E10
M_CKE 20 2HGT E10
M33 DDR2-D23
21
2HGU E12
D DDR2-CLK_N
DDR2-CLK_P
AB33
AB34
N
P
M_CLK
22
23
T33
M34
DDR2-D20
DDR2-D21 2HGV E13 D
P31 DDR2-D24 2HGW E13
24
DDR2-CS W31 T32 DDR2-D30
M_CSB 25
P32
2HGY E13
26 DDR2-D26
DDR2-CLK_P DDR2-DQM0 AJ34 U31 DDR2-D25 2HGZ E13
0 27
3HJ0 DDR2-CLK_N DDR2-DQM1 AJ31 U32 DDR2-D28 2HH0 E13
1 28
DDR2-DQM2 R34 M_DQM M31 DDR2-D31 2HH1 E14
220R 2 29
DDR2-DQM3 R31 R32 DDR2-D27 2HH2 E14
3 30
M32 DDR2-D29
E DDR2-DQS0_N AG33
31 2HH3 H13
E
C DDR2-DQS0_P
N
AG34 M_DQS0
P IREF
AA31 IHG0 3HJ5 +1V8-PNX85XX
C 2HH4 C8
2HH5 C8
5K6
DDR2-DQS1_N AH31 V31 2HHA H7
N ODT 3HJY 2HH4
DDR2-DQS1_P AH32 M_DQS1 2HHB A11
P
V32
M RASB 820R 100n 2HHK E6
DDR2-DQS2_N N34
N DDR2-VREF-CTRL 2HHM E6
DDR2-DQS2_P N33 M_DQS2 AB32 2HH5
P VREF
100n 2HHN E11
DDR2-DQS3_N N31 AE32 2HHP E12
N WEB
F DDR2-DQS3_P N32
P
M_DQS3 DDR2-ODT 3HGP F7
3HGR F7
F
DDR2-RAS
3HGS F8
DDR2-WE 3HGT G7
D D 3HGU G8
3HGV G7
3HGW G8
3HGY G7
3HGZ G8
G +1V8-PNX85XX
+1V8-PNX85XX
3HH0 G7 G
3HH1 G8
3HH2 G7
330u 6.3V
330u 6.3V
RES 2HHK
RES 2HHN
3HH3 G8
2HHM
2HHP
1u0
1u0
3HH4 G7
3HH5 G8
3HH6 G7
E E 3HH7 H3
H 3HH8 H4 H
3HH9 H3
2HGW
2HGM
2HGG
2HGC
2HGD
2HGH
2HGN
2HGR
2HGU
2HGA
2HGB
2HGE
2HGK
2HGP
2HGS
2HGV
2HGY
2HGF
2HGT
2HGZ
2HG0
2HG1
2HG2
2HG3
2HG4
2HG5
2HG6
2HG7
2HG8
2HG9
2HGJ
2HH0
2HH1
2HH2
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
3HHA H4
22u
22u
3HHB F13
3HHC F13
7HG1
M9
M9
G1
G3
G7
G9
G1
G3
G7
G9
R1
C1
C3
C7
C9
R1
C1
C3
C7
C9
7HG0
A1
E1
A9
E9
A1
E1
A9
E9
3HHD G14
J9
J1
J9
J1
3HHE F13
VDDL
VDDL
VDD VDDQ VDD VDDQ
DDR2-ODT K9 DDR2-ODT K9 3HHF G13
ODT ODT
I DDR2-CKE K2
K3
CKE
A2
E2
DDR2-CKE K2
K3
CKE Φ A2
E2
3HHG G13 I
Φ
DDR2-WE DDR2-WE
L8
WE
R3 L8
WE SDRAM R3
3HHH G14
DDR2-CS DDR2-CS
F DDR2-RAS
DDR2-CAS
K7
L7
CS
RAS SDRAM
NC
R7
R8
DDR2-RAS
DDR2-CAS
K7
L7
CS
RAS
NC
R7
R8
F 3HHJ G13
3HHK G14
CAS CAS
3HHM G13
DDR2-BA0 L2 DDR2-BA0 L2 3HHN G14
0 3HGP 0 3HHB
is prohibited without the written consent of the copyright
VSSDL
DDR2-DQS1_N 33R 3HH8 A8 UDQS DDR2-DQS3_N 33R 3HHW A8 UDQS
33R 33R
7HG1 F11
VSS VSSQ VSS VSSQ FH06 A12
FH07 A11
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
A3
E3
J3
N1
P9
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
IHG0 C7
M M
I I
N N
1 2 3 4 5 6 7 8 9 10 11 12 13 14
O O
CHN SETNAME
CLASS_NO 2 2008-11-21
DDR2 INTERFACE
P 8204 000 8927
PNX8543 TV543 R2 LDIPNX
2008-10-10 3 P
NAME Maelegheer Ingrid SUPERS. 16 130 7 A2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
18310_509_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 95
3HK0 B2
A 1 2 3 4 5 6 7 7H00-4 A3 A
9HK0 D2
IHSM B2
TH01 C2
TH02 C2
PNX 8543 : DIGITAL VIDEO IN TH03 C2
TH04 C2
TH05 C2
TH06 C2
B A A
TH07 D2
TH08 D2
B
TH09 B2
TH10 B2
7H00-4
PNX85439EH/M2/24182 TH11 B2
TH12 B2
C18
HDMI_DV
DDCA-SCL DDC_SCL_A TH13 B2
DDCA-SDA E19 TH14 C2
DDC_SDA_A
C15
TH15 C2
DDC-SCL
C DDC-SDA D15
DDC_SCL_B
DDC_SDA_B
TH16 C2 C
RREF-PNX85XX 3HK0 IHSM
C16 B8
HDMI_RREF CLK
is prohibited without the written consent of the copyright
C9
B 12K DV FID
B
All rights reserved. Reproduction in whole or in parts
F D D F
G G
E E
H H
1 2 3 4 5 6 7
I I
CHN SETNAME
CLASS_NO 2 2008-11-21
VIDEO IN
J 8204 000 8927 J
PNX8543 TV543 R2 LDIPNX
2008-10-10 3
1 2 3 4 5 6 7 8 9 10 11 12 13
18310_510_090302.eps
090302
2009-May-08
Circuit Diagrams and PWB Layouts Q549.2E LA 10. EN 96
A A
2HM1 G5
1 2 3 4 5 6 7 8 9 10 11 12 13 2HM2 H5
2HM3 G4
2HM4 G5
2HM5 H5
2HM8 H4
B 2HMG B3
2HMJ A10
B
2HMP C10
A PNX 8543 : AUDIO A 2HMT E10
2HMW G10
2HMY H9
AUDIO-VDD
2HMZ I10
2HN1 F9
2HMJ 3HM0-1 C5
C FHR3
100n
3HM0-2 B4 C
IHMW 4 3HM0-3 C4
ADAC(7) 3 7HM1-1
LM324 1 FHM0 3HM0-4 D5
AUDIO-CL-L
IHMV 2 3HM1 D4
9HM0 3HMA G6
11 3HMB H6
B 7HM5 B 3HMC G5
3HMF BC807-25W 3HMD I5
D +AUDIO-POWER 2 3 AUDIO-VDD 3HME-1 B10 D
BZX384-C6V8
IHM6 4R7 IHM0 3HME-2 B9
7
3HM0-2
2HMG
6HM0
3HME-3 E9
22K
1u0
3HME-2 3HME-1
1 2 7 8 1 3HME-4 E10
3HMF B3
2
10K 10K
2HMP 3HML G6
IHM8 3HMM-1 I10
33p
3HMM-2 I9
E E
8 3HM0-1 1
3HMM-3 G9
22K
C C 3HMM-4 G10
3HMU H6
3HMV H5
IHM7
3HMW H5
3HM0-3 3HMY F5
6 3 7HM6 AUDIO-VDD
IHM2
BC847BW
3HMZ F5
22K IHM4 6HM0 B4
7HM1-1 B10
F IHM5
7HM1-2 D10 F
IHN3 4 7HM1-3 F10
ADAC(8) 5 7HM1-2
LM324 7 FHM1 7HM1-4 H10
IHN6 AUDIO-CL-R
7HM2-1 F5
5 3HM0-4 4
6
D D
3HM1
7HM2-2 H5
10K
22K
11 7HM3 F7
7HM4 H7
7HM5 B5
G 7HM6 C5 G
9HM0 B5
FHM0 B11
3 3HME-3 6 5 3HME-4 4 FHM1 D11
10K 10K FHM2 F11
2HMT FHM3 H11
FHR3 A10
33p
IH22 F4
H E E IH23 H4
H
IHM0 B3
IHM1 F7
IHM2 C4
AUDIO-VDD IHM4 C4
AUDIO-VDD IHM5 D5
IHM6 B3
IHM7 C5
IHM8 C5
I 2 ADAC(5)
IHNB
10
4
7HM1-3
FHM2 IHMG H7 I
3HMY
LM324 8
2K2
BC857BW IHNA AUDIO-OUT-L IHMV B9
1 7HM3 9
F F IHMW B9
2HN1
3n3
IHN8 3 11 IHN0 F5
6 IHN3 D9
IHN4 H5
is prohibited without the written consent of the copyright
470R
3HMA 10K 10K IHND H9
2HM3
2HM4
100n
3n3
K K
22K
IHNK I5
AUDIO-VDD
owner.
AUDIO-VDD
3HMW
2
2K2
BC857BW
1 7HM4
IHNF
L 3 3
ADAC(6)
IHND
12
4
7HM1-4 L
H ADAC(2)
IH23 3HMV IHN4
5 7HM2-2
BC847BS(COL)
IHNE
13
LM324 14 FHM3
AUDIO-OUT-R H
22K
2HMY
4 IHNH
3n3
2HM2 3HMU IHMG
-AUDIO-R 11
1u0 2K2
3HMB
470R
2HM8
2HM5
100n
3n3
22K