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Term Paper

Topic- PAL AND PLA

Submitted To: Submitted By:

Rupendeep Kaur Rahul Kumar
R.No. RE6911 A31
B.Tech ECE
Subject.ECE (202)
 CONTENTS

1. INTRODUCTION IS PAL AND PLA

2. HISTORY OF PAL AND PLA

3. DIFFERENCE BETWEEN PAL AND PLA

4. PAL AND PLA SINGLE DETALS

5. FEATURED CONTENT

6. ADVANTAGE PAL AND PLA

7. DISADVANTAGE PLA AND PLA

8. APPLICATION

9. REFERENCE
1. INTRODUCTION:-
PROGRAMMABLE LOGIC ARRAY (PLA):- A PLA is an SPLD that consist of a
programmable AND array and a programmable OR array the PLA was developed to
overcome some of the limitations of the PROM. The PLA is also called an FPLA (field
programmable array logic ) because the user in the field not the manufacture

x2 x1 x0 z1 z0 IMPLEMENT A TRUTH TABLE WITH A PLA.

0 0 0 0 0

0 0 1 1 0

0 1 0 0 0

0 1 1 1 0

1 0 0 1 1

1 0 1 0 0

1 1 0 0 0

1 1 1 0 1

One way to design a combinational logic circuit it to get gates and connect them with wires.
One disadvantage with this way of designing circuits is its lack of portability. You can now
get chips called programmable logic arrays (PLA) and program them to implement Boolean
function

PROGRAMMABLE ARRAY LOGIC (PAL):-

The term Programmable Array Logic :- is used to describe a family of programmable logic
device semiconductors used to implement logic functions in digital circuits introduced by
Monolithic Memories Inc. in March .
PAL devices consisted of a small PROM (programmable read-only memory) core and
additional output logic used to implement particular desired logic functions with few
components.
Using specialized machines PAL devices were field-programmable Each PAL device was
one-time programmable. meaning that it could not be updated and reused after its
initial programming.
PAL were programmed electrically using binary patterns as hexadecimal
files and a special electronic programming system available from either the manufacturer or
a third-party such as data\IN. In addition to single-unit device programmers, device
feeders and gang programmers were often used when more than just a few ALs needed to be
programmed. For large volumes electrical programming costs could be eliminated by
having the manufacturer fabricate a custom metal mask used to program the customers
patterns at the time of manufacture, MMI used the term to refer to
devices programmed in this way.
PROGRAMMABLE ARRAY LOGIC CIRCUT DIAGRAM:-

The term Programmable Array Logic (PAL) is used to describe a family of programmable
logic device semiconductors used to implement logic functions in digital circuits introduced
by Monolithic Memories Inc. (MMI) in March.PAL devices consisted of a small PROM
(programmable read-only memory) core andadditional output logic used to implement
particular desired logic functions with fewcomponents.
Using specialized machines PAL devices were field-programmabl. Each PAL device was
one-time programmable OTP meaning that it could not be updated and reused after its
initial programming.
PALs were programmed electrically using binary patterns (as JEDEC ASCII/hexadecimal
files) and a special electronic programming system available from either the manufacturer or
a third-party such as data input. In addition to single-unit device programmers device
feeders and gang programmers were often used when more than just a few PALs needed to be
programmed.
Logic devices can be classified into two broad categories - fixed and programmable. As the
name suggests . the circuits in a fixed logic device are permanent. they perform one function
or set of functions - once manufactured.they cannot be changed. On the other hand,
programmable logic devices are standard, off-the-shelf parts that offer customers a wide
range of logic capacity, features, speed, and voltage characteristics - and these devices can be
changed at any time to perform any number of functions. During the design phase
customers can change the circuitry as often as they want until the design operates to their
satisfaction. That's because PLDs are based on re-writable memory technology - to change
the design, the device is simply reprogrammed. Once the design is final, customers can go
into immediate production by simply programming as many PLDs as they need with the final
software design file.

2. HISTORY OF PAL AND PLA:-

Before pal were introduced designers of digital logic circuit logic circuit would use small –
scale integration (SSI) component such as those in the 7400 series (TTL) transistor-transistor
logic family the 7400 family include a variety of logic buiding blocks such as gates
(NOT,NAND,NOR ,AND,OR),multiplexers (MUXes) and demultiplexers (DEMUSes) flip
flops (D type ,jk) and others. One PAL device would typically replace dozens of such discrete
logic package so the SSI business went into decline as the pal business took off.pal were used
advantage in many products such as minicomputer as documented in tracy kidder best
selling book .the soul of a new machine PAL were not the first commercial prograrmm its
filed programmable logic array.these device were completely unfamiliar to most circuit
designers and were perceived to be too difficult to use.the FPLA had a relatively slow
maximum operating speed due to having both programming –AND and programmable –OR
array was expensive and had a poor reputation for testability. Another factor limiting the
acceptance of the was the large package a 600 mil wide 28 –dual in line package .the project
to create the PAL device was managed by john Birkner and the actual PAL circuit was
designed by H.T.Chua In a previous job had developed a 16-bit processor that using standard
logic device.His experience with standard logic him to believe that user programmable device
would be more attractive to user if the device were desing to replace standard logic .this
meant that the package size had to be more type of the existing device and the speed had be
improved
3.PROGRAMMING LANGUAGES:-

Though some engineers programmed PAL devices by manually editing files containing the
binary fuse pattern data most opted to design their logic using a hardware description
language [hdl or vhdl] such as data base logical device cupl and mmi there were computer
assisted desing cad now referred to as desing automobile programs which translated and
compile the designer logic equations into binary fuse map files used to program and often test
each device

4.ADVANTAGE OF PAL AND PLA:-

 Less board space

 Fewer printed circuit board
 Smaller enclosures
 Lower power requirements(i.e. smaller power supplies)
 Faster and less costly assembly processes
 Higher reliabilty(fewer ICs and circuit connections=>easier troubleshooting)
 Availability of design software
 Increase in speed
 Better security(copying is less likely to take place)
 Low production cost as compare to PLA
 More flexibility to designer
 Modification can be carried out within a short span of time
 Implementation of combinational and sequential circuits can be done with the help of
PAL.
 For given internal complexity a PAL can have larger inputs and implement a number
of functions
 Some PALs have outputs that can be complemented adding pos functions
 PAL do not require long lead times for prototypes or production parts - the PALs are
already on a distributor's shelf and ready for shipment.
 No multilevel circuit implementations in ROM without external connections from
output to input.PAL has outputs from OR terms as internal inputs to all AND terms
making implementation of multi-level circuits easier.
  PAL allow customers to order just the number of parts they need. when they
needthem allowing them to control inventory. Customers who use fixed logic
devicesoften end up with excess inventory which must be scrapped or if demand for
theirproduct surges they may be caught short of parts and face production delays
SEGMENT OF A SEQUENTIAL PAL:-

Below shows a logic diagram for a typical sequential PAL.This PAL has
an AND gate array with 16 input variables and it has 4 D flip-flops. Each flip-flop output
goes through a tristate-inverting buffer . One input pin 11 is used to

enable these buffers. The rising edge of a common clock .causes the flip-flops to
change the state. Each D flip-flop input is driven from an OR gate and each OR gate is fed
from 8 AND gates. The AND gate inputs can come from the external PAL inputs or
from the flip-flop outputs which are fed back internally. In addition there are four
input/output terminals. which can be used as either network
outputs or as inputs to the AND gates.When used as an output each I/O terminal is driven
from an inverting tristate buffer. Each of these buffers is fed from an OR gate and each OR
gate is fed from Gates. An eighth AND gate is used to enable the buffer.
LOGIC DIAGRAM FOR 16R4 PAL
When the 16R4 PAL is used to realize a sequential network, the I/O terminals are
normally used for the z outputs. Thus, a single 16R4 with no additional logic could
realize a sequential network with up to 8 inputs, 4 outputs, and 16 states. Each next state
equation could contain up to 8 terms, and each output equation could contain up to 7 terms.
As an example, we will realize the BCD to Excess-3 code converter using three flip-flops to
store Q1,Q2 and Q3, and the array logic that drives these flip-flops is programmed to realize
D1, D2 and D3, as shown in figure 3 .The Xs on the diagram indicate the connections to the
AND-gate inputs. AnX inside an AND gate indicates that the gate is not used. For D3, three
AND gates are used, and the function realized is

D3 = Q1Q2Q3 + X’Q1Q3’ + XQ1’Q2’

The flip-flop outputs are not used externally, so the output buffers are disabled. Since the Z

output comes through the inverting buffer, the array logic must realize

Z’ = (X + Q3)(X’ + Q3’) = XQ3’ + X’Q3

The z output buffer is permanently enabled in this example, so there are no connections to the
AND gate that drives the enable input, in which case the AND gate output is logic1. When
designing with PALS, we must simplify our logic equations and try to fit them in
one or more PALs. Unlike the more general PLA, the AND terms cannot be shared among
two or more OR gates; therefore, each function to be realized can be simplified by itself
without regard to common terms. For a given type of PAL the number of AND terms that

5.CONCLUSION:-

The value of programmable logic has always been its ability to shorten development
cyclesfor electronic equipment manufacturers and help them get their product to market
faster. As PAL and PLA suppliers continue to integrate more functions inside their devices,
reduce costs andincrease the availability of time-saving IP cores, programmable logic is
certain to expand itspopularity with digital designers

6.REFERENCE:-

1. Digital electornic circut

2. Digital circuits and logic design
3 www.wikipedia.com
4 www.globalspec.com
5.www.writphotec.com
6.www.scribd.com
[6] .http://www.scribd.com/doc/4139730/Programmable-Logic-and-Software
[7] DIGITAL CIRCUITS AND LOGIC DESIGN by J.S.Katre