Total No. of Questions: 10] [Total No.

of Pages: 2

Pl153 [3064]-101
B.E. (E & TIC & Electronics)
VLSI DESIGN
(Elective -I) : (1997 Course)
Time.. 3 Hours) [Max. Marks.. 100
Instructions..
1) A"swer any three questions from each section.
2) Answers to the two sections should be written in separate books.
3) Neat diagrams must be drawn wherever necessary.
4) Use of electronic pocket calculator is allowed.
5) Assume suitable data, if necessary.

SECTION - I

Ql) a) Design Mealy 100 sequence detector. [10]

b) Differentiate Moore & Mealy machines. [6]

Q2) a) Design CMOS logic for Y =AU + CD calGulate total width needed. [8]
b) What is power delay product? Derive the expression for dynamic power
dissipation. [8]

Q3) a) Write VHDL code for 2048 bit shift Register. [8]
b) Explain with suitable example any two attributes in VHDL [8]

Q4) a) Explain the following in one sentence each.

i). CLB ii) LUT ill) Speed Grade iv) JOB [8]
b) Withneat schematic explain the architc;cture of CPLD. Explove Function
Block & Macrocell. [8]

Q5) Write short notes on any three: [18]

a) VLSI Design flow .
b} ,Configuration in VHDL
c) JTAG'
d) Place & Route
e) Synthesizable statements in VHDL.

RT.O.
 SECTION - II
Q6) a) With neat schematic explain the architecture of FPGA. Explore CLB in
detaiL [10]
b) What do you mean by system clock? What is speed grade of PLD? [6]

Q7) a) Write VHDL code for lift controller. Also write test bench for it. [10]
b) Differentiate signal w.r.t.variable. - [6]

Q8) a) Write VHDL code for 2:4 decoder by different ways. Comment on
hard ware infrred. [8]
. b) Explain the concept of package.in VHDL with suitable example. [8]

Q9) a) Answer the following in one sentence each: [10]

i) Boundary scan ii) ISE ill). xnf
iv) Switch matrix v) Global clock
b) What are the advance tools available for simulation and synthesis? [6]
,
QI0)Write short notes on any three. [18]
a) Data objects b) Resolution function c) Test benches
d) Qualified expression e) Subprogram Overloading.

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