Professional Documents
Culture Documents
Q552.1E
LA
18770_000_100210.eps
100210
©
Copyright 2010 Koninklijke Philips Electronics N.V.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic, mechanical,
photocopying, or otherwise without the prior permission of Philips.
Published by ER/TY 1066 BU TV Consumer Care, the Netherlands Subject to modification EN 3122 785 18772
2010-Jun-18
EN 2 1. Q552.1E LA Revision List
1. Revision List
Manual xxxx xxx xxxx.0 Manual xxxx xxx xxxx.2
• First release. • Chapter 2: Table 2-1 updated (added CTNs with Italian
region; **PFL****M/08, MHEG).
Manual xxxx xxx xxxx.1 • Chapter 5: Paragraph 5.8.5 Exit “Factory Mode” updated.
• All chapters: Textual and graphical updates. • Chapter 6: Missing alignment values added.
• Chapter 2: Table 2-1 updated (added CTNs). • Chapter 10: New PWB layouts: 310431364004,
• Chapter 3 and 4: Index hyperlinks recovered. 310431364054, 310431364173, and 310431364065,
• Chapter 4: packing instructions Yong panel (Rembrandt including (where applicable) new schematics.
styling) added.
• Chapter 5: Figure 5-11 updated for TV550.
• Chapter 6: Alignment values added.
• Chapter 10: SRP list added.
SSB 2 4 7 9 10
Mechanics Descriptions Schematics
ALxx (Ambilight) Everlight
ALxx (Ambilight) LiteOn
B06 (non-DVBS-LVDS)
B09 (non-DVBS-conn.)
B03 (DC/DC / Class D)
Assembly Removal
B08 (DVBS-Supp.)
B11 (TCON-LGD)
B14 (TCON-SHP)
B02 (PNX85500)
Wiring Diagram
3104 313 xxxxx
B07 (DVBS-FE)
Wire Dressing
LCD Removal
B01 (Tuner)
AmbiLight
B05 (DDR)
B04 (I/O)
TCON
Tuner
PSU
CTN Styling
32PFL5405H/05 Rembrandt 64025 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-1
32PFL5405H/12 Rembrandt 64025 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-1
32PFL5405H/60 Rembrandt 64025 2.3 4-1 4.5 4.5.9 7.2 7.4.1 - 7.10 9-1 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-1
32PFL5605H/05 van Gogh 64003 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
32PFL5605H/12 van Gogh 64003 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
32PFL5605M/08 van Gogh 64173 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-15 10-18 10-19 - - - - - - -
11-3
32PFL5625H/12 van Gogh 64003 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-4 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
32PFL6605H/12 Matisse 64025 2.3 4-9 4.7 4.7.8 7.2 7.4.1 - 7.10 9-4 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-4
32PFL6605H/60 Matisse 64026 2.3 4-9 4.7 4.7.8 7.2 7.4.1 - 7.10 9-4 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-30 10-32 -
11-4
32PFL7605H/05 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7605H/12 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7605H/60 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7605M/08 Matisse 64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-2 10-7
2010-Jun-18 back to
div. table
Technical Specifications, Diversity, and Connections Q552.1E LA 2. EN 3
SSB 2 4 7 9 10
Mechanics Descriptions Schematics
B09 (non-DVBS-conn.)
B06 (non-DVBS-LVDS)
B03 (DC/DC / Class D)
Assembly Removal
B08 (DVBS-Supp.)
B11 (TCON-LGD)
B14 (TCON-SHP)
B02 (PNX85500)
Wiring Diagram
3104 313 xxxxx
B07 (DVBS-FE)
Wire Dressing
LCD Removal
B01 (Tuner)
AmbiLight
B05 (DDR)
B04 (I/O)
TCON
Tuner
PSU
CTN Styling
32PFL7665H/12 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7665M/08 Matisse 64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-2 10-7
32PFL7675H/12 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7675K/02 Matisse 64015 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - 10-23 10-25 - 10-30 10-34 -
11-4 10-2 10-7
32PFL7675M/08 Matisse 64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-2 10-7
32PFL7685H/12 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7685K/02 Matisse 64015 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - 10-23 10-25 - 10-30 10-34 -
11-4 10-2 10-7
32PFL7685M/08 Matisse 64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-2 10-7
32PFL7695H/12 Matisse 64064 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-2 10-7
64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-2 10-7
32PFL7695K/02 Matisse 64015 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - 10-23 10-25 - 10-30 10-34 -
11-4 10-2 10-7
32PFL7695M/08 Matisse 64065 2.3 4-9 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-2 10-7
37PFL5405H/05 Rembrandt 64025 2.3 4-2 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
37PFL5405H/12 Rembrandt 64025 2.3 4-2 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
37PFL5405H/60 Rembrandt 64025 2.3 4-2 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
37PFL7605H/05 Matisse 64064 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-3 10-8
64065 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-3 10-8
37PFL7605H/12 Matisse 64064 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-3 10-8
64065 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-3 10-8
37PFL7605H/60 Matisse 64064 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-3 10-8
64065 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-3 10-8
37PFL7605M/08 Matisse 64065 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
11-4 10-3 10-8
37PFL7675H/12 Matisse 64064 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-29 10-33 -
11-4 10-3 10-8
64065 2.3 4-10 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - - - - 10-30 10-33 -
10-3 10-8
37PFL7675K/02 Matisse 64014 2.3 4-11 4.7 4.7.8 7.2 7.4.1 7.9 7.10 9-4 10-1 10-6 10-11 10-14 10-15 10-17 10-19 - 10-23 10-25 - 10-31 10-34 -
11-4 10-3 10-8
40PFL5605H/05 van Gogh 64003 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
40PFL5605H/12 van Gogh 64003 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
40PFL5605K/02 van Gogh 64053 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-14 10-15 10-17 10-19 - 10-23 10-25 - - 10-34 10-37
11-3 64054 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-14 10-16 10-18 10-19 - 10-24 10-25 - - 10-34 10-38
40PFL5605M/08 van Gogh 64173 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-14 10-15 10-18 10-19 - - - - - - -
11-3
40PFL5625H/12 van Gogh 64003 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-5 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
40PFL6605H/12 Matisse 63643 2.3 4-12 4.7 4.7.8 7.2 7.4.1 - - 9-5 - - 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4
40PFL6605H/60 Matisse 64173 2.3 4-12 4.7 4.7.8 7.2 7.4.1 - - 9-5 - - 10-11 10-14 10-15 10-18 10-19 - - - - - - -
11-4
back to 2010-Jun-18
div. table
EN 4 2. Q552.1E LA Technical Specifications, Diversity, and Connections
SSB 2 4 7 9 10
Mechanics Descriptions Schematics
B09 (non-DVBS-conn.)
B06 (non-DVBS-LVDS)
B03 (DC/DC / Class D)
Assembly Removal
B08 (DVBS-Supp.)
B11 (TCON-LGD)
B14 (TCON-SHP)
B02 (PNX85500)
Wiring Diagram
3104 313 xxxxx
B07 (DVBS-FE)
Wire Dressing
LCD Removal
B01 (Tuner)
AmbiLight
B05 (DDR)
B04 (I/O)
TCON
Tuner
PSU
CTN Styling
40PFL7605H/05 Matisse 63643 2.3 4-12 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
40PFL7605H/12 Matisse 63643 2.3 4-12 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
40PFL7605H/60 Matisse 63643 2.3 4-12 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
40PFL7605M/08 Matisse 63643 2.3 4-12 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL5405H/05 Rembrandt 64025 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
42PFL5405H/12 Rembrandt 64025 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
42PFL5405H/60 Rembrandt 64025 2.3 4-3 4.5 4.5.9 7.2 7.4.1 - 7.10 9-2 - - 10-11 10-13 10-15 10-17 10-20 - - - - 10-28 10-32 -
11-2
42PFL7655H/12 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7655K/02 Matisse 63723 2.3 4-14 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-3 10-8
42PFL7655M/08 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7665H/12 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7665M/08 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7675H/12 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7675K/02 Matisse 63723 2.3 4-14 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-3 10-8
42PFL7675M/08 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7685H/12 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7685K/02 Matisse 63723 2.3 4-14 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-3 10-8
42PFL7685M/08 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-9
42PFL7695H/12 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-8
42PFL7695K/02 Matisse 63723 2.3 4-14 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-3 10-8
42PFL7695M/08 Matisse 63643 2.3 4-13 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-3 10-9
46PFL5605H/05 van Gogh 64003 2.3 4-7 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-7 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
46PFL5605H/12 van Gogh 64003 2.3 4-7 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-7 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
46PFL5605M/08 van Gogh 64173 4-7 2.3 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-15 10-18 10-19 - - - - - - -
11-3
46PFL7605H/05 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7605H/12 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7605H/60 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7605M/08 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7655H/12 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7655K/02 Matisse 63723 2.3 4-16 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-4 10-9
46PFL7655M/08 Matisse 63643 2.3 4-16 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7665H/12 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
46PFL7695H/12 Matisse 63643 2.3 4-15 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
2010-Jun-18 back to
div. table
Technical Specifications, Diversity, and Connections Q552.1E LA 2. EN 5
SSB 2 4 7 9 10
Mechanics Descriptions Schematics
B09 (non-DVBS-conn.)
B06 (non-DVBS-LVDS)
B03 (DC/DC / Class D)
Assembly Removal
B08 (DVBS-Supp.)
B11 (TCON-LGD)
B14 (TCON-SHP)
B02 (PNX85500)
Wiring Diagram
3104 313 xxxxx
B07 (DVBS-FE)
Wire Dressing
LCD Removal
B01 (Tuner)
AmbiLight
B05 (DDR)
B04 (I/O)
TCON
Tuner
PSU
CTN Styling
46PFL7695K/02 Matisse 63723 2.3 4-16 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-22 10-23 10-25 10-27 - - -
11-4 10-4 10-9
46PFL7695M/08 Matisse 63643 2.3 4-16 4.7 4.7.8 7.2 7.4.1 7.9 - 9-5 10-1 10-6 10-11 10-14 10-15 10-17 10-19 10-21 - - 10-26 - - -
11-4 10-4 10-9
52PFL5605H/12 van Gogh 64003 2.3 4-8 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-11 10-13 10-15 10-17 10-20 - - - - - 10-32 10-35
11-3 64004 2.3 4-8 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-16 10-18 10-20 - - - - - 10-32 10-36
52PFL5605M/08 van Gogh 64173 2.3 4-8 4.6 4.6.8 7.2 7.4.1 - 7.10 9-3 - - 10-12 10-13 10-15 10-18 10-19 - - - - - - -
11-3
back to 2010-Jun-18
div. table
EN 6 2. Q552.1E LA Technical Specifications, Diversity, and Connections
2.3 Connections
17
5 6 7 8 9
10 11 12 12 13 14 15 16
18771_001_100429.eps
100429
Note: The following connector colour abbreviations are used 4 - Vdd Supply k
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= 5 - CLOCK Signal k
Grey, Rd= Red, Wh= White, Ye= Yellow. 6 - GND2 Gnd H
7 - DAT0/D0 Signal jk
2.3.1 Side Connections 8 - DAT1/IRQ Signal jk
9 - DAT2/NC Signal jk
10 - CD Signal j
1 - SD-Card: Secure Digital Card - In/Out (optional)
11 - GND Gnd H
14
GND 12 - WP Signal j
13 - GND Gnd H
WP 12
14 - GND Gnd H
GND 11
CD 10
8 DAT1/IRQ
2 - Common Interface
68p - See diagram B01F HDMI & CI jk
7 DAT0/D0
6 GND2
5 CLOCK
3 - USB2.0
4 VDD
3 GND1 1 2 3 4
2 CMD/DI 10000_022_090121.eps
1 DAT3/CS 090121
9 DAT2/NC
Figure 2-3 USB (type A)
GND
13
10000_049_100210.eps 1 - +5V k
100210
2 - Data (-) jk
Figure 2-2 SD-Card connector 3 - Data (+) jk
4 - Ground Gnd H
1 - DAT3/CS Signal jk
2 - CMD/DI Signal k
3 - GND1 Gnd H
2010-Jun-18 back to
div. table
Technical Specifications, Diversity, and Connections Q552.1E LA 2. EN 7
back to 2010-Jun-18
div. table
EN 8 2. Q552.1E LA Technical Specifications, Diversity, and Connections
11
6
15
9 - +5VDC +5 V
10000_002_090121.eps
10 - Ground Sync Gnd H
090127 11 - n.c.
12 - DDC_SDA DDC data j
Figure 2-8 VGA Connector 13 - H-sync 0-5V j
14 - V-sync 0-5V j
1 - Video Red 0.7 VPP / 75 ohm j 15 - DDC_SCL DDC clock j
2 - Video Green 0.7 VPP / 75 ohm j
3 - Video Blue 0.7 VPP / 75 ohm j 17 - SAT - In (optional)
4 - n.c. - - F-type Coax, 75 ohm D
5 - Ground Gnd H
6 - Ground Red Gnd H
2010-Jun-18 back to
div. table
Precautions, Notes, and Abbreviation List Q552.1E LA 3. EN 9
The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g. AP Asia Pacific
AG is Bruges), digit 3 refers to the B.O.M. code, digit 4 refers AR Aspect Ratio: 4 by 3 or 16 by 9
to the Service version change code, digits 5 and 6 refer to the ASF Auto Screen Fit: algorithm that adapts
production year, and digits 7 and 8 refer to production week (in aspect ratio to remove horizontal black
example below it is 2006 week 17). The 6 last digits contain the bars without discarding video
serial number. information
ATSC Advanced Television Systems
MODEL : 32PF9968/10 MADE IN BELGIUM Committee, the digital TV standard in
220-240V ~ 50/60Hz the USA
128W
ATV See Auto TV
PROD.NO: AG 1A0617 000001 VHF+S+H+UHF
Auto TV A hardware and software control
S BJ3.0E LA system that measures picture content,
and adapts image parameters in a
10000_024_090121.eps dynamic way
100105
AV External Audio Video
AVC Audio Video Controller
Figure 3-1 Serial number (example)
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
3.3.7 Board Level Repair (BLR) or Component Level Repair carrier distance is 5.5 MHz
(CLR) BDS Business Display Solutions (iTV)
BLR Board-Level Repair
If a board is defective, consult your repair procedure to decide BTSC Broadcast Television Standard
if the board has to be exchanged or if it should be repaired on Committee. Multiplex FM stereo sound
component level. system, originating from the USA and
If your repair procedure says the board should be exchanged used e.g. in LATAM and AP-NTSC
completely, do not solder on the defective board. Otherwise, it countries
cannot be returned to the O.E.M. supplier for back charging! B-TXT Blue TeleteXT
C Centre channel (audio)
3.3.8 Practical Service Precautions CEC Consumer Electronics Control bus:
remote control bus on HDMI
• It makes sense to avoid exposure to electrical shock. connections
While some sources are expected to have a possible CL Constant Level: audio output to
dangerous impact, others of quite high potential are of connect with an external amplifier
limited current and are sometimes held in less regard. CLR Component Level Repair
• Always respect voltages. While some may not be ComPair Computer aided rePair
dangerous in themselves, they can cause unexpected CP Connected Planet / Copy Protection
reactions that are best avoided. Before reaching into a CSM Customer Service Mode
powered TV set, it is best to test the high voltage insulation. CTI Color Transient Improvement:
It is easy to do, and is a good service precaution. manipulates steepness of chroma
transients
CVBS Composite Video Blanking and
Synchronization
DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
low frequency amplification
DCM Data Communication Module. Also
referred to as System Card or
Smartcard (for iTV).
DDC See “E-DDC”
D/K Monochrome TV system. Sound
carrier distance is 6.5 MHz
DFI Dynamic Frame Insertion
2010-Jun-18 back to
div. table
Precautions, Notes, and Abbreviation List Q552.1E LA 3. EN 11
DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote ITV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (color
Telecommunication Union relating to carrier= 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (color carrier PAL M=
back to 2010-Jun-18
div. table
EN 12 3. Q552.1E LA Precautions, Notes, and Abbreviation List
3.575612 MHz and PAL N= 3.582056 SVHS Super Video Home System
MHz) SW Software
PCB Printed Circuit Board (same as “PWB”) SWAN Spatial temporal Weighted Averaging
PCM Pulse Code Modulation Noise reduction
PDP Plasma Display Panel SXGA 1280 × 1024
PFC Power Factor Corrector (or Pre- TFT Thin Film Transistor
conditioner) THD Total Harmonic Distortion
PIP Picture In Picture TMDS Transmission Minimized Differential
PLL Phase Locked Loop. Used for e.g. Signalling
FST tuning systems. The customer TS Transport Stream
can give directly the desired frequency TXT TeleteXT
POD Point Of Deployment: a removable TXT-DW Dual Window with TeleteXT
CAM module, implementing the CA UI User Interface
system for a host (e.g. a TV-set) uP Microprocessor
POR Power On Reset, signal to reset the uP UXGA 1600 × 1200 (4:3)
PSDL Power Supply for Direct view LED V V-sync to the module
backlight with 2D-dimming VESA Video Electronics Standards
PSL Power Supply with integrated LED Association
drivers VGA 640 × 480 (4:3)
PSLS Power Supply with integrated LED VL Variable Level out: processed audio
drivers with added Scanning output toward external amplifier
functionality VSB Vestigial Side Band; modulation
PTC Positive Temperature Coefficient, method
non-linear resistor WYSIWYR What You See Is What You Record:
PWB Printed Wiring Board (same as “PCB”) record selection that follows main
PWM Pulse Width Modulation picture and sound
QRC Quasi Resonant Converter WXGA 1280 × 768 (15:9)
QTNR Quality Temporal Noise Reduction XTAL Quartz crystal
QVCP Quality Video Composition Processor XGA 1024 × 768 (4:3)
RAM Random Access Memory Y Luminance signal
RGB Red, Green, and Blue. The primary Y/C Luminance (Y) and Chrominance (C)
color signals for TV. By mixing levels signal
of R, G, and B, all colors (Y/C) are YPbPr Component video. Luminance and
reproduced. scaled color difference signals (B-Y
RC Remote Control and R-Y)
RC5 / RC6 Signal protocol from the remote YUV Component video
control receiver
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a 4-
wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY
SVGA 800 × 600 (4:3)
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 13
4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing Rembrandt Styling • Figures below can deviate slightly from the actual situation,
4.2 Cable Dressing Van Gogh Styling due to the different set executions.
4.3 Cable Dressing Matisse Styling
4.4 Service Positions
4.5 Assy/Panel Removal Rembrandt Styling
4.6 Assy/Panel Removal Van Gogh Styling
4.7 Assy/Panel Removal Matisse Styling
4.8 Set Re-assembly
18770_100_100211.eps
100211
back to 2010-Jun-18
div. table
EN 14 4. Q552.1E LA Mechanical Instructions
18770_101_100211.eps
100216
18770_102_100211.eps
100211
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 15
18770_103_100211.eps
100211
18770_105_100211.eps
100216
back to 2010-Jun-18
div. table
EN 16 4. Q552.1E LA Mechanical Instructions
18770_104_100211.eps
100211
18771_100_100503.eps
100512
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 17
18771_101_100503.eps
100512
back to 2010-Jun-18
div. table
EN 18 4. Q552.1E LA Mechanical Instructions
18770_106_100211.eps
100211
18771_102_100503.eps
100503
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 19
18771_103_100503.eps
100503
18770_107_100211.eps
100211
back to 2010-Jun-18
div. table
EN 20 4. Q552.1E LA Mechanical Instructions
18771_104_100503.eps
100503
18771_105_100503.eps
100503
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 21
18771_106_100503.eps
100503
18771_107_100503.eps
100503
back to 2010-Jun-18
div. table
EN 22 4. Q552.1E LA Mechanical Instructions
4.4 Service Positions The stand and -subframe do not need to be removed for
removing the central subwoofer.
For easy servicing of a TV set, the set should be put face down When defective, replace the whole unit.
on a soft flat surface, foam buffers or other specific workshop
tools. Ensure that a stable situation is created to perform 4.5.3 Mains Switch
measurements and alignments. When using foam bars take
care that these always support the cabinet and never only the The mains switch is mounted on the front bezel with one screw.
display. Caution: Failure to follow these guidelines can
seriously damage the display! 4.5.4 Main Power Supply
Ensure that ESD safe measures are taken.
Refer to Figure 4-18 and Figure 4-19 for details.
4.5 Assy/Panel Removal Rembrandt Styling
2
The instructions apply to the 42PFL5405H/xx. 2 2
1
4.5.1 Rear Cover
1
With the Rembrandt styling, a new concept of housing has
been introduced, having consequences for Service when
opening the set. 2 2
Part of the “back cover” now forms one assy with the LCD
panel and will be swapped together with this panel. For
opening the set, only remove the “smaller” part of the rear
2 2
cover as described below! 1
2
Warning: The white round clips on the rear side of the LCD 18770_122_100212.eps
100216
panel secure the backlight units and should therefore NEVER
be released! Release will destroy the LCD Panel and voids Figure 4-18 Main Power Supply
warranty!
Refer to Figure 4-27 for details.
18770_123_100215.eps
100215
18770_120_100212.eps
100216
1. Unplug all connectors [1].
2. Remove the fixation screws [2].
Figure 4-17 Rear cover 3. Take the board out.
When defective, replace the whole unit.
When remounting, ensure that the back shielding plate is
1. Remove all screws of the rear cover; the part to be
removed [1] is indicated on Figure 4-17. positioned correctly.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
the set.
4.5.2 Speakers
Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.
Subwoofer
The central subwoofer is located in the centre of the set, behind
the stand and the -subframe, and is secured by two bosses.
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 23
3
3
3
3
2 3
1
3 3
18770_125_100215.eps
100215
3 3
3 3 3 3
3 3
3 3
2 2
1
3 2 3
18770_126_100215.eps
100215
back to 2010-Jun-18
div. table
EN 24 4. Q552.1E LA Mechanical Instructions
Refer to Figure 4-23 for details. Refer to Figure 4-25 and Figure 4-27 for details.
1
3 3
3 3
18770_127_100215.eps
100215
2 2
Figure 4-23 IR & LED board
2 2
1. Detach the front bezel from the set as described earlier.
2. Release the clips [1] that secure the IR & LED board in the 18770_128_100215.eps
bezel and take the board out. 100215
3. Unplug the connectors.
When defective, replace the whole unit. Figure 4-25 LCD board -1-
1 2
18850_104_100203.eps
100203
18930_107_100315.eps
Figure 4-24 Keyboard Control board 100315
1. Detach the front bezel from the set as described earlier. Figure 4-26 Vesa spacer
2. Unplug the connector [1].
3. Release the clips that secure the board [2] and take the 1. Remove the SSB as described earlier.
board out. 2. Remove the PSU as described earlier.
When defective, replace the whole unit. 3. Remove the stand support plate as described earlier.
4. Remove the bezel as described earlier.
5. Remove the Vesa spacer as shown in Figure 4-26 by using
a 10 mm wrench. Note that it has been secured with
Loctite 2440.
6. Lift the LCD Panel from the bezel.
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 25
18770_121_100212.eps
100407
Warning!
The white clips on the rear side of the LCD Panel secure
the backlight units and should NEVER be released!
Refer to Figure 4-27 for details.
1. Remove the tweeters as described earlier.
2. Remove the central subwoofer as described earlier.
3. Remove the mains switch as described earlier.
4. Remove the Main Power Supply board as described
earlier, together with its back shielding.
5. Remove the Small Signal Board as described earlier,
together with its back shielding.
6. Remove the cable from the clamp [1].
7. Remove the stand [2] together with its subframe [3].
8. Detach the front bezel together with the IR & LED board
and Keyboard Control board as described earlier.
18931_100_100510.eps
9. Ensure all (sub-) frames, boards and cables that do not 100510
belong to the LCD panel are removed before sending the
LCD Panel in.
Figure 4-28 LCD panel
back to 2010-Jun-18
div. table
EN 26 4. Q552.1E LA Mechanical Instructions
Special note:
Some models come with mechanical catches at top of the rear
cover. To open them, refer to Figure 4-29 to Figure 4-32 for
18770_152_100218.eps
details. 100218
2
3
2 4
2 5
2 6
2
18770_150_100218.eps
100219
18770_153_100218.eps
Figure 4-29 Rear cover 40" -1- 100317
4.6.2 Speakers
Tweeters
Each tweeter unit is mounted with one screw.
When defective, replace the whole unit.
Subwoofer
18770_151_100218.eps The central subwoofer is located in the centre of the set, and is
100218 mounted with two screws.
When defective, replace the whole unit.
Figure 4-30 Rear cover 40" -2-
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 27
Refer to Figure 4-33 for details. Refer to Figure 4-35, Figure 4-36 and Figure 4-37 for details.
2 2
1
2 2
1 1
1 1
2 2
1
18770_142_100215.eps
18770_140_100215.eps 100215
100217
Figure 4-35 IR & LED Board -1-
Figure 4-33 Main Power Supply
3
3
1
18770_143_100215.eps
100215
18770_141_100215.eps
100217 3 3
18770_144_100215.eps
4.6.5 Mains Switch 100215
The mains switch is mounted on the front bezel with two Figure 4-37 IR & LED Board -3-
screws.
1. Remove the stand [1].
2. Remove the IR & LED board cover [2].
3. Release the clips [3] that secure the IR & LED board.
4. Remove the connectors [4] on the IR/LED board.
back to 2010-Jun-18
div. table
EN 28 4. Q552.1E LA Mechanical Instructions
18770_145_100216.eps
100217
Refer to Figure 4-39 for details. 7. Remove the IR & LED board as described earlier.
1. Remove the stand as described earlier. 8. Remove the keyboard control board as described earlier.
2. Remove the brackets [1]. 9. Remove the clamps [3].
3. Remove the stand support [2]. 10. Remove the flare.
4. Remove the central subwoofer as described earlier. 11. Remove all remaining screws [4].
5. Remove the tweeters as described earlier. Now the LCD Panel can be lifted from the front cabinet.
6. Remove the mains switch as described earlier.
1 1
4 1 4 1 4
4 4 4
3 3
1 1
4 4
1 1
2 2 2
3 3
1 1
4 4 4 4
3 2 4 2 2 4 2 3
18770_146_100216.eps
100407
4.7 Assy/Panel Removal Matisse Styling 1. Remove all screws of the rear cover.
2. Lift the rear cover from the TV. Make sure that wires and
flat coils are not damaged while lifting the rear cover from
The instructions apply to the 40PFL7605H/12.
the set.
2010-Jun-18 back to
div. table
Mechanical Instructions Q552.1E LA 4. EN 29
Refer to Figure 4-40 for details. Refer to Figure 4-42 for details.
2 2
1 1
2 2
1 1
3 1
3
2 2
18771_108_100504.eps 18771_110_100504.eps
100504 100504
Figure 4-40 Main Power Supply Figure 4-42 IR & LED Board
3
3
1
1
2
3
3 4
3
5
18771_109_100504.eps
100505
back to 2010-Jun-18
div. table
EN 30 4. Q552.1E LA Mechanical Instructions
4 4 4 4
3 3
5 5
2 2 2 2
3 3
18771_112_100504.eps
100504
Pay special attention to use the correct screws at the 4.8 Set Re-assembly
proper location when mounting a new LCD panel!
To re-assemble the whole set, execute all processes in reverse
Using the wrong screws will damage the LCD panel! order.
Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
set. Ensure that EMC foams are mounted correctly.
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 31
Note: For the new model range, a new remote control (RC) is
used with some renamed buttons. This has an impact on the
activation of the Service modes. For instance the old “MENU”
button is now called “HOME” (or is indicated by a “house” icon).
Purpose
• To create a pre-defined setting, to get the same
measurement results as given in this manual.
• To override SW protections detected by stand-by
processor and make the TV start up to the step just before
protection (a sort of automatic stepwise start-up). See
18770_249_100215.eps
section “5.3 Stepwise Start-up”. 100407
• To start the blinking LED procedure where only LAYER 2
errors are displayed. (see also section “5.5 Error Codes”). Figure 5-1 Service mode pad
Specifications After activating this mode, “SDM” will appear in the upper right
corner of the screen (when a picture is available).
Table 5-1 SDM default settings
How to Navigate
Default When the “MENU” (or “HOME”) button is pressed on the RC
Region Freq. (MHz) system transmitter, the TV set will toggle between the SDM and the
normal user menu.
Europe, AP(PAL/Multi) 475.25 PAL B/G
Europe, AP DVB-T 546.00 PID DVB-T
How to Exit SDM
Video: 0B 06 PID
Use one of the following methods:
PCR: 0B 06 PID
• Switch the set to STAND-BY via the RC-transmitter.
Audio: 0B 07
• Via a standard customer RC-transmitter: key in “00”-
sequence.
• All picture settings at 50% (brightness, colour, contrast).
• Sound volume at 25%.
back to 2010-Jun-18
div. table
EN 32 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
5.2.2 Service Alignment Mode (SAM) button and “XXX” (where XXX is the 3 digit decimal display
code as mentioned on the sticker in the set). Make sure to key
Purpose in all three digits, also the leading zero’s. If the above action is
• To perform (software) alignments. successful, the front LED will go out as an indication that the
• To change option settings. RC sequence was correct. After the display option is changed
• To easily identify the used software version. in the NVM, the TV will go to the Stand-by mode. If the NVM
• To view operation hours. was corrupted or empty before this action, it will be initialized
• To display (or clear) the error code buffer. first (loaded with default values). This initializing can take up to
20 seconds.
How to Activate SAM
Via a standard RC transmitter: Key in the code “062596”
directly followed by the “INFO” (or “OK”) button. After activating
SAM with this method a service warning will appear on the
Display Option
screen, continue by pressing the “OK” button on the RC. Code
27mm
MODEL:
32PF9968/10
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 33
• NVM editor. For NET TV the set “type number” must be How to Activate CSM
entered correctly.
Also the production code (AG code) can be entered here Key in the code “123654” via the standard RC transmitter.
via the RC-transmitter. Note: Activation of the CSM is only possible if there is no (user)
Correct data can be found on the side/rear sticker. menu on the screen!
back to 2010-Jun-18
div. table
EN 34 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
Mains
off Mains
on
- WakeUp requested
WakeUp
- Acquisition needed
requested
- Tact switch pushed
St by Semi Active
- stby requested and
no data Acquisition St by - St by requested
required - tact SW pushed
Tact switch
pushed
WakeUp
requested
- Tact switch pushed
(SDM)
- last status is hibernate
GoToProtection
after mains ON
Hibernate
GoToProtection
Protection
18770_250_100216.eps
100402
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 35
Off
Mains is applied
Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.
st-by µP resets
Yes
Enter protection
Enable the DCDC converters
(ENABLE-3V3n LOW)
Wait 50ms
EJTAG probe
Yes
connected ?
No
No No Cold boot?
Yes
Release AVC system reset Release AVC system reset Release AVC system reset
Feed warm boot script Feed cold boot script Feed initializing boot script
disable alive mechanism
18770_251_100216.eps
100216
back to 2010-Jun-18
div. table
EN 36 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
No
AVC releases Reset-Ethernet, Reset-USB and AVC releases Reset-Ethernet, Reset-USB and
This cannot be done through the bootscript, Reset-DVBs when the end of the AVC boot- Reset-DVBs when the end of the AVC boot-
the I/O is on the standby µP script is detected script is detected
Bootscript ready
No
in 1250 ms?
Yes
yes
Switch Standby I/O line high
3-th try?
and wait 4 seconds
The first time after the option turn on of the startup screen or
Startup screen cfg file when the set is virgin, the cfg file is not present and hence
present? the startup screen will not be shown.
Yes
yes
Blink Code as
error code
200Hz set? yes
No
Enter protection
85500 sends out startup screen 85500 sends out startup screen
No
200Hz Tcon has started up the
85500 starts up the display.
display.
No
To keep this flowchart readable, the exact Startup screen visible 85500 requests Lamp on
display turn on description is not copied
here. Please see the Semi-standby to On
description for the detailed display startup
Startup screen visible
During the complete display time of the
Startup screen, the preheat condition of
sequence.
100% PWM is valid. Initialize audio
Semi-Standby
18770_252_100216.eps
100216
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 37
No
Start POK line Wait until valid and stable audio and video, corresponding to the
detection algorithm requested output is delivered by the AVC
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time.
return
Yes
Active
18770_253_100216.eps
100216
Figure 5-6 “Semi Stand-by” to “Active” flowchart (EEFL or LED backlight 50/100 Hz only)
back to 2010-Jun-18
div. table
EN 38 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
return
Switch Audio-Reset low and wait 5ms
Release audio mute and wait 100ms before any other audio
The higher level requirement is that audio and handling is done (e.g. volume change)
video should be demuted without transient
effects and that the audio should be demuted
maximum 1s before or at the same time as the
unblank the video.
unblanking of the video.
Yes
Active
18770_254_100216.eps
100216
Figure 5-7 “Semi Stand-by” to “Active” flowchart (LED backlight 200 Hz)
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 39
Active
Wait 100ms
No
Instruct 200Hz
The exact timings to
Tcon to turn off Switch off LVDS output in 85500
switch off the
the display
display (LVDS
delay, lamp delay)
Wait x ms
are defined in the
display file.
Semi Standby
18770_255_100216.eps
100216
back to 2010-Jun-18
div. table
EN 40 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
Semi Stand by
Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.
Wait 10ms
Wait 5ms
Important remarks:
18770_256_100216.eps
100216
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 41
Introduction The error code buffer contains all detected errors since the last
ComPair (Computer Aided Repair) is a Service tool for Philips time the buffer was erased. The buffer is written from left to
Consumer Electronics products. and offers the following: right, new errors are logged at the left side, and all other errors
1. ComPair helps to quickly get an understanding on how to shift one position to the right.
repair the chassis in a short and effective way. When an error occurs, it is added to the list of errors, provided
2. ComPair allows very detailed diagnostics and is therefore the list is not full. When an error occurs and the error buffer is
capable of accurately indicating problem areas. No full, then the new error is not added, and the error buffer stays
knowledge on I2C or UART commands is necessary, intact (history is maintained).
because ComPair takes care of this. To prevent that an occasional error stays in the list forever, the
3. ComPair speeds up the repair time since it can error is removed from the list after more than 50 hrs. of
automatically communicate with the chassis (when the µP operation.
is working) and all repair information is directly available. When multiple errors occur (errors occurred within a short time
4. ComPair features TV software up possibilities. span), there is a high probability that there is some relation
between them.
Specifications
ComPair consists of a Windows based fault finding program New in this chassis is the way errors can be displayed:
and an interface box between PC and the (defective) product.
The ComPair II interface box is connected to the PC via an • If no errors are there, the LED should not blink at all in
USB cable. For the TV chassis, the ComPair interface box and CSM or SDM. No spacer must be displayed as well.
the TV communicate via a bi-directional cable via the service • There is a simple blinking LED procedure for board
connector(s). level repair (home repair) so called LAYER 1 errors
The ComPair fault finding program is able to determine the next to the existing errors which are LAYER 2 errors (see
problem of the defective television, by a combination of Table 5-2).
automatic diagnostics and an interactive question/answer – LAYER 1 errors are one digit errors.
procedure. – LAYER 2 errors are 2 digit errors.
• In protection mode.
– From consumer mode: LAYER 1.
How to Connect
– From SDM mode: LAYER 2.
This is described in the chassis fault finding database in
ComPair. • Fatal errors, if I2C bus is blocked and the set reboots,
CSM and SAM are not selectable.
– From consumer mode: LAYER 1.
TO TV
– From SDM mode: LAYER 2.
TO
UART SERVICE
TO
I2C SERVICE
TO
UART SERVICE • In CSM mode.
CONNECTOR CONNECTOR CONNECTOR
– When entering CSM: error LAYER 1 will be displayed
by blinking LED. Only the latest error is shown.
ComPair II
Multi • In SDM mode.
RC in function
RC out
– When SDM is entered via Remote Control code or the
hardware pins, LAYER 2 is displayed via blinking LED.
Optional Power Link/ Mode
Switch Activity I2C RS232 /UART
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.
PC
Basically there are three kinds of errors:
• Errors detected by the Stand-by software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
ComPair II Developed by Philips Brugge
• Errors detected by the Stand-by software which not
Optional power
HDMI 5V DC lead to protection. In this case the front LED should blink
I2C only
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer”. Note that it can take up several minutes
10000_036_090121.eps
091118 before the TV starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 15 or 53).
Figure 5-10 ComPair II interface connection • Errors detected by main software (MIPS). In this case
the error will be logged into the error buffer and can be read
Caution: It is compulsory to connect the TV to the PC as out via ComPair, via blinking LED method LAYER 1-2
shown in the picture above (with the ComPair interface in error, or in case picture is visible, via SAM.
between), as the ComPair interface acts as a level shifter. If
one connects the TV directly to the PC (via UART), ICs will be 5.5.2 How to Read the Error Buffer
blown!
Use one of the following methods:
How to Order • On screen via the SAM (only when a picture is visible).
ComPair II order codes: E.g.:
• ComPair II interface: 3122 785 91020. – 00 00 00 00 00: No errors detected
• Software is available via the Philips Service web portal. – 23 00 00 00 00: Error code 23 is the last and only
• ComPair UART interface cable for Q55x.x. detected error.
(using 3.5 mm Mini Jack connector): 3138 188 75051. – 37 23 00 00 00: Error code 23 was first detected and
error code 37 is the last detected error.
Note: When you encounter problems, contact your local – Note that no protection errors can be logged in the
support desk. error buffer.
back to 2010-Jun-18
div. table
EN 42 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
• Via the blinking LED procedure. See section 5.5.3 How to content, as this history can give significant information). This to
Clear the Error Buffer. ensure that old error codes are no longer present.
• Via ComPair. If possible, check the entire contents of the error buffer. In
some situations, an error code is only the result of another error
5.5.3 How to Clear the Error Buffer code and not the actual cause (e.g. a fault in the protection
detection circuitry can also lead to a protection).
There are several mechanisms of error detection:
Use one of the following methods:
• Via error bits in the status registers of ICs.
• By activation of the “RESET ERROR BUFFER” command
in the SAM menu. • Via polling on I/O pins going to the stand-by processor.
• Via sensing of analog values on the stand-by processor or
• If the content of the error buffer has not changed for 50+
the PNX85500.
hours, it resets automatically.
• Via a “not acknowledge” of an I2C communication.
Extra Info Other root causes for this error can be due to hardware
• Rebooting. When a TV is constantly rebooting due to problems regarding the DDR’s and the bootscript reading
internal problems, most of the time no errors will be logged from the PNX8550.
or blinked. This rebooting can be recognized via a ComPair • Error 16 (12V). This voltage is made in the power supply
interface and Hyperterminal (for Hyperterminal settings, and results in protection (LAYER 1 error = 3) in case of
see section “5.8 Fault Finding and Repair Tips, 5.8.6 absence. When SDM is activated we see blinking LED
Logging). It’s shown that the loggings which are generated LAYER 2 error = 16.
by the main software keep continuing. In this case • Error 17 (Invertor or Display Supply). Here the status of
diagnose has to be done via ComPair. the “Power OK” is checked by software, no protection will
• Error 13 (I2C bus 3, SSB bus blocked). Current situation: occur during failure of the invertor or display supply (no
when this error occurs, the TV will constantly reboot due to picture), only error logging. LED blinking of LAYER 1
the blocked bus. The best way for further diagnosis here, is error = 3 in CSM, in SDM this gives LAYER 2 error = 17.
to use ComPair. • Error 21 (PNX51X0). When there is no I2C communication
• Error 14 (I2C bus 2, TV set bus blocked). Current towards the PNX51X0 after start-up, LAYER 2 error = 21
situation: when this error occurs, the TV will constantly will be logged and displayed via the blinking LED
reboot due to the blocked bus. The best way for further procedure if SDM is switched on. This device is located on
diagnosis here, is to use ComPair. the 200 Hz panel from the display.
• Error 18 (I2C bus 4, Tuner bus blocked). In case this bus • Error 23 (HDMI). When there is no I2C communication
is blocked, short the “SDM” solder paths on the SSB during towards the HDMI mux after start-up, LAYER 2 error = 23
startup, LAYER error 2 = 18 will be blinked. will be logged and displayed via the blinking LED
• Error 15 (PNX8550 doesn’t boot). Indicates that the main procedure if SDM is switched on.
processor was not able to read his bootscript. This error will • Error 24 (I2C switch). When there is no I2C
point to a hardware problem around the PNX8550 communication towards the I2C switch, LAYER 2
(supplies not OK, PNX 8550 completely dead, I2C link error = 24 will be logged and displayed via the blinking LED
between PNX and Stand-by Processor broken, etc...). procedure when SDM is switched on. Remark: this only
When error 15 occurs it is also possible that I2C1 bus is works for TV sets with an I2C controlled screen included.
blocked (NVM). I2C1 can be indicated in the schematics as • Error 28 (Channel dec DVB-S). When there is no I2C
follows: SCL-UP-MIPS, SDA-UP-MIPS. communication towards the DVB-S channel decoder,
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 43
LAYER 2 error = 28 will be logged and displayed via the 2. Two short blinks of 250 ms followed by a pause of 3 s
blinking LED procedure if SDM is switched on. 3. Eight short blinks followed by a pause of 3 s
• Error 31 (Lnb controller). When there is no I2C 4. Six short blinks followed by a pause of 3 s
communication towards this device, LAYER 2 error = 31 5. One long blink of 3 s to finish the sequence (spacer).
will be logged and displayed via the blinking LED 6. The sequence starts again.
procedure if SDM is activated.
• Error 34 (Tuner). When there is no I2C communication 5.6.2 How to Activate
towards the tuner during start-up, LAYER 2 error = 34 will
be logged and displayed via the blinking LED procedure Use one of the following methods:
when SDM is switched on.
• Activate the CSM. The blinking front LED will show only
• Error 35 (main NVM). When there is no I2C
the latest layer 1 error, this works in “normal operation”
communication towards the main NVM during start-up, mode or automatically when the error/protection is
LAYER 2 error = 35 will be displayed via the blinking LED
monitored by the Stand-by processor.
procedure when SDM is switched “on”. All service modes
In case no picture is shown and there is no LED blinking,
(CSM, SAM and SDM) are accessible during this failure, read the logging to detect whether “error devices” are
observed in the Uart logging as follows: "<< ERRO >>>
mentioned. (see section “5.8 Fault Finding and Repair
PFPOW_.C: First Error (id19, Layer_1= 2 Layer_= 35)".
Tips, 5.8.6 Logging”).
• Error 36 (Tuner DVB-S). When there is no I2C • Activate the SDM. The blinking front LED will show the
communication towards the DVB-S tuner during start-up,
entire content of the LAYER 2 error buffer, this works in
LAYER 2 error = 36 will be logged and displayed via the
“normal operation” mode or when SDM (via hardware pins)
blinking LED procedure when SDM is switched “on”. is activated when the tv set is in protection.
• Error 42 (Temp sensor). Only applicable for TV sets
equipped with temperature devices.
• Error 53. This error will indicate that the PNX8550 has 5.7 Protections
read his bootscript (when this would have failed, error 15
would blink) but initialization was never completed because 5.7.1 Software Protections
of hardware problems (NAND flash, ...) or software
initialization problems. Possible cause could be that there
Most of the protections and errors use either the stand-by
is no valid software loaded (try to upgrade to the latest main
microprocessor or the MIPS controller as detection device.
software version). Note that it can take a few minutes
Since in these cases, checking of observers, polling of ADCs,
before the TV starts blinking LAYER 1 error = 2 or in SDM,
and filtering of input values are all heavily software based,
LAYER 2 error = 53.
these protections are referred to as software protections.
• Error 64. Only applicable for TV sets with an I2C controlled
There are several types of software related protections, solving
screen.
a variety of fault conditions:
• Related to supplies: presence of the +5V, +3V3 and 1V2
5.6 The Blinking LED Procedure needs to be measured, no protection triggered here.
• Protections related to breakdown of the safety check
5.6.1 Introduction mechanism. E.g. since the protection detections are done
by means of software, failing of the software will have to
initiate a protection mode since safety cannot be
The blinking LED procedure can be split up into two situations:
guaranteed any more.
• Blinking LED procedure LAYER 1 error. In this case the
error is automatically blinked when the TV is put in CSM.
Remark on the Supply Errors
This will be only one digit error, namely the one that is
The detection of a supply dip or supply loss during the normal
referring to the defective board (see table “5-2 Error code
overview”) which causes the failure of the TV. This playing of the set does not lead to a protection, but to a cold
reboot of the set. If the supply is still missing after the reboot,
approach will especially be used for home repair and call
the TV will go to protection.
centres. The aim here is to have service diagnosis from a
distance.
• Blinking LED procedure LAYER 2 error. Via this Protections during Start-up
procedure, the contents of the error buffer can be made During TV start-up, some voltages and IC observers are
visible via the front LED. In this case the error contains actively monitored to be able to optimise the start-up speed,
2 digits (see table “5-2 Error code overview”) and will be and to assure good operation of all components. If these
displayed when SDM (hardware pins) is activated. This is monitors do not respond in a defined way, this indicates a
especially useful for fault finding and gives more details malfunction of the system and leads to a protection. As the
regarding the failure of the defective board. observers are only used during start-up, they are described in
Important remark: the start-up flow in detail (see section “5.3 Stepwise Start-up”).
For an empty error buffer, the LED should not blink at all in
CSM or SDM. No spacer will be displayed. 5.7.2 Hardware Protections
When one of the blinking LED procedures is activated, the front The only real hardware protection in this chassis appears in
LED will show (blink) the contents of the error buffer. Error case of an audio problem e.g. DC voltage on the speakers. This
codes greater then 10 are shown as follows: protection will only affect the Class D audio amplifier (item
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 7D10; see diagram B03A) and puts the amplifier in a
2. A pause of 1.5 s continuous burst mode (cyclus approximately 2 seconds).
3. “n” short blinks (where “n”= 1 to 9)
4. A pause of approximately 3 s, Repair Tip
5. When all the error codes are displayed, the sequence • There still will be a picture available but no sound. While
finishes with a LED blink of 3 s (spacer). the Class D amplifier tries to start-up again, the cone of the
6. The sequence starts again. loudspeakers will move slowly in one or the other direction
until the initial failure shuts the amplifier down, this cyclus
Example: Error 12 8 6 0 0. starts over and over again. The headphone amplifier will
After activation of the SDM, the front LED will show: also behaves similar.
1. One long blink of 750 ms (which is an indication of the
decimal digit) followed by a pause of 1.5 s
back to 2010-Jun-18
div. table
EN 44 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
5.8 Fault Finding and Repair Tips +12V is considered OK (=> DETECT2 signal becomes "high",
+12V to +1V8, +12V to +3V3, +12V to +5V DC-DC converter
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra can be started up) if it rises above 10V and doesn’t drop below
9V5. A small delay of a few milliseconds is introduced between
Info”.
the start-up of 12V to +1V8 DC-DC converter and the two other
DC-DC converters via 7U48 and associated components.
5.8.1 Ambilight
Description DVB-S2:
Due to degeneration process of the LED’s fitted on the ambi • LNB-RF1 (0V = disabled, 14V or 18V in normal operation)
module, there can be a difference in the colour and/or light LNB supply generated via the second conversion channel
output of the spare ambilight modules in comparison with the of 7T03 followed by 7T50 LNB supply control IC. It provides
originals ones contained in the TV set. Via SAM => alignments supply voltage that feeds the outdoor satellite reception
=> ambilight, the spare module can be adjusted. equipment.
• +3V3-DVBS (3V3 nominal), +2V5-DVBS (2V5 nominal)
5.8.2 Audio Amplifier and +1V-DVBS (1.03V nominal) power supply for the
silicon tuner and channel decoder. +1V-DVBS is generated
The Class D-IC 7D10 has a powerpad for cooling. When the IC via a 5V to 1V DC-DC converter and is stabilized at the
is replaced it must be ensured that the powerpad is very well point of load (channel decoder) by means of feedback
pushed to the PWB while the solder is still liquid. This is needed signal SENSE+1V0-DVBS. +3V3-DVBS and +2V5-DVBS
to insure that the cooling is guaranteed, otherwise the Class D- are generated via linear stabilizers from +5V-DVBS that by
IC could break down in short time. itself is generated via the first conversion channel of 7T03.
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 45
5.8.6 Logging
5.8.7 Loudspeakers
5.8.8 PSL
5.8.9 Tuner
back to 2010-Jun-18
div. table
EN 46 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
Before starting: ST AR T
- prepare a USB memory stick with the latest software
- download the latest Main Software (Fus) from www.p4c.philips.com
- unzip this file
- create a folder ”upgrades” in the root of a USB stick (size > 50 MB) and
save the autorun.upg file in this "upgrades" folder.
Note: it is possible to rename this file, e.g."Q54x_SW_version.upg"; this in Set is still oper ating?
case there are more than one "autorun.upg" files on the USB stick.
No
Yes
1. D isconnect the WiF i module fr om the PC I connector (only for Q549.x SSB)
2. Replace the SSB by a Service SSB.
3. Place the WiFi module in the PCI connector.
4. Mount the Service SSB in the set.
Set the correct “Display code” via “062598 -HOME- xxx” where
“xxx” is the 3 digit display panel code (see sticker on the side
or bottom of the cabinet)
H_16771_007a.eps
100402
2010-Jun-18 back to
div. table
Service Modes, Error Codes, and Fault Finding Q552.1E LA 5. EN 47
Noisy picture with bands/lines is visible and the An “F” is displayed (and the HDMI 1
RED LED is continuous on. input is displayed).
- Press the “volume minus” button on the TVs local keyboard for 5 ~10
seconds
- Press the “SOURCE” button for 10 seconds until the “F” disappears
from the screen or the noise on the screen is replaced by “blue mute”
H_16771_007b.eps
100322
back to 2010-Jun-18
div. table
EN 48 5. Q552.1E LA Service Modes, Error Codes, and Fault Finding
Attention!
In case the download application has been started manually,
the “autorun.upg” will maybe not be recognized.
What to do in this case:
1. Create a directory “UPGRADES” on the USB stick.
2. Rename the “autorun.upg” to something else, e.g. to
“software.upg”. Do not use long or complicated names,
keep it simple. Make sure that “AUTORUN.UPG” is no
longer present in the root of the USB stick.
3. Copy the renamed “upg” file into this directory.
4. Insert USB stick into the TV.
5. The renamed “upg” file will be visible and selectable in the
upgrade application.
2010-Jun-18 back to
div. table
Alignments Q552.1E LA 6. EN 49
6. Alignments
Index of this chapter: For the next alignments, supply the following test signals via a
6.1 General Alignment Conditions video generator to the RF input:
6.2 Hardware Alignments • EU/AP-PAL models: a PAL B/G TV-signal with a signal
6.3 Software Alignments strength of at least 1 mV and a frequency of 475.25 MHz
6.4 Option Settings • US/AP-NTSC models: an NTSC M/N TV-signal with a
6.5 Reset of Repaired SSB signal strength of at least 1 mV and a frequency of 61.25
6.6 Total Overview SAM modes MHz (channel 3).
• LATAM models: an NTSC M TV-signal with a signal
strength of at least 1 mV and a frequency of 61.25 MHz
6.1 General Alignment Conditions (channel 3).
Perform all electrical adjustments under the following 6.3.1 White Point
conditions:
• Power supply voltage (depends on region):
• Choose “TV menu”, “Setup”, “More TV Settings” and then
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz (± 10%).
“Picture” and set picture settings as follows:
– AP-PAL-multi: 120 - 230 VAC / 50 Hz (± 10%).
– EU: 230 VAC / 50 Hz (± 10%). Picture Setting
• Allow the set to warm up for approximately 15 minutes. Picture format Unscaled
To store the data: Table 6-2 White D alignment values - LED - Minolta CA-210
• Press OK on the RC before the cursor is moved to the
left Value Cool (9420K) Normal (8120K) Warm (6080K)
• In main menu select “Store” and press OK on the RC x 0.282 0.292 0.320
back to 2010-Jun-18
div. table
EN 50 6. Q552.1E LA Alignments
Table 6-3 White D alignment values - LED - Minolta CS-200 Table 6-10 White tone default setting 40" (Matisse)
Value Cool (11000K) Normal (9000K) Warm (6500K) White Tone e.g. 40PFL6605x
x 0.276 0.287 0.313 Colour Temp R G B
y 0.282 0.296 0.329 Normal 114 127 114
Cool 95 122 127
Warm 127 127 65
If you do not have a colour analyser, you can use the default
values. This is the next best solution. The default values are
average values coming from production. White Tone e.g. 40PFL7605x
• Select a COLOUR TEMPERATURE (e.g. COOL, Colour Temp R G B
NORMAL, or WARM). Normal 125 127 95
• Set the RED, GREEN and BLUE default values according Cool 122 127 109
to the values in Table 6-4 to Table 6-15. Warm 127 119 53
• When finished press OK on the RC, then press STORE (in
the SAM root menu) to store the aligned values to the NVM. Table 6-11 White tone default setting 42" (Rembrandt)
• Restore the initial picture settings after the alignments.
White Tone e.g. 42PFL5405x
Table 6-4 White tone default setting 32" (Rembrandt) Colour Temp R G B
Normal t.b.d. t.b.d. t.b.d.
White Tone e.g. 32PFL5405x Cool t.b.d. t.b.d. t.b.d.
Colour Temp R G B Warm t.b.d. t.b.d. t.b.d.
Normal 127 118 116
Cool 123 118 127
Table 6-12 White tone default setting 42" (Matisse)
Warm 127 108 78
2010-Jun-18 back to
div. table
Alignments Q552.1E LA 6. EN 51
6. Select one of 10 matrixes which color correspond with the 6.4.4 Opt. No. (Option numbers)
neighbouring modules, “matrix 0” is the factory alignment
and can always be retrieved. Select this sub menu to set all options at once (expressed in
7. The alignment is stored automatically. two long strings of numbers).
An option number (or “option byte”) represents a number of
6.3.3 TCON/VCOM alignment different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
Sets with forward integration have the TCON on SSB. The via eight option numbers.
alignment of this TCON is stored in the SSB, and is related to When the NVM is replaced, all options will require resetting. To
the used display. When an SSB or a display is replaced, a new be certain that the factory settings are reproduced exactly, you
value must be entered. must set both option number lines. You can find the correct
A default value (see table below) is copied from the display file option numbers on a sticker inside the TV set.
(after entering the correct display code) and is shown in the Example: The options sticker gives the following option
SAM menu. But on top of this, the default value can be numbers:
overruled manually via the menu item “TCON alignment”. • 08192 00133 01387 45160
The current value is shown with 4 digits, and can be changed • 12232 04256 00164 00000
by a digit entry. After pressing “OK”, the value is stored. The first line (group 1) indicates hardware options 1 to 4, the
The menu item "Reset TCON alignment" can be used to return second line (group 2) indicate software options 5 to 8.
to the default value from the display file. A notification is shown: Every 5-digit number represents 16 bits (so the maximum value
"TCON alignment has been reset". will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
Table 6-16 TCON/VCOM default settings values of each Option Byte (OB) will give the option number.
6.4.1 Introduction
6.5 Reset of Repaired SSB
The microprocessor communicates with a large number of I2C
A very important issue towards a repaired SSB from a Service
ICs in the set. To ensure good communication and to make
repair shop (SSB repair on component level) implies the reset
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these of the NVM on the SSB.
A repaired SSB in Service should get the service Set type
PNX51XX ICs (back-end advanced video picture improvement
“00PF0000000000” and Production code “00000000000000”.
IC which offers motion estimation and compensation features
(commercially called HDNM) plus integrated Ambilight control) Also the virgin bit is to be set. To set all this, you can use the
ComPair tool or use the “NVM editor” and “Dealer options”
is made known by the option codes.
items in SAM (do not forget to “store”).
Notes:
• After changing the option(s), save them by pressing the OK After a repaired SSB has been mounted in the set (set repair
button on the RC before the cursor is moved to the left, on board level), the type number (CTN) and production code of
select STORE in the SAM root menu and press OK on the the TV has to be set according to the type plate of the set. For
RC. this (new in this platform), you can use the NVM editor in
• The new option setting is only active after the TV is SAM. This action also ensures the correct functioning of the
switched “off” / “stand-by” and “on” again with the mains “Net TV” feature and access to the Net TV portals. The loading
switch (the NVM is then read again). of the CTN and production code can also be done via ComPair
(Model number programming).
6.4.2 Dealer Options
In case of a display replacement, reset the “Operation hours
For dealer options, in SAM select “Dealer options”. display” to “0”, or to the operation hours of the replacement
display.
See Table 6-17 SAM mode overview.
Select the sub menu's to set the initialisation codes (options) of Whenever ordering a new SSB, it should be noted that the
correct ordering number (12nc) of a SSB is located on a sticker
the model number via text menus.
on the SSB. The format is <12nc SSB><serial number>. The
See Table 6-17 SAM mode overview.
ordering number of a “Service” SSB is the same as the ordering
number of an initial “factory” SSB.
back to 2010-Jun-18
div. table
EN 52 6. Q552.1E LA Alignments
18310_221_090318.eps
090319
2010-Jun-18 back to
div. table
Alignments Q552.1E LA 6. EN 53
back to 2010-Jun-18
div. table
EN 54 6. Q552.1E LA Alignments
2010-Jun-18 back to
div. table
Alignments Q552.1E LA 6. EN 55
back to 2010-Jun-18
div. table
EN 56 7. Q552.1E LA Circuit Descriptions
7. Circuit Descriptions
Index of this chapter: 7.1 Introduction
7.1 Introduction
7.2 Power Supply
The Q552.1E LA is a new chassis launched in Europe in 2010.
7.3 DC/DC Converters
The whole range is covered by PNX8550x main IC so-called
7.4 Front-End Analogue and DVB-T, DVB-C; ISDB-T reception NXP TV550 platform.
7.5 Front-End DVB-S(2) reception
The major deltas versus its predecessor Q543/Q548 are the
7.6 HDMI
DVBS, DLNA1.5+, Wireless Laptop Live (WLL-Dongle),
7.7 Video and Audio Processing - PNX85500 Ethernet, and WiFi Ready (Net-TV) functionality.
7.8 Back-End
7.9 Ambilight
The Q552.1E LA chassis comes with the following stylings:
7.10 TCON • Rembrandt (series xxPFL54xx, with LGD CCFL display),
• Van Gogh (series xxPFL56xx, with Sharp LED display),
Notes: • Matisse (series xxPFL76xx, with LGD LED display).
• Only new circuits (circuits that are not published recently)
are described. 7.1.1 Implementation
• Figures can deviate slightly from the actual situation, due
to different set executions.
Key components of this chassis are:
• For a good understanding of the following circuit
descriptions, please use the wiring, block (see chapter • PNX85500 System-On-Chip (SOC) TV Processor
• TX31XX Hybrid Tuner (DVB-T/C, analogue)
9. Block Diagrams) and circuit diagrams (see chapter
• STV6110AT DVB-S Satellite Tuner
10. Circuit Diagrams and PWB Layouts).Where necessary,
you will find a separate drawing for clarification. • SII9x87 HDMI Switch
• TPA312xD2PWP Class D Power Amplifier
• LAN8710 Dual Port Gigabit Ethernet media access
controller.
18770_244_100203.eps
100219
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 57
18770_245_100203.eps
100219
back to 2010-Jun-18
div. table
EN 58 7. Q552.1E LA Circuit Descriptions
1M 20 1M 71 1 M 59 2D D IM 1M 3 6 1G 51 1G 50
F LASH
D D R2 FPGA
L O W P RO F IL E
1M99
D C /D C
CA
D D R2
LVD S - O U T
S D- S L O T
D DR
CA
PN X85500
M1
27 x27 TS - IN
USB
1.00 m m
1M 9 5
20,00 H D MI
D D R2 E TH G P IO
1
7 D D R2
USB
2 .0
D
3
5
NO S P LIT TE R !!!
1 R J4 5
D
3 ser v
8
USB
Tuner
2 .0
Pb
S ca rt2 /Y P b P r
Pr
L /R
Y
R
L
HD
CT RL
MI
OUT
1 .3
9187
3
0
1 2
S ca rt1 /Y P b P r SPO
VGA
HD
HD
HD
1 .3
1 .3
1 .3
MI
MI
MI
18770_246_100203.eps
100203
Figure 7-3 SSB layout cells (top view) (non-DVBS without TCON)
D V B -S D V B -S
Quad LVDS
D D R2
FPGA
LO W P RO F IL E
1M99
D C /D C
CA
D D R2
LVD S -O U T
S D -S L O T
D DR
CA
PN X85500
M1
27 x27 T S -IN
USB
1.00 m m
1 M 95
20,00 H D MI
D D R2 E TH G P IO
1
7 D D R2
USB
2.0
D
3
5
NO S P LIT T ER !!!
1 R J4 5
D
3 serv
8
USB
T uner
2.0
S ca rt2 /Y P b P r
Pb
Pr
L /R
Y
R
L
HD
CT RL
MI
OUT
1 .3
9187
3
0
1 2
S ca rt1 /Y P b P r SPO
VGA
HD
HD
HD
1 .3
1 .3
1 .3
MI
MI
MI
18770_247_100203.eps
100219
Figure 7-4 SSB layout cells (top view) (DVBS without TCON)
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 59
TDC ON
V B -S
Quad LVDS
FLASH
D D R2
FPGA
LO W P RO F IL E
1M99
D C /D C
CA
D D R2
LVD S -O U T
S D -S L O T
D DR
CA
PN X85500
M1
27 x27 T S -IN
USB
1.00 m m
1 M 95
20,00 H D MI
D D R2 E TH G P IO
1
7 D D R2
USB
2.0
D
3
5
NO S P LIT T ER !!!
1 R J4 5
D
3 serv
8
USB
T uner
2.0
S ca rt2 /Y P b P r
Pb
Pr
L /R
Y
R
L
HD
CT RL
MI
OUT
1 .3
9187
3
0
1 2
S ca rt1 /Y P b P r SPO
VGA
HD
HD
HD
1.3
1.3
1.3
MI
MI
MI
18770_248_100203.eps
100219
Figure 7-5 SSB layout cells (top view) (non-DVBS with TCON)
back to 2010-Jun-18
div. table
EN 60 7. Q552.1E LA Circuit Descriptions
18770_234_100127.eps
100127
Important delta’s with the TV543 platform are: The following displays can be distinguished:
• New power architecture for LED backlight (PSL, PSLS, • CCFL/EEFL backlight: power board is conventional IPB
PSDL) • LED backlight:
• “Boost”-signal is now a PWM-signal + continuous variable. - side-view LED without scanning: PSL power board
- side-view LED with scanning: PSLS power board
The control signals are: - direct-view LED without 2D-dimming: PSL power board
• Stand-by - direct-view LED with 2D-dimming: PSDL power board.
• Lamp “on/off”
• DIM (PWM) (not for PSDL) PSL stands for Power Supply with integrated LED-drivers.
• Boost (PWM except for IPB) PSLS stands for a Power Supply with integrated LED-drivers
• Power-OK: indicates that the main converter is functioning with added Scanning functionality (added microcontroller).
(feedback signal to the SSB). PSDL stands for a Power Supply for Direct-view LED backlight
with 2D-dimming.
In this manual, no detailed information is available because of
design protection issues.
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 61
PNX85500
• +1V8, supply voltage for DDR2 (diagram B03B)
• +2V5, supply voltage for analogue blocks inside + 12V
+ 3V 3
+ 3V 3 + 3V 3
+ 2V 5
+ 2V 5
2919 m A 2371 m A 450 m A
PNX85500 (see diagram B03E) dc -dc s tabiliz er
channel decoder
• +2V5-DVBS, clean voltage for DVB-S2 channel decoder 18770_226_100127.eps
• +1V-DVBS, core voltage for DVB-S2 channel decoder. 100426
+ V -LNB + 3V 3 tuner + 2V 5
Diagram B03D contains the following linear stabilisers: down
c onverter
400 m A
+ 2V 5
s tabiliz er
90 m A
7.4 Front-End Analogue and DVB-T, DVB-C; • Channel decoder; I2C address 0xD0
ISDB-T reception • LNB switching regulator; I2C address 0x14
• Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
7.4.1 European/China region
DVB-C channel decoder and analogue demodulator.
• Hybrid Tuner
• Switchable SAW filter 7/8 MHz (Eur.), or single SAW filter
(8 MHz) (China)
• Bandpass filter
• Amplifier
• PNX85500 SoC TV processor with integrated DVB-T and
DVB-C channel decoder and analogue demodulator.
18770_237_100127.eps
100219
18770_236_100127.eps
100219
18770_243_100203.eps
7.5 Front-End DVB-S(2) reception 100203
The Front-End for the DVB-S(2) application consist of the Figure 7-13 HDMI input configuration
following key components:
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 63
• Multi-standard digital video decoder (MPEG-2, H.264, For a functional diagram of the PNX85500, refer
MPEG-4) to Figure 7-14.
• Integrated DVB-T/DVB-C channel decoder
PNX85500x
MEMORY
CONTROLLER
TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)
DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO
VIDEO ENCODER analog CVBS
OUTPUT
SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION
DMA BLOCK
I2C PWM GPIO IR ADC SPI UART I 2C GPIO Flash USB 2.0 SD Ethernet
x8 Memory MAC
Card
18770_241_100201.eps
100219
back to 2010-Jun-18
div. table
EN 64 7. Q552.1E LA Circuit Descriptions
7.8 Back-End
18770_242_100203.eps
100203
7.9 Ambilight
1
MTK 1 1 1 1
Glue M
or M M M M
logic 5 AmbiLight AmbiLight
PNX85500 8 8 8 8
9
3 4 3 4
SSB
1M09
1M09
PSU
18770_209a_100202.eps
100202
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 65
+3V3
2B17
100n
7B20-1
74LVC2G17
5
6 PWM-CLOCK 2 3B01-2 7 1 6 1 3B30-1 8 PWM-CLOCK-BUF
× 100R 220R
2B00
6 5 3
2
33p
2B02
100p
L × ×
E 6 4 5 2
7B20-2
D L × L × 74LVC2G17
+3V3
E 6 3 E 6 4
5
D L × D L + SPI-CLOCK 1
3B01-1
8 3 4 4
3B30-4
5 SPI-CLOCK-BUF
100R 220R
E 6 E 5
2B01
2
33p
D D
2B10
100p
L L
E E
D D
18770_214_100126.eps
100126
36 30 24 18 15 12 9
Figure 7-20 Ambilight buffer
18770_210_100126.eps
100126 The temperature sensor is built around item no. 7B30 (diagram
AL1A) and indicates overtemperature of the board. Refer to
Figure 7-17 LED grouping per board figure 7-21 Temperature sensor.
6
protocol outside LED board. Between the CPLD and the LED
1K5 1%
1K5 1%
3B39-2
3B39-3
driver, as “extra” line is mentioned: 7B30
3
FB40
• Non-SPI signals that are required for the LED driver
5
1
4 TEMP-SENSOR
• Temperature sensor line. RES
3
LMV331IDCK
2
2B08
3004
10K
10n
3B11
10K
-T
FB41
SPI S P I + e x tra
1M 59
C P LD
1K5 1%
PNX
3B39-1
2B09
10n
8
18770_211_100126.eps 18770_215_100126.eps
100126 100126
Figure 7-18 Communication protocol outside LED board Figure 7-21 Temperature sensor
Refer to figure for an overview of the communication inside the The EEPROM (item no. 7B07; diagram AL1A) contains
LED board. alignment information about the mounted LEDs and is
programmed during the alignment process in production. Refer
to figure 7-22 EEPROM.
E x tra
+3V3
100n
B uffer SPI-DATA-IN-BUF
D river
1M 84
1M 83
SPI-CLOCK-BUF
7B07
8
M95010-WDW6
+3V3 VCC
Tem p EEPRO M
7B06
5
D Φ Q
2
74LVC1G32GW 6 (64K)
5
sensor SPI-CS 1
C
4 1 3B02-2
S
Te m p SPI DATA-SWITCH 2
+3V3 HOLD
7 +3V3
1 3B02-1 8 3 7 10K 2
W
3
SPI 10K
GND
4
18770_213_100126.eps SPI-DATA-RETURN
100219
18770_216_100126.eps
100126
Figure 7-19 Communication protocol inside LED board
Figure 7-22 EEPROM
The buffer is built around item no. 7B20 (diagram AL1A) and
regenerates the clock signals. Refer to figure 7-20 Ambilight
The LED driver is built around item no. 7B26 (diagram AL1A)
buffer.
and controls the LEDs. Refer to figure 7-23 LED driver.
back to 2010-Jun-18
div. table
EN 66 7. Q552.1E LA Circuit Descriptions
+3V3
2B11
100n
7B26-1
27
TLC5946RHB
3B00-1 VCC
BLANK 1 8 31 4 PWM-R1
BLANK 0
PWM-CLOCK-BUF 150R 24 5 PWM-G1
GSCLK 1
3B18 26 6 PWM-B1
IREF 2
1K8 FB35 3 7 PWM-G3
MODE 3
PROG 4 3B00-4 5 1 8 PWM-R3
SCLK 4
SPI-CLOCK-BUF 150R 2 9 PWM-R2
SIN 5
SPI-DATA-IN-BUF 23 10 PWM-G2
SOUT 6
SPI-DATA-IN 3 6 11 PWM-B2
7
SPI-DATA-OUT 3B00-3 150R 3B21 150R 22 OUT 14 PWM-B3
XERR 8
FB20 +3V3 3B22 25 15 PWM-G4
XHALF 9
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
XLAT 10
150R 17 PWM-B4
11
12 18 PWM-B5
12
13 19 PWM-G5
13
7
6
28 NC 20 PWM-R5
2B04-2
2B04-1
2B04-4
2B04-3
14
100p
100p
100p
100p
29 21 DATA-SWITCH
15
3B31
GND GND_HS +3V3
2
30
33
2K0
7B26-2
TLC5946RHB
34 VIA 42
35 41
VIA VIA
36 40
VIA
37
38
39
18770_217_100126.eps
100126
+24V
8 3B07-1 1
7B23-1
10K
BC847BS(COL)
6
2
2 3B07-2 7
1
10K
FB30
PWM-B1
3B35
+24V
+24V 7000 7001 7002 7003 7004 7005
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 270R
3B36
5 3B07-4 4
BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3B37
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3 3B07-3 6
4
10K
1 3B03-1 8
FB31 1K5
PWM-R1
3B03-2
2 7
+24V
1K5
3 3B03-3 6
3 3B13-3 6
1K5
7B25
10K
BC847BW 3 3B03-4
4 5
1K5
1
2B03
100n
5 3B13-4 4
2
10K
FB32
PWM-G1
18770_218_100126.eps
100126
7.10 TCON
2010-Jun-18 back to
div. table
Circuit Descriptions Q552.1E LA 7. EN 67
EEPROM
Control
PNX8550
Signals
Gamma
Reference Source Drive IC
Voltage
+3.3 V
+1.8 V
+16 V
Gate Drive IC
+12 V Power TFT – LCD Panel
Block
VGH (+28 V)
VGL (-6 V)
LC D P anel
SSB
18770_238_100127.eps
100402
For the TCON block diagram, refer to figure 7-26 TCON block
diagram.
R 1 A ~E D a ta M ini-LVDS
LV D S P a th Transmitter
R e c e iv er B lo c k
R 1C LK
(L in e
B u ffer)
OPC ODC DCA RLV P /N
M ini-LVDS
(Optimum
(Dynamic
Transmitter
Contrast
Control)
Control)
Circuit)
Power
(Over
Right h alf
Drive
data
R 2 A ~E
LV D S Gate D river
C trl S ign als
R 2C LK R e c e iv er
Ve rtic a l & H o rizo n ta l
Tim in g g e n e ra tio n Source D river
C trl S ign als
I2 C ROM H s y n c/ Control
I2 C
S lav e M aster Vsync Signal
S S C L K (S p re a d Spectrum C lo c k) Output
DE
EEPROM
18770_239_100127.eps
100127
back to 2010-Jun-18
div. table
EN 68 7. Q552.1E LA Circuit Descriptions
Notes to figure 7-26 TCON block diagram: • Timing Control Function: generates control signals to
• LVDS receiver: converts the data stream back into RGB column drivers and row drivers (Source Enable - SOE,
data and SYNC signals (Vsync, Hsync, Data Enable - DE) Gate Enable - GOE, Gate Start Pulse - GSP).
• ODC: Over Drive Circuit - to improve LC response For an overview of the TCON DC/DC converters, refer to figure
• Data Path Block: the video RGB data input to data path 7-27 TCON DC/DC converters.
block is delayed to align the column driver start pulse with
the column driver data
To G a te D riv e rs (G a te
VGH +2 8 V +3 5 V
H ig h Vo lta g e )
D C /D C
+ 12V C o n tro lle r To G a te D riv e rs (G a te
VGL -6 V -6 V
L o w Vo lta g e )
Tim in g C o n tro lle r IC
Vcc +3 V 3 +3 V 3
S u p p ly Vo lta g e
Tim in g C o n tro lle r IC
Vcc +1 V 8 +1 V 2
S u p p ly Vo lta g e
G a m m a R e fe renc e
Vre f +1 6 V +1 5 V 2
Vo lta g e
S o u rc e D riv e r S u p p ly
Vdd +1 6 V +1 5 V 6
Vo lta g e
18770_240_100128.eps
100128
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 69
8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).
Block diagram
To EEPROM or
To Upstream Upstream SMBus Master
24 MHz
VBUS USB Data SDA SCL
Crystal
3.3 V
Bus- Serial
Power Upstream Regulator PLL Interface
Detect/ PHY
Vbus Pulse
Serial
Repeater Interface Controller
Engine
3.3 V
Regulator
TT
#1
... TT
#x
Port
Controller
CRFILT
PHY#1
Port #1
OC Sense
Switch Driver/
LED Drivers
... PHY#x
Port #x
OC Sense
Switch Driver/
LED Drivers
Pinning information
SDA / SMBDATA / NON_REM[1]
SCL / SMBCLK / CFG_SEL[0]
HS_IND / CFG_SEL[1]
VBUS_DET
RESET_N
VDD33
NC
NC
NC
27
26
25
24
23
22
21
20
19
VDD33 29 17 OCS_N[2]
USBDP_UP 31
SMSC 15 VDD33
USB2512/12A/12B
XTALOUT 32 14 CRFILT
USB2512i/12Ai/12Bi
XTALIN / CLKIN 33 13 OCS_N[1]
(Top View QFN-36)
PLLFILT 34 12 PRTPWR[1] / BC_EN[1]*
Ground Pad
RBIAS 35 (must be connected to VSS) 11 TEST
VDD33 36 10 VDD33
1
2
3
4
5
6
7
8
9
USBDM_DN[1]
USBDM_DN[2]
USBDP_DN[1]
USBDP_DN[2]
VDD33
NC
NC
NC
NC
18770_301_100217.eps
100217
back to 2010-Jun-18
div. table
EN 70 8. Q552.1E LA IC Data Sheets
Block diagram
VCC
LM75B
BIAS POINTER CONFIGURATION
REFERENCE REGISTER REGISTER
TEMPERATURE
BAND GAP COUNTER
REGISTER
TEMP SENSOR 11-BIT
SIGMA-DELTA
A-to-D TOS
TIMER
CONVERTER REGISTER
OSCILLATOR
COMPARATOR/ THYST
INTERRUPT REGISTER
POWER-ON
RESET OS
Pinning information
SDA 1 8 VCC
SCL 2 7 A0
LM75BDP
OS 3 6 A1
GND 4 5 A2
18770_300_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 71
Block diagram
PNX8550x
MEMORY
CONTROLLER
TS input MPEG
CI/CA SYSTEM LVDS for
TS out/in for PROCESSOR PRIMARY flat panel display
PCMCIA VIDEO LVDS (single, dual or
OUTPUT quad channel)
DVB DVB-T/C
channel decoder
AV-PIP
SUB-PICTURE
VIDEO
CVBS, Y/C, 3D COMB
DECODER
RGB
SECONDARY VIDEO analog CVBS
VIDEO ENCODER
OUTPUT analog Y/C
Low-IF
DIGITAL IF MULTI-
Direct-IF STANDARD Motion-accurate
VIDEO pixel processing
DECODER
SCALER,
AUDIO DEMOD DE-INTERLACE
SSIF, LR
AND DECODE AND NOISE
REDUCTION
Scatter/Gather
TS Demux
I2C PWM Px_x IR ADC SPI UART I2C GPIO Flash USB 2.0 SD Ethernet
x 10 Memory MAC
Card
Pinning information
ball A1 PNX8550xE
index area 2 4 6 8 10 12 14 16 18 20 22 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
back to 2010-Jun-18
div. table
EN 72 8. Q552.1E LA IC Data Sheets
Block diagram
TPA3120D2
1 F
0.22 F
LIN BSR
22 H 470 F
RIN ROUT
1 F 0.68 F
PGNDR
PGNDL 0.68 F
1 F
BYPASS LOUT
22 H 470 F
AGND BSL
0.22 F
PVCCL
AVCC
PVCCR
VCLAMP
Shutdown
SD 1 F
Control
MUTE
GAIN0
GAIN1
} Control
Pinning information
PWP (TSSOP) PACKAGE
(TOP VIEW)
PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR
I_18020_142.eps
100402
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 73
Block diagram
Pinning information
VBST1 1 28 DRVH1
NC 2 27 LL1
EN1 3 26 DRVL1
VO1 4 25 PGND1
VFB1 5 24 TRIP1
NC
TPS53124
6 23 VIN
GND 7 22 VREG5
TEST1 8 21 V5FILT
NC 9 20 TEST2
VFB2 10 19 TRIP2
VO2 11 18 PGND2
EN2 12 17 DRVL2
NC 13 16 LL2
VBST2 14 15 DRVH2
18310_300_090319.eps
100416
back to 2010-Jun-18
div. table
EN 74 8. Q552.1E LA IC Data Sheets
Block diagram
Pinning information
DFN8 (4 × 4) PowerSO-8
I_18010_083.eps
100402
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 75
Block diagram
LD1117DT
Pinning information
DPAK
F_15710_166.eps
100402
back to 2010-Jun-18
div. table
EN 76 8. Q552.1E LA IC Data Sheets
Block diagram
MODE0 HP Auto-MDIX
MODE1 Auto- 10M Tx 10M
MODE Control
MODE2 Negotiation Logic Transmitter TXP / TXN
Reset Transmit Section
nRST Control RXP / RXN
Management 100M Tx 100M
RMIISEL SMI Logic Transmitter
Control
MDIX
Control
TXD[0:3] XTAL1/CLKIN
TXEN PLL
100M Rx DSP System: Analog-to-
TXER XTAL2
TXCLK Logic Clock Digital
Data Recovery
Interrupt
Equalizer nINT
Generator
RMII / MII Logic
RXD[0:3]
RXDV 100M PLL
RXER Receive Section
RXCLK LED1
LED Circuitry
LED2
10M Rx Squelch &
CRS Logic Filters
COL/CRS_DV
Central
RBIAS
MDC 10M PLL Bias
MDIO
PHY
Address PHYAD[0:2]
Latches
Pinning information
VDD1A
RBIAS
RXDV
TXD3
RXN
RXP
TXN
TXP
32
31
30
29
28
27
26
25
VDD2A 1 24 TXD2
LED2/nINTSEL 2 23 TXD1
LED1/REGOFF 3 22 TXD0
SMSC
XTAL2 4 LAN8710/LAN8710i 21 TXEN
VDDCR 6
(Top View) 19 nRST
RXCLK/PHYAD1 7 18 nINT/TXER/TXD4
VSS
RXD3/PHYAD2 8 17 MDC
10
11
12
13
14
15
16
9
RXD2/RMIISEL
RXD1/MODE1
RXD0/MDE0
CRS
COL/CRS_DV/MODE2
MDIO
VDDIO
RXER/RXD4/PHYAD0
18770_302_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 77
Block diagram
Pinning information
18770_303_100217.eps
100217
back to 2010-Jun-18
div. table
EN 78 8. Q552.1E LA IC Data Sheets
Block diagram
VDD 8
VDD/2
2 IN 1− VO1 1
−
+
3 BYPASS
6 IN 2−
− VO2 7
+
5 SHUTDOWN Bias 4
Control
Pinning information
D OR DGN PACKAGE
(TOP VIEW)
VO1 1 8 VDD
IN1− 2 7 VO2
BYPASS 3 6 IN2−
GND 4 5 SHUTDOWN
18770_309_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 79
Block diagram
RF_OUT
IP
RF_IN
IN
QP
AGC
QN
XTAL_OUT SDA
18770_304_100217.eps
100217
back to 2010-Jun-18
div. table
EN 80 8. Q552.1E LA IC Data Sheets
Block diagram
2 BOOT1
BP
CLK1 Level
1 PVDD1
Shift
Current
f(IDRAIN1) + DC(ofst) Comparator
S Q
+
GND 4 R
R Q
+
f(IDRAIN1)
FB1 7 Overcurrent Comp
0.8 VREF + 3 SW1
RCOMP f(ISLOPE1) BP
f(IMAX1)
VDD2 f(ISLOPE1)
Ramp
Gen 1
TSD 1.2 MHz Divide CLK1
6 A 6 A Oscilator by 2/4 f(ISLOPE2)
EN1 5 SD1 Ramp
Gen 2
Internal
EN2 6 SD2 CLK2
Control
UVLO
150 k
SEQ 10 BP
FB1 Output
150 k Undervoltage 13 BOOT2
FB2 Detect
BP
CLK2 Level
14 PVDD2
Shift
Current
Comparator FET
f(IDRAIN2) + DC(ofst)
S Q Switch
+
GND 4 R
R Q
+
f(IDRAIN2)
FB2 8
Overcurrent Comp
0.8 VREF + 12 SW2
RCOMP f(ISLOPE2) BP
f(IMAX2)
5.25-V
BP 11 PVDD2
Regulator
150 k
BP
Level
ILIM2 9
Select
UDG-07007
18770_305_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 81
Block diagram
ISEL TTX ADDR SDA SCL Vcc Byp Vcc- L
LX
Preregulator
+U.V.lockout
+P.ON reset
Controller
PWM
Rsense EN
P-GND VSEL
VSEL
TTX EN
TEN
Linear Post-reg
+Modulator
VoRX +Protections
+Diagnostics I2C Diagnostics
VoTX
22KHz
Oscill. 22KHz Tone
TTX DETIN
Amp. Diagn.
EXTM
22KHz Tone
Freq. Detector
DSQOUT
DSQIN
V CTRL LNBH23
A-GND
Pinning information
1 n.c .
2 n.c .
3 n.c .
4 LX
5 P -G N D
6 S DA Epad Connected with power grounds and to
7 n.c . the ground layer through vias
8 n.c .
to dissipate the heat.
9 S CL
10 A D DR
11 DS Q out
12 DS Q IN
13 E XTM
14 TTX
15 B Y P
16 n.c .
17 n.c .
18 V c c -L
19 V c c
20 A -G N D
21 V oRX
22 V oTX
23 n.c .
24 n.c .
25 n.c .
26 n.c .
27 V up
28 IS E L
29 D E TIN
30 V C TRL
31 n.c .
32 n.c .
18770_306_100217.eps
100217
back to 2010-Jun-18
div. table
EN 82 8. Q552.1E LA IC Data Sheets
Block diagram
RLV0~6P/M,
LLV0~6P/M
SOE,POL
LVDS
Input
Source Source Source Source
1RxA~E Driver 1 Driver 2 Driver 5 Driver 8
Internal
2RxA~E
SSIC
3RxA~E VST(GSP)
4RxA~E
ODC + OPC Gate Gate in
1RxCLK TCON Driver panel
2RxCLK 1 1
mini-LVDS
3RxCLK
GCLK1, … , GCLK3, … , GCLK6
18770_310_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 83
Block diagram
VI
Undervoltage +
Vina Lockout _
REF
Thermal
Shutdown
+
I AVG Comparator
_
REF
V V (COMP) 1-MHz
I Oscillator
P-Channel
Comparator S
+ Driver SW
R
_ Control Shoot-Through
Sawtooth
Logic Logic
Generator N-Channel
+
+
_
_ PG
SKIP Comparator +
_
+ _ LBO
Compensation R1
Gm
_ R2 +
+ +
_ _
EN REF
FB LBI P G ND GND
A. The internal feedback divider is disabled and the FB pin is directly connected
to the internal GM amplifier.
Pinning information
P G ND
SW
SW
PG
16 15 14 13
PGND 1 12 GND
Exposed
VIN 2 Thermal
11 GND
Pad
VIN 3 10 FB
EN 4 9 AGND
5 6 7 8
LBI
LBO
V IN A
S Y NC
18770_311_100217.eps
100217
back to 2010-Jun-18
div. table
EN 84 8. Q552.1E LA IC Data Sheets
Block diagram
VIN (12V)
BST
IN2 VL
LX1
3.3V
2A LX2 STEP-UP
STEP-DOWN OSC
PGND
GND2 FB1
COMP
OUT
AGND
FSEL
VL
SWI
P
150mV SWO AVDD
FB2 16V
1.5A
VIN 3.3V
VIN
VL VL
VL PGOOD
PGOOD
RESET CRST
REF
REF REF
AGND DRN
FBN FBP
AVDD
REF
Pinning information
PGND
DEL2
FSEL
OUT
EN2
EN1
IN2
IN2
VIN
VL
30 29 28 27 26 25 24 23 22 21
PGND 31 20 LX2
LX1 32 19 LX2
LX1 33 18 BST
TOP VIEW SWI 34 17 FB2
THIN QFN SWO 35 16 DEL1
FB1 36 MAX17113 15 REF
COMP 37 14 FBN
PGOOD 38 13 AGND
CRST 39 12 DRVN
AGND 40 11 CTL
1 2 3 4 5 6 7 8 9 10
MODE
GND2
CPGND
GON
DRN
DVRP
THR
DLP
FBP
SRC
18770_312_100217.eps
100217
2010-Jun-18 back to
div. table
IC Data Sheets Q552.1E LA 8. EN 85
HVS SAWTOOTH
CM1
LOGIC GENERATOR
GM AMPLIFIER
FBB - SLOPE LX1
+ COMPENSATION LX2
VREF BUFFER
CONTROL
Ε
UVLO COMPARATOR LOGIC
-
+
RSENSE
CURRENT PGND1
0.75 VREF AMPLIFIER PGND2
680kHz
FREQ
OSCILLATOR
VL
CDEL AND
CURRENT LIMIT
EN SEQUENCE CONTROLLER THRESHOLD
VL
PVIN1,2 CB
SUPN
LXL1
LXL2
NOUT CONTROL
LOGIC
CURRENT
BUFFER CM2
LIMIT GM AMPLIFIER
COMPARATOR CURRENT AMPLIFIER
FBN - - FBL
+ - Ε +
+
0.2V VREF
CURRENT LIMIT SLOPE
THRESHOLD COMPENSATION
UVLO COMPARATOR
- SAWTOOTH
+ GENERATOR
0.4V
POUT
SUPP
Pinning information
LDO-CTL
LDO-FB
PGND2
PGND1
AGND
PVIN1
TEMP
PROT
LX2
LX1
40 39 38 37 36 35 34 33 32 31
PVIN2 1 30 COMP
CB 2 29 FBB
LXL1 3 28 RSET
LXL2 4 27 HVS
PGND3 5 ISL97653A 26 EN
40 LD 6X6 QFN
PGND4 6 TOP VIEW 25 CDEL
CM2 7 24 CTL
FBL 8 23 DRN
VL 9 22 COM
VREF 10 21 POUT
11 12 13 14 15 16 17 18 19 20
SUPP
FBP
PGND5
C1P
C2P
FBN
SUPN
NOUT
C1N
C2N
18770_307_100217.eps
100217
back to 2010-Jun-18
div. table
EN 86 8. Q552.1E LA IC Data Sheets
Personal Notes:
10000_012_090121.eps
090121
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 87
9. Block Diagrams
9-1 Wiring diagram Rembrandt 32"
WIRING DIAGRAM 32" REMBRANDT
1M95 (B03C) 1M99 (B03C) 1735 (B03A) 1M20 (B09A) 1JA1 (B11C) 1JA2 (B11C)
1. +3V3-STANDBY 1. +12VD 1. LEFT-SPEAKER 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND-AUDIO 2. GND | |
3. GND 3. GND 3. GND-AUDIO 3. RC 36. VCC 19. VDD
4. GND 4. GND 4. RIGHT-SPEAKER 4. LED-2 37. VCC 20. VDD
5. GND 5. LAMP-ON 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 41. VDD 24. VCC
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 42. VDD 25. VCC
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 60. GND 60. GND
10. GND-AUDIO
11. MAINS-OK
LOUDSPEAKER
(5213)
1316
1P3
1M99
9P
8M20
1M20 1JA2 1JA1
1M95
11P
8P
8JA1
60P 60P
8JA2
HIGH VOLTAGE
CONDITIONAL ACCESS
(1150)
IPB 32 PLHC-P981A B
(1005)
1M99
8M99
9P
1M95
KEYBOARD CONTROL
11P
8M95
1735
4P
2P3 2P3
1311 1308
N L
TUNER
USB
TO BACKLIGHT
TO BACKLIGHT
MAINS CORD
(1114)
8191
HDMI
HDMI
PHONE
HDMI HDMI VGA
3P
J1
SCART
8311
(8311)
18770_400_100217.eps
100225
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 88
1M95 (B03C) 1M99 (B03C) 1735 (B03A) 1M20 (B09A) 1JA1 (B11C) 1JA2 (B11C)
1. +3V3-STANDBY 1. +12VD 1. LEFT-SPEAKER 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND-AUDIO 2. GND | |
3. GND 3. GND 3. GND-AUDIO 3. RC 36. VCC 19. VDD
4. GND 4. GND 4. RIGHT-SPEAKER 4. LED-2 37. VCC 20. VDD
5. GND 5. LAMP-ON 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 41. VDD 24. VCC
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 42. VDD 25. VCC
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 60. GND 60. GND
10. GND-AUDIO
11. MAINS-OK
1316
1P3
1M99
9P
8M20
1M20 1JA2 1JA1
1M95
11P
8P
8JA1
60P 60P
8JA2
HIGH VOLTAGE
IPB 37 PLHD-P982A B B
CONDITIONAL ACCESS
(1150)
IPB 42 PLHF-P983A B
1M99
8M99
9P
(1005)
1M95
KEYBOARD CONTROL
11P
8M95
1735
4P
2P3 2P3
1311 1308
N L
USB
TUNER
TO BACKLIGHT
TO BACKLIGHT
MAINS CORD
(1114)
8191
HDMI
HDMI
PHONE
HDMI HDMI VGA
3P
J1
SCART
8311
18770_401_100217.eps
100224
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 89
8KA2
1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1KA1 (B14E) 1KA2 (B14E)
1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. GND 1. GND
2. STANDBY 2. +12VD 2. GND | |
3. GND 3. GND 3. RC 11. VLS_15V6 11. VLS_15V6
4. GND 4. GND 4. LED-2 12. VLS_15V6 12. VLS_15V6
5. GND 5. LAMP-ON LOUDSPEAKER 5. +3V3-STANDBY | |
6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 33. VCC_3V3 33. VCC_3V3
(5213)
7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 34. VCC_3V3 34. VCC_3V3
8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V | |
9. +24V-AUDIO-POWER 9. POWER-OK 78. VGH_35V 78. VGH_35V
10. GND-AUDIO 79. VGL_-6V 79. VGL_-6V
11. MAINS-OK 1735 (B03A) 80. GND 80. GND
1. LEFT-SPEAKER
KEYBOARD CONTROL
2. GND-AUDIO
3. GND-AUDIO
4. RIGHT-SPEAKER
8M20
32"-12P
1319
1316
8P 80P 80P
1M99
9P
SSB
40"-10P
32"-6P
B
1316
1319
3P
J1
CONDITIONAL ACCESS
(1150)
1M99
8M99
9P
1M95
11P
1M95
11P
8M95
TO BACKLIGHT
32"- FSP124-3MS01 B
40"- DPS-206CP A B
1735
4P
(1005)
USB
TUNER
HDMI
PHONE
SPDIF
HDMI HDMI VGA
SCART
2P3 2P3
1311 1308
N L
8311
MAINS CORD
8191
TWEETER TWEETER
(5216) (5216)
MAINS
J2 J1 IR / LED BOARD
NOT FOR 32" TV-SETS SWITCH NOT FOR 32" TV-SETS
3P 8P (1112)
(8311)
18770_402_100217.eps
100308
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 90
8M83
8M09
TO BACKLIGHT
8JA1
8JA2
8M20
8M59
8M20
1M83
25P
1M84
25P
1M20 1JA2 1JA1 1M72 1M59
1319 1316 1M09 8P 60P 60P 4P 23P
12P 13P 4P
SSB
B
1M99
CONDITIONAL ACCESS
9P
(1150)
1M99
8M99
9P
1M95
11P
1735
KEYBOARD CONTROL
SUB-WOOFER
4P
USB
(5214) ETHER
32" DPS-199DP-1 A B NET
1D38
3P
37" PLDD-P973A B
TUNER
(1005) SCART
HDMI
(1114)
SPDIF
HDMI HDMI HDMI VGA
SCART
(1174)
3P
J1
AL (1174)
AL
Board Level Repair
1M83
25P
1311 1308
MAINS CORD
8191
TO DISPLAY LCD DISPLAY TO DISPLAY
(1004)
8311
SPEAKER R SPEAKER L
MAINS
(5215) (5215)
SWITCH
1M38 (AL1A) 1M48 (AL2A) 1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1735 (B03A) 1JA1 (B11C) 1JA2 (B11C) 1M59 (B13)
1. +24V 14. +3V3 1. SPI-CLOCK-BUF 14. N.C. 1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. LEFT-SPEAKER 1. GND 1. GND 1. AMBI-SPI-CLK-OU 15. AMBI-TEMP
2. +24V 15. BLANK 2. SPI-DATA-OUT 15. TEMP-SENSOR 2. STANDBY 2. +12VD 2. GND 2. GND-AUDIO | | 2. AMBI-SPI-SDO-OUT 16. GND
3. +24V 16. PROG 3. SPI-DATA-RETURN 16. GND 3. GND 3. GND 3. RC 3. GND-AUDIO 36. VCC 19. VDD 3. AMBI-SPI-SDI-OUT-GI 17. GND
4. +24V 17. GND 4. GND 17. GND 4. GND 4. GND 4. LED-2 4. RIGHT-SPEAKER 37. VCC 20. VDD 4. GND 18. GND
5. +24V 18. LATCH 5. PWM-CLOCK-BUF 18. GND 5. GND 5. LAMP-ON 5. +3V3-STANDBY | | 5. AMBI-PWM-CLK_B2 19. GND
6. GND 19. SPI-CS 6. +3V3 19. GND 6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 41. VDD 24. VCC 6. V-AMBI 20. GND
7. GND 20. +3V3 7. SPI-CS 20. GND 7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 1D38 (B03A) 42. VDD 25. VCC 7. AMBI-SPI-CS-OUTn_R2 21. +24V
8. GND 21. PWM-CLOCK 8. LATCH 21. +24V 8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V 1. LEFT-SPEAKER | | 8. AMBI-LATCH1_G2 22. +24V
9. GND 22. GND 9. GND 22. +24V 9. +24V-AUDIO-POWER 9. POWER-OK 2. GND-AUDIO 60. GND 60. GND 9. GND 23. +24V
10. GND 23. SPI-DATA-RETURN 10. PROG 23. +24V 10. GND-AUDIO 3. RIGHT-SPEAKER 10. AMBI-PROG_B1 24. +24V
11. TEMP-SENSOR 24. SPI-DATA-IN 11. BLANK 24. +24V 11. MAINS-OK 1M72 (B13) 11. AMBI-BLANK_R1 25. +24V
12. N.C. 25. SPI-CLOCK 12. +3V3 25. +24V 1. +24V 12. V-AMBI
13. N.C. 13. N.C. 2. +24V 13. AMBI-LATCH2_DIS
3. GND 14. AMBI-SPI-CS-EXTLAMPSn
4. GND
18770_403_100217.eps
100423
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 91
8M83
8M59
8M20
1M83
25P
1M84
25P
1M20 1M59 1G51 1G50
1319 1316 1M09 8P 1M09 23P 51P 41P
4P 4P
SSB
B
1M99
CONDITIONAL ACCESS
9P
(1150)
1M99
8M99
9P
1M95
11P
1M95
11P
8M95
AMBILIGHT MODULE 24 LED
1735
KEYBOARD CONTROL
4P
USB
ETHER
DPS-199DP A B NET
(1005)
TUNER
SCART
HDMI
(1114)
SPDIF
HDMI HDMI HDMI VGA
SCART
3P
J1
(1174)
(1174)
8735
AL
AL
1308
2P3
2P3
1311
TO DISPLAY TO DISPLAY
1M83
+ -
+ -
25P
LOUDSPEAKER RIGHT LCD DISPLAY LOUDSPEAKER LEFT
(5215) (1004) (5215)
MAINS CORD
TCON
8191
8311
MAINS
SWITCH
1M59 (B13) 1M38 (AL1A) 1M48 (AL2A) 1M95 (B03C) 1M99 (B03C) 1M20 (B09A) 1735 (B03A) 1G51 (B06B) 1G50 (B06B)
1. AMBI-SPI-CLK-OU 15. AMBI-TEMP 1. +24V 14. +3V3 1. SPI-CLOCK-BUF 14. N.C. 1. +3V3-STANDBY 1. +12VD 1. LIGHT-SENSOR 1. LEFT-SPEAKER 1. +VDISP 1. GND
2. AMBI-SPI-SDO-OUT 16. GND 2. +24V 15. BLANK 2. SPI-DATA-OUT 15. TEMP-SENSOR 2. STANDBY 2. +12VD 2. GND 2. GND-AUDIO 2. +VDISP 2. GND
3. AMBI-SPI-SDI-OUT-GI 17. GND 3. +24V 16. PROG 3. SPI-DATA-RETURN 16. GND 3. GND 3. GND 3. RC 3. GND-AUDIO 3. +VDISP |
4. GND 18. GND 4. +24V 17. GND 4. GND 17. GND 4. GND 4. GND 4. LED-2 4. RIGHT-SPEAKER 4. +VDISP |
5. AMBI-PWM-CLK_B2 19. GND 5. +24V 18. LATCH 5. PWM-CLOCK-BUF 18. GND 5. GND 5. LAMP-ON 5. +3V3-STANDBY | 40. N.C.
6. V-AMBI 20. GND 6. GND 19. SPI-CS 6. +3V3 19. GND 6. +12V 6. BACKLIGHT-PWM_BL-VS 6. LED-1 51. CTRL-DISP 41. N.C.
7. AMBI-SPI-CS-OUTn_R2 21. +24V 7. GND 20. +3V3 7. SPI-CS 20. GND 7. +12V 7. BACKLIGHT-BOOST 7. KEYBOARD 1M09 (B09)
8. AMBI-LATCH1_G2 22. +24V 8. GND 21. PWM-CLOCK 8. LATCH 21. +24V 8. +12V 8. BACKLIGHT-PWM-ANA-DISP 8. +5V 1. +24V
9. GND 23. +24V 9. GND 22. GND 9. GND 22. +24V 9. +24V-AUDIO-POWER 9. POWER-OK 2. +24V
10. AMBI-PROG_B1 24. +24V 10. GND 23. SPI-DATA-RETURN 10. PROG 23. +24V 10. GND-AUDIO 3. GND
11. AMBI-BLANK_R1 25. +24V 11. TEMP-SENSOR 24. SPI-DATA-IN 11. BLANK 24. +24V 11. MAINS-OK 4. GND
12. V-AMBI 12. N.C. 25. SPI-CLOCK 12. +3V3 25. +24V
13. AMBI-LATCH2_DIS 13. N.C. 13. N.C. 18770_404_100217.eps
14. AMBI-SPI-CS-EXTLAMPSn 100423
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 92
68P
LOUT1 PX1 PX1 37
36
+VCC
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 TO DISPLAY TO TCON SSB 34 TO DISPLAY
ACCESS (TCON ON DISPLAY) (TCON ON SSB)
LML
21
CA-MDI(0-7) MDI LOUT2 PX2 PX2
3 13
B07A DVBS-FE 7R02 7R01 B01K TUNER BRAZIL 7JC1
GMA
2
STV6110AT STV0903BAC 41 MAX9668ETP
N.C. 1
1R01
4 DVB-S 21 IP 7 DVB-S 78 TS-DVBS-VALID 9F27-4 TS-FE-VALID R23 TNR_SER1_MIVAL TIMING
TUNER IM CHANNEL TS-DVBS-SOP 9F27-2 TS-FE-SOP R22 CONTROL GAMMA
SAT IN 20 8
DECODER
75 TNR_SER1_SOP QUAD LVDS 1JA2
XTAL 74 TS-DVBS-CLOCK 9F28 TS-FE-CLOCK T22 REF 60
32 122 TNR_SER1_MICLK 1G51 1920x1080
30 18 QP 12 73 TS-DVBS-DATA 9F27-1 TS-FE-DATA T21 TNR_SER1_DATA SYST 59
N.C.
51 100/120HZ
19 QM 11 50 GMA
1R10
16M
48
2 AGC 16 SSB 3104 313 6401* I2C 49
31 40
SSB 3104 313 6405*
SSB 3104 313 6372* 40 RML
27
B01F HDMI & CI
7F75 LOUT3 PX3 PX3
25
+5V-TUN-PIN UPC3221GV TO DISPLAY
1T01 1 B02I ANALOG VIDEO TO DISPLAY
B11B TCON DC/DC +VDD
24 (TCON ON SSB)
TH2603 VCC TO TCON SSB 20
(TCON ON DISPLAY) 7JD1
2F90 1F75
10 TUN-IF-P 5F73 1 4 2F74 2 AGC AMPLIFIER 7 3F79-1 PNX-IF-P AE12
TUNER_P MAX17119ET 19
IF-OUT1 +VCC
BANDPASS
5F70
LOUT4 PX4 PX4 13
2F78 40
11 TUN-IF-N 2 5 3 6 3F79-4 FILTER PNX-IF-N AF12 GCLK CLK
RF IN IF-OUT2 TUNER_N LEVEL 2
SAW 36MHZ17 4 IN OUT 4 SHIFTER
1
7F70 AGC CONTROL
3
MAIN HYBRID SELECT-SAW
SSB 3104 313 6401*
B02E 2 SSB 3104 313 6402*
TUNER SSB 3104 313 6406*
CONTROL 1
PNX-IF-AGC AD12 +VDISP
IF_AGC B14A TCON CONTROL (SHARP) B14E MINI LVDS (SHARP)
OR
1KA1
81
7KAA B14C P GAMMA & 58
UPD809900F VOM & FLASH
B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A 7KQB
53
M25P32 42
SPI
1E01
15 AV1-R AC13
PNX85500 PX1
SDO
SCS
SCK
FLASH
+VDD
41
37
36
AV1_R +VCC
1 11 AV1-G AE13 50 TO DISPLAY
AV1_G TO TCON SSB
AVI-B (TCON ON SSB)
7 AD13 L_LV
AV1_B 13
7 20 AV1-CVBS AB15
CVBS_Y1 PX2
EXT 1 7E05 13
7EC1 11
SII9187ACNU 19 GMA
15 7E09-1 7KQA 2
SII9287BCNU 16
16 AV1-BLK ISL24837IRZ 1
20
B02G
1P05 21
CONTROL TIMING
8 AV1-STATUS
1 90
SCART1 B02G 7E06 CONTROL REF 1KA2
DRX2+
CONTROL CVBS-MON-OUT1 AF11 VOLTAGE 81
3 DRX2- 89 CVBS1_OUT
1E02 GEN 59
1
4
2
DRX1+ 87
6 15 AV4-PR AC14 GMA
DRX1- 86 AI33 48
RXD 1 11 AV4-Y AE14
7 DRX0+ 84 AI13
7 AV4-PB AD14 AI23 50
9 DRX0- 83
18
7
19
SHIFTER
2
USB HUB
15
VGA_G
5
CONNECTOR
11
14 V-SYNC-VGA AC18 1
VSYNC_IN
Only 7000 Serie
1
R26 USB-DM 9F26 USB-DM2 2
SIDE USB
2
VGA USB_DN
R25 USB-DP 9F25 USB-DP2 3
3
CONNECTOR USB_DP CONNECTOR
9,27,64 4
4
+3V3-HDMI VCC33
B04B ANALOGUE EXTERNALS B B02A FLASH B01B FLASH
Styling Matisse
7F20
1E04 NAND02GW3B2DN6F
AV3-PR AC15 +5V-USB1
2 NAND04GW3B2DN6F
PR PR_R_C1 1P07
1E08 1
AV3-Y NAND
1
1P03 EXT 3 2 AE15 9F21 2
Y Y_G1 USB-DM1
FLASH SIDE USB
2
1 BRX2+ 42 1E03 XIO_D XIO-D(00-07) 9F20 USB-DP1 3
3
AV3-PB CONNECTOR
3 BRX2- 41 2 AD15 4
4
PB PB_B1
256MB
1
2
4 BRX1+ 39
6 BRX1- 39 1ECB Y-SVHS AC12
ATV_CVBS_Y3
512MB Styling Rembrandt
RXB 1 Van Gogh
7 BRX0+ 36 3
SVHS IN 5 C-SVHS AF13 12,37
9 BRX0- 35 CR VCC +3V3
18
19
4
10 BRXC+ 33 2
HDMI 2 12 BRXC- 32 5000 Serie 256MB
CONNECTOR 7000 Serie 512MB
B02C HDMI_DV B02B MEMORY
B05A DDR
1P02 62 HDMIA-RXC+ W25
TXC_P RXC_B_N
1 CRX2+ 72 63 HDMIA-RXC- W26 DQ DDR2-D(0-31)
TXC_N RXC_B_P
3 CRX2- 71 60 HDMIA-RX0+ V25 7B00 7B02
TX0_P RX0_B_N
EDE1116AGBG EDE1116AEBG 7B03 7B01
D(16-23)
D(24-31)
1
D(8-15)
4 CRX1+ 69 61 HDMIA-RX0- V26
2
D(0-7)
TX0_N RX0_B_P EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
6 CRX1- 68 58 HDMIA-RX1+ U25
RXC TX1_P RX1_B_N
7 CRX0+ 66 59 HDMIA-RX1- U26
TXA_N RX1_B_P SDRAM SDRAM SDRAM SDRAM
9 CRX0- 65 56 HDMIA-RX2+ T25
RX2_B_N 128MB 128MB 128MB 128MB
18
TX2_P
19
VDDL
VREF
VDDL
VREF
VDDL
VREF
VDDL
VREF
+3V3 RREF
CONNECTOR
A1 E2 A1 E2 A1 E2 A1 E2
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 93
68P
7S05 PVCC_R
LM324P 1735
ADAC(1) 12 14 +AUDIO-L 5 22 LEFT-SPEAKER 1
CONDITIONAL MDO(0-7) BUFFER CA-MDO(0-7) MD0 AD7 OUT-L
ADAC_1 IN-L
ACCESS
CLASS D 2
CA-MDI(0-7) MDI POWER
SPEAKER L
AMPLIFIER
3
B07A DVBS-FE ADAC_2
AE7 ADAC(2) 10 8 -AUDIO-R 6
IN-R
7R02 7R01
STV6110AT STV0903BAC 7D15 15 RIGHT-SPEAKER 4
OUT-R
A-PLOP A-STBY 2
4 DVB-S 21 IP 7 DVB-S 78 TS-DVBS-VALID B03H STANDBY A-PLOP SD SPEAKER R
TNR_SER1_MIVAL B04E
TUNER IM CHANNEL TS-DVBS-SOP 1D38
SAT IN 20 8 75 TNR_SER1_SOP
30 XTAL
DECODER TS-DVBS-CLOCK AC19 AUDIO-MUTE-UP 4 1
32 122 74 TNR_SER1_MICLK PO_7 MUTE
18 QP 12 73 TS-DVBS-DATA 5D03
1R10
2
16M
TNR_SER1_DATA
19 QM 11 7D03 7D03
DETECT2 3
31 B02G MAIN SWITCH A-STBY STANDBY &
Only For DVBS MAINS-OK PROTECTION
B03C DETECT SUBWOOFER
(OPTIONAL)
B01F HDMI & CI
7F75
+5V-TUN-PIN
1T01
UPC3221GV
B02I ANALOG VIDEO
B04E HEADPHONE B01J TEMP SENSOR + HEADPHONE
1
TH2603 VCC
2F90 1F75 2F74 AGC AMPLIFIER 7 3F79-1 7EE0-1 7EE0-2
10 TUN-IF-P 5F73 1 4 2 PNX-IF-P AE12
IF-OUT1 TUNER_P AD1 RESET-AUDIO A-PLOP B03A
BANDPASS PO_6
5F70
B04A
11 TUN-IF-N 2 5 2F78 3 6 3F79-4 FILTER PNX-IF-N AF12
RF IN IF-OUT2 TUNER_N
SAW 36MHZ17 4 IN OUT
7F70 AGC CONTROL
MAIN HYBRID SELECT-SAW
7EE1
B02E TPA6111A2DGN
TUNER
CONTROL PNX-IF-AGC AD12
IF_AGC
HEADPHONE
AMPLIFIER
5
SHUTDOWN 1328
1 AMP1 2
VO_1
B01H HDMI B04D HDMI B04A ANALOGUE EXTERNALS A B02D PNX85500: AUDIO
ADAC3
AF7 ADAC(3) 2
IN-1 7 AMP2 3
1E01-1 VO_2
7EC1
3 AP-SCART-OUT-L 3EA7-1 7S05 1 HEADPHONE
SII9187ACNU AUDIO-OUT-L 1 3 ADAC(5) AE6
1 ADAC_5 AD6 ADAC(4) 6 8 OUT 3.5mm
SII9287BCNU ADAC4 IN-2 VDD +3V3
1 AP-SCART-OUT-R 3EA7-4 AUDIO-OUT-R ADAC(6)
7 5 AF6 ADAC_6
7
1P05
1
3
DRX2+
DRX2-
90
89
16
11
15
6 AUDIO-IN1-L AE10 AIN1_L
PNX85500 B01C USB HUB
1
4
2
10 81 1P08
DRXC+ 1 3 AP-SCART-OUT-L 7E01
A-PLOP 1
HDMI SIDE 12 DRXC- 80 A-PLOP B03C
1
R26 USB-DM 9F26 USB-DM2 2
CONNECTOR 1 SIDE USB
3 2
7 AP-SCART-OUT-R USB_DN
R25 USB-DP 9F25 USB-DP2 3
USB_DP CONNECTOR
4
HDMI 11
4
6 AUDIO-IN2-L AD10
1P04 15 AIN2_L
1 23
SWITCH 16
7000 Serie
ARX2+
20
2 AUDIO-IN2-R AC10
AIN2_R B02A FLASH B01B FLASH
3 ARX2- 22 21 +5V-USB1
1
SCART2 1P07
2
4 ARX1+ 20 7F20
Only 7000 Serie 1
6 ARX1- 19 NAND02GW3B2DN6F
1
RXA 9F21 USB-DM1 2
7 ARX0+ 17 NAND04GW3B2DN6F SIDE USB
3 2
9 16
B04B ANALOGUE EXTERNALS B 9F20 USB-DP1 3
CONNECTOR
18
ARX0- NAND
19
4
10 14 1E08
ARXC+ FLASH
HDMI 3 12 ARXC- 13 6 AUDIO-IN3-L AE9 XIO_D XIO-D(00-07)
AIN3_L
CONNECTOR
Only 7000 Serie
AUDIO IN
4
256MB 5000 Serie
L+R AUDIO-IN3-R AF9
AIN3_R 512MB
9,27,64
+3V3-HDMI VCC33 12,37
1E09 VCC +3V3
2 AUDIO-IN4-L AD9
AIN4_L
VGA (OR DVI)
5000 Serie 256MB
AUDIO 3 AUDIO-IN4-R AC9
AIN4_R 7000 Serie 512MB
1
+3V3
1P03 B02B MEMORY
1 BRX2+ 42
1E07 7S09 B05A DDR
2
DIGITAL 1 SPDIF-OUT 3 &
3 BRX2- 41 1 SPDIF-OUT-PNX AF5
AUDIO SPDIF_OUT
1
2
4 BRX1+ 39 OUT 4
6 BRX1- 39 B02G STANDBY
RXB DQ DDR2-D(0-31)
7 BRX0+ 36 7B00 7B02
8 5 SEL-HDMI-ARC AF18
35 P0_4 EDE1116AGBG EDE1116AEBG 7B03 7B01
D(16-23)
D(24-31)
9 BRX0-
D(8-15)
18
D(0-7)
19
VDDL
VREF
VDDL
VREF
VDDL
VREF
VDDL
VREF
1 72 60 HDMIA-RX0+ V25
CRX2+ RX0_B_N
3 CRX2- 71 61 HDMIA-RX0- V26
RX0_B_P
58 HDMIA-RX1+ U25
1
4 CRX1+ 69 A1 E2 A1 E2 A1 E2 A1 E2
2
RX1_B_N
6 68 59 HDMIA-RX1- U26
CRX1- RX1_B_P A DDR2-A(0-13)
RXC 56 HDMIA-RX2+ T25
7 CRX0+ 66 RX2_B_N
HDMIA-RX2- T26 +1V8
9 CRX0- 65 57 RX2_B_P
18
DDR2-VREF-DDR
19
10 CRXC+ 63
12 62 3S0W W24 5000 Serie 256MB
HDMI 1 CRXC- 7000 Serie 512MB
+3V3 RREF
CONNECTOR A2
14 5EC2 VREF_1 DDR2-VREF-CTRL2
ARC-eHDMI+ eHDMI+ V1
VREF_2 DDR2-VREF-CTRL3
5000 Serie mux SIL9187 - non Instaport 18770_406_100217.eps
7000 Serie mux SIL9287 - Instaport 100330
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 94
Pin9
CMD
Pin1
5 SDIO-CLK W1 30 AMBI-SPI-CS-OUTn_R2 7
Pin2
CLK
Pin3
Pin4
7 SDIO-DAT0 W5 31 AMBI-LATCH1_G2 8 TO AMBILIGHT
Pin6 Pin5
DAT_0
Pin8 Pin7
8 SDIO-DAT1 W4 AMBI-PROG_B1 10 MODULE
9 SDIO-DAT2 W3
DAT_1
DAT_2
PNX85500 B02G
19
20 AMBI-BLANK_R1 11
SD-CARD 10 SDIO-CDn U6 13
B02E CONTROL V22 PNX-SPI-CS-BLn 3 28 AMBI-LATCH2_DIS
CONNECTOR SDCD
12 SDIO-WP V6 W23 PNX-SPI-CS-AMBIn 2 21 AMBI-SPI-CS-EXTLAMPSn 14
SDWP
32 AMBI-TEMP 15
VCCIO
B04C ETHERNET + SERVICE B02A
B02H POWER AF1 SENSE+1V1
26
7E10 VDD_1V1 B03B VIO
AA15 SENSE+1V2
LAN8710A-EZK VDDA_1V2 B03D
ETH-RXD SDCD
ETHERNET ETH-TXD SDWP
B02B MEMORY B05A DDR
7 ETH-RXCLK AA3
TXCLK DQ DDR2-D(0-31)
20 ETH-TXCLK AA2 7B00 7B02
RXCLK
7B03 7B01
D(16-23)
D(24-31)
EDE1116AGBG EDE1116AEBG
D(8-15)
ETHERNET
D(0-7)
CONNECTOR EDE1108AGBG EDE1108AGBG EDE1108AGBG EDE1108AGBG
RJ45
SDRAM SDRAM SDRAM SDRAM
B07A DVBS-FE B01K TUNER BRAZIL
128MB 128MB 128MB 128MB
B02A VIDEO STREAM
7R02 7R01
STV6110AT STV0903BAC
32 XTAL 122 73 TS-DVBS-DATA 9F27-1 TS-FE-DATA T21
18 QP 12 74 TS-DVBS-CLOCK 9F28 TS-FE-CLOCK T22 F8 E8 F8 E8 F8 E8 F8 E8
SATELLITE MULTI
19 QM 11 STANDARD 75 TS-DVBS-SOP 9F27-2 TS-FE-SOP R22 DDR2-A(0-13)
TUNER A
21 IP 7 DEMODULATOR 78 TS-DVBS-VALID 9F27-4 TS-TS-VALID R23 DDR-CLK_N
FOR SAT DIG TV CLK_N
20 IM 8 62 RESET-DVBS DDR-CLK_P
CLK_P
B02G
SENSE+1V0-DVBS 52 5000 Serie 7000 Serie
A80B
B01B FLASH B01A COMMON INTERFACE B02E CONTROL B02E PNX85500: MIPS B01C USB HUB
U23 SELECT-SAW
1P00 GPI0_11 B01F
MDO U23 BACKLIGHT-PWM
1 CA-MDI(0-7) GPI0_11 B13
AC5 PXCLK54
7F01 CLK_54_OUT B06C B13
AE4 RESET-SYSTEMn +5V-USB2
RESET_SYS B01K B02G
W23 PNX-SPI-CS-AMBIn 1P08
GPI0_6 B06E B06D B13
V22 PNX-SPI-CS-BLn 1
GPI0_7 B01K B02G B02G
1
MDO(0-7) CA-MDO(0-7) MDI R26 USB-DM 9F26 USB-DM2 2
COMMON INTERFACE
3 2
7F02 R25 USB-DP 9F25 USB-DP2 3
USB_DP CONNECTOR
7F03 B02A FLASH 4
4
PCMCIA
7F20
NAND02GW3B2DN6F
B04V ETHERNET + SERVICE
CA-A(00-14) XIO-A(0-14) XIO_A
NAND04GW3B2DN6F +5V-USB1
CONDITIONAL 1E06
7F04 Y23 RXD1-MIPS 1P07
NAND ACCESS GPI0_2 2
1
7F05 UART
FLASH
1
12,37 Y24 TXD1-MIPS 3 SERVICE 9F21 USB-DM1 2
GPI0_3 SIDE USB
3 2
VCC +3V3 CONNECTOR 9F20 3
1 USB-DP1 CONNECTOR
256MB CA-D(0-7) XIO-D(00-15) XIO_D 4
4
68
512MB
CONTROL
AV2-STATUS AE24 AE17
B04A CADC_3 XTAL_I
LCD-PWR-ONn AC20
B03H P2_0
1S02
54M +12V
ENABLE -3V3-5V
B03E
B04D HDMI AF17 +3V3-STANDBY ENABLE -1V8
XTAL_O B03B B03D
TO PIN: AD21 ENABLE-3V3n DETECT2
7EC0 P2_7 B02G B03A
1P02-13
EF
1P03-13 PCEC-HDMI CEC-HDMI AF19
P1_2
1P04-13 AF18 SEL-HDMI-ARC 1M99
P0_4 B02D
1
2
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 95
3S6D
3S6E
B02E
B25 3S5Y SDA-SSB
3_SDA
A24 3S5Z SCL-SSB
3_SCL
3EC5
3EC3
3FD3
3FD4
3FE9
3FE8
3R00
3R01
+3V3 +3V3RF
3T61
3T51
AIN-5V
ERR
PNX85500 13
53 54 46 45 1 2 98 97 6 9
3EC1-1
3EC1-3
3S6A
3R15
3R14
3S69
CONTROL 1P04
C25 3S56 SDA-UP-MIPS 1F52 7EC1 7FE0 7FD1 7R01 W21 SDAT 7T50
29 ARX-DDC-SDA 16
1
2
1_SDA 3F63 3 SII9287B TC90517FG LM75BDP STV903BAC LNBH23QT
C26 3S57 SCL-UP-MIPS SII9187A W22 SCLT
DEBUG 30 ARX-DDC-SCL 15
1_SCL 3F62 1 TUNER TEMP CHANEL DEC LNB
7F52 ONLY
18
19
HDMI BIN-5V BRAZIL SENSOR DVBS CONTROLLER
3F63
3F59
M25P05-AVMN6P B02G B02G PNX85500: STANDBY MUX HDMI
CONTROLER
5 6 CONNECTOR 3 13 12
3ECA-1
3ECA-2
ERR ERR ERR
FLASH 6 PNX-SPI-CLK AF24 +3V3-STANDBY ERR 1P03 42 28 31
8 SPI_CLK 23
3 PNX-SPI-WPn AE22 STANDBY 7F58 33 BRX-DDC-SDA 16 7R02
1
+3V3-STANDBY VCC
2
P6_5
M24C64 STV6110A
3S6W
512K 1 PNX-SPI-CSBn AF23
3S6V
SPI_CSB 34 BRX-DDC-SCL 15
5 PNX-SPI-SDO AE23 ERR ERR 3S2F
18
SPI_SDO
19
15 53 AC23 EEPROM CIN-5V SATELITE
2 PNX-SPI-SDI AF25 SPI_SDI MC_SDA (NVM) TUNER
3S2G HDMI RES RES
STANDBY AC24 CONNECTOR 2
MC_SCL B01H
3ECA-3
3ECA-4
SW ERR
HDMI ERR
RES 1P02
35 36
39 CRX-DDC-SDA 16
1
2
+3V3-STANDBY
MAIN NVM
40 CRX-DDC-SCL 15
SW
B01B
18
FLASH
19
DIN-5V
3S1G
3S1H
1F51 HDMI
AE21 RXD-UP 3F65 1 uP
7F20 CONNECTOR 1
3FBF-2
3FBF-1
P3_0 LEVEL SHIFTED +3V3 1P05
NAND02GW3B2DN6F 3F64
NAND04GW3B2DN6F AF21 TXD-UP 2 FOR DEBUG
P3_1 43 DRX-DDC-SDA 16
1
HDMI
2
USE ONLY
3ECU-2
3ECU-4
CONNECTOR
FLASH 44 DRX-DDC-SCL 15
B02A B02I SIDE
18
Y25 DDCA-SDA
19
(4Gx16) DDC_A_SDA
FLASH Only for sets with DVBS
Y26 DDCA-SCL
XIO-D(00-07) XIO_D DDC_A_SCL +3V3 B01I VGA
HDMI_DV B04C ETHERNET + SERVICE +5V-EDID +5V-VGA
MAIN
3S83
3S84
1E06
3ECP-3
3ECP-1
SW
3FC1
3FC2
Y23 RXD1-MIPS 3E53-4 3E53-3 1E05
3
5000 Serie 256MB GPIO_2 9FC1 12
10
47 VGA-SDA-EDID-HDMI
15
3E53-2 3E53-1 UART
5
7000 Serie 512MB Y24 TXD1-MIPS 2
GPIO_3 SERVICE EDID
48 VGA-SCL-EDID-HDMI 9FC3 15
1 CONNECTOR SW
1
B02I B02I
6
PNX85500: ANALOG VIDEO
11
AD25 3S5V-1 9FC2
B05A DDR
VGA_EDID_SDA
VGA-SDA-EDID VGA
3S5V-3 CONNECTOR
AD24 VGA-SCL-EDID 9FC4
VGA_EDID_SCL
7B00
EDE1116AEBG 7B01 RES
EDE1108AGBG EDE1108AGBG ANALOGUE
VIDEO B11C MINI LVDS (LGD) B11A TCON CONTROLLER (LGD) B14C P GAMMA & VCOM & FLASH (SHARP) B14A TCON CONTROL
(SHARP)
SDRAM SDRAM
9S15 1KQB
VGA-SDA-EDID-TCON
1
9S14
D(8-15)
D(0-7)
B02B VGA-SCL-EDID-TCON
2
VCC_3V3
MEMORY
RES
2 1
3KTU
3KTV
DDR2-A(0-13) A 7JB1 VCOM_SDA
DDR2-D(0-31) DQ 7 SDA-TCON
7JB3 VCOM_SCL 7KQH
7B02 +3V3
B01F HDMI & CI VCC
PCA9540B
EDE1116AEBG 7B03 8 SCL-TCON
9JB6
9JB7
EDE1108AGBG EDE1108AGBG 2 CHANNEL
3J36
3J35
3S6G
3S6F
D(16-23)
D(24-31)
1 20 MULTIPLEXER
9JBB SDA-TCON
SDRAM SDRAM B24 3S60 SDA-TUNER 3F75 TUN-P7 12 13 E19 E20
9JB6
9JB7
4_SDA VCC 7JC1 9JBA
3S61 3F76 RES SCL-TCON
A23 SCL-TUNER TUN-P6 MAX9668ETP
4_SCL 7KQA 7KAA
RES
3J38
3J37
ISL24837IRZ 7KQB UPD809900F1
10 BIT M25P32
ERR PROG GAMMA
18 175 176 5 6 8-CHANNEL CONTROL
7 6 REF SYST RES PROG I2C
5000 Serie 256MB 7J01 7J02 1J02 REF VOLT GEN FLASH
7000 Serie 512MB 1T01 TL2429MC M24C32-WDW6 +VDISP 2
TH2603 SCD
TCON EEPROM
3J04
1
B04C ETHERNET + SERVICE MAIN (4Kx8) SCL
TUNER 9JBB TCON
4
SDA-DISP
SCL-DISP
SDA-DISP
SCL-DISP
7
WP SW
ERR
7E10 34 TCON
LAN8710A-EZK SW
Only for LGD display with TCON on SSB Only for LGD display with TCON on SSB Only for SHARP display with TCON on SSB
11 ETH-RXD(0) Y5
ETH-RXD(1)
RXD_0 B06B VIDEO OUT - LVDS
10 Y6 +3V3
RXD_1
9 ETH-RXD(2) AB4
RXD_2
ETHERNET 8 ETH-RXD(3) AC1
3S6C
3S6B
RXD_3 1G51
7 ETH-RXCLK AA3
RXCLK B26 3S58 SDA-SET 9S12 SDA-DISP 3G2W 50
2_SDA LVDS
22 ETH-TXD(0) AA1 A25 3S5W SCL-SET 9S11 SCL-DISP 3G2Y 49 CONNECTOR
TXD_0 2_SCL
23 ETH-TXD(1) AA4
TXD_1 +3V3
24 ETH-TXD(2) AB1
ETHERNET TXD_2 ERR +3V3 ERR
25 ETH-TXD(3) AB2 14 64
CONNECTOR TXD_3 2 1
3S67
3S65
3S68
3S66
RJ45 20 ETH-TXCLK AA2 B09A DVBS CONNECTOR BOARD B11D CONNECTORS (LGD) B14F CONNECTORS (SHARP)
TXCLK Programmable via USB
3S81
3S80
4 SW
7S01 1F53 1F53 1F53
W21 RXD2-MIPS PCA9540B 3C84 2 3J84 2 3K84 2 SW Programmable via ComPair
GPIO_2 5
2D 2D 2D SW Pre-programmed device
W22 TXD2-MIPS 2 CHAN. 3C85 3 3J85 3 3K85 3
GPIO_3 DIMMING DIMMING DIMMING
MULTIPLEX.
7
ERR 1M71 1M71 1M71
24 8 3C83 3 3J83 3 3K83 1
TO TO TO
3C81 1 TEMPERATURE 3J81 1 TEMPERATURE 3K81 3 TEMPERATURE
RES SENSOR SENSOR SENSOR
RES RES RES
9S13 SDA-BL
9S10 SCL-BL
Only for LGD display with TCON on SSB Only for SHARP display with TCON on SSB
18770_408_100217.eps
100223
2010-Jun-18 back to
div. table
Block Diagrams Q552.1E LA 9. EN 96
1M99 1M99 +1V2-BRA-VDDC +1V2-BRA-VDDC +1V8 +1V8 +1V8 +1V8 VCC VCC
+12VD B01g B03b B03b B11b
1 1 +1V2-BRA-DR1 +1V2 3B20
+12V +1V2-BRA-DR1 7UA3 DDR2-VREF-DDR
B03h VDD VDD
B01g B02h
2 2 B11b
+12V +3V3 3JC0
+3V3
3 3 B03e
GND1 3JC1
5FE7 +3V3-BRA +12V B06A DISPLAY INTERFACING-VDISP P_VDD
PSU GND1
4 4
5FE4 +3V3-BRA-FLT B03e
+5V +5V
+VDISP-INT +VDISP-INT
5 5 LAMP-ON 3U16 B03h
BL_ON_OFF B02G +3V3
DIM
6 6 BACKLIGHT-PWM_BL-VS
B06C B03e
+5V +5V
7UC0 1G03 +VDISP B11D CONNECTORS (LGD)
7 7 BACKLIGHT-BOOST B06b
BOOST B01E 7FE3 3U15 +2V5 +3V3 +3V3
8 8 BACKLIGHT-PWM-ANA-DISP IN OUT T 3.0A B03e
OR
N.C B02G 5FE9 +2V5-BRA COM B02d,h
IN OUT +2V5-LVDS 5G01
CUA0 +3V3-STANDBY +3V3-STANDBY
COM B03c
9 9 B02h
POWER-OK 5G02 1G00
POK B02G NOT FOR 5000 SERIES +5V +5V
B03e
7 10 BL-SPI-SDO +5V5-TUN +5V5-TUN T 3.0A 1M20
N.C. B03e 5
N.C.
8 11 BL-SPI-CSn B02A PNX85500: NANDFLASH 7UA6 +5V-TUN TO
9 12 BL-SPI-CLK CONDITIONAL ACCESS B01f 8 IR/LED
N.C.
+3V3 +3V3 PANEL
Optional 1M99 is 12 pin connector B03e B06B VIDEO OUT - LVDS +12V +12V
ENABLE-1V8 B03c
+12V +12V
1M95 1M95 B03c +3V3 +3V3
B01e,B02e, 7UA0 B03e
1 1 +3V3-STANDBY 3UA0
3V3_ST g,h,B03a,b,h, VOLT. +2V5-REF
2 2 STANDBY B04d,e,B09a, B02B PNX85500: SDRAM REG. B06a
+VDISP +VDISP B13 AMBILIGHT CPLD
STANDBY B02G
3 3 B11d,B14f +3V3 +3V3
GND1 B03e
4 4 +1V8 +1V8
B03b
GND1 5HA0 VINT
5 5
GND1
3S20 DDR2-VREF-CTRL3 B06C .
5HA1 VIO
1U40 +12V 3S06 DDR2-VREF-CTRL2
B03E DC / DC
+3V3 +3V3
6 6 B03b,d,e,g, B03e
+12V +1V1 +1V1 1M72
7 7 B08b,B09a, B01,a,b,c,d,e, 1HA0 +24V
T 3.0A B03b 5GA0 VINT 1
+12V B11d,B14f g,j,jk,B14f
8 8 +12V +12V 2 1M59
+12V B03c B02a,c,d,e,h, T 1.5A
9 9 +24V-AUDIO-POWER 5GA1 VIO 21 TO
+VSND 7UD1 B03c,f,g,h,
B02d,B03a AMBILIGHT
GND_SND
10 10 B02C PNX85500: DIGITAL VIDEO IN 5UD3
IN OUT
5UD2 +3V3 B04a,c,d,e,
MODULE
11 11 MAINS-OK COM B06b,c,d,
N.C. B03A +3V3 +3V3 7UD0 B08a,B09a,
B03e
5UD0 5UD1 +5V5-TUN B11d,B13 B06D SPI-BUFFER
B14A TCON CONTROL (SHARP)
IN OUT
COM B03d +3V3 +3V3 +VDISP +VDISP
B03e B14b
6UD0 +5V 7KAC
B01,a,c,e,k,
+3V3 +3V3 5KAG VCC_1V2
B03e
B02D PNX85500: AUDIO B03c,d,B04a,b,d, VIN SW
GND B14b
B09a,B11d,
+5V +5V B03d
+2V5 +2V5 7UD2
B14f B07A DVBS-FE
5KAA VDD12
B03e +2V5
IN OUT
+3V3 +3V3 +1V-DVBS +1V-DVBS
B03e COM B08a 5KAB LVDS_AVDD
3S11 +3V3-ARC
+2V5-DVBS +2V5-DVBS 5KAC mini_AVDD
B01A COMMON INTERFACE 7S08
7UD3 B08a
+2V5-AUDIO IN OUT
+3V3 5KAD SSCG_AVDD
+3V3 +3V3 IN OUT B02h COM +3V3-DVBS +3V3-DVBS
COM B08a VCC_3V3 VCC_3V3
B03e
+24V-AUDIO-POWER +24V-AUDIO-POWER 5R00 +3V3-DEMOD B14b
+5V +5V B03c ONLY FOR 5000 SERIES
5KAE VDD33
B03e 3S0Z +24V-AUDIO-VDD 5R01 +3V3RF
3F01 +5VCA 5KAF VDDQ
+T B03F TEMPSENSOR + AMBILIGHT
+3V3 +3V3
B02E PNX85500: MIPS B08A DVBS-SUPPLY
B01B FLASH B03e B14B TCON DC / DC (SHARP)
+3V3 +3V3 5UM1 1UM0 V-AMBI
B03e VCC_1V2 VCC_1V2
+3V3 +3V3
+3V3-STANDBY +3V3-STANDBY T 1.0A B14a
B03e +3V3 +3V3
B03c B03e +VDISP-INT +VDISP-INT
B03h
5T02
B02H PNX85500: POWER
+12VD +12VD
7T01
10
3KFP VGL_-6V
+2V5-DVBS
B01D SD-CARD
+1V1 +1V1
B03c IN OUT B07a B14e
B03b COM
7UU1 +VDISP-INT B06a,B11b,
+3V3 +3V3
+1V2 +1V2 B14b
B03e
3F40 +3V3-SD
B03d
12 5T04 +V-LNB
B08b
B14C P GAMMA & VCOM & FLASH (SHARP)
+1V8 +1V8
+T B03b 7UU2 VCC_3V3 VCC_3V3
+2V5 +2V5 LCD-PWR-ONn B14b
B03d
+VDISP +VDISP
+2V5-AUDIO +2V5-AUDIO
B02d B08B DVBS-SUPPLY B14b
B01E PNX85500: CONTROL
B03d
+2V5-LVDS +2V5-LVDS B04A ANALOGUE EXTERNALS A
+3V3-DVBS +3V3-DVBS
VLS_15V6 VLS_15V6
+3V3 +3V3 B08a B14b
+3V3 +3V3 +3V3 +3V3 7KQA
B03e B03e +12V +12V
B03e +5V +5V 5 ISL248371RZ
+3V3-STANDBY +3V3-STANDBY +3V3-STANDBY +3V3-STANDBY B03e B03c 32 VREF_15V2
B03c +V-LNB +V-LNB IC B14d
B03c B08a
+5V +5V LCD
B03e SUPPLY
B04B ANALOGUE EXTERNALS B
+5V +5V B09A (*NON) DVBS CONNECTOR BOARD
B03e
B01F HDMI & CI B03A AUDIO B03e
+3V3 +3V3 B14D MPD (SHARP)
B01k
VGH_35V VGH_35V
7U03 +5V-EDID
12V/1V8 B14b
7U02-1
TPS53126PW B11A TCON CONTROLLER (LGD)
6EC1
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 97
27
+24V TLC5946RHB
1
2 3B00-1 VCC 2B04-2 B6
BLANK 1 8 31 4 PWM-R1
3
PWM-CLOCK-BUF 150R 24
BLANK 0
5 PWM-G1
2B04-3 B8
4 GSCLK 1
5
3B18 26
IREF 2
6 PWM-B1 2B04-4 B7
FB35 3 7 PWM-G3
6
FB03 PROG 4 3B00-4 5
1K8
1
MODE 3
8 PWM-R3
2B08 E12
7 SCLK 4
8 SPI-CLOCK-BUF 150R 2
SIN 5
9 PWM-R2 2B09 E12
SPI-DATA-IN-BUF 23 10 PWM-G2
9
SPI-DATA-IN 3 6
SOUT 6
11 PWM-B2 2B10 F9
10 FB04 7
11 TEMP-SENSOR SPI-DATA-OUT 3B00-3 150R 3B21 22
XERR
OUT
8
14 PWM-B3 2B11 A9
FB20 +3V3 150R 3B22 25 15 PWM-G4
12 XHALF 9 2B17 D8
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
B 13
14
FB05
+3V3 FB06 150R
12
XLAT 10
11
17
18
PWM-B4 B 2B20 D4
15 BLANK 12 PWM-B5
16
FB07 PROG 13
13
19 PWM-G5 3004 E12
6
FB08 28 NC 20
FB10 PWM-R5 3B00-1 A6
2B04-2
2B04-1
2B04-4
2B04-3
17 14
100p
100p
100p
100p
LATCH 29 21 DATA-SWITCH
18 15
19
FB11 SPI-CS
3B31
3B00-2 B6
GND GND_HS
+3V3 FB12 +3V3 3B00-3 B6
3
20
30
33
21 PWM-CLOCK 2K0
22 7B26-2 3B00-4 B6
FB13 SPI-DATA-RETURN TLC5946RHB
23
FB15 SPI-DATA-IN 34 VIA 42 3B01-1 E7
24
25
FB16 SPI-CLOCK 35
VIA VIA
41 3B01-2 D7
27 26 36 40
VIA 3B02-1 E3
C 1M83 C 3B02-2 E5
37
38
39
3B03-1 H14
3B03-2 H14
3B03-3 H14
+3V3
3B03-4 H14
3B07-1 F3
+3V3 3B07-2 G3
3B34 3B07-3 H3
2B20
100n
2B17
100n
SPI-CLOCK-BUF +3V3
3B13-3 H3
6
1K5 1%
1K5 1%
7B07
3B39-2
3B39-3
7B20-1
3B13-4 I3
8
M95010-WDW6 74LVC2G17
+3V3 VCC
5
7B30
3B18 A8
5
Φ 2
3
D Q FB40
2 3B01-2 7 1 3B30-1 8
5
7B06 (64K) PWM-CLOCK 1 6 PWM-CLOCK-BUF 1
4 TEMP-SENSOR
3B21 B7
74LVC1G32GW 6
5
RES
2B00
2
4 1 3B30-1 D9
33p
3B02-2
2
S
2B02
2B08
100p
3004
10K
2 7
10n
DATA-SWITCH
3B11
HOLD +3V3
+3V3 1 3B02-1 8 3 7 10K 2 3B30-4 E9
W
10K
3
3B31 B10
-T
10K
GND
E FB41
E 3B34 D13
4
7B20-2
74LVC2G17 3B35 G14
1
1K5 1%
3B39-1
+3V3 3B36 G14
2B09
10n
5
3B37 G14
8
3B01-1 3B30-4
SPI-DATA-RETURN SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF 3B39-1 E13
100R 220R 3B39-2 D12
3B39-3 D13
2B01
2
33p
2B10
100p
+24V 7000 G5
7001 G7
F F 7002 G8
8 3B07-1 1
7B23-1
7003 G10
10K
BC847BS(COL)
6
7004 G11
2 7005 G13
7B06 D3
2 3B07-2 7
1
10K
7B07 D4
7B20-1 D8
PWM-B1
FB30 7B20-2 E8
3B35
+24V 7B23-1 F4
+24V 7000
G LTW-008RGB 7001
LTW-008RGB
7002
LTW-008RGB
7003
LTW-008RGB
7004
LTW-008RGB
7005
LTW-008RGB
270R
3B36
G 7B23-2 G4
7B25 H3
5 3B07-4 4
BC847BS(COL) 3B37
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 7B26-2 C9
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
3 3B07-3 6
4
FB03 B1
10K
1 3B03-1 8
FB04 B1
FB31 1K5
FB05 B1
H PWM-R1
2
3B03-2
7 H FB06 B2
+24V
1K5
FB07 B1
3 3B03-3 6
FB08 B1
FB10 B2
3 3B13-3 6
1K5
7B25
10K
BC847BW 3 4
3B03-4
5
FB11 B1
1K5 FB12 B2
1
FB13 C1
2B03
100n
5 3B13-4 4
FB15 C1
2
10K
FB16 C1
FB20 B7
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007 6 2009-12-04
5 2009-10-28
AL 2K10 LiteOn
8204 000 8978 4 2009-10-07
15 LED Common 3 2009-08-27
2 2009-07-03
18770_600_100212.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 98
5 3B55-4 4
A 7B50-1
A
10K
BC847BS(COL) 6 3B52 B7
2
3B53-1 B7
3 3B55-3 6
3B53-2 C7
1
10K
FB70
3B53-3 C7
PWM-B2
3B50 3B53-4 C7
+24V 7105 7104 7103 7102 7101 7100
LTW-008RGB LTW-008RGB 270R
3B51
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB 3B55-1 C3
B B 3B55-2 B3
7 3B55-2 2
5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6
7B50-2
10K
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 3B52 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
3B55-3 A3
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
1
3B53-1
8 3B55-4 A3
1 3B55-1 8
+24V
4
1K5
3B57-2 D3
10K
2 3B53-2 7
1K5
3B57-3 C3
2B50
100n
FB71
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
C +24V
4 3B53-4 5 C
1K5
3C00-2 F3
3 3B57-3 6
7B51 3C00-3 F3
10K
BC847BW 3
1 3C00-4 E3
3C06-1 G3
7 3B57-2 2
2
10K
3C06-2 H3
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
3C15-4 G4
5 3C00-4 4
E 7C20-1 E
10K
BC847BS(COL) 6
7100 B11
2
7101 B10
3 3C00-3 6
7102 B9
1
10K
FC01
7103 B7
PWM-B3
+24V
1 3C10 2
7202
7104 B6
270R 7200 7201
F 1 3C11 2
LTW-008RGB LTW-008RGB LTW-008RGB
F 7105 B5
7 3C00-2 2
7C20-2
270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 Blue
7200 F8
10K
5
68R
3 RED 4 3 RED 4 3 RED 4
7201 F9
Red
1 3C15-1 8
7202 F10
1 3C00-1 8
7B50-1 A3
10K
1K5
3C15-2
2 7
PWM-G3
FC02 1K5 7B50-2 B3
3 3C15-3 6
G +24V
1K5
G 7B51 C3
4 3C15-4 5 7C20-1 E3
1 3C06-1 8
1K5
7C22 7C20-2 F3
10K
BC847BW 3
1 7C22 G3
FB70 B3
7 3C06-2 2
2
10K
FB71 C3
H FC03
H FB72 D3
PWM-R3
FC01 F3
FC02 G3
FC03 H3
1 2 3 4 5 6 7 8 9 10 11 12
6 2009-12-04
18770_601_100212.eps
100212
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 99
3 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2C15 B6
7203 A3
7204 A4
7205 A5
A A
FH12-25S-0.5SH(55)
7203 7204 7205
LTW-008RGB LTW-008RGB LTW-008RGB
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B
2C15
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
26 27
1M84
D D
1 2 3 4 5 6 7 8 9 10
B003
3 2009-10-07
1
2009-08-27
2009-07-20
AL 2K10 3104 313 63895
18770_630_100212.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 100
9 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
A A 7204 A4
7205 A5
7203 7204 7205 1M84
LTW-008RGB LTW-008RGB LTW-008RGB
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B
2D01
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27
FH12-25S-0.5SH(55)
FD04
D D
1 2 3 4 5 6 7 8 9 10
B003 B004
1 2009-10-07
18770_610_100212.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 101
9 LED LiteOn
9 LED LiteOn
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13
2D10 D13
+24V 3D02-1 A1
A A 3D02-2 B1
8 3D02-1 1
7D01-1
3D02-3 B1
10K
BC847BS(COL)
6
2 3D02-4 C1
3D05-3 C1
2 3D02-2 7
10K 1
3D05-4 D1
PWM-B4
FD01
1 3D10 2
3D10 B12
B +24V 7300 7301 7302 7303 7304 7305 270R
+24V
B 3D11 B12
LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D11
1 2
3D12 B12
6 3D02-3 3
BC847BS(COL) 3D12
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
3D13-1 C12
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
3D13-2 C12
4 3D02-4 5
4
3D13-3 C12
10K
1 3D13-1 8
C FD02 1K5
C 3D13-4 D12
PWM-R4
+24V
2 3D13-2 7
1K5
7300 B5
3 3D13-3 6 7301 B6
3 3D05-3 6
1K5
7D02 7302 B7
10K
BC847BW 3 4 3D13-4 5
1
1K5 7303 B8
2D10
100n
7304 B10
5 3D05-4 4
2
10K
D D 7305 B11
PWM-G4
FD03
7D01-1 A2
7D01-2 B2
7D02 C2
FD01 B1
FD02 C1
E E FD03 D1
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2009-10-07
18770_611_100212.eps
100212
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 102
15 LED LiteOn
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
A A
FD18 C7
FH12-25S-0.5SH(55)
2D01
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27
FD18
D D
1 2 3 4 5 6 7 8 9 10
3 2009-12-07
1
2009-10-07
2009-07-02
AL 2K10 3104 313 63823
18770_620_100212.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 103
15 LED LiteOn
15 LED LiteOn
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13 2D10 C13
2D11 H13
3D02-1 A1
+24V
3D02-2 A1
3D02-3 B1
8 3D02-1 1
7D01-1
10K
BC847BS(COL)
6
3D02-4 B1
A 2 3D02-2 7
2
A 3D03-3 H2
1
3D03-4 G2
10K
FD01
3D04-1 F2
PWM-B4
BC847BS(COL) 3D12
B 3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
B
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
68R 3D05-3 C1
3D05-4 D1
4 3D02-4 5
4
10K
1 3D13-1 8
3D10 B12
PWM-R4
FD02 1K5
3D11 B12
2 3D13-2 7
+24V
1K5 3D12 B12
3 3D13-3 6
C C 3D13-1 B12
3 3D05-3 6
1K5
7D02
10K
2D10
100n
5 3D05-4 4
3D13-4 C12
2
10K
FD03
3D15 F12
PWM-G4
3D16 F12
D D 3D17 F12
3D18-1 G12
3D18-2 G12
3D18-3 G12
+24V
3D18-4 G12
7300 B5
E E
3
7301 B6
3D04-3
7D03-1
10K
BC847BS(COL)
6
7302 B7
6
7303 B8
5
1
3D04-4
10K
7304 B10
4
PWM-B5
FD04 7305 B11
3D15
+24V 7400 7401 7402 7403 7404 7405 270R
+24V
7400 F5
F LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB LTW-008RGB
3D16 F 7401 F6
1
7D03-2
7402 F7
10K
BC847BS(COL) 3D17
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
8
4
7404 F10
3D04-2
10K
FD05 1K5
G
PWM-R5
2 3D18-2 7
G 7D01-1 A2
+24V
1K5
7D01-2 B2
3 3D18-3 6
7D02 C2
5
1K5
3D03-4
7D04
10K
BC847BW 3 4 3D18-4 5
7D03-1 E2
4
1K5
1
7D03-2 F2
2D11
100n
3
2
3D03-3
7D04 G2
10K
FD01 A1
6
H PWM-G5
FD06 H
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2009-12-07
1 2009-07-02
AL 2K10 3104 313 63823
18770_621_100212.eps
100219
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 104
AmbiLight LiteOn
9 LED
3B31 3B50
3B51
FC01
3B56
9B53
3B52 FB01
2B03
FB32
3B54
7B06
3B53
2B50
9B50
7B25
3B55
7C02
B001
B007
B002
B003
9B51
7000 7001 FB12
7002 7003 7004 7100 7101 7102 7103
3B18
FB04
FB11
2B11
2B09
3B30
3C08
7B26
1M83 1M84
FB07
3B34
3004 3001
3C06 3C05
3B07
3B13
9B52
3B01
3C09
2B17
3C02
3C01
7B07
FB40 FB70
FB05 FB06
FB41
3B21 3B22 FB35
3C07
7C01
3B02
2B00
3B00
7B30
2B10
2B02
2B20
2B04
2B08
3B11
12 LED
3B31 3B50
3B51
3B56
9B53
3B52 FC01
2B03
FB32 FB01
3B54
7B06 3E04
3B53
2B50
9B50
3B55
7B25
B001
B007
B002
B003
B004
9B51
FD03
7000 7001 7002 7003 7004 7100 7101 7102 7103 7104 7105 7106
3E06
3B18
FB04 FB12
FB11 3E03
2B11
2B09
3B30
7B26
1M83 1M84
FB07
3E05
3B34
3004 3001
3B07
3B13
9B52
3B01
7E02
3E01
2B17
7B07
FB41
FB40 FB05 FB06
3B21 FB35
FB70
3E02
3B22
3B02
3B00
2B00 7E01
FD01
FD02
2B10
2B02
7B30 2B20 2B04
FB13
2B08
3B11
FB10
FB20
FB08 2B01 FB16 FB31 FB15
FB72
FC02 FC03 FB71
15 LED
3B31 3B50
3B51
3B56
9B53
3B52 FC01
3D07
3C09
FB01
2B03
FB32
3D05 3D06
3B54
7B06
3B53
2B50
9B50
7B25
3B55
B001
B007
B002
B003
B004
B005
FD03
9B51
FD05
3D01
FB11
2B11
2B09
3B30
3D02
7B26
3C08
1M83 1M84
7D02
FB07
3D09
3B34
3004 3001
3B07
3B13
9B52
7C02
2C03
3B01
3C01
2B17
7B07
FB40 FB05 FB06
FB70 3C02
FB41
3B21 3B22 FB35
7D01 7C01
3B02
2B00
3B00
7B30
2B10
2B02
2B20
2B04
FB13
FD01 FD02
2B08
3B11
FB20 FD04
FB08 2B01 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71 FD06
18 LED
3B35
3B36
FB01 FC01
FB32
3B03
7B06
3B37
3C00
3B31
3B52
7B25 3B51
3B55
B001
B007
B002
B003
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205
3B18
FB04 FB12
FB11
2B09
3B50 2C15
3B30
2B03
3C12
3B53
7B26
1M83 1M84
FB07
3C15
3B01
3B34
3B07
3B13
7B50
7B07
2B01
7C20
FB70 3C11
FB40
3B21 3B22 2B50
7C22
2B17 2B11
7B51
FB05 FB06
2B00
FB41 FB35
3B00
7B30
3C06
3B02
2B04
2B10
2B02
2B20
3C10
7B20
2B08
3B11
7B23 3B57
3004
FB13 FB03
FB20
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71
24 LED
3B35
3B36
7B26
FB32
3B37
7B06
3C00
3B31
3B52
7B25
3B55
3B51
B001
B007
B002
B003
B004
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305
3B18
FB04 FB12
FB11
2B09
3B30
2B03 3B50
3C12
3B53
1M83 1M84
3C15
3B01
FB07
FD03
3B34
2D10
3B07
3B13
7D02
7B50
7B07
2B01
7C20
FB70 3C11
FB40
3B21 3B22 2D01
7C22
2B50
7B51
2B17 2B11 3D05
2B00
3D13
3D10
3B00
3D12
7B30 3D02
3C06
3B02
7D01
2B10
2B02
2B20
2B04 3C10
2B08
3B11
7B20
3004
30 LED
3B35
3B36
FB01 FC01
FB32
3B03
7B06
3B37
3C00
3B31
3B52
7B25 3B51
3B55
FB12
B001
B007
B002
B003
B005
B004
FD03 FD05
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405
3B18
FB04
FB11
2B09
3B50
3B30
2B03
FB07
3C12
3B53
7B26
1M83 1M84
3C15
3B01
2D10
3B34
3B07
3B13
7D02
3D15
7D04
3D10
2D11
3D17
7B50
3D13
3D03
7B07
2B01
3D12
FD18
7C20
FB70 3C11
FB40
3B21 3B22 2B50
7C22
FB05 FB06
2D01
3D04
2B00
FB41 FB35
7D01 7D03
3B00
3D11 3D16
7B30 3D02
3C06
3B02
2B04
2B10
2B02
2B20
7B23 3B57
3004
FB13 FB03
FB20 FD04
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71 FD06
36 LED
3B35
3B36
FB01 FC01
3D21
FB32
3B03
7B06
3B37
3C00
3B31
3B52
7B25 3B51
3B55
B001
B007
B002
B003
B005
B004
B006
FD03 FD05
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 3D18
7404 7405 7500 7501 7502 7503 7504 7505
3D22
3B18
FB04 FB12
FB11
2B09
2E10
3B50 2D04
3B30
2B03
7D26
3C12
3B53
2D10
7B26
2D11
1M83 1M84
FB07
3C15 3D00
3B01
3B34
7F02
3B07
3B13
2F10
7D02
7E02
3E12
3F12
3F02
3F05
7B50
3D13
7B07
3E02
3F10
2B01
3D10 FD18
7C20
3E11
3E05
FB70
3E13
3D02
3D12
3C11
FB40
3B21 3B22 2B50 2C01 FD19
7C22
2B17 2B11
7B51
FB05 FB06
2B00
FB41 FB35
FF02 FF01
7B30
3C06
3F11
3B02
3D11
2B04 3E10
2B10
2B02
2B20
3C10
3D05 FD01 FD02
7B20
2B08
3B11
FB13 FB03
FB20 FD04
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71 FD06 FF03
18770_602_100216.eps
100526
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 105
27
1 +24V TLC5946RHB 2B04-2 B6
3B00-1 VCC
2
BLANK 1 8 31 4 PWM-R1 2B04-3 B8
3 BLANK 0
4 PWM-CLOCK-BUF 150R 24
GSCLK 1
5 PWM-G1 2B04-4 B7
3B18 26 6 PWM-B1
5 IREF 2 2B08 E12
1K8 FB35 3 7 PWM-G3
6 MODE 3
4 3B00-4 5 1 8
7 FB03 PROG
150R 2
SCLK 4
9
PWM-R3 2B09 E12
8 SPI-CLOCK-BUF SIN 5 PWM-R2
9 SPI-DATA-IN-BUF 23
SOUT 6
10 PWM-G2 2B10 F9
SPI-DATA-IN 3 6 11 PWM-B2
10 FB04
3B00-3 150R 3B21 22 OUT
7
14
2B11 A9
11 TEMP-SENSOR SPI-DATA-OUT XERR 8 PWM-B3
12 FB20 +3V3 150R 3B22 25
XHALF 9
15 PWM-G4 2B17 D8
LATCH 2 3B00-2 7 10K 32 16 PWM-R4
B 13
14
FB05
+3V3 FB06 150R
XLAT 10
11
17 PWM-B4 B 2B20 D4
15 BLANK 12
12
18 PWM-B5 3004 E12
FB07 PROG 13 19 PWM-G5
16 13 3B00-1 A6
6
FB08 28 NC 20 PWM-R5
FB10
2B04-2
2B04-1
2B04-4
2B04-3
17 14
3B00-2 B6
100p
100p
100p
100p
LATCH 29 21 DATA-SWITCH
18 15
FB11 SPI-CS
19
+3V3 FB12 GND GND_HS
3B31
+3V3
3B00-3 B6
3
20
3B00-4 B6
30
33
21 PWM-CLOCK 2K0
7B26-2
22
FB13 SPI-DATA-RETURN TLC5946RHB 3B01-1 E7
23
FB15 SPI-DATA-IN 34 VIA 42 3B01-2 D7
24
FB16 SPI-CLOCK 35 41
25 VIA VIA 3B02-1 E3
27 26 36 40
VIA
C C 3B02-2 E5
1M83
3B03-1 H14
37
38
39
3B03-2 H14
3B03-3 H14
3B03-4 H14
+3V3 3B07-1 F3
3B07-2 G3
+3V3
3B07-3 H3
3B34
3B07-4 G3
2B20
100n
SPI-DATA-IN-BUF +3V3 +3V3 3B11 E12
D 100K RES
D
2B17
100n
SPI-CLOCK-BUF +3V3 3B13-3 H3
6
1K5 1%
1K5 1%
7B07 3B13-4 I3
3B39-2
3B39-3
7B20-1
8
M95010-WDW6 74LVC2G17
+3V3 VCC 3B18 A8
5
7B30
5
Φ 2
3B21 B7
3
D Q FB40
2 3B01-2 7 1 3B30-1 8
5
7B06 PWM-CLOCK 1 6 PWM-CLOCK-BUF 1
74LVC1G32GW 6 (64K) 4 TEMP-SENSOR 3B22 B8
5
C 100R 220R
SPI-CS 1 3
LMV331IDCK 3B30-1 D9
RES
2B00
2
4 1
33p
3B02-2
2
S
3B30-4 E9
2B02
2B08
100p
3004
10K
2 7
10n
DATA-SWITCH
3B11
+3V3 HOLD +3V3
1 3B02-1 8 3 7 2
W 10K 3B31 B10
10K
3
-T
10K
GND 3B34 D13
E FB41
E
4
1
3B36 G14
1K5 1%
3B39-1
+3V3
2B09
10n
3B37 G14
5
3B39-1 E13
8
3B01-1 3B30-4
SPI-DATA-RETURN SPI-CLOCK 1 8 3 4 4 5 SPI-CLOCK-BUF
100R 220R
3B39-2 D12
3B39-3 D13
2B01
2
33p
7000 G5
2B10
100p
+24V
7001 G7
7002 G8
F F
8 3B07-1 1
BC847BS(COL)
6 7004 G11
2 7005 G13
7B06 D3
2 3B07-2 7
1
7B07 D4
10K
7B20-1 D8
FB30
7B20-2 E8
PWM-B1
3B35 7B23-1 F4
+24V
+24V 7000 7B23-2 G4
G 99-235/RSBB7C-A24/2D 7001
99-235/RSBB7C-A24/2D
7002
99-235/RSBB7C-A24/2D
7003
99-235/RSBB7C-A24/2D
7004
99-235/RSBB7C-A24/2D
7005
99-235/RSBB7C-A24/2D
270R
3B36
G 7B25 H3
7B26-1 A8
5 3B07-4 4
BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3B37 7B26-2 C9
68R 7B30 D13
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
FB01 A1
3 3B07-3 6
4 FB03 B1
10K
FB04 B1
1 3B03-1 8 FB05 B1
FB31 1K5 FB06 B2
PWM-R1
H +24V
2
3B03-2
7 H FB07 B1
1K5
FB08 B1
3 3B03-3 6 FB10 B2
3 3B13-3 6
1K5
7B25 FB11 B1
10K
BC847BW 3 3B03-4
4 5
FB12 B2
1K5
1 FB13 C1
2B03
100n
FB15 C1
5 3B13-4 4
FB16 C1
10K
FB20 B7
I FB32
I FB30 G3
PWM-G1
FB31 H3
FB32 I3
FB35 A8
FB40 D12
FB41 E13
1 2 3 4 5 6 7 8 9 10 11 12 13 14
B001 B002 B007
2 2009-11-27
1 2009-11-03
AL 2K10 Everlight
8204 000 9059
15 LED Common
18770_670_100212.eps
100219
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 106
5 3B55-4 4
A 7B50-1
A 3B52 B7
10K
BC847BS(COL) 6
2 3B53-1 B7
3B53-2 C7
3 3B55-3 6
1
10K
3B53-3 C7
PWM-B2
FB70
3B50
3B53-4 C7
+24V 7105
99-235/RSBB7C-A24/2D
7104
99-235/RSBB7C-A24/2D 270R 7103
99-235/RSBB7C-A24/2D
7102
99-235/RSBB7C-A24/2D
7101
99-235/RSBB7C-A24/2D
7100
99-235/RSBB7C-A24/2D 3B55-1 C3
3B51
B B 3B55-2 B3
7 3B55-2 2
5 BLUE 6 5 BLUE 6 270R 5 BLUE 6 5 BLUE 6 5 BLUE 6 5 BLUE 6
7B50-2
10K 3B55-3 A3
BC847BS(COL) 3 1 GREEN 2 1 GREEN 2 3B52 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
1
3B53-1
8 3B55-4 A3
1 3B55-1 8
+24V
4
1K5
3B57-2 D3
10K
2 3B53-2 7
1K5 3B57-3 C3
2B50
100n
FB71
PWM-G2 3 3B53-3 6
1K5 3C00-1 G3
C +24V
4 3B53-4 5 C 3C00-2 F3
1K5
3 3B57-3 6
7B51 3C00-3 F3
10K
BC847BW 3
1
3C00-4 E3
3C06-1 G3
7 3B57-2 2
2
10K
3C06-2 H3
D FB72 D 3C10 F4
PWM-R2
3C11 F4
3C12 F4
3C15-1 G4
3C15-2 G4
+24V
3C15-3 G4
3C15-4 G4
5 3C00-4 4
E 7C20-1 E
10K
BC847BS(COL) 6
7100 B11
2
7101 B10
3 3C00-3 6
7102 B9
10K
PWM-B3
FC01 7103 B7
1 3C10 2
+24V
270R 7200 7201 7202
99-235/RSBB7C-A24/2D
7104 B6
99-235/RSBB7C-A24/2D
F 1 3C11 2
99-235/RSBB7C-A24/2D
F 7105 B5
7 3C00-2 2
5
68R
3 RED 4 3 RED 4 3 RED 4 Red 7201 F9
1 3C15-1 8
7202 F10
1 3C00-1 8
4
10K
1K5
2
3C15-2
7 7B50-1 A3
FC02 1K5
PWM-G3
3 3C15-3 6
7B50-2 B3
G +24V G
1K5
7B51 C3
4 3C15-4 5
7C20-1 E3
1 3C06-1 8
1K5
7C22
10K
BC847BW 3
7C20-2 F3
1
7C22 G3
7 3C06-2 2
FB70 B3
10K
H H FB71 C3
FC03
PWM-R3
FB72 D3
FC01 F3
FC02 G3
1 2 3 4 5 6 7 8 9 10 11 12 FC03 H3
2 2009-11-27
18770_671_100212.eps
100212
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 107
3 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2C15 B6
7203 A3
A A 7204 A4
7205 A5
FH12-25S-0.5SH(55)
7203 7204 7205
99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
SPI-CLOCK-BUF 1
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B
2C15
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22 C
23
24
+24V 25
26 27
1M84
D D
1 2 3 4 5 6 7 8 9 10
B003
1 2009-11-27
18770_650_100212.eps
100219
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 108
9 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
7204 A4
7205 A5
A A
2D01
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
26 27
FH12-25S-0.5SH(55)
D D
1 2 3 4 5 6 7 8 9 10
B003 B004
1 2009-11-03
18770_640_100212.eps
100219
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 109
9 LED Everlight
9 LED Everlight
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13
2D10 C13
+24V 3D02-1 A1
3D02-2 A1
8 3D02-1 1
7D01-1
3D02-3 B1
10K
BC847BS(COL)
6
2 3D02-4 B1
A A
2 3D02-2 7
1
3D05-3 C1
10K
FD01
3D05-4 C1
PWM-B4
+24V
1 3D10 2 +24V 3D10 A12
7300 7301 7302 7303 7304 7305 270R
99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D 99-135/RSGBB7C-A24/2D
1
3D11
2 3D11 B12
6 3D02-3 3
BC847BS(COL) 3D12
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
4
10K
1K5
7D02
C
10K
BC847BW 3 4 3D13-4 5 C
1
1K5 7302 B7
7303 B8
2D10
100n
5 3D05-4 4
2
10K
7304 B10
PWM-G4
FD03
7305 B11
7D01-1 A2
D FD04
D 7D01-2 B2
7D02 C2
FD01 A1
FD02 C1
FD03 D1
FD04 D1
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2009-11-03
18770_641_100212.eps
100212
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 110
15 LED Everlight
AL2A AL2A
1 2 3 4 5 6 7 8 9 10
1M84 A10
2D01 B6
7203 A3
A A 7204 A4
7205 A5
7203
99-235/RSBB7C-A24/2D
7204
99-235/RSBB7C-A24/2D
7205
99-235/RSBB7C-A24/2D
SPI-CLOCK-BUF
1M84
1
FD18 C7
SPI-DATA-OUT 2
Blue 5 BLUE 6 5 BLUE 6 5 BLUE 6 SPI-DATA-RETURN
+24V 3
4
Green 1 GREEN 2 1 GREEN 2 1 GREEN 2 PWM-CLOCK-BUF 5
+3V3 6
Red 3 RED 4 3 RED 4 3 RED 4 SPI-CS 7
B LATCH 8 B
2D01
100n
9
PROG 10
BLANK 11
+3V3 12
13
14
TEMP-SENSOR 15
16
17
18
19
20
21
C 22
23
C
24
+24V 25
FD18 26 27
D D
1 2 3 4 5 6 7 8 9 10
1 2009-11-27
18770_660_100212.eps
100526
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 111
15 LED Everlight
15 LED Everlight
AL2B AL2B
1 2 3 4 5 6 7 8 9 10 11 12 13
2D10 C13
+24V 2D11 H13
3D02-1 A1
8 3D02-1 1
7D01-1
3D02-2 A1
10K
BC847BS(COL)
6
A 2
A 3D02-3 B1
2 3D02-2 7
10K
1 3D02-4 B1
3D03-3 H2
PWM-B4
FD01
3D10
3D03-4 G2
+24V 7300
99-235/RSBB7C-A24/2D
7301
99-235/RSBB7C-A24/2D
7302
99-235/RSBB7C-A24/2D
7303
99-235/RSBB7C-A24/2D
7304
99-235/RSBB7C-A24/2D
7305
99-235/RSBB7C-A24/2D
68R
+24V
3D04-1 F2
3D11 RES
3D04-2 G2
6 3D02-3 3
B BC847BS(COL)
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 3D12
B 3D04-3 E2
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3D04-4 F2
4 3D02-4 5
4
3D05-3 C1
10K
1 3D13-1 8 3D05-4 D1
FD02 1K5
PWM-R4
2 3D13-2 7
3D10 B12
+24V
1K5
3D11 B12
3 3D13-3 6
C C 3D12 B12
3 3D05-3 6
1K5
7D02
10K
4 3D13-4 5
BC847BW 3
1K5
3D13-1 B12
1
3D13-2 C12
2D10
100n
5 3D05-4 4
3D13-3 C12
10K
FD03
3D13-4 C12
PWM-G4
3D15 F12
D D 3D16 F12
3D17 F12
3D18-1 G12
3D18-2 G12
+24V
3D18-3 G12
3D18-4 G12
E E
3
7300 B5
3D04-3
7D03-1
10K
BC847BS(COL)
6
7301 B6
6
2
7302 B7
5
1
3D04-4
10K
7303 B8
4
PWM-B5
FD04 7304 B10
3D15
+24V 7400 7401 7402 7403 7404 7405 68R
+24V 7305 B11
F 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D 99-235/RSBB7C-A24/2D
3D16 RES F 7400 F5
1
7D03-2
7401 F6
10K
BC847BS(COL) 3D17
3 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2 1 GREEN 2
7402 F7
8
68R
5 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4 3 RED 4
7403 F8
7
4
3D04-2
10K
1 3D18-1 8
7404 F10
2
PWM-R5
FD05 1K5
7405 F11
2 3D18-2 7
G +24V
1K5
G 7D01-1 A2
3 3D18-3 6
7D01-2 B2
5
1K5
3D03-4
7D04
10K
1K5
1
7D03-1 E2
2D11
100n
3
7D03-2 F2
2
3D03-3
10K
7D04 G2
6
H FD06 H
PWM-G5
FD01 A1
FD02 C1
FD03 D1
FD04 F1
FD05 G1
FD06 H1
1 2 3 4 5 6 7 8 9 10 11 12 13
1 2009-11-27
18770_661_100212.eps
100212
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 112
AmbiLight Everlight
18 LED
3B35
3B36
FB01 FC01
FB32
3B03
7B06
3B37
3C00
3B31
3B52
7B25 3B51
3B55
B001
B007
B002
B003
FB12
3B18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202
FB04
FB11
2B09
3B50 2C15
3B30
2B03
FB07
3C12
3B53
7B26
1M83 1M84
3C15
3B01
3B34
3B07
3B13
3B22
7B50
2B01 7B07
7C20
FB70
2B04
FB40
2B17
7C22
2B11
7B51
FB41 FB05 FB06 FB35
3B21 2B50
3B00
3C11
7B30
3B02
2B10
2B02
2B20
2B08
3B11
2B00
7B23 7B20 3B57
3004
FB13 FB03
FB20 3C10 3C06
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71
24 LED
3B35
3B36
7B26
FB01 FC01
FB32
3B03
7B06
3B37
3C00
3B31
3B52
7B25 3B51
3B55
B001
B007
B002
B003
B004
FD03
FB12
3B18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202 7203 7204 7205 7300 7301 7302 7303 7304 7305
FB04
FB11
2B09
3B50
3B30
2B03
3C12
3B53
1M83 1M84
FB07
3C15
3B01
3B34
2D10
3B07
3B13
7D02
3B22
7B50
7B07
2B01
7C20
FB70
2B04
FB40
2B17
7C22
2B11 3D05
7B51
FB41 FB05 FB06 FB35
3B21 2B50
3D13
3D10
3B00
3C11
7B30 3D02
3D12
7D01
3B02
2B10
2B02
2B20
2B00
FB13 FB03
FB20 3C10 3C06 FD04 3D11
FB30 3B39 FB08 FB16 FB10 FB31 FB15
FB72
FC02 FC03 FB71
30 LED
3B35
3B36
FB01 FC01
3B03
FB32
B003
B005
B004
3B37
7B06
3C00
3B31
3B52
7B25
3B55
3B51
FB12
B001
B007
B002
7203 7204 7205 7300 7301 7302 7303 7304 7305 7400 7401 7402 7403 7404 7405
FD03 FD05
3B18
7000 7001 7002 7003 7004 7005 7100 7101 7102 7103 7104 7105 7200 7201 7202
FB04
FB11
2B09
3B30
2B03 3B50
FB07
3C12
3B53
7B26
1M83 1M84
3C15
3B01
2D10
3B34
3B07
3B13
7D02
3B22
7D04
2D11
3D12
3D17
7B50
3D03
2B01
7B07
7C20
FD18
2B04
FB70
7C22
FB40
3D13
2B17
7B51
2B11 3D05 3D10
3D04
FB05 FB06
FB41
3B21 2B50
FB35
2D01 3D15
3B00
7B30 3C11
3D02 7D01 7D03
3B02
2B10
2B02
2B20
FD01 FD02
3D18
2B08
3B11
2B00
3004
18770_672_100216.eps
100527
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 113
Common Interface
B01A B01A
1 2 3 4 5 6 7 8 9 10 11 1P00-A D10
1P00-B G10
2F00 A6
+3V3
3F06
2F01 A2
3F01 CA-RST 100K
2F00
+5V +5VCA TRANSPORT STREAM FROM CAM
7F00
RES
CA-CD1n 4 3F07-4 5
2F02 B6
+T 0R4 100n
20
22u 16V
74LVC245A 10K
2 3F07-2 7
2F03 D6
2F01
1 CA-CD2n
3EN1
3EN2 3F07-3
10K
2F04 E6
RES
19 CA-DATAENn 3 6
A IF01
G3
10K
+3V3
A
CA-MOCLK
3F02
2
1
18 MOCLK CA-DATADIR 1
3F07-1
8 2F05 G6
100R IF02 2 10K
3F03-1
CA-MOVAL
CA-MOSTRT 3F03-2 2 7
1 8
100R
3
4
17
16
MOVAL
MOSTRT CA-ADDENn 1 3F08-1 8
2F06 H6
100R IF03 5
6
15
14 MOCLK
10K
2 3F08-2 7 3F01 A2
7 13 10K
8 12 MOVAL 3 3F08-3 6 3F02 A4
9 11 10K
MOSTRT 4 3F08-4 5 3F03-1 A4
10
10K
MDO0 1 3F09-1 8
3F03-2 A4
B +3V3 10K
2 3F09-2 7
B 3F04-1 C4
2F02 MDO1
RES 10K
7F01 100n MDO2 3 3F09-3 6 3F04-2 C4
20
74LVC245A 10K
1
3EN1 MDO3 4 3F09-4 5
10K
IF04
3F04-3 C4
3EN2
IF05
19
G3
MDO4 1
3F10-1
8
3F04-4 C4
3F04-1 1 8 100R 2 18
CA-MDO0
IF06 2
1 MDO0
MDO5 2
10K
3F10-2
7 3F05-1 C4
CA-MDO1 3F04-2 2 7 100R 3 17 MDO1 10K
CA-MDO2 3F04-3 3 6 100R
3F04-4 4 5 100R
4
5
16
15
MDO2 MDO6 3 3F10-3 6 3F05-2 C4
CA-MDO3 MDO3 10K
C CA-MDO4 3F05-1 1 8 100R
3F05-2 2 7 100R
6
7
14
13
MDO4 MDO7 4 3F10-4 5
10K
C 3F05-3 C4
CA-MDO5 MDO5
CA-MDO6
CA-MDO7
3F05-3 3 6 100R
3F05-4 4 5 100R
8
9
12
11
MDO6
MDO7
3F12
3F05-4 C4
CA-RDY
IF07 +3V3
3F06 A9
10
10K
CA-WAITn 2 3F11-2 7
15-BIT ADDRESS
2F03
RES CA-WP
10K
4 3F11-4 5
3F07-2 A9
7F02 100n 3F11-1
10K
3F07-3 A9
20
74LVC245A CA-VS1n 8 1 +3V3 ROW_A
1 10K 1P00-A
D 3EN1
3EN2
GND1
1 D 3F07-4 A9
19 CA-ADDENn CA-D03 D3
G3 2
XIO-A00 18 2 CA-A00
CA-D04
CA-D05
D4
D5
3 3F08-1 A9
1 4
XIO-A01 17
2
3 CA-A01
CA-D06
CA-D07
D6
D7
5
6
3F08-2 A9
16 4 CE1
XIO-A02
XIO-A03 15 5
CA-A02
CA-A03
CA-CE1n
CA-A10 A10
7
8
3F08-3 B9
XIO-A04 14 6 CA-A04 CA-OEn OE
XIO-A05 13
12
7
8
CA-A05 CA-A11 A11
A9
9
10 3F08-4 B9
XIO-A06 CA-A06 CA-A09 11
XIO-A07 11 9 CA-A07 CA-A08
CA-A13
A8
A13
12 3F09-1 B9
13
3F09-2 B9
10
CA-A14 A14
E CA-WEn WE|P
RDY|BSY
14
15 E
CA-RDY
+3V3 +5VCA VCC1
16
17
3F09-3 B9
VPP1
7F03
2F04
RES CA-MIVAL A16
A15
18
19 3F09-4 B9
100n CA-MICLK 20
3F10-1 C9
20
F XIO-A09
XIO-A10
17
16
3
4
CA-A09
CA-A10
CA-A01
CA-A00
A1
A0
28
F 3F10-4 C9
29
XIO-A11
XIO-A12
15
14
5
6
CA-A11
CA-A12
CA-D00
CA-D01
D0
D1
30 3F11-1 D9
31
13 7 D2
XIO-A13
XIO-A14 12 8
CA-A13
CA-A14
CA-D02
CA-WP WP|IOIS16
32
33
3F11-2 C9
11 9 GND2
70 69
34
3F11-3 D9
10
10074595-050MLF 3F11-4 D9
+3V3
2F05
ROW_B
1P00-B 3F12 C9
8-BIT DATA RES GND3
7F04 CA-CD1n CD1
35 7F00 A5
G 100n 36
G
20
VPP2
52
CA-MDI4 A22
+3V3
CA-MDI5 A23
A24
53
54
IF03 A4
CA-MDI6 55
CONTROL
2F06
RES
CA-MDI7
MOCLK
A25
VS2
56 IF04 B9
57
7F05 100n CA-RST RESET
58 IF05 C4 1X04 1X01
20
18
G3
2
MOSTRT BVD1|STSCHG
D8
62
63 IF07 C5
XIO-D11 CA-REGn MDO0
I 17
1
2
3
MDO1 D9
D10
64
65 I IF08 D9
XIO-D09 CA-CE1n MDO2 66
XIO-D08 16 4 CA-CE2n CA-CD2n CD2
67
XIO-OEn 15 5 CA-OEn GND4
68
XIO-WEn 14 6 CA-WEn 72 71
XIO-D14 13 7 CA-IORDn
XIO-D15 12 8 CA-IOWRn 10074595-050MLF
CA-WAITn 11 9 XIO-D10
10
3 2009-10-22
18770_500_100118.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 114
Flash
Flash
B01B B01B
1 2 3 4
2F20 A3 3F20-1 B1 3F20-4 C2 3F21-3 C1 3F22-2 C1 3F23 C2 IF21 C3
2F21 A3 3F20-2 B2 3F21-1 C1 3F21-4 C2 3F22-3 C2 3F24 D2 IF22 D3
3F19 D2 3F20-3 B1 3F21-2 C2 3F22-1 C2 3F22-4 C2 7F20 B3 IF23 D3
+3V3
A A
2F20
2F21
100n
100n
7F20
12
37
NAND04GW3B2DN6F
B Φ VCC
1
2 B
[FLASH] 3
4Gx16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
C NAND-CE1n
IF21
25
26
C
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
WE
NAND-WPn IF22 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
3F19
48
10K
D VSS
D
13
36
+3V3
1 2 3 4
3 2009-10-22
18770_501_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 115
USB Hub
USB Hub
B01C B01C
1F24 E9
1 2 3 4 5 6 7 8 9 1F25 B1
1P07 B9
1P08 D9
2F25 A2
2F26 A2
2F27 A2
2F28 A4
IF44 +5V
2F29 A4
+3V3 2F30 A4
+T 0R4
2F31 A5
3F25
2F25
100n
2F32 A5
FF40 2F33 A5
+5V-USB1
3F26-1 2F34 B1
A 1
100K
A 2F35 B2
IF43 3F26-2 3F25 A8
USB-OC1n 2 7
3F26-1 A8
100K 3F26-2 A8
3F26-3 3F26-3 A8
2F26
2F27
2F28
2F29
2F30
2F31
2F32
2F33
100n
100n
100n
100n
100n
100n
3 6
1u0
1u0
100K 3F26-4 B8
3F26-4 3F28 B2
4 5
3F30 C2
100K 3F31-2 C2
3F28
1M0
14
34
36
23
15
10
29
USB2513B-AEZG 3F31-4 D2
5
1F25
B 1 3 CR PLL
FILT
VDD_3V3 USB-DP 9F25 USB-DP2
B 3F32 C8
24M Φ USB-DM 9F26 USB-DM2
3F34-1 C8
4
2
2F34
2F35
10K
10p
10p
IF33 IF35
33 13 USB-OC1n SIDE USB BOTTOM 3F34-3 D8
XTALIN|CLKIN OSC1
9F20
9F21
USBDP_DN1|PRT_DIS_P1
2 USB-DP1 3F34-4 D8
IF34
32 1 USB-DM1 1P07 3F35 B1
XTALOUT USBDM_DN1|PRT_DIS_M1
12 +5V-USB1
IF30 BC_EN1|PWRTPWR1 1 3F36 D6
RESET-USBn 26 IF36 USB-DM1 FF34
RESET 2 7F25 B2
17 USB-OC2n USB-DP1 FF35
OSC2 3 9F20 B7
11 4 USB-DP2
TEST USBDP_DN2|PRT_DIS_P2 +5V 4
IF42 USBDM_DN2|PRT_DIS_M2
3 USB-DM2 5 6 9F21 B7
3F31-2
2 7 28 16 9F25 B8
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
IF37 292303-4
10K 9F26 B8
C USB-DP IF31
IF32
31
DP OSC3
19 USB-OC3n
C FF30 E8
+T 0R4
USB-DM 30 USBUP 7 USB-DP3
3F32
DM USBDP_DN3|PRT_DIS_P3 FF31 E9
+3V3 27 6 USB-DM3
VBUS_DET USBDM_DN3|PRT_DIS_M3
BC_EN3|PWRTPWR3
18 FF32 E9
3F30 IF41 3F34-1 FF33
35 1 +5V-USB2 FF33 C9
RBIAS
12K IF40 8
3F31-3 100K FF34 C7
3 6 22 9
SDA|SMBDATA|NON_REM1 3F34-2 FF35 C7
10K 24 NC 20 USB-OC2n 2 7
3F31-4 IF39 SCL|SMBCLK|CFG_SEL0 FF36 D7
4 5 25 21 100K
HS_IND|CFG_SEL1
10K FF37 D7
3F34-3
3 6 FF38 E9
VIA
GND_HS
3F36 100K FF39 E8
37
38
39
40
41
+3V3 USB-OC3n
4
3F34-4
5 FF40 A8
10K
IF30 C2
D 100K SIDE USB TOP D IF31 C1
1P08 IF32 C1
+5V-USB2 1 IF33 B2
USB-DM2 FF36
2 IF34 B2
USB-DP2 FF37
3 IF35 B5
4 IF45
FF32 5 6 IF36 C5
IF37 C5
292303-4
IF39 D2
IF40 C2
IF41 C2
IF42 C2
E FF39 +5V
FF38
1F24
1
E IF43 A3
IF44 A3
USB-DM3 2
USB-DP3
IF45 D9
3
FF30 4
FF31 5
7 6
502382-0570
1 2 3 4 5 6 7 8 9
3 2009-10-22
18770_502_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 116
SD Card
SD Card
B01D B01D
1 2 3 4
1P09-1 C4
1P09-2 D4
2F40 A2
3F40 A2
3F41-1 C1
A A 3F41-2 C1
3F40 FF45
3F41-3 C1
+3V3 +3V3-SD
+T
3F41-4 C1
0R4
22u 16V
3F42-1 C1
2F40
3F42-2 D1
3F42-3 D1
3F43-1 C3
3F43-2 C3
3F43-3 C3
B B 3F44-1 C3
+3V3 3F44-2 C3
3F44-3 C3
3F41-2 IF47 3F44-2
3F45 C1
2 7 SDIO-DAT3 SDIO-DAT3 2 7 FF47
1P09-1
FF41 C3
47K 3F41-3 100R 3F43-2
3 6 SDIO-CMD SDIO-CMD 2 7 FF48
1 FF42 C3
47K 100R 2
+3V3-SD 3 FF43 C3
3F45 RES
SDIO-CLK SDIO-CLK 1 3F44-1 8
4 FF44 D3
C 10K 100R
FF49
5
6 C FF45 A2
3F41-1 3F43-3 7
1 8 SDIO-DAT0 SDIO-DAT0 3 6 FF41
8 FF46 C4
47K 3F41-4 100R 3F43-1 9 FF46
4 5 SDIO-DAT1 SDIO-DAT1 1 8 FF42 1314 FF47 C3
1
3F42-1
8
47K
SDIO-DAT2 SDIO-DAT2 3
3F44-3
6
100R
FF43 1939115-1 FF48 C3
47K 100R FF49 C3
FF50 D3
IF46 D1
1P09-2
2
3F42-2
7 SDIO-CDn SDIO-CDn FF44
IF47 B1
D 47K
10
11 D
3F42-3 IF46 12
3 6 SDIO-WP SDIO-WP FF50
1939115-1
47K
18770_503_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 117
PNX85500 Control
PNX85500 Control
B01E B01E
1 2 3 4 5 6 7 8 9
1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
A A 3F51 B1
+3V3-STANDBY +3V3-STANDBY
3F52 B3
3F53 C6
+3V3-STANDBY
+3V3 +3V3
3F54 D7
+3V3
3F51
100n
2F52
RES
10K
3F58 E1
3F59 E3
3F60 E3
RES
3F66
10K
3F52
10K
3F62 D5
8
7F52
B B
3F67
M25P05-AVMN6
3F63 E5
RES
10K
BACKLIGHT-BOOST
VCC IF50
PNX-SPI-SDI IF51 2
Q Φ D
5 PNX-SPI-SDO 7F53 RES
PDTA114EU +5V
3F64 F5
512K IF52
3F65 F5
6 PNX-SPI-CLK
FLASH C
IF53 3F66 B7
RES
1 PNX-SPI-CSBn
S
IF54
IF55
3F67 B6
3
3F68
47K
W PNX-SPI-WPn BOOST-PWM
7F54-1 RES 3F68 C7
7 BC847BPN(COL) 6
HOLD +3V3-STANDBY
FF29 IF61 7F54-2 RES
3F69 D7
IF56
VSS SPI-PROG BC847BPN(COL)
4 2
7F52 B2
C IF57
1 C 7F53 B7
4
IF62 5
FF04
SDM 7F54-1 C7
3
7F54-2 C7
3F53
9CH0 FF58
7F58 D1
10K RES 9CH0 C7
RES
RES
FF04 C4
2F53
3F69
3F54
RES
1K0
FF29 C4
1u0
10K
+3V3 MAIN NVM FF55 E3
D D FF56 E3
DEBUG ONLY
FF57 E2
IF58 2F58 RES FF61 3F62 100R
1F52 FF58 C7
SCL-SSB 1 SCL
100n
FF62
2
FF61 D4
SDA-SSB SDA
7F58
3F63
3 FF62 D7
8
FF63 100R 4 5
Φ FF63 E4
3F58
10K
(8K×8) 7 FF64 F7
WC
EEPROM 3F59 FF55
FF65 F4
IF59 1 6 SCL-UP-MIPS
0 SCL
2
1 ADR 100R FF56 FF66 F4
E 3
2 SDA
5
3F60
SDA-UP-MIPS E IF50 B3
100R
4
IF51 B1
FF57 IF52 B3
DEBUG / RS232 INTERFACE LEVEL IF53 B3
IF54 C3
SHIFTED
1F51 IF55 C6
FF65 3F64
TXD-UP
FF64
1
FOR IF56 C7
FF66 100R 3F65 2
RXD-UP UP IF57 C7
3
F RESET-STBYn
SPI-PROG
100R
4 DEBUG F IF58 D2
5
7 6
USE ONLY IF59 E1
IF61 C4
IF62 C4
1 2 3 4 5 6 7 8 9
3 2009-10-22
18770_504_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 118
HDMI & CI
HDMI & CI
B01F B01F
1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7
1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5F72 E4 7F70 D8 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5
2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 7F75 A6 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B8 IF79 C5 IF87 C2
2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79-1 B8 5F66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2
2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79-4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5
1 2 3 4 5 6 7 8 9 10
IF10
IF11
A 1T01
TX31XX PNX-IF-P
A
2F71
9F00
9F01
9F02
9F03
FF71 +5V-TUN-PIN
15
TUNER 14
4MHZ_REF 10n
2F72
2F73
15p
1p0
I2C_ADR
I2C_SDA
IF_OUT1
IF_OUT2
RF_AGC
I2C_SCL
7F75
B+_TUN
B+_LNA
1
16 13
RF_IO
UPC3221GV-E1
TUN
NC
AF72
2F65
VCC
15p
IF75 2F74 IF73 2F75 IF76 3F79-1
1F75 2 INPUT1 OUTPUT1 7 IF74 1
10
11
12
2p2 RES
1 4
1
5F71
2F76
2F77
5F74
2F62
2F70
680n
820n
2 5
22p
10p
1p0
IGND O2 2F78 IF77
3 INPUT2 OUTPUT2 6 IF78
2F79 IF80 3F79-4
AF71 TUN-IF-N 3 4
GND IF81 10n
820R
5F76
3F82
330n
AF70 TUN-IF-P
GND1
GND2
FF74 FF76 220R
B TUN-P1 FF00
9F04 IF-AGC
X7251X
36M17
4 VAGC AGC CONTROL
10n AF73
B
RES
RES
2F80
2F82
15p
1p0
2F81
2F59
2F60
100n
4u7
5
2F61 FF75
4n7
4u7
PNX-IF-N
2F93
100n
IF82 3F77
TUN-P6 FF81 PNX-IF-AGC IF12 IF13
3F80 2F63
TUN-P7 FF82 4K7 IF79 IF-
FF01 220R 10n
5F66
680n
22p
IF-AGC IF72
+5V-TUN-PIN 2F66
+5V-TUN-PIN
9F05
9F06
IF+
C C
BA591
2F85
3F71
6F72
2F92
4K7
1K0
47n
10n
3F72 220R 10n
IF86 2F90
2F84 3F76 IF87 SCL-TUNER 10n
3F78
3K3
15p 47R 3 5F73 2
TUN-P6 TUN-IF-N
5F70
470n
2F86 3F75 IF88 4 1
SDA-TUNER TUN-IF-P
15p 47R ATB2012 2F91
TUN-P7
10n RES
D IF89
SELECT-SAW
IF90
7F70
D
PDTC114EU
2F94
RES
10n
9F71
E 5F72
+5V-TUN-PIN
E
+5V-TUN
30R RES
2F88
22u
1 2 3 4 5 6 7 8 9 10
3 2009-10-22
18770_505_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 119
Toshiba Supply
Toshiba Supply
B01G B01G
1 2 3
2FA2 C1
2FA3 C2
2FA4 C3
A A 5FA3 B2
5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2
+3V3 +1V2-BRA-DR1
+1V2-BRA-VDDC
B B
5FA3
5FA4
30R
30R
7FA3
LD1117DT12
FFAF
3 2
IN OUT
COM
2FA2
2FA3
2FA4
100n
100n
10u
1
FFA2
C C
D D
18770_506_100118.eps
100525
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 120
HDMI
HDMI
B01H B01H
1P05 B1 3FBF-1 C4 3FBF-2 C4 FFB1 C2 FFB2 C2 FFB3 C2 FFB4 C2 FFB5 C1 FFB6 C2
1 2 3 4
A A
B 4
5
DRX1+
B
6 DRX1-
7 DRX0+
8
9 DRX0-
1 3FBF-1 8
10 DRXC+
47K
11
12 DRXC-
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15 3FBF-2
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 7 DIN-5V
16
17 47K
FFB3
C 18
19 FFB4
DIN-5V
DRX-HOTPLUG C
FFB5 21 20
23 22 FFB6
1 2 3 4 3 2009-10-22
18770_507_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 121
VGA
VGA
B01I B01I
1 2 3 4 5 6 7 8 9 1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
1FC4 C4
A A 1FC5 D4
FFC1 3FC5
1FC6 F4
R-VGA
2FC1 B4
CDS4C12GTA
18R
2FC2 B4
2FC1
1FC1
RES 6FC1
100p
12V
2FC3 C4
2FC4 C4
FFC2 3FC6
G-VGA 2FC5 D4
B B
CDS4C12GTA
18R
2FC6 E4
RES 6FC2
2FC2
1FC2
100p
12V
2FC7 E4
1E05 2FC8 F4
1
2 3FC7
3FC1 D3
B-VGA
3
3FC2 E3
CDS4C12GTA
4 FFC3 18R
5
3FC3 C6
RES 6FC3
2FC3
1FC3
100p
12V
6
VGA 7
3FC4 D6
8
CONNECTOR
C 9
10
FFC4 C 3FC5 A6
11
12
FFC5
9FC5 H-SYNC-VGA 3FC6 B6
13
3FC7 C6
RES 6FC4
CDS4C12GTA
14
2FC4
1FC4
3FC3
12V
47p
4K7
15 16 6FC1 B5
17
1216-00D-15S-1EF
FFC6 6FC2 B5
FFC7
6FC3 C5
9FC6 V-SYNC-VGA
6FC4 C5
CDS4C12GTA
D D
RES 6FC5
6FC5 D5
2FC5
1FC5
3FC4
12V
47p
4K7
6FC6 E5
RES
9FC1 VGA-SDA-EDID-HDMI 6FC7 E5
3FC1 FFC8
9FC2 VGA-SDA-EDID 6FC8 F5
RES
CDS4C12GTA
10K
9FC1 D6
6FC6
2FC6
12V
47p
9FC2 E6
9FC3 E6
E RES
3FC2 FFC9
9FC3 VGA-SCL-EDID-HDMI
E 9FC4 E6
9FC4 VGA-SCL-EDID
9FC5 C6
CDS4C12GTA
10K RES
9FC6 D6
2FC7
6FC7
12V
47p
FFC1 A4
FFC2 B4
+5V-VGA FFC3 C4
CDS4C12GTA
FFC4 C3
F
2FC8
1FC6
6FC8
F
12V
47p
FFC5 C4
FFC6 D2
FFC7 D4
FFC8 D4
FFC9 E4
1 2 3 4 5 6 7 8 9
3 2009-10-22
18770_508_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 122
3FD1
3FD2 RES
1K0
RES 3FD3 B3
2FD1
9FD1
9FD2
100n
1K0
3FD4 B2
LTST-C190KGKT
3FD6 C4
8
RES 7FD1
LM75BDP 3FD7 C4
6FD1
+VS
B 3
OS A0
7 IFD1
B 3FDG-1 D4
IFD2
SDA-SSB
3FD3
1
SDA A1
6 IFD3 3FDG-2 D4
100R IFD4
SCL-SSB
3FD4
2
SCL A2
5 IFD5 6FD1 B3
GND
100R
6FD2 D4
3FD6 RES
3FD7 RES
9FD5
1K0
1K0
6FD3 D5
4 7FD1 B3
9FD1 A4
C C 9FD2 A4
9FD5 C5
1329
FFDA D5
1
2
FFDB D5
5 4
3 FFDC D6
502382-0370 IFD1 B4
IFD2 B3
D FFDA 1328
D IFD3 B4
AMP1 2
AMP2 3 IFD4 B3
1
CDS4C12GTA
CDS4C12GTA FFDB
IFD5 B4
8
FFDC
3FDG-1
3FDG-2
2FDC
2FDD
1FD2
6FD2
1FD3
6FD3
1K0
1K0
12V
12V
1n0
1n0
MSJ-035-29D PPO (PHT)
1
E E
1 2 3 4 5 6 7 8 9
3 2009-10-22
18770_509_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 123
Tuner Brazil
Tuner Brazil
B01K B01K
1 2 3 4 5 6 7 8 9 10 11 12 13
1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
A A 2FF1 A7
5FE0 IF63 IF64 2FF2 B6
+2V5-BRA +1V2-BRA-VDDC 2FF3 B6
30R
2FF4 B6
2FE0
2FE3
2FE4
2FE5
2FF0
2FF1
100n
100n
100n
100n
1u0
1u0
2FF5 B6
+3V3-BRA-FLT
2FF6 B7
2FF7 C6
AGND 2FF8 C6
5FE3 IF65 IF66 5FE4
+3V3-BRA-FLT
+3V3-BRA 2FF9 C7
30R 30R 2FG0 C6
B B 2FG1 C7
2FE6
2FF2
2FF3
2FF4
2FF5
2FF6
100n
100n
100n
100n
1u0
1u0
2FG2 C1
2FG3 C2
AGND
2FG4 D3
5FE5 IF67 IF68 2FG6 D3
+1V2-BRA-DR1
5FE7 IF48 2FG7 E3
30R
+3V3 +3V3-BRA 2FG8 E3
2FE8
2FF7
2FF8
2FF9
100n
100n
1u0
1u0
30R 2FG9 E3
2FH2 D11
2FH3 D12
C IF69 5FE8
+2V5-BRA C 2FH4 D12
30R 7FE3 2FH5 D6
1FE0 LD3985M25
2FH6 E3
2FG0
2FG1
100n
1 3
1u0
5FE9 FF03
25M4 +5V
1
IN OUT
5 +2V5-BRA 2FH7 E3
30R 2FH8 E7
2FG2
4 2
2FG3
3 4
18p
18p
INH BP
3FE5 E7
COM 3FE6 F3
7FE0
3FE7 F3
32
22
20
16
36
56
63
13
35
49
64
34
DR1VDD 48
43
2FH2
2FH3
2FH4
TC90517FG
1u0
10n
1u0
2
AGND AGND AGND
3FE8 F3
AD_DVDD
AD_AVDD
PLLVDD
DR2VDD
19
VDDC Φ VDDS
21
2FH5
I FIL
AGND 3FE9 F3
D 18
O
X
PBVAL
58
1n5
3FG6-4 4 5 33R TS-FE-VALID D 3FG2-1 F6
3 53
DFE6
4 9F27-4 5
3FG2-2 F7
0 RERR TS-DVBS-VALID
2 XSEL 3FG4-1 F7
1 DFE7
RLOCK
54 3FG4-2 F6
IF+ 2FG4 10n IF17 30
IF- 2FG6 10n IF18 29
P
ADI_AI 55
DFE8
2 9F27-2 7 TS-DVBS-SOP
3FG6-2 E7
N RSEORF
3FG6-3 E7
2FG7 100n BFE1 28 59 3FG6-3 3 6 33R
P SBYTE TS-FE-SOP 3FG6-4 D7
2FG8 100n BFE2 27 ADQ_AI
N DFE9
52 9F28 TS-DVBS-CLOCK 5FG0
3FG7 E7
AGND BFE3 SLOCK
2FG9 100n 24 5FE0 A3
BFE4 P
2FH6 100n 25 AD_VREF 61 3FG7 33R TS-FE-CLOCK
N SRCK 30R 5FE3 B3
E AGND
2FH7 100n BFE5 26
AD_VREF SRDT
60 3FG6-2 2 7 33R TS-FE-DATA 5FG2 E 5FE4 B7
39 38
DFF1
1 9F27-1 8
5FE5 B3
AGND DTCLK STSFLG1 TS-DVBS-DATA 30R
IF27 IF28 5FE7 C11
3FE5 AGND
40 9 IF-AGC 5FE8 C7
+3V3-BRA-FLT DTMB AGCCNTI
18K 5FE9 C11
2FH8
8 10
10n
S_INFO AGCCNTR
DFF2 5FG0 E11
3FE6 10K 1 51
41
0
TSMD
STSFLG0 5FG2 E11
1
SYRSTN
42 7FE0 D4
3FE7 10K IF29 7 7FE3 C11
AGCI 3FG2-1
6 RESET-SYSTEMn
11 SLADRS
0
5 10K 3FG2-2 9F27-1 E8
F CKI 1
3FG4-2
10K F 9F27-2 D8
AD_DVSS
AD_AVSS
31
17
4
15
33
37
44
47
50
57
62
BFE2 E4
BFE3 E4
BFE4 E4
AGND AGND
BFE5 E4
DFE6 D6
DFE7 D6
G G DFE8 D6
DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
H H IF48 C12
IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
IF67 B4
IF68 B5
IF69 C6
1 2 3 4 5 6 7 8 9 10 11 12 13
3 2009-10-22
18770_510_100118.eps
100525
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 124
Common Interface
B01A B01A
1 2 3 4 5 6 7 8 9 10 11 1P00-A D10
1P00-B G10
2F00 A6
2F01 A2
+3V3
3F06
2F02 B6
100K
+5V
3F01
TRANSPORT STREAM FROM CAM
2F00
RES
CA-RST 2F03 D6
+5VCA
+T 0R4 7F00 CA-CD1n 4 3F07-4 5 2F04 E6
100n
20
74LVC245A 10K
22u 16V
2 3F07-2 7 2F05 G6
2F01
1 CA-CD2n
3EN1
10K
3EN2 3F07-3 2F06 H6
RES
19 CA-DATAENn 3 6
A 3F02 IF01
2
G3
18 1
3F07-1
10K
8
+3V3
A 3F01 A2
CA-MOCLK 1 MOCLK CA-DATADIR
100R 3F03-1 IF02 2 10K 3F02 A4
CA-MOVAL 1 8 3 17 MOVAL
CA-MOSTRT 3F03-2 2 7 100R 4 16 MOSTRT CA-ADDENn 1 3F08-1 8 3F03-1 A4
5 15 10K
100R IF03
6 14 MOCLK 2 3F08-2 7 3F03-2 A4
7
8
13
12
10K
3 3F08-3 6
3F04-1 C4
MOVAL
9 11 10K 3F04-2 C4
MOSTRT 4 3F08-4 5
3F04-3 C4
10
10K
MDO0 1 3F09-1 8
3F04-4 C4
B +3V3 10K
2 3F09-2 7
B 3F05-1 C4
2F02 MDO1
RES 10K 3F05-2 C4
7F01 MDO2 3 3F09-3 6
100n 3F05-3 C4
20
74LVC245A 10K
4 3F09-4 5 IF04
1
3EN1 MDO3
10K
3F05-4 C4
3EN2
19
G3 3F10-1
3F06 A9
IF05 MDO4 1 8
CA-MDO0 3F04-1 1 8 100R 2
1
18 MDO0
3F10-2
10K 3F07-1 A9
MDO5 2 7
CA-MDO1 3F04-2 2 7 100R
IF06
3
2
17 MDO1 10K
3F07-2 A9
CA-MDO2 3F04-3 3 6 100R 4 16 MDO2 MDO6 3 3F10-3 6 3F07-3 A9
CA-MDO3 3F04-4 4 5 100R 5 15 MDO3 10K
C CA-MDO4 3F05-1 1 8 100R
3F05-2 2 7 100R
6
7
14
13
MDO4 MDO7 4 3F10-4 5
10K
C 3F07-4 A9
CA-MDO5 MDO5
CA-MDO6 3F05-3 3 6 100R 8 12 MDO6 3F08-1 A9
3F05-4 4 5 100R 9 11
CA-MDO7 MDO7
CA-RDY
3F12 3F08-2 A9
IF07 +3V3
3F08-3 B9
10
10K
CA-WAITn 2 3F11-2 7
10K 3F08-4 B9
+3V3 CA-INPACKn 3 3F11-3 6 IF08
10K
+5VCA 3F09-1 B9
2F03
15-BIT ADDRESS RES 4 3F11-4 5
CA-WP
10K
3F09-2 B9
7F02 100n
8 3F11-1 1
20
74LVC245A CA-VS1n +3V3 ROW_A 3F09-3 B9
1 10K 1P00-A
D 3EN1
3EN2
19
GND1
D3
1 D 3F09-4 B9
CA-ADDENn CA-D03
G3
CA-D04 D4
2 3F10-1 C9
3
XIO-A00 18
1
2 CA-A00 CA-D05 D5
D6
4 3F10-2 C9
2 CA-D06 5
XIO-A01 17 3 CA-A01 CA-D07 D7
6 3F10-3 C9
XIO-A02 16 4 CA-A02 CA-CE1n CE1
XIO-A03 15 5 CA-A03 CA-A10 A10
7
8
3F10-4 C9
14 6 OE
XIO-A04
XIO-A05 13 7
CA-A04
CA-A05
CA-OEn
CA-A11 A11
9 3F11-1 D9
10
XIO-A06 12
11
8
9
CA-A06 CA-A09 A9
A8
11 3F11-2 C9
XIO-A07 CA-A07 CA-A08 12
CA-A13 A13
13
3F11-3 D9
10
CA-A14 A14
E CA-WEn WE|P
RDY|BSY
14
15 E 3F11-4 D9
+3V3
CA-RDY
VCC1
16 3F12 C9
+5VCA 17
2F04
VPP1
18 7F00 A5
RES CA-MIVAL A16
19
7F03 100n CA-MICLK A15
20
7F01 B5
20
10074595-050MLF IF06 C5
+3V3 ROW_B IF07 C5
1P00-B
8-BIT DATA
2F05
RES GND3 IF08 D9
35
7F04 CA-CD1n CD1
G 100n 36
G
20
VPP2
52
CA-MDI4 A22
53
CA-MDI5 A23
54
+3V3 CA-MDI6 A24
55
CA-MDI7 A25
2F06 56
CONTROL RES MOCLK VS2
57
7F05 CA-RST RESET
100n 58
20
1 2 3 4 5 6 7 8 9 10 11
1X04 1X01
REF EMC HOLE REF EMC HOLE
4 2010-02-16
18770_830_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 125
Flash
Flash
B01B B01B
1 2 3 4
2F20 A3 3F20-1 B1 3F20-4 C2 3F21-3 C1 3F22-2 C1 3F23 C2 IF21 C3
2F21 A3 3F20-2 B2 3F21-1 C1 3F21-4 C2 3F22-3 C2 3F24 D2 IF22 D3
3F19 D2 3F20-3 B1 3F21-2 C2 3F22-1 C2 3F22-4 C2 7F20 B3 IF23 D3
+3V3
A A
2F20
2F21
100n
100n
7F20
12
37
NAND04GW3B2DN6F
B Φ VCC
1
2 B
[FLASH] 3
4Gx16 4
5
XIO-D00 3F20-1 1 8 100R 29 6
0
XIO-D01 3F20-2 2 7 100R 30 10
1
XIO-D02 3F20-3 3 6 100R 31 11
2
XIO-D03 3F20-4 4 5 100R 32 14
3
XIO-D04 3F21-1 1 8 100R 41 IO 15
4
XIO-D05 3F21-2 2 7 100R 42 20
5
XIO-D06 3F21-3 3 6 100R 43 21
6
XIO-D07 3F21-4 4 5 100R 44 22
7
NC 23
24
C NAND-CE1n
IF21
25
26
C
NAND-CLE 3F22-2 2 7 100R 16 27
CLE
NAND-ALE 3F22-3 3 6 100R 17 28
ALE
+3V3 3F23 10K 9 33
CE
XIO-OEn 3F22-1 1 8 100R 8 34
RE
XIO-WEn 3F22-4 4 5 100R 18 35
WE
NAND-WPn IF22 19 38
WP
+3V3 3F24 7 39
R
40
2K2 B
NAND-RDY1n 45
IF23 46
47
3F19
48
10K
D VSS
D
13
36
+3V3
18770_831_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 126
USB Hub
USB Hub
B01C B01C
1 2 3 4 5 6 7 8 9
1F24 E9
1F25 B1
1P07 B9
1P08 D9
2F25 A2
IF44 +5V
2F26 A2
+3V3 2F27 A2
+T 0R4
2F28 A4
3F25
2F25
100n
2F29 A4
FF40
+5V-USB1 2F30 A4
3F26-1
A 1
100K
A 2F31 A5
2F32 A5
IF43 3F26-2
USB-OC1n 2 7 2F33 A5
100K 2F34 B1
3F26-3 2F35 B2
2F26
2F27
2F28
2F29
2F30
2F31
2F32
2F33
100n
100n
100n
100n
100n
100n
3 6
1u0
1u0
100K
3F25 A8
3F26-4 3F26-1 A8
4 5
3F26-2 A8
100K
3F26-3 A8
3F28
1M0
14
34
36
23
15
10
29
USB2513B-AEZG
5
1F25 3F28 B2
B 1 3 CR PLL
FILT
VDD_3V3 USB-DP 9F25 USB-DP2
B 3F30 C2
24M Φ USB-DM 9F26 USB-DM2 3F31-2 C2
4
2
USB HUB
3F35
2F34
2F35
10K
10p
10p
9F20
9F21
2 USB-DP1
IF34 USBDP_DN1|PRT_DIS_P1
32
XTALOUT USBDM_DN1|PRT_DIS_M1
1 USB-DM1 1P07 3F32 C8
IF30 12 +5V-USB1 3F34-1 C8
BC_EN1|PWRTPWR1 1
RESET-USBn 26 IF36 USB-DM1 FF34
RESET
17 USB-OC2n USB-DP1 FF35
2 3F34-2 C8
OSC2 3
11
TEST USBDP_DN2|PRT_DIS_P2
4 USB-DP2 4
3F34-3 D8
3 +5V 5 6
3F31-2 IF42 USBDM_DN2|PRT_DIS_M2 USB-DM2 3F34-4 D8
2 7 28 16
SUSP_IND|LOCAL_PWR|NON_REM0BC_EN2|PWRTPWR2
292303-4 3F35 B1
10K IF37
3F36 D6
C USB-DP IF31
IF32
31
DP OSC3
19 USB-OC3n
C
+T 0R4
USB-DM 30 USBUP 7 USB-DP3 7F25 B2
3F32
DM USBDP_DN3|PRT_DIS_P3
+3V3 27 6 USB-DM3
VBUS_DET USBDM_DN3|PRT_DIS_M3
18
9F20 B7
3F30 IF41 BC_EN3|PWRTPWR3 3F34-1 FF33 9F21 B7
35 1 +5V-USB2
RBIAS
3F31-3 12K IF40 8 100K 9F25 B8
3 6 22 9
24
SDA|SMBDATA|NON_REM1
NC 20 2
3F34-2
7
9F26 B8
10K IF39 SCL|SMBCLK|CFG_SEL0 USB-OC2n
3F31-4 FF30 E8
4 5 25 21 100K
HS_IND|CFG_SEL1
10K 3F34-3
FF31 E9
3 6
GND_HS
VIA FF32 E9
3F36 100K FF33 C9
37
38
39
40
41
+3V3 USB-OC3n
3F34-4
10K 4 5 FF34 C7
D 100K SIDE USB TOP D FF35 C7
1P08 FF36 D7
+5V-USB2 1
FF37 D7
USB-DM2 FF36 FF38 E9
2
USB-DP2 FF37
3 FF39 E8
4 IF45
FF32 5 6 FF40 A8
IF30 C2
292303-4
IF31 C1
IF32 C1
IF33 B2
IF34 B2
E FF39 +5V
FF38
1F24
1
E IF35 B5
USB-DM3 2 IF36 C5
USB-DP3 3 IF37 C5
FF30 4
FF31 IF39 D2
5
7 6 IF40 C2
IF41 C2
502382-0570
IF42 C2
IF43 A3
IF44 A3
IF45 D9
1 2 3 4 5 6 7 8 9
4 2010-02-16
18770_832_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 127
SD Card
SD Card
B01D B01D
1 2 3 4
1P09-1 C4
1P09-2 D4
2F40 A2
3F40 A2
3F41-1 C1
3F41-2 C1
3F41-3 C1
3F41-4 C1
3F42-1 C1
A A 3F42-2 D1
3F40 FF45 3F42-3 D1
+3V3 +3V3-SD
+T
3F43-1 C3
0R4
3F43-2 C3
22u 16V
2F40
3F43-3 C3
3F44-1 C3
3F44-2 C3
3F44-3 C3
3F45 C1
FF41 C3
FF42 C3
B B FF43 C3
FF44 D3
FF45 A2
+3V3
FF46 C4
FF47 C3
FF48 C3
3F41-2 IF47 3F44-2
2 7 SDIO-DAT3 SDIO-DAT3 2 7 FF47 FF49 C3
1P09-1 FF50 D3
47K 3F41-3 100R 3F43-2
3 6 SDIO-CMD SDIO-CMD 2 7 FF48
1 IF46 D1
47K 100R 2 IF47 B1
+3V3-SD 3
3F45 RES 4
SDIO-CLK SDIO-CLK 1 3F44-1 8
C 10K 100R
FF49
5
6 C
3F41-1 3F43-3 7
1 8 SDIO-DAT0 SDIO-DAT0 3 6 FF41
8
47K 3F41-4 100R 3F43-1 9 FF46
4 5 SDIO-DAT1 SDIO-DAT1 1 8 FF42 1314
3F42-1 47K 3F44-3 100R
1 8 SDIO-DAT2 SDIO-DAT2 3 6 FF43 1939115-1
47K 100R
1P09-2
3F42-2 FF44
2 7 SDIO-CDn SDIO-CDn
D 47K
10
11 D
3F42-3 IF46 12
3 6 SDIO-WP SDIO-WP FF50
1939115-1
47K
4 2010-02-16
18770_833_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 128
PNX85500 Control
PNX85500 Control
B01E B01E
1 2 3 4 5 6 7 8 9
1F51 F8
1F52 D8
2F52 B1
2F53 D6
2F58 D2
A A 3F51 B1
+3V3-STANDBY +3V3-STANDBY 3F52 B3
3F53 C6
+3V3-STANDBY
3F54 D7
+3V3 +3V3
+3V3
3F58 E1
3F51
100n
2F52
RES
10K
3F59 E3
3F60 E3
RES
3F66
10K
3F62 D5
3F52
10K
8
7F52
B B 3F63 E5
3F67
M25P05-AVMN6
RES
10K
BACKLIGHT-BOOST
VCC IF50
PNX-SPI-SDI IF51 2 Φ 5 PNX-SPI-SDO 7F53 RES 3F64 F5
Q D PDTA114EU +5V
512K
6
IF52
PNX-SPI-CLK
3F65 F5
FLASH C
IF53 3F66 B7
RES
1 PNX-SPI-CSBn
S
IF54 3F67 B6
3 IF55
3F68
47K
PNX-SPI-WPn BOOST-PWM
W
7F54-1 RES
3F68 C7
HOLD
7
+3V3-STANDBY
BC847BPN(COL) 6 3F69 D7
FF29 IF61 7F54-2 RES IF56
VSS SPI-PROG BC847BPN(COL) 7F52 B2
4 2
C IF57
1 C 7F53 B7
4
5
FF04 IF62
SDM
7F54-1 C7
3
7F54-2 C7
3F53 FF58
7F58 D1
9CH0
10K RES 9CH0 C7
RES
RES
FF04 C4
2F53
3F69
3F54
RES
1K0
FF29 C4
1u0
10K
+3V3 MAIN NVM FF55 E3
D DEBUG ONLY D FF56 E3
FF57 E2
IF58 2F58 RES
SCL-SSB
FF61 3F62 100R
1F52
FF58 C7
1 SCL
100n
FF62
2 FF61 D4
SDA-SSB SDA
7F58
3F63
3 FF62 D7
8
FF63 100R 4 5
Φ FF63 E4
3F58
10K
(8K × 8) 7 FF64 F7
WC
EEPROM 3F59 FF55
IF59 1
0 SCL
6 SCL-UP-MIPS FF65 F4
2 100R
E 3
1
2
ADR
SDA
5
3F60 FF56
SDA-UP-MIPS E FF66 F4
100R IF50 B3
4
IF51 B1
FF57
IF52 B3
DEBUG / RS232 INTERFACE LEVEL IF53 B3
SHIFTED IF54 C3
FF65 3F64
1F51 IF55 C6
TXD-UP 1
FF66 100R 3F65
FF64
2
FOR IF56 C7
RXD-UP UP
F RESET-STBYn 100R
3
F IF57 C7
4 DEBUG
SPI-PROG
7 6
5 IF58 D2
USE ONLY IF59 E1
IF61 C4
IF62 C4
1 2 3 4 5 6 7 8 9
4 2010-02-16
18770_834_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 129
HDMI & CI
HDMI & CI
B01F B01F
1 2 3 4 5 6 7 8 9 10
IF10
IF11
A TH2603
1T01
PNX-IF-P
A
2F71
9F00
9F01
9F02
9F03
FF71 +5V-TUN-PIN
RF-IN 15 14 10n
2F72
2F73
15p
1p0
IF_OUT1
IF_OUT2
RF_AGC
7F75
1
16 13 UPC3221GV-E1
4Mhz
SDA
NC1
NC2
NC3
SCL
+5V
DC
AS
AF72
2F65
VCC
15p
IF75 2F74 IF73 2F75 IF76 3F79-1
1F75 2 INPUT1 OUTPUT1 7 IF74 1
10
11
12
2p2 RES
1 4
1
2
3
4
5
6
7
8
9 I O1 10n 10n 220R IF16
5F71
2F76
2F77
5F74
2F62
2F70
680n
820n
2 5
22p
10p
1p0
IGND O2 2F78 IF77
3 INPUT2 OUTPUT2 6 IF78
TUN-P1 2F79 IF80 3F79-4
AF71 TUN-IF-N 3 4
GND IF81 10n
820R
5F76
3F82
330n
AF70 TUN-IF-P
GND1
GND2
FF74 FF76 220R
B FF00
9F04 IF-AGC
X7251X
36M17
4 VAGC AGC CONTROL
10n AF73
B
RES
RES
2F80
2F82
15p
1p0
2F81
2F59
2F60
100n
4u7
5
2F61 FF75
4n7
4u7
PNX-IF-N
2F93
100n
IF82 3F77
TUN-P6 FF81 PNX-IF-AGC IF12 IF13
3F80 2F63
TUN-P7 FF82 4K7 IF79 IF-
FF01 220R 10n
5F66
680n
22p
IF-AGC IF72
+5V-TUN-PIN 2F66
+5V-TUN-PIN
9F05
9F06
IF+
C C
BA591
2F85
3F71
6F72
2F92
4K7
1K0
47n
10n
3F72 220R 10n
IF86 2F90
2F84 3F76 IF87 SCL-TUNER 10n
3F78
3K3
15p 47R 3 5F73 2
TUN-P6 TUN-IF-N
5F70
470n
2F86 3F75 IF88 4 1
SDA-TUNER TUN-IF-P
15p 47R ATB2012 2F91
TUN-P7
10n RES
D IF89
SELECT-SAW
IF90
7F70
D
PDTC114EU
2F94
RES
10n
9F71
E 5F72
+5V-TUN-PIN
E
+5V-TUN
30R RES
2F88
22u
1 2 3 4 5 6 7 8 9 10
1F75 B5 2F62 B10 2F70 B10 2F75 B8 2F80 B9 2F86 D1 2F93 C2 3F76 C2 3F80 C9 5F71 B9 6F72 C7 9F02 A8 9F71 E4 FF00 B2 FF76 B1 IF12 C9 IF72 C5 IF77 B6 IF82 C4 IF90 D7
1T01 A1 2F63 C9 2F71 A7 2F76 B9 2F81 B1 2F88 E5 2F94 D7 3F77 C4 3F81 C9 5F72 E4 7F70 D8 9F03 A8 AF70 B3 FF01 C4 FF81 C1 IF13 C9 IF73 B6 IF78 B8 IF86 C5
2F59 B1 2F64 C9 2F72 A9 2F77 B9 2F82 B9 2F90 C6 3F71 C7 3F78 C7 3F82 B10 5F73 C5 7F75 A6 9F04 B3 AF71 B3 FF71 A1 FF82 C2 IF14 C9 IF74 B8 IF79 C5 IF87 C2
2F60 B1 2F65 B10 2F73 A9 2F78 B6 2F84 C1 2F91 D6 3F72 C7 3F79-1 B8 5F66 C10 5F74 B10 9F00 A6 9F05 C4 AF72 B9 FF74 B1 IF10 A5 IF15 C9 IF75 B6 IF80 B8 IF88 D2
2F61 B1 2F66 C10 2F74 B6 2F79 B8 2F85 C4 2F92 C7 3F75 D2 3F79-4 B8 5F70 D6 5F76 B10 9F01 A6 9F06 C4 AF73 B9 FF75 B2 IF11 A5 IF16 B10 IF76 B8 IF81 B6 IF89 D5
4 2010-02-16
18770_835_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 130
Toshiba Supply
Toshiba Supply
B01G B01G
1 2 3
2FA2 C1
2FA3 C2
2FA4 C3
5FA3 B2
A A 5FA4 B3
7FA3 B2
FFA2 C2
FFAF B2
+3V3 +1V2-BRA-DR1
+1V2-BRA-VDDC
B B
5FA3
5FA4
30R
30R
7FA3
LD1117DT12
FFAF
3 2
IN OUT
COM
2FA2
2FA3
2FA4
100n
100n
10u
1
FFA2
C C
D D
18770_836_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 131
HDMI
HDMI
B01H B01H
1 2 3 4
A A
B 4
5
DRX1+
B
6 DRX1-
7 DRX0+
8
9 DRX0-
1 3FBF-1 8
10 DRXC+
47K
11
12 DRXC-
13 PCEC-HDMI
14
FFB1 DRX-DDC-SCL DRX-DDC-SCL
15 3FBF-2
FFB2 DRX-DDC-SDA DRX-DDC-SDA 2 7 DIN-5V
16
17 47K
FFB3
C 18
19 FFB4
DIN-5V
DRX-HOTPLUG C
FFB5 21 20
23 22 FFB6
1 2 3 4
1P05 B1 3FBF-1 C4 3FBF-2 C4 FFB1 C2 FFB2 C2 FFB3 C2 FFB4 C2 FFB5 C1 FFB6 C2 TUNER, HDMI & CI
4 2010-02-16
18770_837_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 132
VGA
VGA
B01I B01I
1 2 3 4 5 6 7 8 9
1E05 B2
1FC1 B4
1FC2 B4
1FC3 C4
1FC4 C4
1FC5 D4
1FC6 F4
A A 2FC1 B4
2FC2 B4
2FC3 C4
FFC1 3FC5
R-VGA 2FC4 C4
CDS4C12GTA
18R 2FC5 D4
2FC6 E4
2FC1
1FC1
RES 6FC1
100p
12V
2FC7 E4
2FC8 F4
3FC1 D3
3FC2 E3
FFC2 3FC6 3FC3 C6
G-VGA
3FC4 D6
B B
CDS4C12GTA
18R
3FC5 A6
RES 6FC2
2FC2
1FC2
100p
3FC6 B6
12V
3FC7 C6
1E05
6FC1 B5
6FC2 B5
1
6FC3 C5
2 3FC7
3 B-VGA 6FC4 C5
CDS4C12GTA
4 FFC3 18R 6FC5 D5
5 6FC6 E5
RES 6FC3
2FC3
1FC3
100p
12V
6 6FC7 E5
VGA 7
6FC8 F5
8
CONNECTOR
C 9
10
FFC4 C 9FC1 D6
9FC2 E6
11 FFC5 9FC3 E6
9FC5 H-SYNC-VGA
12 9FC4 E6
13
9FC5 C6
RES 6FC4
CDS4C12GTA
14
2FC4
1FC4
3FC3
9FC6 D6
12V
47p
4K7
15 16
FFC1 A4
17
FFC6 FFC2 B4
1216-00D-15S-1EF FFC3 C4
FFC4 C3
FFC7
9FC6 V-SYNC-VGA FFC5 C4
FFC6 D2
CDS4C12GTA
D D
RES 6FC5
FFC7 D4
2FC5
1FC5
3FC4
12V
47p
4K7
FFC8 D4
FFC9 E4
9FC1 VGA-SDA-EDID-HDMI
RES
3FC1 FFC8
9FC2 VGA-SDA-EDID
RES
CDS4C12GTA
10K
6FC6
2FC6
12V
47p
E RES
3FC2 FFC9
9FC3 VGA-SCL-EDID-HDMI
E
9FC4 VGA-SCL-EDID
CDS4C12GTA
10K RES
2FC7
6FC7
12V
47p
+5V-VGA
CDS4C12GTA
F
2FC8
1FC6
6FC8
F
12V
47p
1 2 3 4 5 6 7 8 9
4 2010-02-16
18770_838_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 133
3FD1
3FD2 RES
1K0
RES 3FDG-2 D4
2FD1
9FD1
9FD2
100n
1K0
6FD1 B3
6FD2 D4
LTST-C190KGKT
6FD3 D5
7FD1 B3
8
RES 7FD1
LM75BDP 9FD1 A4
6FD1
9FD2 A4
+VS
B 3FD3 IFD2
3
OS A0
7 IFD1
B 9FD5 C5
FFDA D5
SDA-SSB 1 6 IFD3
SDA A1 FFDB D5
3FD4 100R IFD4 FFDC D6
SCL-SSB 2 5 IFD5
SCL A2 IFD1 B4
GND
100R
3FD6 RES
3FD7 RES
IFD2 B3
9FD5
1K0
1K0
IFD3 B4
IFD4 B3
4
IFD5 B4
C C
1329
1
2
3
5 4
502382-0370
D FFDA 1328
D
AMP1 2
AMP2 3
1
CDS4C12GTA
CDS4C12GTA
FFDB
8
FFDC
3FDG-1
3FDG-2
2FDC
2FDD
1FD2
6FD2
1FD3
6FD3
1K0
1K0
12V
12V
1n0
1n0
MSJ-035-29D PPO (PHT)
1
E E
1 2 3 4 5 6 7 8 9
4 2010-02-16
18770_839_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 134
Tuner Brazil
Tuner Brazil
B01K B01K
1 2 3 4 5 6 7 8 9 10 11 12 13
1FE0 C2
2FE0 A3
2FE3 A6
2FE4 A6
2FE5 A6
2FE6 B3
2FE8 C3
2FF0 A6
2FF1 A7
A A 2FF2 B6
5FE0 IF63 IF64
+2V5-BRA +1V2-BRA-VDDC 2FF3 B6
30R 2FF4 B6
2FF5 B6
2FE0
2FE3
2FE4
2FE5
2FF0
2FF1
100n
100n
100n
100n
1u0
1u0
+3V3-BRA-FLT
2FF6 B7
2FF7 C6
AGND 2FF8 C6
5FE3 IF65 IF66 +3V3-BRA-FLT
5FE4 2FF9 C7
+3V3-BRA
30R 30R
2FG0 C6
2FG1 C7
B B
2FE6
2FF2
2FF3
2FF4
2FF5
2FF6
100n
100n
100n
100n
1u0
1u0
2FG2 C1
2FG3 C2
2FG4 D3
AGND
5FE5 IF67 IF68
2FG6 D3
+1V2-BRA-DR1 2FG7 E3
5FE7 IF48
30R
+3V3-BRA
2FG8 E3
+3V3
2FE8
2FF7
2FF8
2FF9
100n
100n
2FG9 E3
1u0
1u0
30R
2FH2 D11
2FH3 D12
2FH4 D12
C IF69 5FE8
+2V5-BRA C 2FH5 D6
30R 7FE3
1FE0 LD3985M25 2FH6 E3
2FG0
2FG1
100n
1 3
1u0
5FE9
1 5
FF03 2FH7 E3
+5V IN OUT +2V5-BRA
25M4
30R
2FH8 E7
4 2
2FG2
2FG3
3 4 3FE5 E7
18p
18p
INH BP
COM 3FE6 F3
7FE0 3FE7 F3
32
22
20
16
36
56
63
13
35
49
64
34
DR1VDD 48
43
2FH2
2FH3
2FH4
TC90517FG
1u0
10n
1u0
3FE8 F3
2
AGND AGND AGND
AD_DVDD
AD_AVDD
PLLVDD
DR2VDD
19
VDDC Φ VDDS
21
2FH5
3FE9 F3
I FIL
AGND 3FG2-1 F6
D 18
O
X
PBVAL
58
1n5
3FG6-4 4 5 33R TS-FE-VALID D 3FG2-2 F7
DFE6
3
0 RERR
53 4 9F27-4 5 TS-DVBS-VALID 3FG4-1 F7
2 XSEL
1
54
DFE7 3FG4-2 F6
RLOCK
IF+ 2FG4 10n IF17 30
P DFE8
3FG6-2 E7
IF- 2FG6 10n IF18 29 ADI_AI 55 2 9F27-2 7 TS-DVBS-SOP 3FG6-3 E7
N RSEORF
2FG7 100n BFE1 28 59 3FG6-3 3 6 33R TS-FE-SOP
3FG6-4 D7
BFE2 P SBYTE
2FG8 100n 27
N
ADQ_AI
DFE9 3FG7 E7
52 9F28 TS-DVBS-CLOCK
AGND
2FG9 100n BFE3 24
SLOCK 5FG0 5FE0 A3
P
2FH6 100n BFE4 25
N
AD_VREF
SRCK
61 3FG7 33R TS-FE-CLOCK 30R
5FE3 B3
5FE4 B7
E AGND
2FH7 100n BFE5 26
AD_VREF SRDT
60 3FG6-2 2 7 33R TS-FE-DATA 5FG2 E 5FE5 B3
DFF1
AGND
39
DTCLK STSFLG1
38 1 9F27-1 8 TS-DVBS-DATA 30R 5FE7 C11
IF27 3FE5 IF28 AGND 5FE8 C7
40 9 IF-AGC
+3V3-BRA-FLT DTMB AGCCNTI
18K
5FE9 C11
2FH8
8 10 5FG0 E11
10n
S_INFO AGCCNTR
DFF2 5FG2 E11
3FE6 10K 1 51
0 STSFLG0
41
1
TSMD 7FE0 D4
42
3FE7 10K IF29 7
SYRSTN 7FE3 C11
AGCI
6 3FG2-1 RESET-SYSTEMn 9F27-1 E8
0 3FG2-2
11 SLADRS 5 10K 9F27-2 D8
F CKI 1
3FG4-2
10K F 9F27-4 D8
AD_DVSS
AD_AVSS
31
17
4
15
33
37
44
47
50
57
62
BFE3 E4
BFE4 E4
BFE5 E4
AGND AGND DFE6 D6
DFE7 D6
DFE8 D6
G G DFE9 E6
DFF1 E6
DFF2 F6
FF03 C12
IF17 D4
IF18 D4
IF27 E7
IF28 E7
IF29 F4
IF48 C12
H H IF49 F4
IF63 A4
IF64 A5
IF65 B4
IF66 B5
1 2 3 4 5 6 7 8 9 10 11 12 13
4 2010-02-16
18770_840_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 135
3S01-1 E2
3S01-2 E3
3S01-3 E2
A 7S00-5 A 3S01-4 E3
PNX85500
FLASH
00
01
D25
D26
XIO-D00
XIO-D01
3S02-1 E3
C24 XIO-D02
NAND-ALE D22
ALE
02
03
04
D23
C23
XIO-D03
XIO-D04
3S02-2 E2
C21 NAND B23
NAND-CLE
XIO-A00 J25
CLE 05
06
A22
E22
XIO-D05
XIO-D06
XIO-D07
3S02-3 E2
00 07
XIO-A01
XIO-A02
J26
H21
H22
01
02
XIO_D
08
09
F24
F25
F26
XIO-D08
XIO-D09 3S02-4 E3
B XIO-A03 03 10 XIO-D10
B
XIO-A04
XIO-A05
XIO-A06
H23
H24
H25
04
05
11
12
E23
E24
E25
XIO-D11
CA-DATAENn K26
DATA_DIR
DATA_EN
VS
1
2
K24 9S00 *
RES
CA-MOCLK
IS26 B6
K21 CA-CD1n
3S03 1
N23 CD K22
F CA-MICLK
10R
I
MCLK
2 CA-CD2n
F
CA-MOCLK L25
O CA
3S04-2 +3V3
CA-MISTRT 7 2 N24
MISTRT
3S04-1 33R
CA-MIVAL 8 1 N25 TS-FE-DATA 3S1R
MIVAL
33R 560R
CA-MOSTRT L22 TS-FE-CLOCK 3S1S
MOSTRT
560R
CA-MOVAL L23 TS-FE-VALID 3S1T 1X06
MOVAL EMC HOLE
560R
J21 TS-FE-SOP 3S1U
OOB_EN
560R
L24
G CA-RDY RDY
TS-FE-DATA
G
CA-RST L26 T21 TS-FE-DATA 3S23
RST DATA
T23 TS-FE-ERR RES 470R
ERR
J23 T22 TS-FE-CLOCK TS-FE-CLOCK 3S24
VCCEN TNR_SER1 MICLK
R23 TS-FE-VALID RES 470R
MIVAL
J24 R22 TS-FE-SOP TS-FE-VALID 3S28
VPPEN SOP
470R
TS-FE-SOP 3S29
470R
H H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_841_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 136
PNX SDRAM
PNX SDRAM
B02B B02B
1 2 3 4 5 6 7 8 9 10 11
2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
A A 3S06 D3
3S07 D3
3S0V F8
3S20 D2
3S22 D2
3S30 C7
3S33 C8
3S6Q E10
B B 7S00-8 B6
7S00-8
PNX85500
DDR2-BA0 H1
0
MEMORY
0
J1 DDR2-A0
FS01 D3
H2 J3
DDR2-BA1
DDR2-BA2 G1
1 BA 1
K1
DDR2-A1
DDR2-A2
FS02 D2
2 2
DDR2-DQM0 D1 M0
3
G4
L3
DDR2-A3
DDR2-A4
IS42 E8
0 4
DDR2-DQM1 D5 G3 DDR2-A5
1 5
DDR2-DQM2 R3 DM L2 DDR2-A6
2 6
DDR2-DQM3 T5 H5 DDR2-A7
3 7
L1 DDR2-A8
A 8
DDR2-D0 F3 J5 DDR2-A9
0 9
C2 J2
C +1V8
DDR2-D1
DDR2-D3 F2
1
2
10
11
M3
DDR2-A10
DDR2-A11 C
DDR2-D2 C3 J4 DDR2-A12
3 12
DDR2-D6 B4 M2 DDR2-A13
4 13
DDR2-D5 F1 K5 DDR2-A14
5 14
DDR2-D4 C1
6
DDR2-D7 E1 N5 3S30 DDR2-CLK_N
7 N
100u 2.0V
180R 1%
DDR2-D8 8 P
3S20
3S06
2S12
DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%
DDR2-D14 14 P
3S22
F5
D DDR2-D15
U3
15
DQ R1 DDR2-DQS2_N D
180R 1%
DDR2-D16 16 N
3S07
IS42
2S20
2S17
1%
2S24
2S25
100p
100n
100n
100p
3S0V
261R
F F
1 2 3 4 5 6 7 8 9 10 11
5 2009-10-22
PNX85500
8204 000 8950
18770_842_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 137
2S2E F5
3S0W E5
7S00-6 D6
A A IS01 E6
IS10 E7
B B
C C
D D
7S00-6
PNX85500
HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A
E HDMIA-RXC+ W25
P
E
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W W24
RREF
12K
2S2E
10u
RES
F F
G G
H H
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_843_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 138
PNX Audio
PNX Audio
B02D B02D
1 2 3 4 5 6 7 8 9 10 11 12 13 14
2S3J
220n
7S08
100R LD3985M25
1
3S12-1
1 3S16-1 8
2S2W 3S53-3 FS08 FS03 2S2V B3 3S37 F11
AUDIO-IN1-L 8 10K 5 1
22K 1u0 100R IS12
OUT IN
IS13 3S14
4 2S2W B3 3S38 B13
RES
4 3 ADAC(1) 12 7S05-4
2
B 3S53-4 BP INH +2V5 LM324 14 3S38
B 2S2Y C3 3S39 C13
2S2R
2S2S
3S16-2 7
10u
2 3S12-2 2S2V 22K +AUDIO-L
AUDIO-IN1-R 7 10K COM IS02 13
10u
100R 100R
2S2Z B3 3S3F E4
2S2T
100n
22K 1u0 11
2S34
100n
2S30 C3 3S3G-1 C7
2
3S16-3 3 6
3S12-3 6 2S2Z
3 10K
AUDIO-IN2-L
2S31 C3 3S3G-2 D8
22K 1u0 10K
2 3S36-2 7
IS0V 4
3S16-4 5 8 3S36-1 1
2S32 D3 3S3G-3 C8
2S2Y 10K
4 3S12-4
100u 4V
2S33 C3 3S3G-4 D7
3S51
2S42
2S41
10K
4R7
5
1u0
AUDIO-IN2-R 2S2G
22K 1u0
4 3S17-4 5
47p 2S34 B9 3S3H D7
3S13-4 IS0R 2S31 7S00-2
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD 2S36 C6 3S3U D8
C 4
22K
5
3
1u0
AE10 AUDIO AC7
2S36
1
3S3G-1
8 ADAC(1)
C 2S38 E9 3S51 C6
6 L P
3S13-3 3S17-3 AF10 AIN1 ADACL AB7 IS1N
AUDIO-IN3-R 3 6 10K
2S30 R N 1u0 33R
3
3S3G-3
6 ADAC(2) ADAC(2)
IS03
10
4
7S05-3
LM324 8 3S39
2S39 E9 3S53-1 A6
AD10 AC6 -AUDIO-R
22K
3S17-1
1u0
AC10
L
R
AIN2 ADACR
P
N
AB6
33R
9
100R
2S3A E8 3S53-2 B6
1 8
AUDIO-IN4-L
3S13-1
10K
2S33
AE9 AD7 11 2S3B E8 3S53-3 B6
L 1 3S3G-2
1 22K 8 AF9 AIN3 AE7 2 7
1u0 R 2
AF7
ADAC(3)
2S3C E8 3S53-4 B6
2 3 33R
4 3S3G-4 5
AUDIO-IN4-R 2 3S13-2
3S17-2 7
10K
2S32
AD9
AC9
L
AIN4
ADAC
4
AD6
AE6 IS1S 33R
ADAC(4)
2S3D E8 3S6L F12
7 R 5
22K 1u0 AF8
6
AF6
2S3E E3 3S6M H8
L
D 3S10
AE8
R
AIN5
OSCLK
AD4
AD1
3 3S36-3 6
10K
5 3S36-4 4
D 2S3F E2 7S00-2 C5
I2S_OUT SCK 3S3H 10K
2S2L 100R AB9
POS WS
AD2 ADAC(5) 2S2H 2S3G E3 7S05-1 E12
IS1B AB8 VR_AADC 33R
1u0 NEG
IS19 1
AE1
3S3U 47p
2S3H E3 7S05-2 G12
AD8 AF2 ADAC(6)
IS1A
VREF_AADC 2
I2S_OUT_SD 3
AE3
33R
+24V-AUDIO-VDD 2S3J B11 7S05-3 C12
AC8 AF3
3S3F
VCOM_AADC 4 2S3K G6 7S05-4 B12
AF5
SPDIF_OUT 2S3L H8 7S08 B8
2S3D
2S3C
2S3B
2S3A
2S39
2S38
1n0
1n0
1n0
1n0
1n0
1n0
56R DBS8 AE5
SPDIF_IN1 IS07 4 2S3M H9 7S09-1 G6
2S3G
2S3H
2S3E
2S3F
100n
100n
3 7S05-1
10u
10u
ADAC(5)
LM324 1
9S06
AUDIO-OUT-L
2S3Q G5 7S09-2 H6
E 2 E
11 2S41 C6 7S09-3 H7
2S42 C6 7S09-4 I7
3S0Z A11 9S06 E4
3S10 D4 DBS8 E4
3S37 3S6L
3S11 F5 FS03 B12
10K 22K
2S2K
3S12-1 B2 FS08 B7
+3V3 47p
3S12-2 B2 IS02 B11
F +3V3-ARC F 3S12-3 B2 IS03 C11
+24V-AUDIO-VDD
3S12-4 C2 IS06 G11
3S11 IS1L
3S13-1 C2 IS07 E11
1R0
3S13-2 D2 IS0R C2
4
3S13-3 C2 IS0V C2
2S3Q
100n
ADAC(6) 5 7S05-2
LM324 7
IS06 AUDIO-OUT-R
6 3S13-4 C2 IS12 B8
7S09-1
11 3S14 B9 IS13 B9
14
74LVC00APW
G SPDIF-OUT-PNX SPDIF-OUT-PNX
IS1D
1 & 2S3K G 3S16-1 B3 IS19 D3
3 IS1G 1 3S18-1 8 SPDIF-OUT
2
100n 220R
3S16-2 B3 IS1A D3
3S34 3S32
2 3S18-2 7
3 3S18-3 6
+3V3 3S16-3 B3 IS1B D4
220R
220R
7
+3V3-ARC
3S17-2 D3
10K
7S09-2
14
74LVC00APW 7S09-3
14
4 &
6
74LVC00APW
9
3S17-3 C3 IS1K H9
& 2S3L 180R IS1K 2S3M IS44
IS1E
SEL-HDMI-ARC 5 8 eHDMI+ 3S17-4 C3 IS1L F5
H +3V3
10
100n 3S6M 100n H 3S18-1 G7 IS1N C7
7
3S18-2 G8 IS1S D7
3S25
68R
3S18-3 G8 IS44 H9
+3V3-ARC
7S09-4
14
74LVC00APW
12 &
11
I +3V3
13 I
7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_844_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 139
PNX Mips
PNX Mips
B02E B02E
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1F10 A12
2S89 D8
3S00 B5
3S21 B1
3S26 C5
3S27 C6
+3V3
A 7S00-3
PNX85500 A 3S40 A1
CONTROL 3S45 A1
C25 1 3S56 2 SDA-UP-MIPS SDA-UP-MIPS
3S69 1F10
3S45 IS05
BOOTMODE 1
SDA
C26 100R 1 2 3S57 SCL-UP-MIPS SCL-UP-MIPS 3S6A 4K7 4K7 EJTAG-TRSTn-PNX85500 FS44 3S55 C3
+3V3 SCL 1
10K
Y21 B26 1 3S58 2
100R
3S6B 4K7
EJTAG-TMS-PNX85500 FS49
FS50
2 3S56 A5
BOOTMODE SDA-SET SDA-SET EJTAG-TDO-PNX85500
3S40
GPIO1 GPIO1 Y22
GPIO_0
2
SDA
A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51
3 FOR FACTORY 3S57 A6
+3V3 GPIO_1 SCL 4
10K RXD1-MIPS Y23
GPIO_2
100R EJTAG-TDI-PNX85500 FS52
5 USE ONLY 3S58 A5
DS52 TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2
3S82 RES GPIO_3 SDA 3S5Z 6
+3V3 BOOST-PWM RXD2-MIPS W21
W22
GPIO_4
3
SCL
A24 100R 1
100R
2 SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53
7 3S5W B6
10K TXD2-MIPS GPIO_5 8
+3V3
3S80 FS10 TXD2-MIPS PNX-SPI-CS-AMBIn W23
GPIO_6 SDA
B24 1 3S60 2 SDA-TUNER SDA-TUNER 3S6F 4K7 10 9 3S5Y B5
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 4K7
+3V3 GPIO_7 SCL 3S5Z B6
B +3V3
3S21
10K
PNX-SPI-CS-AMBIn
BOOST-PWM
SELECT-SAW
V23
U23
GPIO_10
GPIO_11 TRSTN
AA25
100R
EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K B 3S60 B5
IS04 AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3
10K TMS +3V3-STANDBY FS57
3S62 PNX-SPI-CS-BLn
USB-DM R26
DN TCK
AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3 BM08B-SRSS-TBT 3S61 B6
USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
+3V3
IS4Z R24 DP USB TDO
AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4 3S62 B1
10K RREF TDI
AE4 3S00
10K 3S64 C1
RESET_SYS RESET-SYSTEMn
3S55 3S65 E11
5K6
3S64 FS64 33R
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM 3S66 E11
10K
CLK_54_OUT
AC5 3S67 E11
3S26
3S27
3S6J
10K
10K
10K
3S68 E11
C +3V3
3S83
RXD1-MIPS
C 3S69 A9
10K 3S6A A8
+3V3 +3V3
+3V3
3S84
TXD1-MIPS
3S72 IS40 3S6B A9
PXCLK54
10K 3S6C B8
47R
3S6D B9
3S6E B8
3S6F B9
RES
3S6G B8
D D 3S6H-1 B8
+3V3 3S6H-2 B9
3S6H-3 B9
2S89
3S6H-4 B9
100n +3V3 3S6J C5
3
7S01
PCA9540B
3S6K B9
3S65
VDD SC0 5 SCL-DISP SCL-DISP 2 1 3S72 C6
3S66 4K7 3S80 B1
SC1 8 SCL-BL SCL-BL 2 1
3S67 4K7 3S81 B1
E SCL-SET 1 SCL
INP
I 2 C
-BUS
SD0 4 SDA-DISP SDA-DISP 2 1
3S68 4K7
E 3S82 B1
SDA-SET 2 SDA FIL SD1 7 SDA-BL SDA-BL 2 1
CTRL
4K7 3S83 C1
VSS 3S84 C1
7S00-3 A4
6
FS31
7S00-4 G12
7S01 E8
9S10 F8
9S10 SCL-BL
9S11 F8
IS08
F SCL-SET 9S11 FS2W SCL-DISP
F 9S12 F8
9S12 FS2Y SDA-DISP 9S13 F8
SDA-SET
IS09
9S13 SDA-BL
DS52 B2
FS10 B2
FS11 B2
7S00-4
FS2W F9
PNX85500 FS2Y F9
ETH-RXCLK AA3
RXCLK ETHERNET FS31 F8
FS44 A12
G ETH-RXD(0)
ETH-RXD(1)
Y5
Y6
0
1 TXCLK
AA2 ETH-TXCLK
G FS49 A12
ETH-RXD(2) IS50 AB4 RXD ETH
2
ETH-RXD(3) AC1
3 0
AA1 ETH-TXD(0) FS50 A12
AA4 ETH-TXD(1)
ETH-RXDV AC2 TXD
1
AB1 ETH-TXD(2)
FS51 B12
RXDV 2
ETH-RXER Y4
RXER 3
AB2 ETH-TXD(3) FS52 B12
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2
CC_DAT3 TXER
AB3 ETH-TXER FS53 B12
SDIO-CLK W1 AC3 ETH-COL
SDIO-CMD W6
CLK COL
Y2 ETH-CRS
FS57 B12
CMD CRS
SDIO-DAT0 W5
0 MDC
Y3 ETH-MDC FS64 C2
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3
2
IS04 B2
H SDIO-CDn
SDIO-WP
U6
V6
SDCD
SDWP
H IS05 A2
IS08 F8
IS09 F8
IS40 C6
IS4Z B4
IS50 G12
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_845_100330.eps
100330
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 140
7S00-7 C8
A A
B B
C 7S00-7
PNX85500 C
PX1A- A7 LVDS D7 PX3A-
N N
PX1A+ B7 A A E7 PX3A+
P P
PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P
F F
G G
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-29
PNX85500
8204 000 8950
18770_846_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 141
+1V1
POL
2S4G B9
2S4K G10
IS3B 3S1B C2
3S1C C1
5S04
RES
30R
3S1D C2
2S10
100n
1u0
2S13 3S1E C1
2S37 3S1F C2
1u0
3S1G D2
9S24
RES
3S1H D1
B 2S11 B 3S1J D2
100n IS20 3S1K D1
DS50 2S4G
3S1L E2
3
1 10p 3S1P D11
AC17
AA17
AF26
1S02
54M
7S00-9
PNX85500 2S4F
3S2A D2
3S2F D7
VDDA_1V1_DCS
VDDA_ADC2V5
VDD_XTAL
AE17
1
+3V3-STANDBY 2S4D +3V3-STANDBY
3S1B 1n0 RC RC AD19
XTAL_IN 10p 3S2G D7
0
3S1C RES 10K TACHO TACHO AE19
1 XTAL_OUT
AF17 3S2H D7
10K 3S1D CEC-HDMI CEC-HDMI AF19
3S1E RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20
2 P1
AA26 RESET-STBYn
3S2K D7
3 RESET_IN
C +3V3-STANDBY
10K 3S1F
10K
SDM SDM AB20
7
STANDBY EA
AB24 EA EA
IS3F 3S44 C 3S2L D10
3S2M E10
3S3L RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3E 10K 3S43
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20
1 ALE
AB23 ALE 3S2S E10
10K 3S3N RES AE20
3S3P 10K
LAMP-ON LAMP-ON
AF20
2
AC26
IS3D
10K 3S42
10K 3S2V F11
STANDBY STANDBY 3 PSEN PSEN PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2 3S3L C2
RES 3S3S 4 3S2F 100R RES 3S6V
10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 SDA-UP-MIPS SDA-UP-MIPS 3S3M C1
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
3S3T 10K RES ENABLE-3V3n ENABLE-3V3n AD21
6 SCL
RES
3S3N C2
7 LED1 RES 3S1P 4K7
+3V3-STANDBY 10K AD26 3S2H 100R LED1 3S3P C1
3S1G 0 3S2K 100R
RXD-UP RXD-UP AE21 PWM AC25 LED2 LED2 10K 3S41
3S1H 10K TXD-UP TXD-UP AF21
0 1 3S3Q C2
1 10K
10K
3S2A RES
DETECT2 AA22
2 SDO
AE23 PNX-SPI-SDO 3S3R D2
D 10K
DETECT2 AB22
AC22
3
4
P3
SPI
SDI
CLK
AF25
AF24
PNX-SPI-SDI
PNX-SPI-CLK
D 3S3S D1
AD22
5 CSB
AF23 PNX-SPI-CSBn 3S3T D1
3S1K RES
RESET-SYSTEMn AD23 AB17 IS2V RES 3S2L 3S3W E9
RESET-SYSTEMn 0 0 CTRL-DISP CTRL-DISP
10K AV2-BLK AE26
1 1
AA18 IS2Z RESET-DVBS RESET-DVBS 10K RES 3S46 3S3Y D9
AE25 P5 AD18 RES 3S3Y 10K
3S1J KEYBOARD
AV1-BLK
AE24
2 2
AE18
RESET-USBn RESET-USBn
10K 3S47 +3V3-STANDBY 3S41 D12
KEYBOARD 3 3 RESET-ETHERNETn RESET-ETHERNETn RES
100K LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 3S2S 10K 3S42 C11
2S4E 4 3S2M
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES 3S43 C11
4 5
VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K RES
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49 3S44 C11
7
AD17
3S1L
SPI-PROG SPI-PROG 4K7 3S46 D10
PNX-SPI-WPn
10K 3S47 E10
E E 3S49 E10
3S6V C11
3S6W D12
5S04 B6
7S00-9 B6
7S20 G10
9S0D G9
9S0E G9
9S24 B6
F F DS50 B8
+3V3-STANDBY +3V3-STANDBY FS0Z G11
FS45 G9
IS20 B6
1 3S2V 2
IS2U G10
10K
9S0E
FS0Z IS2V D7
7S20 RESET-STBYn
NCP303LSN28 IS2Z D7
FS45 2 IS3B A6
INP
1 IS2U 1
OUTP IS3D C10
5
CD
NC GND IS3E C10
G G IS3F C10
3
9S0D
2S4K
100n
RES
H H
1 2 3 4 5 6 7 8 9 10 11 12 13
5 2009-10-22
PNX85500
8204 000 8950
18770_847_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 142
PNX Power
PNX Power
B02H B02H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
IS3Q 5S80
2S21 F6
+1V1
30R 2S23 B6
RES 10u
2S26 A6
2S6A
2S5A
100n
2S27 B3
1
2S28 B3
5S81 2S29 C6
2S43 B2
A +2V5
A
2
30R 2S45 F11
RES 10u
2S6B
2S5B
100n
2S46 F11
2S4M B12
2S4N C11
1
+1V8
IS3S 5S82 2S4P C11
2S26
2S60
2S61
2S62
2S63
2S64
2S65
2S66
2S67
100n
100n
100n
100n
100n
100n
100n
100n
47u
+3V3 2S4Q B3
30R
RES 10u
2S4R B4
2S5C
2S5D
100n
2S4S F5
2S4T H11
SENSE+1V1 c001
2S4U D11
5S93
7S00-10 2S4V D11
G6
G7
R6
R7
U7
C6
D6
A5
A6
B5
B6
E6
F6
F7
L6
L7
+2V5
B PNX85500 30R
B 2S4W D11
2S6E 2
220u 6.3V
VDD_1V8 2S4Y D11
2S4M
2S6D
100n
100n
+1V1 AF1 V20
7
AE2 HDMI_VDDA_1V1 V21 2S4Z E11
5
AD3
1
2S50 E11
2S5G-1
2S5G-2
2S5G-3
2S5G-4
2S5H-1
2S5H-2
2S5H-3
2S5H-4
2S4Q
2S4R
2S43
2S28
2S27
2S23
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
AC4 VDD U20
22u
22u
47u
1
AB5 HDMI_VDDA_2V5 U21 2S51 E9
H20
2S52 E9
4
F11 U22 +2V5-LVDS
2
HDMI_VDDA_3V3_TERM 2S53 H11
G11
F13 N6 2S55 G11
2S4N
2S4P
100n
G13 VDD_2V5 N7
10u
F15 2S56 G11
2S5J-3 6
2S5J-1 8
8
5
G15 C7 2S57 G11
2S5K-1
2S5K-2
2S5K-3
2S5K-4
2S5J-2
2S5J-4
C C
100n
100n
100n
100n
100n
100n
100n
100n
100u 2.0V
F17 C9
G17 C11
2S58 H11
2S29 5S85 2S59 I11
F19 VDD_2V5_LVDS C14
4
+3V3
2
1 2S6G 2
G19 C16 2S5A A11
1
30R
2S6N
2S6C
2S6P
2S6F
100n
100n
100n
100n
J9 C18
10u
J11 2S5B A11
AA16
AA8
2S5C B11
Y11
Y14
J13 W20
Y16
Y9
7S00-12
1
PNX85500 J15 P20
J17 M20
2S5D B11
VSSA
A1 M7 L9 VDD_3V3 K20 2S5G-1 B4
A10 N2 L11 V7 +3V3-STANDBY
2S5G-2 B4
2S4U
2S4V
100n
A12 N20 L13 Y8
10u
A15 P10 L15 2S5G-3 B4
VDD_1V1
A17 P12 L17 Y19 2S5G-4 B5
D A19
A26 VSS
P14
P16
N9
N11
VDD_3V3_SBY Y18
IS3K 5S83
D 2S5H-1 B5
A3 P18 N13
VDDA_1V1_LVDS_PLL
B13 2S5H-2 B5
A8 P4 N15 +1V1
IS3L 30R 2S5H-3 B5
2S4W
2S4Y
100n
B1 P6 N17 AA15
RES 1u0
B20 P7 R9 Y15 2S5H-4 B5
VDDA_1V2
C20 T10 R11 AA13 2S5J-1 C5
C4 T12 R13
D2 VSS T14 R15 Y12
5S95 +2V5 2S5J-2 C5
VSS VDDA_2V5 5S84
D20 T16 R17
30R
2S5J-3 C5
6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R 2S5J-4 C5
2S4Z
2S51
2S52
2S50
100n
100n
E20 T2 U11
10u
E4 T6 U13 AA7 c000 SENSE+1V2 2S5K-1 C4
10u
VDDA_2V5_ADAC
F10 T7 U15 2S5K-2 C4
E F12
F14
U4
V10
U17
J6
VDDA_2V5_DCS
Y17
E 2S5K-3 C4
F16 V12 AA6
VDDA_2V5_LVDS_BG
D13 2S5K-4 C5
F18 V14 Y7
F20 V16 W7 T20 POL 2S5M G11
VSSA_1V1_LVDS_PLL
VSSA_2V5_LVDS_BG
VDDA_2V5_USB 2S5P F5
F8 V18 F9
G10 V2 G9 Y13 +2V5-AUDIO 2S60 A6
VDDA_2V5_VADC
G12 Y20
V24 HDMI_AGND
5S94 2S61 A6
2S46
100n
J7 Y10
VSSA_USB
VSS +1V1 VDD_1V1_DDR VDDA_2V5_VDAC
30R 2S62 A7
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6
R21
VDDA_3V3_USB 2S63 A7
2S4S
2S5P
2S21
100n
10u
1u0
RES
2S64 A7
U24
A13
C13
R20
2S65 A7
1
F +2V5-AUDIO F 2S66 A7
2S45
100n
2S67 A8
2S6A A11
2S6B A11
5S87 2S6C C11
+2V5 2S6D B11
30R
2S6E B11
2S55
2S56
100n
1u0
2S6F C11
2S6G C11
2S6H H11
G 5S88 G 2S6K H11
+2V5-LVDS
30R 2S6L I11
2S5M
2S57
100n
10u
2S6M I11
2S6N C11
2S6P C12
5S89
2SHW I11
+2V5
2
30R 5S80 A12
2S6H
2S6K
100n
100n
2S58
10u
5S81 A12
5S82 A12
1
5S83 D12
H 5S90 H 5S84 E12
+2V5
30R 5S85 C12
5S87 F12
2S4T
2S53
100n
10u
5S88 G12
5S89 H12
5S90 H12
5S92 I12
5S93 B12
2SHW
100n
5S94 F5
5S95 E10
I I 7S00-10 B6
IS58 5S92 7S00-12 C1
+3V3 IS3K D10
2
30R
2S6M
2S6L
2S59
100n
100n
IS3L D10
1u0
IS3Q A10
1
IS3S A10
IS58 I10
c000 E13
c001 B5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_848_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 143
3S59
47R
Connectivity 22n
2S22 A11
3S5B
47R
A A 2S40 B11
AV1-R 2S7J 2S75 F11
22n 2S22 C-SVHS 2S76 F11
3S4J
56R
22n 2S77 F12
3S05
56R
2S78 G12
2S7E G6
EU: SCART1 CVBS-MON-OUT1 2S7H B6
AV1-B 2S7K
AP: - 2S7J A6
3S5E
560R
22n
2S7K B6
3S4L
56R
B B 2S7L C6
IS4V
2S7M C6
2S7N D6
560R
2S40
3S08
47p
2S7H
AV1-G 2S7P D6
22n 2S7Q E6
3S4K
56R
IS4W
2S7R F6
2S7U F6
3S09
8K2
2S84 G6
C C
YPBPR1-SYNCIN1
2S7M
2S85 H6
10n
2S7L
2S86 H6
AV3-Y
2S87 A6
22n
2S8A A11
3S4P
56R
2S8G E6
2S7N
AV3-PR 3S05 A11
EU: YPBPR1 22n 3S08 B11
3S4R
56R
D AP: YPBPR1
7S00-1
PNX85500 D 3S09 C11
2S7P ANALOG_VIDEO 3S4G G6
AV3-PB
22n
AB15
CVBS_Y1 ATV_CVBS_Y3 AC12 3S4J A6
2S19
2S18
2S16
2S15
2S14
3S4T
AC13 IS5C
56R
AF13
22n
22n
22n
22n
22n
AD13
R
B AV1
C3
3S4K C6
AE13 AD11
G CVBS_Y7
C7
AC11 3S4L B6
2S8G AF15
AV2-CVBS
AE15
SYNCIN1
AF11
BS13 3S4P D6
22n Y_G1 CVBS1_OUT
AC15
PR_R_C1 CVBS2_OUT AE11 3S4R D6
3S5L
AD15
47R
PB_B1
RESREF AB10 3S4T D6
AB14 AA11 IS5E 3S5S
E 2S7Q
AF14
CVBS_Y2
SYNCIN2
CURREF
10K E 3S4U F6
YPBPR2-SYNCIN2 AE14 AC16 IS5D
10n
AC14
Y_G2
PR_R_C2
1
2 AB16 IS5F 3S4W F6
AD14 IS5G
PB_B2
REF 4
3 AB13
AB12 IS5H
3S50 H6
AF16
AD16
R 5 AA12
AA10
IS5J
3S75 3S52 H6
G VGA 6 PNX-IF-AGC
AE16
B 47K 3S54 I6
2S75
2S7R AB18 BS15
10n
AV4-Y AD12
AC18
HSYNC_IN
IN
IF_AGC
RF_AGC AB11 BS17 3S59 A6
EU: 22n AF4 VSYNC
SCART2 OUT 3S5B A11
3S4U
AD24 BS09
56R
2S76
AGND
10n
3S5S E9
AA14
AV4-PR 2S7U
22n 3S5T-1 I5
3S4W
56R
2S77
PNX-IF-P 3S5T-2 I11
10n 3S5T-3 I5
3S5T-4 I11
2S7E
AV4-PB 3S5V-1 I5
22n 2S78
3S5V-2 I12
3S4G
56R
G 10n
PNX-IF-N
G 3S5V-3 I5
3S5V-4 I12
2S84
R-VGA 3S75 E12
22n
3S76 F12
3S50
56R
7S00-1 D8
2S85
9S14 I3
G-VGA
9S15 I3
22n
9S17 A13
3S52
56R
H H
BS09 F9
2S86
BS10 F10
B-VGA
22n
BS13 E9
3S54
56R
4 3S5T-4 5
2 3S5T-2 7
4 3S5V-4 5
2 3S5V-2 7
AP: VGA
BS17 F10
100R
100R
100R
100R
H-SYNC-VGA 1 3S5T-1 8 IS11 F13
100R
IS4V B10
V-SYNC-VGA 3 3S5T-3 6
100R
IS4W C10
IS5C D9
I VGA-SCL-EDID 3 3S5V-3 6
I IS5D E9
100R
IS5E E9
VGA-SDA-EDID 1 3S5V-1 8
100R
IS5F E9
VGA-SCL-EDID-TCON 9S14
* IS5G E9
VGA-SDA-EDID-TCON 9S15
* *
= TCON ONLY
IS5H E9
IS5J E9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
5 2009-10-22
PNX85500
8204 000 8950
18770_849_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 144
D D
7S00-11
PNX85500
H H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_511_100118.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 145
PNX SDRAM
PNX SDRAM
B02B B02B
1 2 3 4 5 6 7 8 9 10 11
2S12 D4
2S17 E7
2S20 E7
2S24 E7
2S25 E7
A A 3S06 D3
3S07 D3
3S0V F8
3S20 D2
3S22 D2
B B 3S30 C7
7S00-8
DDR2-BA0
PNX85500
H1 MEMORY J1 DDR2-A0
3S33 C8
0 0
DDR2-BA1
DDR2-BA2
H2
G1
1 BA
2
1
2
J3
K1
G4
DDR2-A1
DDR2-A2 3S6P E10
3 DDR2-A3
DDR2-DQM0
DDR2-DQM1
D1
D5
0
1
M0 4
5
L3
G3
DDR2-A4
DDR2-A5
3S6Q E10
DDR2-DQM2 R3 DM L2 DDR2-A6
DDR2-DQM3 T5
2
3
6
7
H5
L1
DDR2-A7
DDR2-A8
7S00-8 B6
A 8
C FS01 D3
DDR2-D0 F3 J5 DDR2-A9
0 9
C +1V8
DDR2-D1
DDR2-D3
C2
F2
1
2
10
11
J2
M3
DDR2-A10
DDR2-A11
DDR2-D2
DDR2-D6
C3
B4
3
4
12
13
J4
M2
DDR2-A12
DDR2-A13
FS02 D2
DDR2-D5 F1 K5 DDR2-A14
DDR2-D4
DDR2-D7
C1
E1
5
6
7
14
N
N5 3S30 DDR2-CLK_N
IS42 E8
100u 2.0V
180R 1%
DDR2-D8 8 P 10R
3S20
3S06
2S12
DDR2-D9 B2 10R
9
DDR2-D10 E5 E2 DDR2-DQS0_N
10 N
DDR2-D11 C5 DQS0 E3 DDR2-DQS0_P
FS02 11 P
DDR2-D12 A4
DDR2-VREF-CTRL3 FS01 12
DDR2-D13 G5 D3 DDR2-DQS1_N
DDR2-VREF-CTRL2 13 N
B3 DQS1 D4 DDR2-DQS1_P
180R 1%
DDR2-D14 14 P
3S22
D DDR2-D15 F5
U3
15
DQ R1 D
180R 1%
DDR2-D16 16 N DDR2-DQS2_N
3S07
IS42
2S20
2S17
1%
2S24
2S25
100p
100n
100n
100p
3S0V
261R
F F
1 2 3 4 5 6 7 8 9 10 11
6 2009-12-07
PNX85500
8204 000 8950
18770_512_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 146
2S2E F5
3S0W E5
A A 7S00-6 D6
IS01 E6
IS10 E7
B B
C C
D D
7S00-6
PNX85500
HDMIA-RX1+ U25
P
HDMIA-RX1- U26 RX1_A Y26 DDCA-SCL
N SCL
DDC_A Y25 DDCA-SDA
SDA
HDMIA-RX0+ V25 IS10
P
HDMIA-RX0- V26 RX2_A T24
N HOT_PLUG_A
E HDMIA-RXC+ W25
P
E
HDMIA-RXC- W26 RXC_A
N
+3V3 IS01
3S0W W24
RREF
12K
2S2E
10u
RES
F F
G G
H H
I I
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_513_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 147
PNX Audio
PNX Audio
B02D B02D
2S2G C12 IS1G G7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S2H D12 IS1K H9
2S2J G12 IS1L F5
2S2K F12 IS1N C7
2S2L D4 IS1S D7
2S2R B7 IS44 H9
2S2S B9
2S2T B8
2S2V B3
A A 2S2W B3
2S2Y C3
2S2Z B3
3S0Z 2S30 C3
3S53-1 +2V5-AUDIO +24V-AUDIO-POWER 2S31 C3
4R7 +24V-AUDIO-VDD
100R
2S32 D3
+3V3
3S53-2
2S33 C3
2S3J
220n
7S08 2S34 B9
100R LD3985M25
1 3S16-1 8 2S36 C6
1 2S2W FS03
3S12-1 8 10K 3S53-3 FS08 5 1 2S38 E9
AUDIO-IN1-L OUT IN
22K 100R IS12 4 2S39 E9
1u0 IS13 3S14
RES
4 3 ADAC(1) 12 7S05-4 2S3A E8
2 BP INH
B 3S53-4 +2V5 LM324 14 3S38
B
2S2R
2S2S
3S16-2 7
10u
2 3S12-2 2S2V 22K +AUDIO-L 2S3B E8
AUDIO-IN1-R 7 10K COM IS02 13
10u
100R 100R 2S3C E8
2S2T
100n
22K 1u0 11 2S3D E8
2S34
100n
2
3S16-3 3 6
3S12-3 6 2S3E E3
3 2S2Z
AUDIO-IN2-L 10K 2S3F E2
22K 1u0 10K 2S3G E3
2 3S36-2 7
3S16-4 5 8 3S36-1 1
2S3H E3
IS0V 4 2S2Y 10K
4 3S12-4
100u 4V
2S3J B11
3S51
2S42
2S41
10K
4R7
5
1u0
AUDIO-IN2-R 2S2G
22K
2S3K G6
1u0
47p 2S3L H8
3S13-4 IS0R 4 3S17-4 5 7S00-2 2S3M H9
2S31
AUDIO-IN3-L 10K PNX85500 +24V-AUDIO-VDD
2S3Q G5
C 4
22K
5
3
1u0
AE10 AUDIO AC7
2S36
1
3S3G-1
8 ADAC(1)
C 2S41 C6
L P
3S13-3 3S17-3 6 AF10 AIN1 ADACL AB7 IS1N 33R 3S3G-3 4
2S42 C6
2S30 R N 1u0 IS03
AUDIO-IN3-R 3 6 10K 3 6 ADAC(2) ADAC(2) 10 7S05-3 3S0Z A11
AD10 AC6 LM324 8 3S39
22K 1u0 L P 33R -AUDIO-R 3S10 D4
AC10 AIN2 ADACR AB6 9
3S17-1 R N 100R 3S11 F5
1 8
3S13-1 2S33 11 3S12-1 B2
AUDIO-IN4-L 10K AE9 AD7
L 1 3S3G-2
1 22K 8 AF9 AIN3 AE7 2 7 ADAC(3) 3S12-2 B2
1u0 R 2
AF7 3S12-3 B2
2 3 33R
3S17-2 7 AD9 ADAC AD6 4 3S3G-4 5 ADAC(4) 3S12-4 C2
2S32 L 4
AUDIO-IN4-R 2 3S13-2 10K AC9 AIN4 AE6 IS1S 33R
7 R 5
AF6
3S13-1 C2
22K 1u0 6 3S13-2 D2
AF8
L
D 3S10
AE8
R
AIN5
OSCLK
AD4
AD1
3 3S36-3 6
10K
5 3S36-4 4
D 3S13-3 C2
3S13-4 C2
I2S_OUT SCK 3S3H 10K
2S2L 100R AB9 AD2 ADAC(5) 3S14 B9
POS WS 2S2H
IS1B AB8 VR_AADC 33R
1u0 NEG
AE1
3S16-1 B3
IS19 1 3S3U 47p
AD8 AF2 ADAC(6)
3S16-2 B3
VREF_AADC 2
AE3 +24V-AUDIO-VDD 3S16-3 B3
IS1A I2S_OUT_SD 3 33R
AC8 AF3 3S16-4 C3
VCOM_AADC 4
3S3F 3S17-1 C3
AF5
SPDIF_OUT 3S17-2 D3
2S3D
2S3C
2S3B
2S3A
2S39
2S38
1n0
1n0
1n0
1n0
1n0
1n0
56R DBS8 3S17-3 C3
AE5 IS07 4
SPDIF_IN1
2S3G
2S3H
2S3E
3S17-4 C3
2S3F
100n
100n
3 7S05-1
10u
10u
ADAC(5)
LM324 1
9S06
AUDIO-OUT-L 3S18-1 G7
E 2 E 3S18-2 G8
11 3S18-3 G8
3S19 H5
3S25 H9
3S32 G12
3S34 G11
3S36-1 C12
3S37 3S6L 3S36-2 B11
10K 22K
3S36-3 D11
2S2K 3S36-4 D12
3S37 F11
+3V3 47p 3S38 B13
F +3V3-ARC F 3S39 C13
+24V-AUDIO-VDD 3S3F E4
3S11
3S3G-1 C7
IS1L 3S3G-2 D8
1R0 3S3G-3 C8
3S3G-4 D7
4
2S3Q
3S3H D7
100n
ADAC(6) 5 7S05-2
LM324 7
IS06 AUDIO-OUT-R 3S3U D8
6 3S51 C6
11 3S53-1 A6
7S09-1
3S53-2 B6
14
74LVC00APW
IS1D
G SPDIF-OUT-PNX SPDIF-OUT-PNX 1 &
3
2S3K
IS1G 1 3S18-1 8 SPDIF-OUT
G 3S53-3 B6
3S53-4 B6
2 220R 3S6L F12
100n 3S34 3S32
2 3S18-2 7
3 3S18-3 6
+3V3 3S6M H8
220R
220R
7
+3V3-ARC
10K
74LVC00APW 7S09-3
7S08 B8
14
4 & 74LVC00APW
6 9 & IS1K IS44 7S09-1 G6
IS1E 2S3L 180R 2S3M
SEL-HDMI-ARC 5 8 eHDMI+ 7S09-2 H6
H +3V3
10
100n 3S6M 100n H 7S09-3 H7
7
7S09-4 I7
7
9S06 E4
3S25
68R
DBS8 E4
FS03 B12
FS08 B7
+3V3-ARC IS02 B11
IS03 C11
7S09-4 IS06 G11
14
IS19 D3
IS1A D3
IS1B D4
IS1D G5
IS1E H5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_514_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 148
PNX Mips
PNX Mips
B02E B02E
1F10 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S89 D8
3S00 B5
3S21 B1
3S26 C5
3S27 C6
3S40 A1
3S45 A1
3S55 C3
3S56 A5
3S57 A6
+3V3 3S58 A5
A 7S00-3
PNX85500 A 3S5W B6
3S5Y B5
CONTROL C25 1 3S56 2 3S69 1F10 3S5Z B6
IS05 SDA SDA-UP-MIPS SDA-UP-MIPS
3S45 1 C26 100R 1 2 3S57 3S6A 4K7 4K7 FS44
+3V3 BOOTMODE SCL SCL-UP-MIPS SCL-UP-MIPS EJTAG-TRSTn-PNX85500 1 3S60 B5
100R EJTAG-TMS-PNX85500 FS49
10K 2 3S61 B6
BOOTMODE Y21 B26 1 3S58 2 SDA-SET SDA-SET 3S6B 4K7 EJTAG-TDO-PNX85500 FS50
3S40
GPIO1 GPIO1 Y22
GPIO_0
2
SDA
A25 100R 1 2 3S5W SCL-SET SCL-SET 3S6C 4K7 EJTAG-TCK-PNX85500 FS51
3 FOR FACTORY 3S62 B1
+3V3 GPIO_1 SCL 4
RXD1-MIPS Y23 100R EJTAG-TDI-PNX85500 FS52 USE ONLY 3S64 C1
10K GPIO_2 5
DS52 TXD1-MIPS Y24 B25 1 3S5Y 2 SDA-SSB SDA-SSB 3S6D 2K2 3S65 E11
3S82 RES GPIO_3 SDA 3S5Z 6
BOOST-PWM RXD2-MIPS W21 3 A24 100R 1 2 SCL-SSB SCL-SSB 3S6E 2K2 EJTAG-DETECTn FS53 3S66 E11
+3V3 GPIO_4 SCL 7
TXD2-MIPS W22 100R
10K GPIO_5 8 3S67 E11
3S80 FS10 TXD2-MIPS PNX-SPI-CS-AMBIn W23 B24 1 3S60 2 SDA-TUNER SDA-TUNER 3S6F 4K7 10 9
+3V3 GPIO_6 SDA 3S68 E11
3S81 10K FS11 RXD2-MIPS PNX-SPI-CS-BLn V22 4 A23 100R 1 2 3S61 SCL-TUNER SCL-TUNER 3S6G 4K7
+3V3 GPIO_7 SCL 3S69 A9
B +3V3
3S21
10K
PNX-SPI-CS-AMBIn
BOOST-PWM
SELECT-SAW
V23
U23
GPIO_10
GPIO_11 TRSTN
AA25
100R
EJTAG-TRSTn-PNX85500 EJTAG-TRSTn-PNX85500 3S6K B 3S6A A8
IS04 AA24 EJTAG-TMS-PNX85500 EJTAG-TMS-PNX85500 1 8 3S6H-1 10K +3V3 3S6B A9
10K TMS +3V3-STANDBY FS57 BM08B-SRSS-TBT
USB-DM R26 AA23 EJTAG-TCK-PNX85500 EJTAG-TCK-PNX85500 10K 3 6 3S6H-3
3S62 PNX-SPI-CS-BLn DN TCK 3S6C B8
+3V3 USB-DP R25 AB26 EJTAG-TDO-PNX85500 EJTAG-TDO-PNX85500 10K 2 7 3S6H-2
IS4Z R24 DP USB TDO
AB25 EJTAG-TDI-PNX85500 EJTAG-TDI-PNX85500 10K 4 5 3S6H-4 3S6D B9
10K RREF TDI
10K 3S6E B8
3S00
3S55
RESET_SYS
AE4 RESET-SYSTEMn 3S6F B9
5K6
3S64 FS64 33R 3S6G B8
SELECT-SAW AD5 BACKLIGHT-PWM
+3V3 BL_PWM 3S6H-1 B8
10K 3S6H-2 B9
AC5
CLK_54_OUT 3S6H-3 B9
3S26
3S27
3S6J
10K
10K
10K
3S6H-4 B9
C +3V3
3S83
RXD1-MIPS
C 3S6J C5
3S6K B9
10K 3S72 C6
3S84 +3V3 +3V3
TXD1-MIPS IS40 3S80 B1
+3V3 3S72
10K PXCLK54 3S81 B1
47R 3S82 B1
3S83 C1
3S84 C1
7S00-3 A4
7S00-4 G12
RES
7S01 E8
9S10 F8
D D 9S11 F8
+3V3 9S12 F8
9S13 F8
2S89 DS52 B2
FS10 B2
100n +3V3 FS11 B2
FS2W F9
3
7S01
PCA9540B 3S65 FS2Y F9
VDD SC0 5 SCL-DISP SCL-DISP 2 1 FS31 F8
3S66 4K7 FS44 A12
SC1 8 SCL-BL SCL-BL 2 1
FS49 A12
3S67 4K7
FS50 A12
E SCL-SET 1 SCL
INP
I 2 C
-BUS
SD0 4 SDA-DISP SDA-DISP 2
3S68
1
4K7 E FS51 B12
2 SDA FIL SD1 7 2 1
SDA-SET CTRL SDA-BL SDA-BL FS52 B12
4K7
FS53 B12
VSS
FS57 B12
FS64 C2
6
FS31 IS04 B2
IS05 A2
IS08 F8
IS09 F8
9S10 SCL-BL IS40 C6
IS08 IS4Z B4
F SCL-SET 9S11 FS2W SCL-DISP
F IS50 G12
9S12 FS2Y SDA-DISP
IS09
SDA-SET 9S13 SDA-BL
7S00-4
PNX85500
ETH-RXCLK AA3
RXCLK ETHERNET
G ETH-RXD(0)
ETH-RXD(1)
Y5
Y6
0
1 TXCLK
AA2 ETH-TXCLK
G
ETH-RXD(2) IS50 AB4 RXD ETH
2
ETH-RXD(3) AC1 AA1 ETH-TXD(0)
3 0
AA4 ETH-TXD(1)
1
ETH-RXDV AC2 TXD AB1 ETH-TXD(2)
RXDV 2
ETH-RXER Y4 AB2 ETH-TXD(3)
RXER 3
ETH AA5 ETH-TXEN
TXEN
SDIO-DAT3 W2 AB3 ETH-TXER
CC_DAT3 TXER
SDIO-CLK W1 AC3 ETH-COL
CLK COL
SDIO-CMD W6 Y2 ETH-CRS
CMD CRS
SDIO-DAT0 W5 Y3 ETH-MDC
0 MDC
SDIO-DAT1 W4 SDIO Y1 ETH-MDIO
1 DAT MDIO
SDIO-DAT2 W3
2
H SDIO-CDn
SDIO-WP
U6
V6
SDCD
SDWP
H
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_515_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 149
A A
B B
C 7S00-7
PNX85500 C
PX1A- A7 LVDS D7 PX3A-
N N
PX1A+ B7 A A E7 PX3A+
P P
PX1B- C8 E8 PX3B-
N N
PX1B+ B8 B B D8 PX3B+
P P
F F
G G
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_516_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 150
+1V1
POL
3S1B C2
3S1C C1
3S1D C2
IS3B
3S1E C1
3S1F C2
5S04
RES
30R
3S1G D2
2S10
100n
1u0
2S13 3S1H D1
2S37 3S1J D2
3S1K D1
1u0 3S1L E2
9S24
RES
3S1P D11
B 2S11 B 3S2A D2
100n 3S2F D7
IS20 DS50 2S4G 3S2G D7
3
3S2H D7
1 10p
AC17
3S2K D7
AA17
AF26
1S02
54M
7S00-9
PNX85500 2S4F 3S2L D10
VDDA_1V1_DCS
VDDA_ADC2V5
VDD_XTAL
3S2M E10
AE17
1
+3V3-STANDBY 2S4D XTAL_IN 10p +3V3-STANDBY 3S2S E10
3S1B 1n0 AD19
RC RC
3S1C RES 10K AE19
0
AF17
3S2V F11
TACHO TACHO 1 XTAL_OUT
10K 3S1D CEC-HDMI CEC-HDMI AF19 3S3L C2
2 P1
3S1E RES 27K BACKLIGHT-PWM-ANA-DISP BACKLIGHT-PWM-ANA-DISP AA20 AA26 RESET-STBYn 3S3M C1
3 RESET_IN
C +3V3-STANDBY
10K 3S1F
10K
SDM SDM AB20
7
STANDBY EA
AB24 EA EA
IS3F 3S44 C 3S3N C2
3S3P C1
3S3L RES LCD-PWR-ONn LCD-PWR-ONn AC20
0 ALE IS3E 10K 3S43 3S3Q C2
3S3M 10K EJTAG-DETECTn EJTAG-DETECTn AD20 AB23 ALE
3S3N RES 1 ALE 3S3R D2
10K LAMP-ON LAMP-ON AE20 IS3D 10K
2 10K 3S42
3S3P 10K STANDBY STANDBY AF20 AC26 PSEN PSEN 3S3S D1
3 PSEN
10K 3S3Q RES FAN-CTRL1 FAN-CTRL1 AA21 P2 3S3T D1
RES 3S3S 4 3S2F 100R RES 3S6V
10K FAN-CTRL2 FAN-CTRL2 AB21 AC23 SDA-UP-MIPS SDA-UP-MIPS 3S3W E9
5 SDA
10K 3S3R POWER-OK POWER-OK AC21 MC AC24 3S2G 100R SCL-UP-MIPS SCL-UP-MIPS 4K7 3S6W
3S3T 10K RES AD21
6 SCL 3S3Y D9
ENABLE-3V3n ENABLE-3V3n 7 4K7 RES
10K AD26 3S2H 100R LED1
LED1 RES 3S1P 3S41 D12
+3V3-STANDBY 3S1G 0
RXD-UP RXD-UP AE21 PWM AC25 3S2K 100R LED2 LED2 10K 3S41 3S42 C11
0 1
3S1H 10K TXD-UP TXD-UP AF21 3S43 C11
1 10K
10K DETECT2 AA22 AE23 PNX-SPI-SDO 3S44 C11
3S2A RES 2 SDO
D 10K
DETECT2 AB22
AC22
3
4
P3
SPI
SDI
CLK
AF25
AF24
PNX-SPI-SDI
PNX-SPI-CLK
D 3S46 D10
AD22 AF23 PNX-SPI-CSBn
3S47 E10
5 CSB
3S49 E10
3S1K RES RES 3S2L
RESET-SYSTEMn RESET-SYSTEMn AD23 AB17 IS2V CTRL-DISP CTRL-DISP 3S6V C11
0 0 RES 3S46
AV2-BLK AE26 AA18 IS2Z RESET-DVBS RESET-DVBS 10K 3S6W D12
10K 1 1
AV1-BLK AE25 P5 AD18 RESET-USBn RESET-USBn RES 3S3Y 10K
3S1J KEYBOARD AE24
2 2
AE18 10K 3S47 +3V3-STANDBY 5S04 B6
KEYBOARD 3 3 RESET-ETHERNETn RESET-ETHERNETn RES
LIGHT-SENSOR P0 AF18 SEL-HDMI-ARC SEL-HDMI-ARC 3S2S 10K 7S00-9 B6
100K 2S4E 4
AV1-STATUS AF22 AA19 RESET-AVPIP RESET-AVPIP 10K RES 3S2M 7S20 G10
4 5
VSS_XTAL
AV2-STATUS AE22 P6 AB19 RESET-AUDIO RESET-AUDIO 3S3W 10K RES 9S0D G9
100n 5 6
AC19 AUDIO-MUTE-UP AUDIO-MUTE-UP 4K7 3S49 9S0E G9
7
AD17
3S1L
SPI-PROG SPI-PROG 4K7
9S24 B6
10K PNX-SPI-WPn
DS50 B8
E E FS0Z G11
FS45 G9
IS20 B6
IS2U G10
IS2V D7
IS2Z D7
IS3B A6
IS3D C10
IS3E C10
IS3F C10
F F
+3V3-STANDBY +3V3-STANDBY
1 3S2V 2
10K
9S0E
FS0Z
7S20 RESET-STBYn
NCP303LSN28
FS45 2
INP
1 IS2U 1
OUTP
5
CD
NC GND
G G
3
9S0D
2S4K
100n
RES
H H
1 2 3 4 5 6 7 8 9 10 11 12 13
6 2009-12-07
PNX85500
8204 000 8950
18770_517_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 151
PNX Power
PNX Power
B02H B02H
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2S21 F6 2S5K-4 C5
IS3Q 5S80 2S23 B6 2S5M G11
+1V1
30R 2S26 A6 2S5P F5
RES 10u
2S6A
2S5A
100n
2S27 B3 2S60 A6
2S28 B3 2S61 A6
1
5S81 2S29 C6 2S62 A7
A +2V5
A 2S43 B2 2S63 A7
2
30R
RES 10u
2S45 F11 2S64 A7
2S6B
2S5B
100n
2S46 F11 2S65 A7
2S4M B12 2S66 A7
1
+1V8
IS3S 5S82
2S26
2S60
2S61
2S62
2S63
2S64
2S65
2S66
2S67
2S68
100n
100n
100n
100n
100n
100n
100n
100n
100n
2S4N C11 2S67 A8
47u
+3V3
30R
2
2S4P C11
RES 10u
2S68 A8
2S5C
2S5D
100n
2S4Q B3 2S6A A11
2S4R B4 2S6B A11
SENSE+1V1 c001
7S00-10
5S93
2S4S F5 2S6C C11
G6
G7
R6
R7
U7
C6
D6
A5
A6
B5
B6
E6
F6
F7
L6
L7
+2V5
B PNX85500 30R
B 2S4T H11 2S6D B11
2S6E 2
220u 6.3V
VDD_1V8
2S4M
2S6D
100n
100n
AF1 V20
+1V1 2S4U D11 2S6E B11
7
AE2 HDMI_VDDA_1V1 V21
5
AD3
2S4V D11 2S6F C11
1
2S5G-1
2S5G-2
2S5G-3
2S5G-4
2S5H-1
2S5H-2
2S5H-3
2S5H-4
2S4Q
2S4R
2S43
2S28
2S27
2S23
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
100n
AC4 VDD U20
22u
22u
47u
1
AB5
H20
HDMI_VDDA_2V5 U21 2S4W D11 2S6G C11
4
F11 U22 +2V5-LVDS 2S4Y D11 2S6H H11
2
HDMI_VDDA_3V3_TERM
G11
F13 N6 2S4Z E11 2S6K H11
2S4N
2S4P
100n
G13 VDD_2V5 N7
10u
F15 2S50 E11 2S6L I11
2S5J-3 6
2S5J-1 8
8
5
G15 C7
2S51 E9 2S6M I11
2S5K-1
2S5K-2
2S5K-3
2S5K-4
2S5J-2
2S5J-4
C C
100n
100n
100n
100n
100n
100n
100n
100n
100u 2.0V
F17 C9
G17 C11
2S29 F19 VDD_2V5_LVDS C14
5S85 2S52 E9 2S6N C11
1
4
+3V3
2
1 2S6G 2
G19 C16
2S53 H11 2S6P C12
1
30R
2S6N
2S6C
2S6P
2S6F
100n
100n
100n
100n
J9 C18
10u
J11 2S55 G11 2SHW I11
AA16
AA8
Y11
Y14
J13 W20
Y16
Y9
7S00-12
1
PNX85500 J15 P20 2S56 G11 5S80 A12
VSSA J17 M20
A1 M7 L9 VDD_3V3 K20
+3V3-STANDBY
2S57 G11 5S81 A12
A10 N2 L11 V7
2S58 H11 5S82 A12
2S4U
2S4V
100n
A12 N20 L13 Y8
10u
A15 P10 L15
A17 P12 L17
VDD_1V1
Y19 2S59 I11 5S83 D12
D A19
A26 VSS
P14
P16
N9
N11
VDD_3V3_SBY Y18
IS3K 5S83
D 2S5A A11 5S84 E12
A3
A8
P18
P4
N13
N15
VDDA_1V1_LVDS_PLL
B13
+1V1 2S5B A11 5S85 C12
IS3L 30R
2S4W
2S4Y
2S5C B11
100n
B1 P6 N17 AA15
5S87 F12
RES 1u0
B20 P7 R9 Y15
VDDA_1V2
C20 T10 R11 AA13 2S5D B11 5S88 G12
C4 T12 R13 5S95 +2V5
D2
VSS
VSS T14 R15
VDDA_2V5
Y12
5S84 2S5G-1 B4 5S89 H12
D20 T16 R17
30R 2S5G-2 B4 5S90 H12
6.3V
E13 T18 U9 AA9 +1V2
VDDA_2V5_AADC 30R
2S4Z
2S51
2S52
2S50
100n
100n
E20 T2 U11
10u
E4 T6 U13 AA7 c000 SENSE+1V2 2S5G-3 B4 5S92 I12
10u
VDDA_2V5_ADAC
F10 T7 U15
2S5G-4 B5 5S93 B12
E F12
F14
U4
V10
U17
J6
VDDA_2V5_DCS
Y17
E 2S5H-1 B5 5S94 F5
F16 V12 AA6 D13
VDDA_2V5_LVDS_BG
F18
F20
V14
V16
Y7
W7 T20 POL 2S5H-2 B5 5S95 E10
VSSA_1V1_LVDS_PLL
VSSA_2V5_LVDS_BG
VDDA_2V5_USB
F8 V18 F9 2S5H-3 B5 7S00-10 B6
G10 V2 G9 Y13 +2V5-AUDIO
VDDA_2V5_VADC
G12 Y20 2S5H-4 B5 7S00-12 C1
V24 HDMI_AGND
5S94
2S46
100n
J7 Y10
VSSA_USB
VSS +1V1
30R
VDD_1V1_DDR VDDA_2V5_VDAC
2S5J-1 C5 IS3K D10
2
G14
G16
G18
G2
G20
G8
H4
H6
H7
J20
K10
K12
K14
K16
K18
K2
K6
K7
L20
L4
M10
M12
M14
M16
M18
M6
R21
VDDA_3V3_USB 2S5J-2 C5 IS3L D10
2S4S
2S5P
2S21
100n
10u
1u0
RES
2S5J-3 C5 IS3Q A10
U24
A13
C13
R20
1
2S45
100n
IS58 I10
2S5K-2 C4 c000 E13
5S87 2S5K-3 C4 c001 B5
+2V5
30R
2S55
2S56
100n
1u0
G 5S88
+2V5-LVDS
G
30R
2S5M
2S57
100n
10u
5S89
+2V5
2
30R
2S6H
2S6K
100n
100n
2S58
10u
1
1
H 5S90
+2V5
H
30R
2S4T
2S53
100n
10u
2SHW
100n
I I
IS58 5S92
+3V3
2
30R
2S6M
2S6L
2S59
100n
100n
1u0
1
1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_518_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 152
3S59
47R
Connectivity 22n
2S22 A11
3S5B
47R
A A 2S40 B11
AV1-R 2S7J 2S75 F11
22n 2S22 C-SVHS
2S76 F11
3S4J
2S77 F12
56R
22n
3S05
56R
2S78 G12
2S7E G6
EU: SCART1 CVBS-MON-OUT1 2S7H B6
AV1-B 2S7K
AP: - 2S7J A6
3S5E
560R
22n
2S7K B6
3S4L
56R
B B 2S7L C6
IS4V
2S7M C6
2S7N D6
560R
2S40
3S08
47p
2S7H
AV1-G 2S7P D6
22n 2S7Q E6
3S4K
56R
IS4W
2S7R F6
2S7U F6
3S09
8K2
C C 2S84 G6
2S7M
YPBPR1-SYNCIN1 2S85 H6
10n
2S7L
2S86 H6
AV3-Y
2S87 A6
22n
3S4P
2S8A A11
56R
2S8G E6
2S7N
AV3-PR 3S05 A11
EU: YPBPR1 22n
3S08 B11
3S4R
56R
D AP: YPBPR1
7S00-1
PNX85500 D 3S09 C11
2S7P ANALOG_VIDEO 3S4G G6
AV3-PB
22n
AB15
CVBS_Y1 ATV_CVBS_Y3 AC12 3S4J A6
2S19
2S18
2S16
2S15
2S14
3S4T
AC13 IS5C
56R
AF13
22n
22n
22n
22n
22n
R C3
AD13
AE13
B AV1
AD11
3S4K C6
G CVBS_Y7
C7
AC11 3S4L B6
AV2-CVBS 2S8G AF15
AE15
SYNCIN1
Y_G1 CVBS1_OUT
AF11
BS13
3S4P D6
22n AC15 AE11
PR_R_C1 CVBS2_OUT 3S4R D6
3S5L
AD15
47R
PB_B1
AB14
RESREF AB10
AA11 IS5E 3S5S
3S4T D6
E 2S7Q
AF14
CVBS_Y2
SYNCIN2
CURREF
10K E 3S4U F6
YPBPR2-SYNCIN2 AE14 AC16 IS5D
Y_G2 1
10n
AC14
PR_R_C2 2 AB16 IS5F
IS5G
3S4W F6
AD14 AB13
PB_B2 3
REF 4 AB12 IS5H 3S50 H6
AF16 AA12 IS5J
AD16
R
G VGA
5
6
AA10 3S75
PNX-IF-AGC 3S52 H6
AE16
B 47K 3S54 I6
2S75
2S7R AB18 BS15
10n
AV4-Y HSYNC_IN IF_AGC AD12
AC18 BS17
EU: 22n AF4
IN
VSYNC
RF_AGC AB11
3S59 A6
SCART2 OUT
3S4U
2S76
AGND
10n
AA14
AV4-PR 2S7U
3S5S E9
22n
3S5T-1 I5
3S4W
56R
2S77
PNX-IF-P 3S5T-2 I11
10n
3S5T-3 I5
2S7E
3S5T-4 I11
AV4-PB
22n 2S78
3S5V-1 I5
3S4G
56R
G 10n
PNX-IF-N
G 3S5V-2 I12
3S5V-3 I5
R-VGA
2S84 3S5V-4 I12
22n 3S75 E12
3S50
56R
3S76 F12
7S00-1 D8
G-VGA
2S85 9S14 I3
22n 9S15 I3
3S52
56R
H H 9S17 A13
BS09 F9
2S86
B-VGA BS10 F10
22n BS13 E9
3S54
56R
EU: VGA
BS15 F9
4 3S5T-4 5
2 3S5T-2 7
4 3S5V-4 5
2 3S5V-2 7
AP: VGA
100R
100R
100R
100R
H-SYNC-VGA 1 3S5T-1 8
BS17 F10
100R IS11 F13
V-SYNC-VGA 3 3S5T-3 6 IS4V B10
100R
IS4W C10
I VGA-SCL-EDID 3 3S5V-3 6
I IS5C D9
100R IS5D E9
VGA-SDA-EDID 1 3S5V-1 8 IS5E E9
100R
VGA-SCL-EDID-TCON 9S14
* IS5F E9
VGA-SDA-EDID-TCON 9S15
* *
= TCON ONLY IS5G E9
IS5H E9
IS5J E9
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 2009-12-07
PNX85500
8204 000 8950
18770_519_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 153
Audio
B03A B03A
1 2 3 4 5 6 7 8 9 1735 E8 FD06 E8
1D38 E9 FD07 F4
1D50 E8 FD14 A5
1D52 F8 ID05 C8
2D01 F7 ID06 C8
+AVCC
2D02 F4 ID07 C8
7D03-1 +24V-AUDIO-POWER 2D03 E3 ID08 C8
3D09 BC847BS(COL) FD14 2D05 A5 ID09 C7
1
+24V-AUDIO-POWER
2D06 A5 ID10 C7
4R7
A A 2D07 B5 ID11 A4
2D06
220n
2D08 B6 ID12 A5
2D09 C7 ID13 E3
2
3D16 ID12
ID11 2D10 C7 ID14 B3
5D07
220R
5D08
220R
22K
2D11 C8 ID15 B3
10u 35V
GND-AUDIO
2D05
2D12 C8 ID18 C5
2D13 F8 ID19 C5
ID27 ID28
FD01 2D28 ID14 2D24 2D14 E8 ID27 B6
-AUDIO-R
2D16 C4 ID28 B6
220u 35V
220u 35V
1u0 47n 2D17 C4 ID29 C5
8
2D20
2D07
2D19
2D08
220n
220n
6
3D02-1
3D14-4
3D14-3
3D14-2
3D14-1
2D22
2D26
220n
220n
2D19 B6 ID30 C5
4K7
22K
22K
22K
22K
3D02-3
A-PLOP 6 3 2 7D15-1 2D20 B5 ID31 C6
B BC847BS(COL)
B 2D21 D8 ID32 C6
1
4K7
1
2D22 B8 ID33 F4
2D23 B4 ID34 D3
GND-AUDIO GND-AUDIO 2D24 B4 ID35 D3
2D26 B8 ID36 E2
7D10-1
FD03 2D29 ID15 2D23 TPA3120D2PWP 2D27 D8 ID37 D4
19
20
10
12
+AUDIO-L
1
3
2D28 B2 ID38 D5
1u0 47n AVCC L R
2D29 B2 ID39 E2
5
3
3D02-4
PVCC ID32 2D10
Φ 16 3D01-1 D3
4K7
3D02-2 ID19 BSR ID10 5D02 5D05 2D12 RIGHT-SPEAKER
7 2 5 7D15-2 6 3D01-2 D3
BC847BS(COL) ID18
R CLASS-D 15
220n
ID06 ID08 3D01-4 E2
4
4K7 IN R 22u 220R 25V 220u
4 5 AUDIO AMP
L OUT 3D02 B3
C 18
0
L
22
ID31 2D09
ID09 5D01 5D04 ID07 2D11 LEFT-SPEAKER C 3D02 C3
17
1
GAIN
BSL
21 22u ID05 220R 25V 220u
3D02 B4
GND-AUDIO 2D16 ID29 220n 3D02 C4
11
VCLAMP 3D04 E2
2D17 1u0 7
BYPASS 3D06-1 F4
1u0 ID30 4
MUTE 3D06-2 F4
2
AUDIO-MUTE-UP ID37 SD
3D06-3 F3
PGND
AGND L R 3D06-4 F3
A-STBY ID38 GND_HS
3D09 A3
8
9
23
24
13
14
25
3D10-1 D8
5
3D15-4
+3V3-STANDBY 3D10-2 D8
8
8
4K7
3D01-1
3D10-4
3D10-3
3D10-2
3D10-1
D D
2D21
2D27
220n
220n
6 3D10-3 D7
47K
22K
22K
22K
22K
CD10
MAINS SWITCH DETECT 3D10-4 D7
4
7D11-1 2
3D14-1 B8
1
1
BC847BS(COL)
ID34 GND-AUDIO 3D14-2 B8
1 3 +3V3-STANDBY
+3V3-STANDBY ID35 3D14-3 B7
3D01-2
7D11-2 5 2 7 DETECT2 3D14-4 B7
5
BC847BS(COL) 3D15-1 E2
47K
3D01-4
6 4
47K
40
39
38
2D03
100p
GND-AUDIO 7D10-2
7D13-1 2 TPA3120D2PWP 3D15-4 D5
4
V_NOM
3D15-1 3D15-2 ID13 6D01
E E
1D50
2D14
7D13-2 5 1 8 7 2 28 VIA VIA 35
10n
BC847BS(COL)
5D03 E7
4K7 4K7 29 34
BZX384-C GND-AUDIO GND-AUDIO 5D04 C8
4
VIA 5D05 C8
3D04
2K2
MAINS-OK
1735 1D38 5D07 A6
30
31
32
33
FD05 5D08 A6
GND-AUDIO GND-AUDIO 5D03 1 1
FD06
2 2 6D01 E3
GND-AUDIO 220R 3 3 7D03-1 A5
2D01
GND-AUDIO FD02
10n
GND-AUDIO 4 7D03-2 F5
2D13
3 7D03-2 1735446-3
10n
BC847BS(COL) 1735446-4 7D10-1 B6
3D06-4 FD07 3D06-2
LEFT-SPEAKER 5 7D10-2 E5
4 100K 5 7 2
100K 7D11-1 D2
4
7D11-2 D3
F 8
3D06-1
1
ID33
RIGHT-SPEAKER
F 7D13-1 E1
7D13-2 E2
V_NOM
100K
1D52
GND-AUDIO 7D15 B3
7D15 C3
2D02
RIGHT-SPEAKER 3
3D06-3
6 CD10 D5
FD01 B1
100K 10u
GND-AUDIO
FD02 F8
FD03 B1
FD05 E8
1 2 3 4 5 6 7 8 9
4 2009-10-22
CLASS D
8204 000 8951
18770_520_100118.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 154
DC/DC
DC/DC
B03B B03B
2U00 D2 2U04 F4 2U08 G9 2U12 F11 2U16 C10 2U20 B14 2U24 B5 3U01 F1 3U05 E4 3U11 B6 3U19 G9 3U23-1 C9 3U24-1 F9 3U27 D5 5U02 B13 7U01 D8 7U04 E8 FU02 B9 FU06 E8 IU04 G3 IU08 D4 IU12 D7 IU16 E5 IU20 G9 IU24 E3
2U01 E3 2U05 F4 2U09 F9 2U13 F12 2U17 C9 2U21 C6 2U25 B12 3U02 F2 3U08 G2 3U14 D7 3U20 F11 3U23-2 C9 3U24-2 F9 3U28 D5 5U03 A13 7U02-1 B6 CU00 H7 FU03 C14 IU01 F3 IU05 D3 IU09 C6 IU13 D7 IU17 F9 IU21 H9 IU25 F4
2U02 D4 2U06 F1 2U10 F10 2U14 E14 2U18 D9 2U22 D8 2U29 G14 3U03 F3 3U09 H3 3U17 G10 3U21 G13 3U23-3 C9 3U24-3 F9 5U00 C10 6U00 E8 7U02-2 C6 FU00 G13 FU04 F4 IU02 F3 IU06 D3 IU10 B 6 IU14 E8 IU18 F9 IU22 B13
2U03 E2 2U07 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3U00 F1 3U04 D3 3U10 H3 3U18 G10 3U22 G2 3U23-4 C8 3U24-4 F8 5U01 E10 7U00 F1 7U03 E3 FU01 E14 FU05 B9 IU03 F1 IU07 D4 IU11 C6 IU15 C9 IU19 G10 IU23 C9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
5U03 RES
30R
FU05 5U02 IU22
+12V
30R
7U02-1
2U24
2U23
2U25
2U19
2U20
10u
10u
10u
10u
1u0
SI4952DY
B IU10
7 8 B
2
12V/1V8 CONVERSION
1
3U11
3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6
3 3U23-3 6
2 3U23-2 7
1 3U23-1 8
22u
3U23-4
2U15
2U16
47R
47R
47R
47R
47u
7U02-2
SI4952DY
4
5 6
C IU09
4 IU23 C
2U17
1n0
IU15
7U01
SI4778DY
2U18
1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
D D
2U00
3U14
10u
3R3
3U04
3R3
2U22
IU06 2U02 IU07
IU05 IU13 220p
3U28
10R
100n
2U01
3U05
100n
3R3
7U04
7U03 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
12V/1V1 CONVERSION
E ENABLE-1V8
3
10
1
2
EN DRVH
1
2
1
12 E
1n0 RES
+1V1 4 24 +1V1
1 1
STPS2L30A
+1V8 9 VO SW 13
6U00
2U14
5 22
3U24-4
3U24-3
3U24-2
3U24-1
1 1
3U20
2U12
2U13
8 VFB PGND 15
22u
47R
47R
47R
47R
10R
RES
47u
RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 22K IU02 GND-SIG
GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5
F F
2U11
1n0
+3V3-STANDBY 3U00 2U06
+1V1 GND
2U04
2U05
6
10u
1u0
10K 100n
IU18
10K
3U01
GND-SIG
2U09
2U10
1n0
1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%
3U17
1% 330R
2U29
100n
RES
G IU20 G
100p RES
3U19
2U08
3U18
5K6
1% 1K0
3U08 3U22
IU04
+1V8
330R 1% 1K0 1% IU21
RES 100p
1K0 1%
3U09
3U10
2U07
22K
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
4 2009-10-22
DC/DC
8204 000 8951
18770_521_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 155
DC/DC
DC/DC
B03C B03C
1 2 3 4 5 6 7 8 9 1M95 E1 3U84 D2
1M99 C1 6U40 E3
1U40 E2 7U40-1 F4
2U41 B1 7U40-2 E4
2U42 C2 7U41-1 F4
2U43 D2 7U41-2 F5
2U44 D3 7U42 B5
2U45 D3 7U43 B3
2U46 D3 7U48-1 C6
A +3V3 +3V3-STANDBY A 2U47 E1 7U48-2 E6
2U48 F1 9U41 B5
LED-2
2U49 F1 9U42 B4
RES 10K
RES 10K
3U74
3U75
+5V +3V3-STANDBY
2U50 F1 FU07 C3
IU43
2U51 D1 FU48 C1
9U41
2U52 D1 FU49 C1
RES 10K
2U53 D2 FU50 C1
3U68
3U69
10K
LED-1
IU44 2U54 F2 FU51 C1
3U41 LED2 LED2 3U59
IU45 2U55 F3 FU52 C3
B ∗ optionally 1M99 is a 9 pin connector 9U42
RES
10K RES 10K RES
B 2U68 E1 FU53 C2
7U42 RES +3V3 2U71 D5 FU54 C2
BC847BW 2U72 D1
IU47
FU55 C1
2U41 RES
∗
3U70 3U53
7U43 LED1 LED1 3U41 B5 FU56 D1
BC847BW
100p 10K 10K 3U42 C3 FU57 D1
+12VD
3U43 C3 FU58 E1
3U44 C3 FU59 E1
1M99
FU48 2U42 3U45 C3 FU60 E1
1 3U81 IU56
2
FU49
1u0 +3V3 3U53 B6 FU61 E1
FU50
3 10K 3U56 D3 FU62 E1
4
C 5
FU51
FU52
3U45
LAMP-ON
IU64
C 3U59 B6
3U60-1 F5
FU63 E1
FU64 F1
6 100R 3U82
FU53 3U42 BACKLIGHT-PWM_BL-VS
7 3U60-2 F4 FU65 F1
8 100R 1K0 RES
9
FU55 3U64 3U43 BACKLIGHT-BOOST
7U48-1
3U60-3 E5 FU66 F1
10 1K0 FU54 100R
3U44
FU07
BACKLIGHT-PWM-ANA-DISP 4
3U83-4
5
BC857BS(COL)
ENABLE-3V3-5V
3U60-4 F5 FU67 F1
6
11 3U61 E5 FU68 F1
RES 1K0
RES 100p
RES 100p
12 100R 100K
100p
2U51
2U52
2U53
3U65
1n0
10n
10n
3U62-1 F4
1n0
1
1-1735446-2
3U62-2 E3
3U83-1
FU73 E5
2U72
100K
+3V3
2
10K
2U44
2U45
2U46
2U43
2U71
3U62-3 E4
100n
FU74 D1
RES
IU55 3U62-4 E3
8
POWER-OK
IU40 E5
D 3U66
BL-SPI-SDO
D 3U63 F5
3U64 C2
IU41 D5
FU56 IU43 B5
RES 100R 3U67
BL-SPI-CSn +3V3-STANDBY
3U65 D2 IU44 B5
FU57
100R RES 3U84 3U66 D2 IU45 B4
BL-SPI-CLK
3
FU74 3U67 D2 IU47 B4
100R RES 3U71
STANDBY 3U68 B3 IU48 E4
7U48-2
2U68 100R BC857BS(COL) 3U69 B3 IU49 E3
5
3U70 B4 IU50 F4
5
7U40-2 3U83-2
3U62-4
1u0 3U83-3 7 2
3 6 3U71 D3 IU51 F3
10K
BC847BPN(COL)
2U47
4
IU48 100K IU40 100K 3U72 F3 IU52 F5
4
10n
E 1M95
+3V3-STANDBY
5
E 3U73 F3 IU55 D3
2
FU58 3
3U74 A4 IU56 C3
3U62-2
1 3U60-3 FU73
FU59 3 6 ENABLE-1V8
10K
2 IU61
FU60 3U75 A4 IU57 F6
BZX384-C6V2
3 22K
RES 10K
6
3U61
3U62-3
4
6U40
FU62
10K
5
FU63
1U40 +12V IU49 3U80 F4 IU62 F4
6 6
2
FU67 1
1K0
7U41-2
7
10 FU68 3U76
1u0 RES
100R IU57
3U83-3 E5
3U60-4
3U60-1 ENABLE-3V3n
100p RES
3U80
100p RES
1-1735446-1 5 8 1
4K7
22K
2U49
2U50
2U54
4 IU52
10n
10n
+3V3-STANDBY
8 1
10K 6
3K3
3U63
RES 10K
7U41-1
BC847BS(COL) 2
1
1 2 3 4 5 6 7 8 9
4 2009-10-22
DC/DC
8204 000 8951
18770_522_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 156
DC/DC
DC/DC
B03D B03D
1 2 3 4 5 6 7 8 9 2UA0 A5 3UB3 F6
2UA1 A4 3UB4 F5
2UA2 B5 3UB5 F5
RESERVED 2UA3 B5 3UB6-1 C2
2UA4 A7 3UB6-2 C2
+2V5-REF +12V +3V3
7UC0
LF25ABDT
∗ 2UA5 B6 3UB6-3 C2
3K3 1%
1K0
2UA0
2UA6 B7 3UB6-4 C2
3UA4
+12V 1 3
A 3UA1
100n 7UA2
PHD38N02LT
IN
COM
OUT
A 2UA7 D4 3UB7-1 D3
2UA4
3UB7-2 D2
1u0
7UA1-1 2UA8 D5
*
3UA0
8
IUA1 3 LM833
2K2
IUA3 IUA4
2
3UA5
2
1 1 2UA9 D5 3UB7-3 D2
100n
FUA0
3
22R
2UB0 C7 3UB7-4 C2
2UA1
FUA1
3K3 1%
+2V5-REF
4
3UA3
2UA3
47K
1
3UA2 2UB1 D6 5UA0 E8
1n0
7UA0
TS2431 2UB2 D7 7U06-1 F2
2UA2
K
IUA9
2UB3 F6 7U06-2 F1
330p
R
2
2UB4 F6 7UA0 B2
3UA6
A
B B
1K0
3 FUA4
2UB5 F8 7UA1-1 A5
3UA7
+2V5 2UB6 F8 7UA1-2 C5
IUA2 1K0
2UB7 F7 7UA2 A6
22K
1u0
1u0
3UA8
2UA5
2UA6
CUA0 +2V5-LVDS
IUB6
+5V5-TUN +5V-TUN 2UB8 D2 7UA3 C6
3U12 C3 7UA4 E5
7UA6 3U13 C3 7UA5 E8
BC817-25W
3U15-1 C8 7UA6 C3
3U12
330R
1%
3UB6-2
2 7
∗
+12V IUB3
C 3UB6-3
3
1K0 IUB2
6 6 +12V
+1V8
+3V3
∗ +3V3 C
3U15-2 C8
3U15-3 D8
7UA7-1 C3
1K0 +5V 1
3U15-1
8 +5V 1
3U16-1
8 7UA7-2 D2
3UB6-4
4 5
1K0
2 IU26 100R 100R 3U15-4 D8 7UC0 A8
3UB6-1 7UA3 3U15-2 3U16-2
3U16-1 C9
2UB0
IUB5
1 8 3 1 7UA7-1 PHD38N02LT 2 7 2 7 CUA0 B9
1u0
BC847BS(COL)
3U13
330R
1%
8
4 5 5 IUA7 5 LM833 FUA2 3UB0 IUA5 3U15-3 3U16-3
7 3 6 3 6
470R
7UA7-2 4 IUB4 6 100R 100R
3U16-3 D9 FUA1 A7
BC847BS(COL) 22R
3U16-4 D9 FUA2 D5
4
3U15-4 3U16-4
470R
470R
100n
FUA3 4 5 4 5
3U25-1 E3
7
2UA7
3UB7-3
3UB7-1
2UB8
2UA9
470R
22u
1n0
3U25-2 E3 FUA4 B9
D D
2UB1
2UB2
RES 1u0
1u0
3U25-3 E2 IU26 C3
2
2UA8
330p
IUA8
∗ NOT FOR 5000 SERIES 3U25-4 E2 IU29 E2
3U26-1 F3
3UA9
IU30 F3
1K0
ENABLE-1V8 3U26-2 F3 IUA1 A4
4
3U25-4
5 3U26-3 F3 IUA2 B5
3UB1 SENSE+1V2
100K RES RESERVED 3U26-4 F3 IUA3 A6
7
100K RES
IUA6 5UA0
3U25-2
1K0
3U25-3
3U29-1 E3 IUA4 A6
3 6
30R 3U29-2 E3 IUA5 C6
E E
2
2 7 1 5
100K RES
+5V5-TUN +5V-TUN
3U25-1
IN OUT
3UA0 A2 IUA8 D5
3UB2
4K7
470R 7UA4 3 4
3 6 +3V3 3
3U29-3
6
RES TS431AILT INH BP IUB1
3UA1 A3 IUA9 B6
8
RES 5 3 COM
RES IU30 470R A K 3UA2 B3 IUB0 F6
2UB7
2UB5
2UB6
100n
7U06-2 5 7U06-1 2
1u0
1u0
3U29-4 RES
BC847BS(COL) BC847BS(COL) 4 5 2 1 3UA3 B4 IUB1 E8
2
NC NC
3UB3
3U26-1 RES
3UA4 A4 IUB2 C2
1 8
3UA5 A6 IUB3 C3
4
470R
F 2
3U26-2
7
RES
3UB5 3UB4 IUB0 2UB3
F 3UA6 B5 IUB4 D3
470R +5V 3UA7 B6 IUB5 C2
100K 1K0 22n
+3V3 3
3U26-3
6
RES
2UB4
3UA8 B5 IUB6 B3
470R 3UA9 D5
3U26-4 RES 330p
4 5 RES 3UB0 D6
470R
3UB1 E6
3UB2 E6
1 2 3 4 5 6 7 8 9
4 2009-10-22
DC/DC
8204 000 8951
18770_523_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 157
DC/DC
DC/DC
B03E B03E
1 2 3 4 5 6 7 8
2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
2UD2 A3
2UD3 B3
A 5UD0 IUD0
A 2UD4 B5
+12V
30R +5V5-TUN 2UD5 B5
7UD0-1
2UD6 B6
2UD0
2UD1
2UD2
ST1S10PH
10u
10u
10u
6
A
SW
ENABLE-3V3-5V 2 7
IUD3 5UD1 IUD7
6UD0 FUD3 2UD7 B6
INH SW +5V
VIN
3u6 SS36 +1V1
2UD8 C2
RES 2UE9
5 3
220u 16V
RES 1n0
SYNC VFB 2UD9 C2
2UD3
2UD4
2UD5
2UD6
RES 2U27
100n
GND
22u
22u
22u
A P HS 2UE0 C3
9
6
2UE1 D5
7U05-1 2
2UE2 D6
B IUD6 2UD7
BC847BS(COL)
RES 1
IU27
B 2UE3 D6
7UD0-2 4n7 2UE4 D6
13
15
RES 3U06
ST1S10PH
10K
3UD2
3UD0
3UD1
2UE5 E4
68K
33K
1%
1%
10 VIA 12 120K
2UE6 E6
11
2UE7 F4
14
2UE8 F5
2UE9 B8
∗∗ 5UD3
3U06 B8
C +12V
IUD1
C 3U07 D8
30R
7UD1-1
3UD0 B5
2UD8
2UD9
2UE0
ST1S10PH 3UD1 B5
10u
10u
10u
6
A
SW
IUD4 5UD2 FUD2
ENABLE-3V3-5V 2
INH SW
7 +3V3 3UD2 B6
VIN
5 3
3u6 +1V1 3UD3 D5
220u 16V
SYNC VFB
3UD4 D5
2UE1
2UE2
2UE3
2UE4
RES 2U28
1% 100K
100n
GND
4n7
22u
22u
A P HS 3UD3
3UD5 D5
4
9
3 BC847BS(COL)
5 IU28
5UD0 A2
7U05-2
RES 5UD1 A5
D 7UD1-2
IUD2 4 D 5UD2 C5
13
15
5UD3 C2
RES 3U07
ST1S10PH
10K
3UD4
3UD5
33K
1M0
1%
10 VIA 12 6UD0 A6
11
6UD1 E4
7U05-1 B7
14
7U05-2 D7
7UD0-1 A4
∗
7UD2
LD1117DT25 7UD0-2 B4
6UD1 IUD5 7UD1-1 C4
E +5V 3
IN OUT
2 +2V5 E 7UD1-2 D4
S1D COM (∗) FOR 5000 SERIES ONLY
22u 16V
7UD2 E5
2UE5
2UE6
100n
FUD2 C5
FUD3 A7
7UD3 IU27 B8
LD1117DT33
IU28 D8
3 2
IN OUT +3V3 IUD0 A2
F COM F IUD1 C2
22u 16V
2UE7
2UE8
100n
IUD2 D5
1
IUD3 A5
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5
1 2 3 4 5 6 7 8
4 2009-10-22
DC/DC
8204 000 8951
18770_524_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 158
A 30R
5UM0
T 1.0A 63V
A
+5V
RES 30R
B B
C C
D D
E E
1 2 3 4 5 6 7 DC/DC
8204 000 8951
4 2009-10-22
18770_525_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 159
Fan Control
Fan-Control
B03G B03G
1 2 3 4 5 6 7 8 9
2US3 A7
+12V +12V
3US2 A3
+3V3 3US3 B3
8
3US4-1
3US4-1 A4
10K
7
+12V
3US5-2
3US2
2US3
100n
A A
10K
3US4-2 D4
10K
1
3 7US1-1
3US7 LM339P
9
2
FAN-CTRL1
1K0
8
14
IUS3 3US5-3
6 3
IUS6
3US4-3 C4
10K
IUT1 12
7US2
BC807-25W 3US4-4 C5
+12V
+3V3
IUS7
3US5-1 B6
3US9
3US5-2 A6
22R
8
3US5-1
+12V
10K
3US5-3 A5
3US3
10K
B 3 7US1-2
B
1
IUT2
11 LM339P
13
IUS4 3US5-4
5 4 BC807-25W
3US5-4 B5
FAN-CTRL2 10 7US3
12
10K IUS8
3US6 C6
IUS9
3US7 A4
3US6
3US9 B6
47R
FAN-DRV 7US1-1 A5
C
+3V3
C 7US1-2 B5
+12V 7US1-3 C5
5
IUS5
3US4-4
+12V
7US1-4 D5
10K
6
3US4-3
10K
7US1-3
7US2 A6
4
3
5 LM339P
2
3
TACH01 4
7US3 B6
12
+12V
9US0 D4
IUS0 D5
9US0
D D
RES
+12V
7
IUS3 A5
3US4-2
10K
7US1-4
3
7 LM339P
1
IUS4 B5
2
IUS0
TACH02 6
IUS5 C5
12
TACHO IUS6 A6
IUS7 B7
E E IUS8 B6
IUS9 B6
IUT1 A4
IUT2 B4
F F
1 2 3 4 5 6 7 8 9
4 2009-10-22
DC/DC
8204 000 8951
18770_526_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 160
Vdisp Switch
VDisp-Switch
B03H B03H
1 2 3 4 5 6 7 2UU0 C6
2UU1 C4
3UU0-1 C4
1 9UU0-1 8
RES 3UU0-2 C4
2 9UU0-2 7
RES 3UU0-3 C2
3 9UU0-3 6
RES
4 9UU0-4 5
3UU1 C4
A RES
1 9UU1-1 8
A 3UU2 D6
RES
2 9UU1-2
3UU3-1 C4
7
RES
3 9UU1-3 6
3UU3-2 C5
RES
4 9UU1-4 5
FUU0 3UU3-3 C6
RES 3UU3-4 C7
7UU0 B4
7UU1 B5
7UU2-1 C3
B 7UU0
B 7UU2-2 C3
SI4835DDY
RES 7UU1 +VDISP-INT 7UU3 C6
+12VD SI3441BDV
9UU0-1 A4
8
3UU3-1
1
9UU0-2 A4
4
PUMD12
47K RES
IUU3
9UU0-3 A4
7UU2-2 3UU1 2UU1 3UU3-2
5
47R IUU2
2
47K RES
7
9UU0-4 A4
IUU1 1u0
3
C
IUU0
7
3UU0-2
2
7UU3 RES
BC847BW C 9UU1-1 A4
1
47K 9UU1-2 A4
3UU0-1
6
47K
3 IUU4 3UU3-3 IUU5 3UU3-4
1 6 3 4 5
3UU0-3
2 7UU2-1
+3V3
9UU1-3 A4
8
+3V3-STANDBY 47K RES 47K RES
6 3 PUMD12
47K 2
9UU1-4 A4
2UU0
100n
1
FUU0 A5
IUU6
VDISP-SWITCH IUU0 C3
3UU2
4K7 RES
+3V3 IUU1 C4
D D IUU2 C5
LCD-PWR-ONn IUU3 C6
IUU4 C6
IUU5 C7
IUU6 D6
E E
1 2 3 4 5 6 7
4 2009-10-22
DC/DC / CLASS D
8204 000 8951
18770_527_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 161
Audio
B03A B03A
1 2 3 4 5 6 7 8 9
1735 E8 3D16 A5
1D38 E9 5D01 C7
+AVCC
1D50 E8 5D02 C7
3D09
7D03-1
BC847BS(COL) FD14
+24V-AUDIO-POWER 1D52 F8 5D03 E7
2D01 F7 5D04 C8
1
+24V-AUDIO-POWER
4R7
A A 2D02 F4 5D05 C8
2D06
220n
2D03 E3 5D07 A6
2
3D16 ID12
ID11 2D05 A5 5D08 A6
5D07
220R
5D08
220R
22K
2D06 A5 6D01 E3
10u 35V
GND-AUDIO
2D05
2D07 B5 7D03-1 A5
ID27 ID28
-AUDIO-R
FD01 2D28 ID14 2D24 2D08 B6 7D03-2 F5
2D09 C7 7D10-1 B6
220u 35V
220u 35V
1u0 47n
8
2D20
2D07
2D19
2D08
220n
220n
6
3D02-1
3D14-4
3D14-3
3D14-2
3D14-1
2D10 C7 7D10-2 E5
2D22
2D26
220n
220n
4K7
22K
22K
22K
22K
3D02-3
A-PLOP 6 3 2 7D15-1
2D11 C8 7D11-1 D2
B BC847BS(COL)
B
1
4K7
1
2D12 C8 7D11-2 D3
GND-AUDIO GND-AUDIO
2D13 F8 7D13-1 E1
2D14 E8 7D13-2 E2
7D10-1
FD03 2D29 ID15 2D23 TPA3120D2PWP 2D16 C4 7D15 B3
19
20
10
12
+AUDIO-L
1
3
1u0 47n AVCC L R 2D17 C4 7D15 C3
5
3
2D19 B6 CD10 D5
3D02-4
PVCC ID32 2D10
Φ 16
4K7
3D02-2 ID19 BSR ID10 5D02 5D05 2D12 RIGHT-SPEAKER
7 2 5 6
7D15-2
BC847BS(COL) R CLASS-D 15
220n
ID06
2D20 B5 FD01 B1
ID18 ID08
4
4K7 IN R 22u 220R 25V 220u
4 5 AUDIO AMP 2D21 D8 FD02 F8
L OUT
C 18
0
L
22
ID31 2D09
ID09 5D01 5D04 ID07 2D11 LEFT-SPEAKER C 2D22 B8 FD03 B1
17 GAIN 21 22u
1 BSL ID05 220R 25V 220u 2D23 B4 FD05 E8
GND-AUDIO 2D16 ID29 220n
11
VCLAMP 2D24 B4 FD06 E8
2D17 1u0 7
1u0 ID30 4
BYPASS
MUTE
2D26 B8 FD07 F4
2
AUDIO-MUTE-UP ID37 SD 2D27 D8 FD14 A5
PGND
ID38 AGND L R GND_HS
2D28 B2 ID05 C8
A-STBY
2D29 B2 ID06 C8
8
9
23
24
13
14
25
5
3D01-1 D3 ID07 C8
3D15-4
+3V3-STANDBY
8
8
4K7
3D01-1
3D10-4
3D10-3
3D10-2
3D10-1
D D ID08 C8
2D21
2D27
3D01-2 D3
220n
220n
6
47K
22K
22K
22K
22K
CD10
MAINS SWITCH DETECT
7D11-1 2 4 3D01-4 E2 ID09 C7
1
1
BC847BS(COL)
1 3
ID34
+3V3-STANDBY
GND-AUDIO 3D02 B3 ID10 C7
+3V3-STANDBY ID35
3D01-2 3D02 C3 ID11 A4
7D11-2 5 2 7 DETECT2
3D02 B4 ID12 A5
5
BC847BS(COL)
47K
3D01-4
6 4
47K
40
39
38
2D03
100p
GND-AUDIO 7D10-2
7D13-1 2 TPA3120D2PWP 3D04 E2 ID14 B3
4
BC847BS(COL) LEFT-SPEAKER
ID36 VIA
1 3
GND-AUDIO GND-AUDIO 26 37 3D06-1 F4 ID15 B3
ID39 +AVCC 27 36
VIA 3D06-2 F4 ID18 C5
V_NOM
3D15-1 3D15-2 ID13 6D01
E E
1D50
2D14
7D13-2 5 1 8 7 2 28 VIA VIA 35
10n
BC847BS(COL)
4
4K7 4K7 BZX384-C GND-AUDIO
29 34
GND-AUDIO 3D06-3 F3 ID19 C5
VIA
3D06-4 F3 ID27 B6
3D04
2K2
MAINS-OK
1735 1D38
3D09 A3 ID28 B6
30
31
32
33
FD05
GND-AUDIO GND-AUDIO 5D03 1 1
FD06
2 2 3D10-1 D8 ID29 C5
GND-AUDIO 220R 3 3
3D10-2 D8 ID30 C5
2D01
GND-AUDIO FD02
10n
GND-AUDIO 4
2D13
3 7D03-2 1735446-3
10n
BC847BS(COL) 1735446-4 3D10-3 D7 ID31 C6
3D06-4 FD07 3D06-2
LEFT-SPEAKER
4
5
3D10-4 D7 ID32 C6
100K 5 7 100K 2
4 3D14-1 B8 ID33 F4
F 8
3D06-1
1
ID33
RIGHT-SPEAKER
F 3D14-2 B8 ID34 D3
3D14-3 B7 ID35 D3
V_NOM
100K
1D52
GND-AUDIO
3D14-4 B7 ID36 E2
2D02
RIGHT-SPEAKER 3
3D06-3
6 3D15-1 E2 ID37 D4
100K 10u 3D15-2 E3 ID38 D5
GND-AUDIO
3D15-4 D5 ID39 E2
1 2 3 4 5 6 7 8 9 5 2010-02-19
CLASS D
8204 000 8951
18770_850_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 162
DC/DC
DC/DC
B03B B03B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A A
5U03 RES
30R
FU05 5U02 IU22
+12V
30R
7U02-1
2U24
2U23
2U25
2U19
2U20
10u
10u
10u
10u
1u0
SI4952DY
B IU10
7 8 B
2
12V/1V8 CONVERSION
1
3U11
3R3
2U21 FU02 5U00 FU03
+1V8
IU11 220p 3u6
3 3U23-3 6
2 3U23-2 7
1 3U23-1 8
22u
3U23-4
2U15
2U16
47R
47R
47R
47R
47u
7U02-2
SI4952DY
4
5 6
C IU09
4 IU23 C
2U17
1n0
IU15
7U01
SI4778DY
2U18
1n0
3U27 5 6 7 8
IU08 IU12
4
10R 1 2 3
D D
2U00
3U14
10u
3R3
3U04
3R3
2U22
IU06 2U02 IU07
IU05 IU13 220p
3U28
10R
100n
2U01
3U05
100n
3R3
7U04
7U03 SI4778DY
TPS53126PW
5 6 78
IU16
2 23 4
1 1 1 2 3
IU24 11 VBST DRVL 14 IU14
2 2
12V/1V1 CONVERSION
E ENABLE-1V8
3
10
1
2
EN DRVH
1
2
1
12 E
1n0 RES
+1V1 4 24 +1V1
1 1
STPS2L30A
+1V8 9 VO SW 13
6U00
2U14
5 22
3U24-4
3U24-3
3U24-2
3U24-1
1 1
3U20
2U12
2U13
8 VFB PGND 15
22u
47R
47R
47R
47R
10R
RES
47u
RES GND-SIG 2 2
7U00 3U02 IU01
BC847BW 21 7
1 1
3 22K 3U03 16 TRIP TEST 17
IU03 2 2
1 22K IU02 GND-SIG
GND-SIG
20 18 FU04 IU17
GND-SIG VIN V5FILT
2 19 IU25
VREG5
F F
2U11
1n0
+3V3-STANDBY 3U00 2U06
+1V1 GND
2U04
2U05
6
10u
1u0
10K 100n
IU18
10K
3U01
GND-SIG
2U09
2U10
1n0
1u0
GND-SIG
3U21 FU00
IU19 SENSE+1V1
100R 1%
3U17
1% 330R
2U29
100n
RES
G IU20 G
100p RES
3U19
2U08
3U18
5K6
1% 1K0
3U08 3U22
IU04
+1V8
330R 1% 1K0 1% IU21
RES 100p
1K0 1%
3U09
3U10
2U07
22K
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
2U00 D2 2U04 F4 2U08 G9 2U12 F11 2U16 C10 2U20 B14 2U24 B5 3U01 F1 3U05 E4 3U11 B6 3U19 G9 3U23-1 C9 3U24-1 F9 3U27 D5 5U02 B13 7U01 D8 7U04 E8 FU02 B9 FU06 E8 IU04 G3 IU08 D4 IU12 D7 IU16 E5 IU20 G9 IU24 E3
2U01 E3 2U05 F4 2U09 F9 2U13 F12 2U17 C9 2U21 C6 2U25 B12 3U02 F2 3U08 G2 3U14 D7 3U20 F11 3U23-2 C9 3U24-2 F9 3U28 D5 5U03 A13 7U02-1 B6 CU00 H7 FU03 C14 IU01 F3 IU05 D3 IU09 C6 IU13 D7 IU17 F9 IU21 H9 IU25 F4
2U02 D4 2U06 F1 2U10 F10 2U14 E14 2U18 D9 2U22 D8 2U29 G14 3U03 F3 3U09 H3 3U17 G10 3U21 G13 3U23-3 C9 3U24-3 F9 5U00 C10 6U00 E8 7U02-2 C6 FU00 G13 FU04 F4 IU02 F3 IU06 D3 IU10 B 6 IU14 E8 IU18 F9 IU22 B13
2U03 E2 2U07 H3 2U11 F9 2U15 C10 2U19 B12 2U23 B5 3U00 F1 3U04 D3 3U10 H3 3U18 G10 3U22 G2 3U23-4 C8 3U24-4 F8 5U01 E10 7U00 F1 7U03 E3 FU01 E14 FU05 B9 IU03 F1 IU07 D4 IU11 C6 IU15 C9 IU19 G10 IU23 C9
5 2010-02-19
DC/DC
8204 000 8951
18770_851_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 163
DC/DC
DC/DC
B03C B03C
1 2 3 4 5 6 7 8 9
1M95 E1 3U83-3 E5
1M99 C1 3U83-4 C5
1U40 E2 3U84 D2
2U41 B1 6U40 E3
2U42 C2 7U40-1 F4
2U43 D2 7U40-2 E4
2U44 D3 7U41-1 F4
A +3V3 +3V3-STANDBY A 2U45 D3 7U41-2 F5
LED-2
2U46 D3 7U42 B5
2U47 E1 7U43 B3
RES 10K
RES 10K
3U74
3U75
+5V +3V3-STANDBY 2U48 F1 7U48-1 C6
9U41
IU43 2U49 F1 7U48-2 E6
2U50 F1 9U41 B5
RES 10K
3U68
3U69
10K
LED-1
IU44
2U51 D1 9U42 B4
3U41 LED2 LED2 3U59
IU45 2U52 D1 FU07 C3
B ∗ optionally 1M99 is a 9 pin connector
9U42
RES
10K RES 10K RES
B 2U53 D2 FU48 C1
7U42 RES
BC847BW
+3V3 2U54 F2 FU49 C1
2U41 RES IU47 3U70 LED1 3U53
2U55 F3 FU50 C1
∗
7U43 LED1
BC847BW
10K 10K
2U68 E1 FU51 C1
100p
2U71 D5 FU52 C3
+12VD
2U72 D1 FU53 C2
1M99
FU48 2U42 3U41 B5 FU54 C2
1 3U81 IU56
2
FU49
1u0 +3V3 3U42 C3 FU55 C1
FU50
3 10K 3U43 C3 FU56 D1
4
C 5
FU51
FU52
3U45
LAMP-ON
IU64
C 3U44 C3 FU57 D1
6 100R
7
FU53 3U42 BACKLIGHT-PWM_BL-VS
3U82 3U45 C3 FU58 E1
8
FU55 3U64
100R
3U43 BACKLIGHT-BOOST
1K0 RES 3U53 B6 FU59 E1
9 7U48-1
10 1K0 FU54 100R FU07 3U83-4 BC857BS(COL) 3U56 D3 FU60 E1
3U44 BACKLIGHT-PWM-ANA-DISP 4 5 ENABLE-3V3-5V
6
11 3U59 B6 FU61 E1
RES 1K0
RES 100p
RES 100p
12 100R 100K
100p
2U51
2U52
2U53
3U65
1n0
10n
FU62 E1
10n
3U60-1 F5
1n0
3U56 IU41
100p
1
1-1735446-2
3U83-1
3U60-2 F4 FU63 E1
2U72
100K
+3V3
2
10K
2U44
2U45
2U46
2U43
2U71
100n
3U60-3 E5 FU64 F1
RES
IU55
8
POWER-OK 3U60-4 F5 FU65 F1
D 3U66
BL-SPI-SDO
D 3U61 E5 FU66 F1
FU56
RES 100R 3U67 3U62-1 F4 FU67 F1
FU57 BL-SPI-CSn +3V3-STANDBY
100R RES 3U84 3U62-2 E3 FU68 F1
BL-SPI-CLK
FU72 F4
3
FU74
100R RES
3U62-3 E4
3U71
STANDBY
7U48-2
3U62-4 E3 FU73 E5
2U68 100R BC857BS(COL) 3U63 F5 FU74 D1
5
5
1u0 3U83-3 7 2
3 6
10K
BC847BPN(COL)
2U47
IU48
4
100K IU40 100K 3U65 D2 IU41 D5
3U66 D2 IU43 B5
4
10n
E 1M95
+3V3-STANDBY
5
E
2
3
FU58 3U67 D2 IU44 B5
3U62-2
1 3U60-3 FU73
FU59 3 6 ENABLE-1V8
10K
IU61 IU45 B4
2
FU60 3U68 B3
BZX384-C6V2
3 22K
RES 10K
6
3U61
3U62-3
4
6U40
FU62
10K
5 1U40 IU49
6
FU63
+12V 3U70 B4 IU48 E4
6
2
FU64 7U40-1
3U71 D3 IU49 E3
3
3U60-2
FU67 1
1K0
7U41-2
7
MAINS-OK 3 BC847BS(COL)
11 IU63
5
2U55
3U60-1 ENABLE-3V3n
100p RES
3U80
100p RES
1-1735446-1 5 8 1
4K7
22K
2U49
2U50
2U54
4 IU52
10n
10n
3U76 F2 IU56 C3
4
+3V3-STANDBY
8 1
10K 6
3K3
3U63
3U80 F4 IU57 F6
RES 10K
7U41-1
BC847BS(COL) 2
1 3U81 C3 IU61 E4
3U82 C5 IU62 F4
3U83-1 D6 IU63 F3
3U83-2 E5 IU64 C6
1 2 3 4 5 6 7 8 9
5 2010-02-19
DC/DC
8204 000 8951
18770_852_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 164
DC/DC
DC/DC
B03D B03D
1 2 3 4 5 6 7 8 9
2UA0 A5 3UB1 E6
2UA1 A4 3UB2 E6
RESERVED 2UA2 B5 3UB3 F6
+12V +3V3 2UA3 B5 3UB4 F5
+2V5-REF 7UC0
LF25ABDT * 2UA4 A7 3UB5 F5
3K3 1%
1K0
2UA0
3UA4
+12V
A 3UA1
1
IN OUT
3
A 2UA5 B6 3UB6-1 C2
100n 7UA2
PHD38N02LT COM 2UA6 B7 3UB6-2 C2
2UA4
1u0
7UA1-1
* 2UA7 D4 3UB6-3 C2
3UA0
8
IUA1 3 LM833
2K2
IUA3 IUA4
2
3UA5
1 1
2
2UA8 D5 3UB6-4 C2
100n
FUA0
3
22R
2UA1
FUA1 2UA9 D5 3UB7-1 D3
3K3 1%
+2V5-REF
4
3UA3
2UA3
47K
1
3UA2 2UB0 C7 3UB7-2 D2
1n0
7UA0
TS2431 2UB1 D6 3UB7-3 D2
2UA2
K
IUA9
330p
2UB2 D7 3UB7-4 C2
R
2
2UB3 F6 5UA0 E8
3UA6
A
B B
1K0
3 FUA4
2UB4 F6 7U06-1 F2
3UA7
+2V5
2UB5 F8 7U06-2 F1
IUA2 1K0
2UB6 F8 7UA0 B2
22K
1u0
1u0
3UA8
2UA5
2UA6
CUA0 +2V5-LVDS
IUB6
+5V5-TUN +5V-TUN 2UB7 F7 7UA1-1 A5
2UB8 D2 7UA1-2 C5
7UA6 3U12 C3 7UA2 A6
BC817-25W
3U13 C3 7UA3 C6
3U12
330R
3UB6-2 1%
+12V 2 7 IUB3
3U15-1 C8 7UA4 E5
C 3UB6-3
3
1K0 IUB2
6 6 +12V
+1V8
∗
3U15-1 +3V3 ∗
3U16-1 +3V3 C 3U15-2 C8 7UA5 E8
1K0 +5V 1 8 +5V 1 8
3UB6-4
4 5
1K0
2 IU26 100R 100R 3U15-3 D8 7UA6 C3
3UB6-1 7UA3 3U15-2 3U16-2
3U15-4 D8 7UA7-1 C3
2UB0
1 8 IUB5 3 1 7UA7-1 PHD38N02LT 2 7 2 7
1u0
BC847BS(COL)
3U13
330R
1%
8
4 5 5 IUA7 5 LM833 FUA2 3UB0 IUA5 3U15-3 3U16-3
7 3 6 3 6
470R
7UA7-2 4 6
3U16-2 C9 7UC0 A8
IUB4 22R 100R 100R
BC847BS(COL)
3U16-3 D9 CUA0 B9
4
3U15-4 3U16-4
470R
470R
100n
FUA3 4 5 4 5
3U16-4 D9 FUA0 A2
7
2UA7
3UB7-3
3UB7-1
2UB8
2UA9
470R
22u
1n0
3U25-1 E3 FUA1 A7
D D
2UB1
2UB2
3U25-2 E3 FUA2 D5
RES 1u0
1u0
2
2UA8
330p
IUA8
∗ NOT FOR 5000 SERIES 3U25-3 E2 FUA3 D7
3U25-4 E2 FUA4 B9
3UA9
1K0
ENABLE-1V8
3U26-1 F3 IU26 C3
3U25-4 3U26-2 F3 IU29 E2
4 5
100K RES
3UB1 SENSE+1V2
RESERVED 3U26-3 F3 IU30 F3
7
100K RES
1K0
3U25-3
3 6
30R 3U29-1 E3 IUA2 B5
E E
2
2 7 1 5
100K RES
IN OUT
3UB2
4K7
470R 7UA4
3 6 3
3U29-3
6
RES TS431AILT
3
INH BP
4 IUB1 3UA0 A2 IUA6 E5
+3V3
8
2UB7
2UB5
2UB6
100n
7U06-2 5 7U06-1 2
1u0
1u0
BC847BS(COL) BC847BS(COL) 4
3U29-4
5
RES
2 1 3UA2 B3 IUA8 D5
2
NC NC
3UB3
4 1 470R REF 4K7 3UA3 B4 IUA9 B6
3U26-1 RES
1 8 3UA4 A4 IUB0 F6
4
470R
3UA5 A6 IUB1 E8
F 2
3U26-2
7
RES
3UB5 3UB4 IUB0 2UB3
F 3UA6 B5 IUB2 C2
470R +5V
3
3U26-3
6
RES 100K 1K0 22n 3UA7 B6 IUB3 C3
+3V3 2UB4
470R 3UA8 B5 IUB4 D3
4
3U26-4
5
RES 330p
RES
3UA9 D5 IUB5 C2
470R 3UB0 D6 IUB6 B3
1 2 3 4 5 6 7 8 9
5 2010-02-19
DC/DC
8204 000 8951
18770_853_100331.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 165
DC/DC
DC/DC
B03E B03E
1 2 3 4 5 6 7 8
2U27 B8
2U28 D8
2UD0 A2
2UD1 A2
2UD2 A3
2UD3 B3
A 5UD0 IUD0
A 2UD4 B5
+12V
30R +5V5-TUN 2UD5 B5
7UD0-1
2UD6 B6
2UD0
2UD1
2UD2
ST1S10PH
10u
10u
10u
6
A
SW
ENABLE-3V3-5V 2 7
IUD3 5UD1 IUD7
6UD0 FUD3 2UD7 B6
INH SW +5V
VIN
3u6
2UD8 C2
SS36 +1V1
RES 2UE9
5 3
220u 16V
2UD9 C2
RES 1n0
SYNC VFB
2UD3
2UD4
2UD5
2UD6
RES 2U27
100n
GND
22u
22u
22u
A P HS 2UE0 C3
9
6
2UE1 D5
7U05-1 2 2UE2 D6
B IUD6 2UD7
BC847BS(COL)
RES 1
IU27
B 2UE3 D6
7UD0-2 4n7 2UE4 D6
13
15
RES 3U06
ST1S10PH
10K
3UD2
2UE5 E4
3UD0
3UD1
68K
33K
1%
1%
10 VIA 12 120K 2UE6 E6
11 2UE7 F4
14
2UE8 F5
2UE9 B8
3U06 B8
∗∗ 5UD3 3U07 D8
C +12V
IUD1
C 3UD0 B5
30R
7UD1-1
3UD1 B5
2UD8
2UD9
2UE0
ST1S10PH
10u
10u
10u
6
A
SW
2 7
IUD4 5UD2 FUD2 3UD2 B6
ENABLE-3V3-5V INH SW +3V3
VIN
3u6
3UD3 D5
5 3 +1V1
3UD4 D5
220u 16V
SYNC VFB
2UE1
2UE2
2UE3
2UE4
RES 2U28
1% 100K
100n
GND
4n7
22u
22u
4 A P HS 3UD3 3UD5 D5
8
9
3 BC847BS(COL)
5UD0 A2
IU28
7U05-2 5 5UD1 A5
RES
D IUD2 4 D 5UD2 C5
7UD1-2 5UD3 C2
13
15
RES 3U07
ST1S10PH
10K
6UD0 A6
3UD4
3UD5
33K
1M0
1%
10 VIA 12
6UD1 E4
11 7U05-1 B7
14
7U05-2 D7
7UD0-1 A4
7UD0-2 B4
∗
7UD2
LD1117DT25
6UD1
7UD1-1 C4
IUD5
E +5V 3
IN OUT
2 +2V5 E 7UD1-2 D4
S1D COM
(∗) FOR 5000 SERIES ONLY 7UD2 E5
22u 16V
2UE5
2UE6
100n
7UD3 F5
(∗∗) NOT FOR 5000 SERIES
1
FUD2 C5
FUD3 A7
IU27 B8
7UD3
LD1117DT33 IU28 D8
IUD0 A2
3 2 +3V3
IN OUT IUD1 C2
F COM F IUD2 D5
22u 16V
2UE7
2UE8
100n
IUD3 A5
1
IUD4 C5
IUD5 E4
IUD6 B6
IUD7 A5
1 2 3 4 5 6 7 8 5 2010-02-19
DC/DC
8204 000 8951
18770_854_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 166
A 30R
5UM0
T 1.0A 63V
A
+5V
RES 30R
B B
C C
D D
E E
1 2 3 4 5 6 7
5 2010-02-19
DC/DC
8204 000 8951
18770_855_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 167
Fan Control
Fan-Control
B03G B03G
1 2 3 4 5 6 7 8 9
+12V +12V 2US3 A7
3US2 A3
+3V3 3US3 B3
8
3US4-1 A4
3US4-1
10K
3US4-2 D4
7
+12V
3US5-2
3US2
2US3
100n
A A
10K
10K
3US4-3 C4
1
3 7US1-1
3US7
9 LM339P 3US4-4 C5
2
IUS3 3US5-3 IUS6
14 6 3
FAN-CTRL1
1K0
8
3US5-1 B6
10K
IUT1
7US2 3US5-2 A6
12 BC807-25W
+12V 3US5-3 A5
IUS7
+3V3
3US5-4 B5
3US6 C6
3US9
22R
8
3US7 A4
3US5-1
+12V
10K
3US9 B6
3US3
10K
B 3 7US1-2
B 7US1-1 A5
1
11 LM339P
IUS4 3US5-4 7US1-2 B5
IUT2 13 5 4 BC807-25W
FAN-CTRL2 10 7US3
10K IUS8 7US1-3 C5
12
IUS9
7US1-4 D5
7US2 A6
7US3 B6
3US6
47R
9US0 D4
FAN-DRV IUS0 D5
IUS3 A5
+3V3
C C IUS4 B5
+12V IUS5 C5
5
IUS5 IUS6 A6
3US4-4
+12V
10K
IUS7 B7
6
3US4-3
IUS8 B6
10K
7US1-3
4
3
5 LM339P
2 IUS9 B6
3
4
TACH01 IUT1 A4
12
IUT2 B4
+12V
9US0
D D
RES
+12V
7
3US4-2
10K
7US1-4
3
7 LM339P
1
2
IUS0
TACH02 6
12
TACHO
E E
F F
1 2 3 4 5 6 7 8 9
5 2010-02-19
DC/DC
8204 000 8951
18770_856_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 168
Vdisp Switch
VDisp-Switch
B03H B03H
1 2 3 4 5 6 7
2UU0 C6
1 9UU0-1 8
2UU1 C4
RES 3UU0-1 C4
2 9UU0-2 7
RES 3UU0-2 C4
3 9UU0-3 6
RES 3UU0-3 C2
4 9UU0-4 5
A RES A 3UU1 C4
1 9UU1-1
RES
8 3UU2 D6
2 9UU1-2 7 3UU3-1 C4
RES
3 9UU1-3 6 3UU3-2 C5
RES
4 9UU1-4 5
FUU0
3UU3-3 C6
RES
3UU3-4 C7
7UU0 B4
7UU1 B5
7UU2-1 C3
B 7UU0
B 7UU2-2 C3
SI4835DDY
RES 7UU1 +VDISP-INT 7UU3 C6
+12VD SI3441BDV 9UU0-1 A4
9UU0-2 A4
3UU3-1
4
8 1
9UU0-3 A4
47K RES
5
PUMD12
7UU2-2 3UU1 2UU1
2
3UU3-2
7
IUU3 9UU0-4 A4
47R IUU1 1u0 IUU2 47K RES 9UU1-1 A4
3 7UU3 RES
IUU0
C 7
3UU0-2
2 BC847BW C 9UU1-2 A4
1
47K 9UU1-3 A4
3UU0-1
6
47K
3 IUU4 3UU3-3 IUU5 3UU3-4
1 6 3 4 5
3UU0-3
2 7UU2-1
+3V3 9UU1-4 A4
8
+3V3-STANDBY 47K RES 47K RES
PUMD12
6
47K
3 2 FUU0 A5
2UU0
100n
1
IUU0 C3
VDISP-SWITCH IUU6 IUU1 C4
3UU2
+3V3
IUU2 C5
4K7 RES IUU3 C6
D D IUU4 C6
LCD-PWR-ONn IUU5 C7
IUU6 D6
E E
1 2 3 4 5 6 7
5 2010-02-19
DC/DC / CLASS D
8204 000 8951
18770_857_100331.eps
100331
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 169
Analogue Externals A
B04A B04A
1 2 3 4 5 6 7 8 9 10 11 12 13 1E00 A4
1E01-1 D5
3E78 F2
3E79 F2
IE22 B2
IE23 C2
1E01-2 H5 3E80 C10 IE48 G2
1E02 C13 3E82 D10 IE51 G10
1E12 D4 3E83 E10 IE52 H2
1E18 F4 3E84 E10 IE53 D1
1E19 F4 3E85 F10 IE54 E1
1E22 H4 3E86 F10 IE55 F1
RESET-AVPIP 1E23 I4 3EA1 D6 IE56 E9
1E24 I11 3EA2 D6 IE57 F9
3E63-1 FE60
AP-SCART-OUT-R 1E25 I4 3EA7-1 A7 IE59 E8
FE70 IEC0 IE67 1 8 1E26 G11 3EA7-2 H13 IE60 E6
3E37-4 3EA7-1 2EA4 100R
AP-SCART-OUT-R AUDIO-OUT-L
CDS4C12GTA
1E27 H11 3EA7-3 H13 IE61 E6
A 4 100R 5 8 470R 1 1u0 16V A 1E31 B4 3EA7-4 B7 IE62 H10
2E29
RES 6E10
1E45
2E50
100p
100p
12V
CDS4C12GTA
FEA0
7E01-1 6 AP-SCART-OUT-L 1E45 A11 3EB1 E6 IE67 A8
2E01
RES 6E01
1E00
2E87
100p
100p
1E46 B11 3EB3 E6 IE68 B8
12V
IEC1
2
1E47 C11 3EB6-1 G6 IE70 E7
1 1E48 C11 3EB6-2 H13 IE89 D7
PUMH7
IE20 FE61
1E49 D11 3EB6-3 H13 IE90 D7
AUDIO-IN2-R 3E11-1
1E52 F11 3EB6-4 G6 IE91 G6
IEC2 2EA5 IE68 1 8
3EA7-4 1K0 1E53 C4 3EB9-1 H6 IE92 G7
AUDIO-OUT-R
CDS4C12GTA
IE22 FE71
AUDIO-IN1-R
3E07-4
5 470R 4 1E54 D4 3EB9-2 I13 IE93 H7
1u0 16V
1E55 E4 3EB9-3 I13 IE94 H6
2E30
RES 6E08
1E46
2E51
100p
100p
12V
4 1K0 5 FEA1
7E01-2 3
CDS4C12GTA
AP-SCART-OUT-R 1E56 E11 3EB9-4 I6 IE96 G6
B FEC8 B 1E57 E11 5E73 D2 IEC0 A7
2E06
RES 6E03
1E31
2E88
100p
100p
12V
5
1EP2 F13 5E74 E2 IEC1 A6
+3V3
4
FE62
2E01 A3 5E76 F2 IEC2 B7
PUMH7 AP-SCART-OUT-L 3E63-4
2E04 D3 5E77 D10
4 5
100R 2E06 B3 5E78 E10
CDS4C12GTA
2E10 C3 5E79 F10
3E25
10K
3E37-1 FE72
2E32
RES 6E12
1E47
2E70
100p
100p
AP-SCART-OUT-L 2E12 F4 5E80 E8
12V
1 100R 8 2E13 G11 6E01 A3
3E24
A-PLOP
CDS4C12GTA
2E14 F4 6E02 E11
2K2
2E15 D4 6E03 B3
RES 6E07
2E10
1E53
2E90
100p
100p
12V
CDS4C12GTA
1E02 2E19 F12 6E10 A11
IE23 3E07-1 * EU
2E31
RES 6E14
1E48
2E82
100p
100p
AUDIO-IN1-L 2E24 G2 6E12 C11
12V
1 1
1K0 8 2E29 A10 6E14 C11
CDS4C12GTA
RES 6E09
1E54
2E91
100p
100p
12V
3EA2
SCART1 4
1R0
CDS4C12GTA
1u8 18R 2E41 H12 6E28 F3
2E89
2E92
150p
150p
RES 6E24
1E49
2E16
2E44 I4 6E29 H3
100p
(AV1) 5
12V
IE53 5E73 IE90
D AV1-B
1u8
BEC3 3E75
1E01-1 6
D 2E50 A12 6E30 I3
CDS4C12GTA
2EB1
3EA1
2E79
2E80
RES 6E23
1E12
2E15
9E01
9E02
150p
150p
100p
100n
1 7
1K0
12V
CDS4C12GTA
RES 3
IE13 3E16 12K FE64
9
2E75 H4 6E36 G11
2E76 I4 6E37 H11
3E18 2
RES 6E02
3E17
1E56
2E33
100p
4K7
YPBPR2-SYNCIN2
12V
IE61
2EB3
4 4 10 2E77 G12 7E01-1 A6
39K
2E99
1u0
* EU 7E06-2 12
IE18 3E31 3E83 18R FE66 11 2E78 I12 7E01-2 B6
AV1-STATUS 5 5 11
5p6 10 2E79 D1 7E04 H6
1
6 7E06-1
CDS4C12GTA
12K FE73 9
6 3 BC847BPN(COL) IE70 5E80 5E78 12 2E80 D2 7E05 G6
2E81 IE59 CVBS-MON-OUT1 IE56 BEC1 8
E AP AV4-Y 3E84
E
3E32
RES 6E22
1E55
2E18
100p
2 2E81 E7 7E06-1 E7
4K7
12V
FE74 7
YPBPR1-SYNCIN1 9E52 9E53 7 IE60 13
CDS4C12GTA
2u2 10u 1u8 18R 6 2E82 C12 7E06-2 E6
2
1 3EB1 2
2E97
2E98
150p
2E94
1
39p
18p
3E76 18R FE75 5 2E83 F1 7E09-1 H2
RES 6E34
3E19
2E93
1E57
2E17
150p
100p
8 BC847BPN(COL) 14
18K
12V
820R 4
2E84 F2 7E09-2 G10
1 3EB3 2
FE67 3
330R
9 15 2E85 F1 9E01 D6
IE54 5E74 BEC4 3E77 FE80 2
1
AV1-G IE08 RES 1 2E86 F2 9E02 D7
9E08 10 16
CDS4C12GTA
2E84
150p
150p
1E18
2E14
100p
11 17
12V
CDS4C12GTA
IE14 IE57 5E79 BEC2 3E86 2E89 D9 9E07 F4
RES 6E35
1E52
2E19
100p
9E07 12 AV4-PR 18
12V
2E90 C4 9E08 F4
RES
150p
YPBPR1-PR 9E10 13 19
2E96
F F
2E95
2E92 D10 9E10 F4
150p
9E54 9E55 IE16 +5V
3E78 18R 9E05 14 20 2E93 E10 9E50 D1
IE55 5E76 BEC5 3E79 FE81 2E94 E9 9E51 D2
AV1-R 15 RES +3V3
21
2E95 F10 9E52 E1
CDS4C12GTA
2E86
2E74
150p
150p
100n
16 2E96 F9 9E53 E2
RES 6E28
1E19
2E12
100p
12V
100n 16V
2E98 E8 9E55 F2
3E73
2E13
4K7
IE17 IE96 IE91
RES 9E06 18 1 3EB6-1 8 2E99 E8 BEC0 D10
FE83 470R 2EA4 A7 BEC1 E10
19
7E05
IE92 3E45 IE51 2EA5 B7 BEC2 F10
CVBS-OUT-SC1 AV2-BLK 3
+3V3 FE84 BC847BW 2EB1 D6 BEC3 D2
* EU 20 68R
G G 2EB3 E7 BEC4 E2
4 3EB6-4 5
7E09-2 5
470R
CDS4C12GTA
FE76
3E44
2E24
100n
4
4K7
3E61
RES 6E36
1E26
RES 2E77
100p
75R
12V
FE85
3E07-3 H13 FE60 A12
MRC-021V-29 PC RES 3E07-4 B3 FE61 B12
3E48 3E37-2
IE48 3E11-1 B11 FE62 B12
AV1-BLK 6 2 100R 7
1E01-2 68R 3E11-2 I13 FE63 D12
7E09-1 2 MT 3E37-3 3E11-3 I13 FE64 D12
+5V
PUMH7 23 22 3 6 3E11-4 C11 FE66 E12
CDS4C12GTA
1E22
RES 2E75
100p
MRC-021V-29 PC
75R
12V
CDS4C12GTA
27R 3E17 E10 FE68 D12
2 1K0 7
H H 3E18 E7 FE70 A5
RES 6E37
1E27
2E41
100n
100p
12V
2E73 3E07-3
3E19 E7 FE71 B4
3EB9-1 IE94 3 1K0 6 3E24 C7 FE72 C4
IE52 1 8
3E62 3EA7-2 2 3EB6-2 7 3E25 C13 FE73 E4
AV1-CVBS 470R
7E04 IE93 2 470R 7 3E31 E3 FE74 E4
CDS4C12GTA
1E25
2E44
100p
3 6
CDS4C12GTA
3E37-1 C3 FE76 G12
12V
68R
470R
RES 6E31
1E24
RES 2E78
100p
12V
3E63-2 2 3EB9-2 7 3E37-3 H13 FE78 H12
2 7 3E37-4 A3 FE79 F13
100R 470R
3E63-3 3E39 H10 FE80 E4
CVBS-OUT-SC1 3 3EB9-3 6
I RES 3 6
I 3E43 H2 FE81 F4
CDS4C12GTA
1E23
RES 2E76
100p
3E45 G7 FE83 G4
12V
68R
2 7
1K0 3E48 G7 FE84 G4
3E11-3 3E49 I7 FE85 G5
3 1K0 6 3E52 H7 FEA0 A7
3E61 G11 FEA1 B7
3E62 H2 FEC8 B13
3E63-1 A11 IE05 D10
3E63-2 I13 IE08 E5
3E63-3 I13 IE13 D6
3E63-4 B11 IE14 F5
3E73 G10 IE16 F5
1 2 3 4 5 6 7 8 9 10 11 12 13 3E74 D2 IE17 G5
3E75 D2 IE18 E3
1X02
REF EMC HOLE 3E76 E2 IE20 B10
3E77 E2 IE21 C10
4 2009-10-22
CLASS D
8204 000 8952
18770_528_100118.eps
100218
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 170
Analogue Externals B
Analogue Externals B
B04B B04B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1E03 B3
1E04 C3
1E07 A12
1E08-1 B3
1E08-2 E3
1E08-3 D3
1E09 F3
1E28 B4
A A 1E29 D4
1E37 F4
SPDIF out 1E38 G4
YPBPR 1E39 C4
1E07 1E42 E4
IE15 5E06
YKC21-5598 FE54 EU 9E29
IE71 3E87 IE72
AV3-Y SPDIF-OUT
FE59 CON_JACK 1E43 B4
2 1 1E44 B10
CDS4C12GTA
1E08-1 18R 30R
CDS4C12GTA
YPBPR1-SYNCIN1
1E75 H5
2E27
1E43
RES 6E40
2E22
1E44
RES 6E46
100p
1 2 YKB11-0946V
12V
12V
10p
YELLOW
AP 9E04 3E88 IE73
AV2-CVBS
FE41 1E76 I5
B 27R B 1ECB I4
2E20 H4
FE51 EU IE74 3E89 IE75
MTJ-032-21B-41 NI FE 9E57 AV3-PB 2E21 I4
2
CDS4C12GTA
1E03 18R
YPBPR1-PB 2E22 B9
2E67
RES 6E51
100p
1E28
1 2E27 B4
12V
2E35 F6
2E36 F4
FE48 2E37 G4
MTJ-032-21B-41 NI FE EU 9E58 IE76 3E90 IE77
AV3-PR
2
2E38 G6
C 1E04 18R
C
CDS4C12GTA
YPBPR1-PR 2E39 D4
2E68
RES 6E52
100p
1E39
1
2E40 E4
12V
FE42 2E67 B4
2E68 C4
2E71 E5
2E72 D5
YPBPR AUDIO 3E14 H6
3E15 H6
YKC21-5598 3E97
AUDIO-IN3-R
3E20 G5
D 6 D 3E21 F5
CDS4C12GTA
1E08-3 FE50 1K0 IE31
3E87 B6
2E39
1E29
RES 6E06
2E72
5
100p
100p
RED 12V
3E88 B6
FE43
3E89 B6
3E90 C6
FE49 3E96 IE29
YKC21-5598 AUDIO-IN3-L 3E96 E5
4
CDS4C12GTA
1E42
2E71
3
100p
100p
RES 6E38
12V
WHITE
6E06 D5
E E 6E15 H5
6E16 I5
6E19 F5
6E20 G5
VGA ( OR DVI ) AUDIO 6E38 E5
6E40 B5
5
4 IE09
6E46 B11
1E09 FE02 3E21
2 AUDIO-IN4-L 6E51 B4
CDS4C12GTA
1K0 6E52 C4
3
F F
V_NOM
2E36
1E37
6E19
2E35
100p
7 9E04 B5
12V
1n0
MSJ-035-10A B AG PPO 8
1 9E29 B5
9E57 B5
FE01
9E58 C5
BE20 H6
FE03 3E20 IE10 BE21 H6
AUDIO-IN4-R
BE22 I4
CDS4C12GTA
1K0
FE01 F4
V_NOM
2E37
1E38
6E20
2E38
100p
12V
1n0
FE02 F5
G G FE03 G5
FE41 B12
FE42 C4
FE43 D4
FE44 H5
SVHS IN FE45 H5
FE44 BE20 3E14 FE46 I4
C-SVHS
FE48 C4
CDS4C12GTA
18R
FE49 E4
2E20
1E75
100p
RES 6E15
12V
6
H H FE50 D4
2 FE51 B4
4 FE54 B4
FE45 BE21 3E15
Y-SVHS FE59 B10
3
CDS4C12GTA
27R IE09 F6
2E21
1E76
100p
RES 6E16
1 IE10 G6
12V
MDC-066H-A LF
FE46
1ECB
BE22
IE15 B9
IE29 E6
IE31 D6
I I IE71 B6
IE72 B7
IE73 B7
IE74 B6
IE75 B7
IE76 C6
IE77 C7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
4 2009-10-22
ANALOG I/O
8204 000 8952
18770_529_100118.eps
100118
2010-Jun-18 back to
div. table
Circuit Diagrams and PWB Layouts Q552.1E LA 10. EN 171
Ethernet + Service
Ethernet + Service
B04C B04C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1E06 A13
1E70 B3
1E85 A11
1E86 A11
5E08 IE07 1N00 G7
+3V3 +3V3-ET-ANA 2E48 B5
30R
IE49 3E53-1 FE56 2E49 B5
2 3E53-2 7
2E62
2E63
2E66
8 1
100n
100n
TXD1-MIPS
A A 2E52 B3
10u
47R 47R 1E06
IE50 3E53-3 FE57 UART 2E53 B4
RXD1-MIPS 4 3E53-4 5 6 3 2
3 SERVICE 2E54 B3
BZX384-C5V1
+3V3-ET-ANA +3V3 47R 47R 1 CONNECTOR 2E55 B3
BZX384-C5V1
YKB21-5157V
6E43
6E44
1E85
1E86
FE58 2E56 H2
IE32 IE38 IE06 2E57 H2
3E30 IE33 2E58 H3
2E59 H4
2E52
2E53
2E48
100n
100n
2E49
10u
4n7
1M0
1E70
+3V3 2E60 H5
B NX3225GA
B 2E62 A3
25M 2E63 A3
3E66 RES
3E67 RES
2E54
10p
10p
7E10-1
2E66 A3
27
12
LAN8710A-EZK
1
2E55 3E22-1 F2
3E33
CR 1A 2A IO
10K
10K
10K
VDD
5
CLKIN 3E22-2 F3
1
4 XTAL 31
2
RX
P
30
ETH-RXP 3E22-3 F2
N ETH-RXN
IE26
RESET-ETHERNETn 19
RST
3E22-4 F2
29 ETH-TXP
ETH-RXD(0) 11 TX
P
28 ETH-TXN
3E26 F5
0 N
ETH-RXD(1) 10 MODE 3E30 B3
C ETH-RXD(2) 9
8
1
RMIISEL TXCLK
20 ETH-TXCLK C 3E33 B2
ETH-RXD(3) PHYAD2
3E69 10K 26
3E70 RES
RXD<0:3> RXDV ETH-RXDV 3E34 D6
IE63
ETH-COL RES 10K 15
COL RXER
13 ETH-RXER 3E35 D6
9E43 3E71 10K 3E64 10K
RES
CRS_DV RXD4 +3V3 3E40 D5
MODE2 0 IE64 RES
21
PHYAD
1
7
3E65 10K
ETH-RXCLK 3E51 E1
ETH-TXEN TXEN RXCLK +3V3
RES
3E53-1 A10
ETH-TXD(0) 22 3 ETH-REGOFF
ETH-TXD(1) 23
0 REGOFF
10K 3E34 3E68 10K 3E53-2 A9
1 1 +3V3
ETH-TXD(2) 24
2 TXD
LED
2
2 RES ETH-INTSEL 3E53-3 A10
ETH-TXD(3) 25 10K 3E72 3E35 10K
D ETH-TXER 18
3
4
INTSEL
14 9E42
RES
+3V3
D 3E53-4 A9
INT CRS ETH-CRS 3E64 C6
TXER
RBIAS
32 3E65 D6
ETH-MDC 17 IE39 3E66 B2
1%
MDC
3E40
12K1
ETH-MDIO 16
MDIO
3E67 B2
3E51 1K5 +3V3 VSS
3E68 D6
33
3E69 C2
7E10-2
LAN8710A-EZK 3E70 C1
34 VIA 36
35 37 3E71 C3
E E 3E72 D6
3E95-1 F3
3E95-2 F3
3E95-3 F4
3E95-4 F4