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-- Create Date: 00:46:42 08/23/2008

-- Design Name:
-- Module Name: dither_pixel - Behavioral
-- Project Name:
-- Tool versions: Xilinx ISE 9.1
--
-- Test VHDL for the article ART001 :
-- "Augmenting perceived color depth with basic hardware".
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dither_pixel is
Port (
x_LSB : in STD_LOGIC;
y_LSB : in STD_LOGIC;
frame : in STD_LOGIC;

componentR : in STD_LOGIC_VECTOR (7 downto 0);

componentG : in STD_LOGIC_VECTOR (7 downto 0);
componentB : in STD_LOGIC_VECTOR (7 downto 0);
outR : out STD_LOGIC_VECTOR (5 downto 0);
outG : out STD_LOGIC_VECTOR (5 downto 0);
outB : out STD_LOGIC_VECTOR (5 downto 0)
);
end dither_pixel;

architecture Behavioral of dither_pixel is

begin
--
-- Conversion from 24 Bit 888 to
-- 24 Pseudo Bit with RGB 666 as physical output.
--
-- Perform 2 stage dithering.
-- - One static stage.
-- - One dynamic stage as described in the document.
--
process(x_LSB, y_LSB, frame, componentR, componentG, componentB)
variable dither : STD_LOGIC;
variable add : STD_LOGIC;
variable addR : STD_LOGIC_VECTOR(8 downto 0);
variable addG : STD_LOGIC_VECTOR(8 downto 0);
variable addB : STD_LOGIC_VECTOR(8 downto 0);
begin
-- Generated table (Spatial 1 Bit Dither)
-- 01
-- 10
dither := (x_LSB xor y_LSB);

--
-- Compute Temporal dither Value for current pixel
--
if (dither = frame) then
add := '1';
 else
add := '0';
end if;

-- 8 Bit -> Spatial Dither 7 Bit -> Temporal Dither 6 Bit.

-- We could have seperated the calculation in two blocks.
-- Original 8 bit + spatial dither -> Temporary 7 Bit + Temporal dither
-> Get 6 bit.
-- But this can be reduced inside the same addition.
--
-- We use one more bit to detect the overflow.
addR := ('0' & componentR) + ("0000000" & add & dither);
addG := ('0' & componentG) + ("0000000" & add & dither);
addB := ('0' & componentB) + ("0000000" & add & dither);

-- Output result. (and perform fix for overflow as described in the

document)
outR <= addR(7 downto 2) or
(addR(8)&addR(8)&addR(8)&addR(8)&addR(8)&addR(8));
outG <= addG(7 downto 2) or
(addG(8)&addG(8)&addG(8)&addG(8)&addG(8)&addG(8));
outB <= addB(7 downto 2) or
(addB(8)&addB(8)&addB(8)&addB(8)&addB(8)&addB(8));
end process;
end Behavioral;