-- All logic gates

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- a,b are switch inputs

-- sel is 3-bit selection mode switch
-- c is output LED

entity logicgatesvg is
Port ( a : in std_logic;
b : in std_logic;
sel : in std_logic_vector(0 to 2);
c : out std_logic);
end logicgatesvg;

architecture Behavioral of logicgatesvg is

begin
process (a,b,sel)
begin
if (sel = "000") then
c <= not a;
elsif (sel = "001") then
c <= not b;
elsif (sel = "010") then
c <= a and b;
elsif (sel = "011") then
c <= a nand b;
elsif (sel = "100") then
c <= a or b;
elsif (sel = "101") then
 c <= a nor b;
elsif (sel = "110") then
c <= a xor b;
end if;
end process;
end Behavioral;
-- 8 to 3 Encoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- x is the 8-bit input switch

-- y is the 3-bit output on LED

entity encoder83vg is
Port ( x : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end encoder83vg;

architecture Behavioral of encoder83vg is

begin
y <= "000" when x = "00000001" else
"001" when x = "00000010" else
"010" when x = "00000100" else
"011" when x = "00001000" else
"100" when x = "00010000" else
"101" when x = "00100000" else
"110" when x = "01000010" else
"111" when x = "10000000";

end Behavioral;
-- 3 to 8 Decoder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- x is 3-bit switch input

-- y is 8-bit output

entity decoder38vg is
Port ( x : in std_logic_vector(2 downto 0);
y : out std_logic_vector(7 downto 0));
end decoder38vg;

architecture Behavioral of decoder38vg is

begin
y <= "00000001" when x = "000" else
"00000010" when x = "001" else
"00000100" when x = "010" else
"00001000" when x = "011" else
"00010000" when x = "100" else
"00100000" when x = "101" else
"01000000" when x = "110" else
"10000000" when x = "111";
end Behavioral;
-- 8 to 1 Multiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity multiplexer81vg is
Port ( S0,S1,S2,S3,S4,S5,S6,S7 : in std_logic;
sel : in std_logic_vector(2 downto 0);
op : out std_logic);
end multiplexer81vg;

architecture Behavioral of multiplexer81vg is

begin
op <= S0 when sel = "000" else
S1 when sel = "001" else
S2 when sel = "010" else
S3 when sel = "011" else
S4 when sel = "100" else
S5 when sel = "101" else
S6 when sel = "110" else
S7 when sel = "111";
end Behavioral;
-- 1 to 4 Demultiplexer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity demultiplexer14vg is
Port ( ip : in std_logic;
sel : in std_logic_vector(1 downto 0);
op : out std_logic_vector(3 downto 0));
end demultiplexer14vg;

architecture Behavioral of demultiplexer14vg is

begin
process (ip,sel)
begin
if (ip = '0') then
op <= "0000";
elsif sel = "00" then
op <= "0001";
elsif sel = "01" then
op <= "0010";
elsif sel = "10" then
op <= "0100";
elsif sel = "11" then
op <= "1000";
else op <= "1111";
end if;
end process;
end Behavioral;
-- Comparator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparatorvg is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
less : out std_logic;
equal : out std_logic;
greater : out std_logic);
end comparatorvg;

architecture Behavioral of comparatorvg is

begin
process (a,b)
begin
if (a < b) then
less <= '1';
equal <= '0';
greater <= '0';
elsif (a = b) then
less <= '0';
equal <= '1';
greater <= '0';
else
less <= '0';
equal <= '0';
greater <= '1';
end if;
end process;
end Behavioral;
-- Full adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladdervg is
Port ( a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum : out std_logic;
cout : out std_logic);
end fulladdervg;

architecture Behavioral of fulladdervg is

begin
sum <= a xor b xor cin;
cout <= (a and b) or (b and cin) or (a and cin);
end Behavioral;
-- 4-bit Arithmetic logic unit (ALU)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity aluvg is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
sel : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end aluvg;

architecture Behavioral of aluvg is

begin
process (a,b,cin,sel)
begin
case sel is
-- arithmetic operations
when "0000" => y <= a;
when "0001" => y <= a + 1;
when "0010" => y <= a - 1;
when "0011" => y <= b;
when "0100" => y <= b + 1;
when "0101" => y <= b - 1;
when "0110" => y <= a + b;
when "0111" => y <= a + not b +1;
when "1000" => y <= a + b + cin;
-- logical operations
when "1001" => y <= not a;
when "1010" => y <= not b;
when "1011" => y <= a and b;
 when "1100" => y <= a nand b;
when "1101" => y <= a or b;
when "1110" => y <= a nor b;
when "1111" => y <= a xor b;
when others => null;
end case;
end process;
end Behavioral;
-- D-flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity flipflopdvg is
Port ( data_in : in std_logic;
clock : in std_logic;
data_out : out std_logic);
end flipflopdvg;

architecture Behavioral of flipflopdvg is

begin
process (data_in, clock)
begin
-- clock rising edge
if (clock = '1' and clock'event) then
data_out <= data_in;
end if;
end process;
end Behavioral;
-- RS-flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity flipfloprsvg is
Port ( r : in std_logic;
s : in std_logic;
q : inout std_logic;
qbar : inout std_logic);
end flipfloprsvg;

architecture Behavioral of flipfloprsvg is

begin
q <= (s nand qbar);
qbar <= (r nand q);
end Behavioral;
-- JK-flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity flipflopjkvg is
Port ( clock : in std_logic;
j : in std_logic;
k : in std_logic;
reset : in std_logic;
q : out std_logic;
qbar : out std_logic);

end flipflopjkvg;

architecture Behavioral of flipflopjkvg is

-- define useful signal here
signal state : std_logic;
signal input : std_logic_vector(1 downto 0);

begin
-- combine inputs into vector
input <= j & k;
p: process (clock, reset) is
begin
if (reset = '1') then
state <= '0';
elsif (rising_edge (clock)) then

-- compare to truth table

case (input) is
when "11" => state <= not state;
when "10" => state <= '1';
 when "01" => state <= '0';
when others => null;
end case;
end if;
end process;

-- concurrent statements
q <= state;
qbar <= not state;
end Behavioral;
-- Toggle flipflop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity flipfloptogglevg is
Port ( clk : in std_logic;
rst : in std_logic;
op : out std_logic);
end flipfloptogglevg;

architecture Behavioral of flipfloptogglevg is

begin
process (clk, rst)
variable S1: std_logic;
begin
if (rst = '1') then
S1:= '0';
elsif (rst = '0') then
if rising_edge (clk) then
S1 := not S1;
end if;
end if;
op <= S1;
end process;

end Behavioral;
-- 4-bit binary counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity binarycountervg is
Port ( clock : in std_logic;
clear : in std_logic;
count : in std_logic;
q : out std_logic_vector(3 downto 0));
end binarycountervg;

architecture Behavioral of binarycountervg is

signal pre_q : std_logic_vector(3 downto 0);

begin
-- behaviour describing the counter
process (clock, count, clear)
begin
if (clear = '1') then
pre_q <= pre_q - pre_q;
elsif (clock = '1' and clock'event) then
if count = '1' then
pre_q <= pre_q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
q <= pre_q;

end Behavioral;