HP Pavilion DV5 - AMD (QT8)

1 2 3 4 5 6 7 8
PCB STACK UP
QT8 SYSTEM DIAGRAM 01
DDRII-SODIMM1 DDRII 667/800 MHz
LAYER 1 : TOP AMD Lion CPU THERMAL
LAYER 2 : IN1 PAGE 7,8 Sabie SENSOR
A LAYER 3 : IN2 Griffin 14.318MHz A
S1G2 Processor PAGE 5
LAYER 4 : VCC DDRII-SODIMM2 DDRII 667/800 MHz
638P (uPGA)/35W
LAYER 5 : IN3 PAGE 7,8 PAGE 3,4,5,6 CPU_CLK
LAYER 6 : BOT NBGFX_CLK CLOCK GEN
NBGPP_CLK ICS9LPRS476AKLFT-->HP
SBLINK_CLK SLG8SP626VTR-->HP
HT3 RTM880N-795 -->HP
PAGE 2
PCI-Express 16X
PCI-E HDMI 10 PCI-E WLAN Card x1
PAGE 23 ATI M82-S
PAGE 36
Cable VGA X1 X1 X3 NORTH BRIDGE for
Discrete
Docking RJ-45 Express Mini PCI-E
CRT 11 TV-TUNER Card x1
LAN RX781 / RS780MN only
CIR/Pwr btn Realtek Card Card PAGE 24 PAGE 36
SPDIF Out PCIE-LAN A12 64 Bit,DDR2*4 7
(NEW CARD) (Wireless LAN/TV
Express Card x1
B Stereo MIC RTL8102E/8111C
TUNNER) 21mm X 21mm, 528pin BGA LVDS M82-SCE A11 PAGE 33 B
Headphone Jack (10/100/GagaLAN)

Side port
PAGE 23
4
USB Port PAGE 31,32 PAGE 33 PAGE 36 PAGE 17,18,19 Cable Docking x1
VOL Cntr PAGE 8,9,10,11, 20,21,22 PAGE 37
PAGE 37 256mb RAM
for UMA only
RJ45
ALINK X4 PAGE 8 SBSRC_CLK
PAGE 31
SYSTEM CHARGER(ISL6251A) USB2.0
PAGE 44
TWO SATA - HDD
SATA0,1 150MB 1,8,9 5 2 6 3
USB2.0 Ports Blueflame Webcam Fingerprint Flash Media Touch Screen
PAGE 33 SOUTH BRIDGE for UMA only for Discrete
SYSTEM POWER ISL6236IRZA-T X3 PAGE 30 PAGE 30 X1 PAGE 30 PAGE 30
RTS5158 only
PAGE 38 SB700 A12
SATA - CD-ROM
SATA0 150MB PAGE 25
21mm X 21mm, 528pin BGA PCIE BUS JMICRON
DDR II SMDDR_VTERM PAGE 33 JMD380 for
1.8V/1.8VSUS(TPS51116REGR) 4.5W(Ext)
Discrete
C PAGE 41
E-SATA
SATA4 150MB 4.3W(Int)
only C
Azalia
PAGE 30 PAGE 12,13.14.15.16 PAGE 27
VCCP +1.1V AND +1.2V(MAX8717)
SMBUS
PAGE 39
Accelerometer
IDT
LIS3LV02DL PAGE 28 LPC 92HD71B7
VGACORE(1.1V~1.2V)Oz8118 MDC CONN PAGE 27
PAGE 42 Keyboard PAGE 34
PAGE 29
Touch Pad PAGE 34 ENE KBC IEEE1394
connect for
Memory
CardReader
Discrete
CPU CORE ISL6265A CIR (AUDIO CONN) KB3926 Cx AUDIO
only
PAGE 40 PAGE 27 Amplifier
TPA6017A2 PAGE 26 PAGE 25
SMBUS TABLE Capacitive Sense PAGE 35

PAGE 28
Clock gen/Robson/TV tuner SW PAGE 34
SB--SCL0/SD0 /DDR2/DDR2 thermal/Accelerometer +3V
D D
Digital MIC AUDIO CONN Audio
epress card (Phone/ MIC) Conn
Wlan Card +3VS5 PAGE 30 PAGE 27 PAGE 28
FAN SPI PROJECT : QT8
EC --SCL/SD Battery charge/discharge +3VPCU Quanta Computer Inc.
PAGE 37 PAGE 35 Size Document Number Rev
EC--SCL2/SD2 VGA thermal/system thermal +3V
Custom 1A
Block Diagram
NB5/RD5
Date: Tuesday, February 19, 2008 Sheet 1 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1
+1.2V L49
600 ohms@100Mhz
60 ohm, 0.5A
BLM18PG181SN1D(180,1.5A)_6
C523
10U/6.3V_8
C518
0.1U/10V_4
C496
0.1U/10V_4
C527
+1.2V_CLKVDDIO
C521
0.1U/10V_4 0.1U/10V_4
C476
0.1U/10V_4
C515
0.1U/10V_4
CLOCKS name
NBGFX_CLKP
NBGFX_CLKN
RX780
RP64 STUFF
RS780
RP64 STUFF
Clock pin function
to NB for VGA reference clock 02

EXT_GFX_CLKP RP66 STUFF RP66 NC to M82-S external reference clock -RX780 only
EXT_GFX_CLKN
DCR: 0.5 ohm NBGPP_CLKP to NB for RX780 for PCIEX2 interface reference clock only
D +3V_CLKVDD D
600 ohms@100Mhz NBGPP_CLKN RP70 STUFF RP70 NC RS780 is internal share with AC-LINK clock,RS780 not need
60 ohm, 0.5A
+3V L51 +3V_CLKVDD
BLM18PG181SN1D(180,1.5A)_6
SBLINK_CLKP to NB for AC-LINK reference clock
C541 C468 C473 C512 C522 C508 C500 C474 C471 C469 SBLINK_CLKN RP72 STUFF RP72 STUFF
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
CLK_VGA_27M_SS R653,R656,R612 R653,R656,R612 To M82-S 27Mhz - RX780 only

Place very CLK_VGA_27M_NSS STUFF NC
+3V_CLKVDD close to
C/G
L42
BLM18PG181SN1D(180,1.5A)_6
+3V_CLK_VDDA
U10A Place within 0.5" R196 *261_4
Del RP for TP on PV
of CLKGEN
C464 C482 49 56 CPUCLKP RP43 4 3 *0_4P2R_4 CPUCLKP
VDDA CPUKG0T_LPRS CPUCLKP 3
10U/6.3V_8 0.1U/10V_4 48 55 CPUCLKN 2 1 CPUCLKN
GNDA CPUKG0C_LPRS CPUCLKN 3
+3V_CLK_VDDA 62 VDDREF ATIG0T_LPRS 33 NBGFX_CLKP RP54 4 3 *0_4P2R_4 NBGFX_CLKP NBGFX_CLKP 10 to NB for external Graphics
66 32 NBGFX_CLKN 2 1 NBGFX_CLKN
GNDREF ATIG0C_LPRS
31 EXT_GFX_CLKP RP53 4 3 *0_4P2R_4 EXT_GFX_CLKP
NBGFX_CLKN 10 reference clock
ATIG1T_LPRS EXT_GFX_CLKP 17
C470 69 VDD48 ATIG1C_LPRS 30 EXT_GFX_CLKN 2 1 EXT_GFX_CLKN
EXT_GFX_CLKN 17 to M82-S -RX780 only
0.1U/10V_4 29 26
VDDATIG ATIG2T_LPRS T196
54 VDDCPU ATIG2C_LPRS 25 T84
61 VDDHTT
38 40 PCIE_MINI2_CLKP RP48 4 3 *0_4P2R_4 PCIE_MINI2_CLKP
VDDSB_SRC SB_SRC0T_LPRS PCIE_MINI2_CLKP 36
17 VDDSRC SB_SRC0C_LPRS 39 PCIE_MINI2_CLKN 2 1 PCIE_MINI2_CLKN
PCIE_MINI2_CLKN 36 to TV TUNER CARD
C +3V_CLKVDD 44 35 CLK_PCIE_CARD RP55 4 3 *0_4P2R_4 CLK_PCIE_CARD C
VDDSATA SB_SRC1T_LPRS CLK_PCIE_CARD 26
3 VDDDOT SB_SRC1C_LPRS 34 CLK_PCIE_CARD# 2 1 CLK_PCIE_CARD#
CLK_PCIE_CARD# 26 to PCIE-CARD READER
53 23 NBGPP_CLKN_R Del RP52 for NBGPP CLK
VDDCPU_IO SRC0T_LPRS T59
28 22 NBGPP_CLKN_L
VDDATIG_IO SRC0C_LPRS T62
37 21 PCIE_NEW_CLKP RP51 4 3 *0_4P2R_4 PCIE_NEW_CLKP
VDDSB_SRC_IO SRC1T_LPRS PCIE_NEW_CLKP 33
12 VDDSRC_IO1 SRC1C_LPRS 20 PCIE_NEW_CLKN 2 1 PCIE_NEW_CLKN
PCIE_NEW_CLKN 33 to EPRESS CARD
+1.2V_CLKVDDIO 18 16 PCIE_MINI1_CLKP RP49 4 3 *0_4P2R_4 PCIE_MINI1_CLKP
VDDSRC_IO2 SRC2T_LPRS PCIE_MINI1_CLKP 36
SRC2C_LPRS 15 PCIE_MINI1_CLKN 2 1 PCIE_MINI1_CLKN
PCIE_MINI1_CLKN 36 to WLAN
14 SBLINK_CLKP RP47 4 3 *0_4P2R_4 SBLINK_CLKP
SRC3T_LPRS SBLINK_CLKP 10
C466 33P/50V_4 CG_XIN 72 GND48 SRC3C_LPRS 13 SBLINK_CLKN 2 1 SBLINK_CLKN
SBLINK_CLKN 10 to NB for AC-LINK reference clock
27 10 SBSRC_CLKP RP45 4 3 *0_4P2R_4 SBSRC_CLKP
GNDATIG1 SRC4T_LPRS SBSRC_CLKP 12
2
6 GNDDOT SRC4C_LPRS 9 SBSRC_CLKN 2 1 SBSRC_CLKN

SBSRC_CLKN 12 to SB
Y2 52 8 PCIE_LAN_CLKP RP44 4 3 *0_4P2R_4 PCIE_LAN_CLKP
GNDCPU SRC5T_LPRS PCIE_LAN_CLKP 31
14.318MHZ 58 GNDHTT SRC5C_LPRS 7 PCIE_LAN_CLKN 2 1 PCIE_LAN_CLKN
PCIE_LAN_CLKN 31 to PCIE-LAN
47 46
1
GNDSATA SRC6T/SATAT_LPRS
C465 33P/50V_4 CG_XOUT 36 GNDSB_SRC SRC6C/SATAC_LPRS 45 SI-1 Modified --remove to ROBSON
11 5 CLK_VGA_27M_SS R527 33_4 OSC_SPREAD
GNDSRC1 SRC7T_LPRS/27Mhz_SS OSC_SPREAD 18
19 GNDSRC2 SRC7C_LPRS/27Mhz_NS 4 CLK_VGA_27M_NSS R215 75/F_4
EVGA-XTALI 18 SSIN - for M82 - 3.3V level input
R490 100/F_4 X_TALIN --for M82 -1.8V level input
HTT0T/66M_LPRS 60
CG_XIN 67 59 NBHTREFCLK0P R193 0_4 NBHT_REFCLKP
X1 HTT0C/66M_LPRS NBHT_REFCLKP 10
CG_XOUT 68 71 NBHTREFCLK0N R194 0_4 NBHT_REFCLKN
X2 48MHz_0 NBHT_REFCLKN 10
70 CLK_48M_CR_L R201 33_4 CLK_48M_CR
48MHz_1 CLK_48M_CR 25
CLK_PD# 57 CLK48MUSB R192 33_4 CLK_48M_USB Ra
PD# CLK_48M_USB 13
can remove MOSFET level shift REF0/SEL_HTT66 65 SEL_HT66 R186 158/F_4
SB/clock gen / DDR2 is 3.3V/S0 64 SEL_SATA
REF1/SEL_SATA T58
PCLK_SMB 1 63 SEL_27 R184 1 2 90.9/F_4
power level 6,7,13,28,36 PCLK_SMB
PDAT_SMB SMBCLK REF2/SEL_27 T167 EXT_NB_OSC 10
6,7,13,28,36 PDAT_SMB 2 SMBDAT
24 CLKREQ0# Rb
B CLKREQ0# EXT_NWD_CLK_REQ# B
CLKREQ1# 51 EXT_NWD_CLK_REQ# 33
50 CLKREQ2#
SB_SRC_SLOW# CLKREQ2# CLKREQ3#
14 CHIPSET_PCIE_SLOW_SB# 1 2 41 SB_SRC_SLOW# CLKREQ3# 43 RX780 RS780
D17 *CH501H-40PT L-F 42 CLKREQ4#
CLKREQ4#
Clock chip has internal serial 1.8V 1.1V
terminations
when driven lowSB_SRC clocks slow only supported with SLG8SP626VTR
for differencial pairs, external resistors Ra 82.5R 158R
to reduced setpoint custom CG IC 73 THERMAL GND 77
are
74
eGND73 eGND77
76
reserved for debug purpose. Rb 130R 90.9R
eGND74 eGND76
75 eGND75 eGND78 78
+3V RES CHIP 130 1/16W +-1%(0402)L-F -->CS11302FB15
U10B RES CHIP 158 1/16W +-1%(0402) -->CS11582FB00
C952 *10P/50V_4 EXT_NB_OSC R756 *8.2K_4 CLKREQ0# SLG8SP626VTR RES CHIP 90.9 1/16W +-1%(0402) -->CS09092FB15
R757 *8.2K_4 CLKREQ2# +3V_CLKVDD RES CHIP 82.5 1/16W +-1%(0402) -->CS08252FB11
C953 *10P/50V_4 CLK_48M_USB R758 *8.2K_4 CLKREQ3#
R759 *8.2K_4 CLKREQ4# ICS ICS9LPR476BKLFT--AJRS4760000
C954 *10P/50V_4 CLK_48M_CR
if use clock SLG SLG8SP626VTR--AJ006260000
C955 *10P/50V_4 EVGA-XTALI +3V
request pin , need RTL RTM880N-795-- AJ008800000
to pull Hi for
C956 *10P/50V_4 OSC_SPREAD
default sttting * default R189 R195 EXT_NWD_CLK_REQ# 8.2K_4 R219
*8.2K_4 8.2K_4
66 MHz 3.3V single ended HTT clock CLK_PD# 8.2K_4 R204
1 SEL_27
SI-1 modified -- reserve for EMT SEL_HTT66 SEL_SATA SB_SRC_SLOW# 8.2K_4 R261
A 0* 100 MHz differential HTT clock SEL_HT66 A
100 MHz non-spreading differential SRC clock

SEL_SATA 1 R203 R202
8.2K_4
0* 100 MHz spreading differential SRC clock *8.2K_4
SEL_27 1* 27MHz non-spreading singled clock PROJECT : QT8

0 100 MHz spreading differential SRC clock
Quanta Computer Inc.
RS780M/RX780M
Size Document Number Rev
Custom 1A
Clock Generator
NB5/RD5
5 4 3 2 1
5 4 3 2 1
BLM21PG221SN1D(220,100M,2A)_8 CPU_THERMDC R569 0_4
03
W/S= 15 mil/20mil H_THRMDC 5
+2.5V +CPUVDDA CPU_THERMDA R567 0_4
H_THRMDA 5
L36 CPU CLK CPU_LDT_RST# 300_4 R142 +1.8V
+1.2V +1.2V_VLDT C416 LS0805-100M-N C392 C368 C363 CPUCLKP CPU_LDT_STOP# 300_4 R140
2 CPUCLKP
10U/6.3V_8 4.7U/6.3V_6 0.22U/6.3V_4 3300P/50V_4 CPUCLKN CPU_PWRGD 300_4 R144
2 CPUCLKN
R474 0_8 CPU_LDT_REQ#_CPU 300_4 R563 SI-2 modified --
Keep trace from resisor to CPU within 0.6" confirm AMD R563
R473 0_8 +1.2V_VLDT +CPUVDDA
keep trace from caps to CPU within 1.2" U31D need to stuff
U31A W/S= 15 mil/20mil
+CPUVDDA F8 M11
C739 4.7U/6.3V_6 +1.2V_VLDT +1.2V_VLDT 4.7U/6.3V_6 C840 CPUCLKIN R137 169/F_4 CPUCLKIN# +CPUVDDA VDDA1 KEY1
D1 VLDT_A0 HT LINK VLDT_B0 AE2 F9 VDDA2 KEY2 W18
C744 4.7U/6.3V_6 +1.2V_VLDT D2 AE3 +1.2V_VLDT 0.22U/6.3V_4 C818
D C758 0.22U/6.3V_4 +1.2V_VLDT VLDT_A1 VLDT_B1 +1.2V_VLDT 180P/50V_4 C829 CPUCLKP C408 3900P/25V_4 CPUCLKIN CPU_SVC_R D
D3 VLDT_A2 VLDT_B2 AE4 A9 CLKIN_H SVC A6
C753 180P/50V_4 +1.2V_VLDT D4 AE5 +1.2V_VLDT CPUCLKN C409 3900P/25V_4 CPUCLKIN# A8 A4 CPU_SVD_R
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_NB_CPU_CAD_H0 E3 AD1 HT_CPU_NB_CAD_H0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 10,12 CPU_LDT_RST# RESET_L
HT_NB_CPU_CAD_L0 E2 AC1 HT_CPU_NB_CAD_L0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_NB_CPU_CAD_H1 E1 AC2 HT_CPU_NB_CAD_H1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_NB_CPU_CAD_L1 F1 AC3 HT_CPU_NB_CAD_L1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_NB_CPU_CAD_H2 L0_CADIN_L1 L0_CADOUT_L1 HT_CPU_NB_CAD_H2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8
HT_NB_CPU_CAD_L2 G2 AA1 HT_CPU_NB_CAD_L2 CPU_SIC AF4
L0_CADIN_L2 L0_CADOUT_L2 5 CPU_SIC SIC
HT_NB_CPU_CAD_H3 G1 AA2 HT_CPU_NB_CAD_H3 SideBand Temp sense I2C 5 CPU_SID AF5
HT_NB_CPU_CAD_H[15..0] L0_CADIN_H3 L0_CADOUT_H3 CPU_SID SID
HT_NB_CPU_CAD_L3 H1 AA3 HT_CPU_NB_CAD_L3 CPU_ALERT AE6 W7 CPU_THERMDC
8 HT_NB_CPU_CAD_H[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 CPU_ALERT ALERT_L THERMDC
HT_NB_CPU_CAD_H4 J1 W2 HT_CPU_NB_CAD_H4 W8 CPU_THERMDA
HT_NB_CPU_CAD_L[15..0] HT_NB_CPU_CAD_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CPU_NB_CAD_L4 R128 44.2/F_4 CPU_HTREF0 THERMDA
8 HT_NB_CPU_CAD_L[15..0] K1 L0_CADIN_L4 L0_CADOUT_L4 W3 R6 HT_REF0
HT_NB_CPU_CAD_H5 L3 V1 HT_CPU_NB_CAD_H5 +1.2V_VLDT R135 44.2/F_4 CPU_HTREF1 P6
HT_NB_CPU_CLK_H[1..0] HT_NB_CPU_CAD_L5 L0_CADIN_H5 L0_CADOUT_H5 HT_CPU_NB_CAD_L5 place them to CPU within 1.5" HT_REF1
8 HT_NB_CPU_CLK_H[1..0] L2 L0_CADIN_L5 L0_CADOUT_L5 U1
HT_NB_CPU_CAD_H6 L1 U2 HT_CPU_NB_CAD_H6 F6 W9 VDDIO_FB_H
HT_NB_CPU_CLK_L[1..0] L0_CADIN_H6 L0_CADOUT_H6 40 CPU_VDD0_RUN_FB_H VDD0_FB_H VDDIO_FB_H VDDIO_FB_H 41
HT_NB_CPU_CAD_L6 M1 U3 HT_CPU_NB_CAD_L6 E6 Y9 VDDIO_FB_L
8 HT_NB_CPU_CLK_L[1..0] L0_CADIN_L6 L0_CADOUT_L6 40 CPU_VDD0_RUN_FB_L VDD0_FB_L VDDIO_FB_L VDDIO_FB_L 41
HT_NB_CPU_CAD_H7 N3 T1 HT_CPU_NB_CAD_H7
HT_NB_CPU_CTL_H[1..0] HT_NB_CPU_CAD_L7 L0_CADIN_H7 L0_CADOUT_H7 HT_CPU_NB_CAD_L7
8 HT_NB_CPU_CTL_H[1..0] N2 L0_CADIN_L7 L0_CADOUT_L7 R1 40 CPU_VDD1_RUN_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_RUN_FB_H 40
HT_NB_CPU_CAD_H8 E5 AD4 HT_CPU_NB_CAD_H8 AB6 G6
HT_NB_CPU_CTL_L[1..0] L0_CADIN_H8 L0_CADOUT_H8 40 CPU_VDD1_RUN_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_RUN_FB_L 40
HT_NB_CPU_CAD_L8 F5 AD3 HT_CPU_NB_CAD_L8
8 HT_NB_CPU_CTL_L[1..0] HT_NB_CPU_CAD_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CPU_NB_CAD_H9 CPU_DBRDY
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_L9 F4 AC5 HT_CPU_NB_CAD_L9 CPU_TMS AA9 E10 CPU_DBREQ# R775 300/F_4
8 HT_CPU_NB_CAD_H[15..0] HT_NB_CPU_CAD_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CPU_NB_CAD_H10 CPU_TCK TMS DBREQ_L
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 AC9 TCK +1.8VSUS
HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_L10 H5 AB3 HT_CPU_NB_CAD_L10 CPU_TRST# AD9 AE9 CPU_TDO
8 HT_CPU_NB_CAD_L[15..0] HT_NB_CPU_CAD_H11 L0_CADIN_L10 L0_CADOUT_L10 HT_CPU_NB_CAD_H11 CPU_TDI TRST_L TDO
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
HT_CPU_NB_CLK_H[1..0] HT_NB_CPU_CAD_L11 H4 AA5 HT_CPU_NB_CAD_L11
8 HT_CPU_NB_CLK_H[1..0] L0_CADIN_L11 L0_CADOUT_L11
HT_NB_CPU_CAD_H12 K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CPU_NB_CAD_H12
T7
CPUTEST23 AD7 TEST23 TEST28_H J7 CPUTEST28H
T40 SI-2
HT_CPU_NB_CLK_L[1..0] HT_NB_CPU_CAD_L12 HT_CPU_NB_CAD_L12 CPUTEST28L
8 HT_CPU_NB_CLK_L[1..0] K4 L0_CADIN_L12 L0_CADOUT_L12 W5 TEST28_L H8 T43 modified for
HT_NB_CPU_CAD_H13 L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CPU_NB_CAD_H13 SI-2 modified for AMD T42
CPUTEST18 H10 TEST18 AMD sighting
C HT_CPU_NB_CTL_H[1..0] HT_NB_CPU_CAD_L13 HT_CPU_NB_CAD_L13 CPUTEST19 CPUTEST17 C
8 HT_CPU_NB_CTL_H[1..0] M5 L0_CADIN_L13 L0_CADOUT_L13 V3 sighting update T45 G9 TEST19 TEST17 D7 T48 update
HT_NB_CPU_CAD_H14 M3 V5 HT_CPU_NB_CAD_H14 E7 CPUTEST16
HT_CPU_NB_CTL_L[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T46
HT_NB_CPU_CAD_L14 M4 U5 HT_CPU_NB_CAD_L14 +1.8VSUS R141 510/F_4 CPUTEST25H E9 F7 CPUTEST15
8 HT_CPU_NB_CTL_L[1..0] L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T44
HT_NB_CPU_CAD_H15 N5 T4 HT_CPU_NB_CAD_H15 R108 510/F_4 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T49
HT_NB_CPU_CAD_L15 P5 T3 HT_CPU_NB_CAD_L15
L0_CADIN_L15 L0_CADOUT_L15 R776 300/F_4 CPUTEST21 AB8 TEST21 TEST7 C3
HT_NB_CPU_CLK_H0 J3 Y1 HT_CPU_NB_CLK_H0 CPUTEST20 AF7 K8
L0_CLKIN_H0 L0_CLKOUT_H0 T116 TEST20 TEST10
HT_NB_CPU_CLK_L0 J2 W1 HT_CPU_NB_CLK_L0 R777 300/F_4 CPUTEST24 AE7
HT_NB_CPU_CLK_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CPU_NB_CLK_H1 CPUTEST22 TEST24
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 T118 AE8 TEST22 TEST8 C4
HT_NB_CPU_CLK_L1 K5 Y3 HT_CPU_NB_CLK_L1 +1.8VSUS CPUTEST12 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 T9 TEST12
R455 300_4 CPUTEST27 AF8
HT_NB_CPU_CTL_H0 HT_CPU_NB_CTL_H0 TEST27 CPUTEST29H
N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 TEST29_H C9 T47
HT_NB_CPU_CTL_L0 P1 R3 HT_CPU_NB_CTL_L0 R535 0_4 C2 C8 CPUTEST29L
L0_CTLIN_L0 L0_CTLOUT_L0 TEST9 TEST29_L T50
HT_NB_CPU_CTL_H1 P3 T5 HT_CPU_NB_CTL_H1 AA6
HT_NB_CPU_CTL_L1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CPU_NB_CTL_L1 TEST6
P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5
A3 RSVD1 RSVD10 H18
FOX PZ63826-284R-41F A5 RSVD2 RSVD9 H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7
RSVD3 RSVD8
MLX 47296-4131 B5 RSVD4 RSVD7 D5
C1 RSVD5 RSVD6 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2)
TYC 4-1903401-2
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN
CNTR_VREF
C854 0.1U/10V_4
CNTR_VREF 5
+3V
Serial VID VFIX MODE VID Override Circuit
B R145 *2.2K_4 B
SVC SVD Voltage Output
+3V R571 20K/F_4 R574 34.8K/F_4 R561 1K/F_4
R562 1K/F_4
+1.8VSUS 0 0 1.4V
CNTR_VREF R577 CPU_SVC_R R554 0_4 CPU_SVC
1K/F_4 CPU_SVD_R R553 0_4 CPU_SVD
CPU_SVC 40 0 1 1.2V
CPU_SVD 40
CPU_PWRGD R147 0_4 CPU_PWRGD_SVID_REG
CPU_PWRGD_SVID_REG 40 1 0 1.0V
2
R143
Q39 *BSS138_NL/SOT23 0_4 R560 *220_4
CPU_LDT_REQ#_CPU 1 3 CPU_LDT_RST# 1 3 CPU_LDT_RST_HTPA# R559 *220_4 1 1 0.8V
CPU_LDT_REQ# 10
Q40
BSS138_NL/SOT23 C926 *0.1U/10V_4
1
R570 0_4 G1
*SHORT_ PAD1 SI-2 remove for power up seq
2
+1.8VSUS R59 10K/F_4

for debug only
2
+1.8VSUS R62 300_4 Q11 CPUTEST20 R798 *300/F_4

MMBT3904 CPUTEST22 R799 *300/F_4
CPU_MEMHOT_L# 3 1 CPU_MEMHOT# CPUTEST12 R800 *300/F_4
CPU_MEMHOT# 7,13
HDT Connector CPUTEST15
CPUTEST14
CPUTEST19
R801
R802
R803
*300/F_4
*300/F_4
*300/F_4
+1.8VSUS CPUTEST18 R804 *300/F_4
1 2
3 4
A
+1.8VSUS R60 10K/F_4 5 6 SI-2 reserve for AMD recommend A
+1.8VSUS R453 10K/F_4 CPU_DBREQ# 7 8

CPU_DBRDY 9 10
+1.8VSUS R454 300_4 CPU_TCK 11 12
2
+1.8VSUS R452 300_4 Q10 CPU_TMS 13 14

2
Q35 MMBT3904 CPU_TDI 15 16
CPU_PROCHOT_L#
CPU_THERMTRIP_L# 1 3 CPU_THERMTRIP# 13
CPU_TRST#
CPU_TDO
17 18 PROJECT : QT8
1 3 CPU_PROCHOT# 12 19 20
MMBT3904 21 22
C54 *0.1U/10V_4 23 24 CPU_LDT_RST_HTPA#
KEY 25
Custom 1A
S1G2 HT,CTL I/F 1/3
CN6 *HDT CONN NB5/RD5
5 4 3 2 1
A B C D E
PLACE THEM CLOSE TO

CPU WITHIN 1"
+0.9VSMVTT
D10
C10
B10
AD10
U31B
VTT1
VTT2
VTT3
MEM:CMD/CTRL/CLK VTT5
VTT6
VTT7
W10
AC10
AB10
AA10
+0.9VSMVTT
750 mA
+1.8VSUS 6 MEM_MB_DATA[0..63]
+0.9VSMVREF 6,41
Processor Memory Interface
MEM_MB_DATA0 C11
U31C
MEM:DATA
G12 MEM_MA_DATA0
MEM_MA_DATA[0..63] 6
04
VTT4 VTT8 R81 R82 Reserved MEM_MB_DATA1 MB_DATA0 MA_DATA0 MEM_MA_DATA1
VTT9 A10 A11 MB_DATA1 MA_DATA1 F12
R459 39.2/F_4 M_ZP AF10 *0_4 MEM_MB_DATA2 A14 H14 MEM_MA_DATA2
39.2/F_4 M_ZN MEMZP MB_DATA2 MA_DATA2
+1.8VSUS R458 AE10 MEMZN VTT_SENSE Y10 CPU_VTT_SENSE CPU_VTT_SENSE 41
2K/F_4 MEM_MB_DATA3 B14 MB_DATA3 MA_DATA3 G14 MEM_MA_DATA3
MEM_MB_DATA4 G11 H11 MEM_MA_DATA4
MEM_MA_RESET# H16 MB_DATA4 MA_DATA4
T41 RSVD_M1 MEMVREF W17 MEMVREF_CPU MEM_MB_DATA5 E11 MB_DATA5 MA_DATA5 H12 MEM_MA_DATA5
MEM_MB_DATA6 D12 C13 MEM_MA_DATA6
4 MB_DATA6 MA_DATA6 4
6,7 MEM_MA0_ODT0 T19 MA0_ODT0 RSVD_M2 B18 MEM_MB_RESET# T51
MEM_MB_DATA7 A13 MB_DATA7 MA_DATA7 E13 MEM_MA_DATA7
V22 MEM_MB_DATA8 A15 H15 MEM_MA_DATA8
6,7 MEM_MA0_ODT1 MA0_ODT1 MB_DATA8 MA_DATA8
U21 W26 R77 MEM_MB_DATA9 A16 E15 MEM_MA_DATA9
MA1_ODT0 MB0_ODT0 MEM_MB0_ODT0 6,7 MB_DATA9 MA_DATA9
V19 W23 2K/F_4 C197 C177 MEM_MB_DATA10 A19 E17 MEM_MA_DATA10
MA1_ODT1 MB0_ODT1 MEM_MB0_ODT1 6,7 MB_DATA10 MA_DATA10
Y26 0.1U/10V_4 1000P/50V_4 MEM_MB_DATA11 A20 H17 MEM_MA_DATA11
MB1_ODT0 MEM_MB_DATA12 MB_DATA11 MA_DATA11 MEM_MA_DATA12
6,7 MEM_MA0_CS#0 T20 MA0_CS_L0 C14 MB_DATA12 MA_DATA12 E14
U19 V26 MEM_MB_DATA13 D14 F14 MEM_MA_DATA13
6,7 MEM_MA0_CS#1 MA0_CS_L1 MB0_CS_L0 MEM_MB0_CS#0 6,7 MB_DATA13 MA_DATA13
U20 W25 MEM_MB_DATA14 C18 C17 MEM_MA_DATA14
MA1_CS_L0 MB0_CS_L1 MEM_MB0_CS#1 6,7 MB_DATA14 MA_DATA14
V20 U22 MEM_MB_DATA15 D18 G17 MEM_MA_DATA15
MA1_CS_L1 MB1_CS_L0 MEM_MB_DATA16 MB_DATA15 MA_DATA15 MEM_MA_DATA16
D20 MB_DATA16 MA_DATA16 G18
J22 J25 MEM_MB_DATA17 A21 C19 MEM_MA_DATA17
6,7 MEM_MA_CKE0 MA_CKE0 MB_CKE0 MEM_MB_CKE0 6,7 MB_DATA17 MA_DATA17
J20 H26 MEM_MB_DATA18 D24 D22 MEM_MA_DATA18
6,7 MEM_MA_CKE1 MA_CKE1 MB_CKE1 MEM_MB_CKE1 6,7 MB_DATA18 MA_DATA18
MEM_MB_DATA19 C25 E20 MEM_MA_DATA19
MEM_MB_DATA20 MB_DATA19 MA_DATA19 MEM_MA_DATA20
N19 MA_CLK_H5 MB_CLK_H5 P22 B20 MB_DATA20 MA_DATA20 E18
N20 R22 MEM_MB_DATA21 C20 F18 MEM_MA_DATA21
MA_CLK_L5 MB_CLK_L5 MEM_MB_DATA22 MB_DATA21 MA_DATA21 MEM_MA_DATA22
6 MEM_MA_CLK1_P E16 MA_CLK_H1 MB_CLK_H1 A17 MEM_MB_CLK1_P 6 B24 MB_DATA22 MA_DATA22 B22
F16 A18 MEM_MB_DATA23 C24 C23 MEM_MA_DATA23
6 MEM_MA_CLK1_N MA_CLK_L1 MB_CLK_L1 MEM_MB_CLK1_N 6 MB_DATA23 MA_DATA23
Y16 AF18 MEM_MB_DATA24 E23 F20 MEM_MA_DATA24
6 MEM_MA_CLK7_P MA_CLK_H7 MB_CLK_H7 MEM_MB_CLK7_P 6 MB_DATA24 MA_DATA24
AA16 AF17 MEM_MB_DATA25 E24 F22 MEM_MA_DATA25
6 MEM_MA_CLK7_N MA_CLK_L7 MB_CLK_L7 MEM_MB_CLK7_N 6 MB_DATA25 MA_DATA25
P19 R26 MEM_MB_DATA26 G25 H24 MEM_MA_DATA26
MA_CLK_H4 MB_CLK_H4 MEM_MB_DATA27 MB_DATA26 MA_DATA26 MEM_MA_DATA27
P20 MA_CLK_L4 MB_CLK_L4 R25 G26 MB_DATA27 MA_DATA27 J19
MEM_MB_DATA28 C26 E21 MEM_MA_DATA28
6,7 MEM_MA_ADD[0..15] MEM_MB_ADD[0..15] 6,7 MB_DATA28 MA_DATA28
MEM_MA_ADD0 N21 P24 MEM_MB_ADD0 MEM_MB_DATA29 D26 E22 MEM_MA_DATA29
MEM_MA_ADD1 MA_ADD0 MB_ADD0 MEM_MB_ADD1 MEM_MB_DATA30 MB_DATA29 MA_DATA29 MEM_MA_DATA30
M20 MA_ADD1 MB_ADD1 N24 G23 MB_DATA30 MA_DATA30 H20
MEM_MA_ADD2 N22 P26 MEM_MB_ADD2 MEM_MB_DATA31 G24 H22 MEM_MA_DATA31
M19 MA_ADD3 MB_ADD3 N23 AA24 MB_DATA32 MA_DATA32 Y24
MEM_MA_ADD4 M22 N26 MEM_MB_ADD4 MEM_MB_DATA33 AA23 AB24 MEM_MA_DATA33
L20 MA_ADD5 MB_ADD5 L23 AD24 MB_DATA34 MA_DATA34 AB22
MEM_MA_ADD6 M24 N25 MEM_MB_ADD6 MEM_MB_DATA35 AE24 AA21 MEM_MA_DATA35
3 L21 MA_ADD7 MB_ADD7 L24 AA26 MB_DATA36 MA_DATA36 W22 3
MEM_MA_ADD8 L19 M26 MEM_MB_ADD8 MEM_MB_DATA37 AA25 W21 MEM_MA_DATA37
K22 MA_ADD9 MB_ADD9 K26 AD26 MB_DATA38 MA_DATA38 Y22
MEM_MA_ADD10 R21 T26 MEM_MB_ADD10 MEM_MB_DATA39 AE25 AA22 MEM_MA_DATA39
L22 MA_ADD11 MB_ADD11 L26 AC22 MB_DATA40 MA_DATA40 Y20
MEM_MA_ADD12 K20 L25 MEM_MB_ADD12 MEM_MB_DATA41 AD22 AA20 MEM_MA_DATA41
V24 MA_ADD13 MB_ADD13 W24 AE20 MB_DATA42 MA_DATA42 AA18
MEM_MA_ADD14 K24 J23 MEM_MB_ADD14 MEM_MB_DATA43 AF20 AB18 MEM_MA_DATA43
K19 MA_ADD15 MB_ADD15 J24 AF24 MB_DATA44 MA_DATA44 AB21
MEM_MB_DATA45 AF23 AD21 MEM_MA_DATA45
6,7 MEM_MA_BANK0 R20 MA_BANK0 MB_BANK0 R24 MEM_MB_BANK0 6,7 AC20 MB_DATA46 MA_DATA46 AD19
R23 U26 MEM_MB_DATA47 AD20 Y18 MEM_MA_DATA47
6,7 MEM_MA_BANK1 MA_BANK1 MB_BANK1 MEM_MB_BANK1 6,7 MB_DATA47 MA_DATA47
J21 J26 MEM_MB_DATA48 AD18 AD17 MEM_MA_DATA48
6,7 MEM_MA_BANK2 MA_BANK2 MB_BANK2 MEM_MB_BANK2 6,7 MB_DATA48 MA_DATA48
MEM_MB_DATA49 AE18 W16 MEM_MA_DATA49
6,7 MEM_MA_RAS# R19 MA_RAS_L MB_RAS_L U25 MEM_MB_RAS# 6,7 AC14 MB_DATA50 MA_DATA50 W14
T22 U24 MEM_MB_DATA51 AD14 Y14 MEM_MA_DATA51
6,7 MEM_MA_CAS# MA_CAS_L MB_CAS_L MEM_MB_CAS# 6,7 MB_DATA51 MA_DATA51
T24 U23 MEM_MB_DATA52 AF19 Y17 MEM_MA_DATA52
6,7 MEM_MA_WE# MA_WE_L MB_WE_L MEM_MB_WE# 6,7 MB_DATA52 MA_DATA52
MEM_MB_DATA53 AC18 AB17 MEM_MA_DATA53
AF16 MB_DATA54 MA_DATA54 AB15
SOCKET_638_PIN MEM_MB_DATA55 AF15 AD15 MEM_MA_DATA55
MEM_MB_DATA57 AC12 AD13 MEM_MA_DATA57
AB11 MB_DATA58 MA_DATA58 Y12
MEM_MB_DATA59 Y11 W11 MEM_MA_DATA59
AE14 MB_DATA60 MA_DATA60 AB14
MEM_MB_DATA61 AF14 AA14 MEM_MA_DATA61
MEM_MB_DATA63 AD11 AA12 MEM_MA_DATA63
MB_DATA63 MA_DATA63
6 MEM_MB_DM[0..7] MEM_MA_DM[0..7] 6
MEM_MB_DM0 MEM_MA_DM0
2 +0.9VSMVTT Place close to socket MEM_MB_DM1
A12
B16
MB_DM0 MA_DM0 E12
C15 MEM_MA_DM1 2
MEM_MB_DM2 MB_DM1 MA_DM1 MEM_MA_DM2

A22 MB_DM2 MA_DM2 E19
MEM_MB_DM3 E25 F24 MEM_MA_DM3
MEM_MB_DM4 MB_DM3 MA_DM3 MEM_MA_DM4
AB26 MB_DM4 MA_DM4 AC24
C112 C399 C99 C398 C213 C369 C364 C201 MEM_MB_DM5 AE22 Y19 MEM_MA_DM5
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 MEM_MB_DM6 MB_DM5 MA_DM5 MEM_MA_DM6
AC16 MB_DM6 MA_DM6 AB16
MEM_MB_DM7 AD12 Y13 MEM_MA_DM7
MB_DM7 MA_DM7
6 MEM_MB_DQS0_P C12 MB_DQS_H0 MA_DQS_H0 G13 MEM_MA_DQS0_P 6

6 MEM_MB_DQS0_N B12 MB_DQS_L0 MA_DQS_L0 H13 MEM_MA_DQS0_N 6
6 MEM_MB_DQS1_P D16 MB_DQS_H1 MA_DQS_H1 G16 MEM_MA_DQS1_P 6
+0.9VSMVTT C16 G15
6 MEM_MB_DQS1_N MB_DQS_L1 MA_DQS_L1 MEM_MA_DQS1_N 6
6 MEM_MB_DQS2_P A24 MB_DQS_H2 MA_DQS_H2 C22 MEM_MA_DQS2_P 6
6 MEM_MB_DQS2_N A23 MB_DQS_L2 MA_DQS_L2 C21 MEM_MA_DQS2_N 6
6 MEM_MB_DQS3_P F26 MB_DQS_H3 MA_DQS_H3 G22 MEM_MA_DQS3_P 6
C401 C202 C400 C185 C183 C189 C390 C396 E26 G21
6 MEM_MB_DQS3_N MB_DQS_L3 MA_DQS_L3 MEM_MA_DQS3_N 6
1000P/50V_4 1000P/50V_4 1000P/50V_4 1000P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 180P/50V_4 AC25 AD23
6 MEM_MB_DQS4_P MB_DQS_H4 MA_DQS_H4 MEM_MA_DQS4_P 6
6 MEM_MB_DQS4_N AC26 MB_DQS_L4 MA_DQS_L4 AC23 MEM_MA_DQS4_N 6
6 MEM_MB_DQS5_P AF21 MB_DQS_H5 MA_DQS_H5 AB19 MEM_MA_DQS5_P 6
6 MEM_MB_DQS5_N AF22 MB_DQS_L5 MA_DQS_L5 AB20 MEM_MA_DQS5_N 6
6 MEM_MB_DQS6_P AE16 MB_DQS_H6 MA_DQS_H6 Y15 MEM_MA_DQS6_P 6
6 MEM_MB_DQS6_N AD16 MB_DQS_L6 MA_DQS_L6 W15 MEM_MA_DQS6_N 6
6 MEM_MB_DQS7_P AF12 MB_DQS_H7 MA_DQS_H7 W12 MEM_MA_DQS7_P 6
Close to CPU within 1500 mils 6 MEM_MB_DQS7_N AE12 MB_DQS_L7 MA_DQS_L7 W13 MEM_MA_DQS7_N 6
MEM_MA_CLK7_P
MEM_MB_CLK7_P SOCKET_638_PIN
C734
C736 1.5P/50V_4
1 1.5P/50V_4 1
MEM_MA_CLK7_N
MEM_MB_CLK7_N
MEM_MA_CLK1_P
MEM_MB_CLK1_P
C367
C366
1.5P/50V_4
1.5P/50V_4
PROJECT : QT8
MEM_MB_CLK1_N
MEM_MA_CLK1_N Quanta Computer Inc.
Custom 1A
S1G2 DDRII MEMORY I/F 2/3
NB5/RD5
A B C D E
5 4 3 2 1
+VCORE0 U31E +VCORE1

AA4
AA11
AA13
AA15
U31F
VSS1
VSS2
VSS3
VSS66
VSS67
VSS68
J6
J8
J10
J12
+VCORE0
BOTTOM SIDE DECOUPLING
05
VSS4 VSS69
G4 VDD0_1 VDD1_1 P8 AA17 VSS5 VSS70 J14
H2 VDD0_2 VDD1_2 P10 AA19 VSS6 VSS71 J16
J9 VDD0_3 VDD1_3 R4 AB2 VSS7 VSS72 J18
J11 R7 AB7 K2 C287 C308 C307 C306 C285 C286 C301
VDD0_4 VDD1_4 VSS8 VSS73 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4
J13 VDD0_5 VDD1_5 R9 AB9 VSS9 VSS74 K7
D
J15 VDD0_6 VDD1_6 R11 AB23 VSS10 VSS75 K9 D
K6 VDD0_7 VDD1_7 T2 AB25 VSS11 VSS76 K11
K10 VDD0_8 VDD1_8 T6 AC11 VSS12 VSS77 K13
K12 VDD0_9 VDD1_9 T8 AC13 VSS13 VSS78 K15
K14 T10 AC15 K17 +VCORE1
VDD0_10 VDD1_10 VSS14 VSS79
L4 VDD0_11 VDD1_11 T12 AC17 VSS15 VSS80 L6
L7 VDD0_12 VDD1_12 T14 AC19 VSS16 VSS81 L8
L9 VDD0_13 VDD1_13 U7 AC21 VSS17 VSS82 L10
L11 VDD0_14 VDD1_14 U9 AD6 VSS18 VSS83 L12
L13 U11 AD8 L14 C230 C272 C273 C267 C206 C226 C205 C225
VDD0_15 VDD1_15 VSS19 VSS84 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.01U/16V_4 180P/50V_4 0.01U/16V_4
L15 VDD0_16 VDD1_16 U13 AD25 VSS20 VSS85 L16
M2 VDD0_17 VDD1_17 U15 AE11 VSS21 VSS86 L18
M6 VDD0_18 VDD1_18 V6 AE13 VSS22 VSS87 M7
M8 VDD0_19 VDD1_19 V8 AE15 VSS23 VSS88 M9
M10 VDD0_20 VDD1_20 V10 AE17 VSS24 VSS89 AC6
N7 V12 AE19 M17 +CPUVDDNB +1.8VSUS
+CPUVDDNB VDD0_21 VDD1_21 VSS25 VSS90
N9 VDD0_22 VDD1_22 V14 AE21 VSS26 VSS91 N4
N11 VDD0_23 VDD1_23 W4 AE23 VSS27 VSS92 N8
3A VDD1_24 Y2 B4 VSS28 VSS93 N10
K16 VDDNB_1 VDD1_25 AC4 B6 VSS29 VSS94 N16
M16 AD2 +1.8VSUS B8 N18 C264 C231 C279 C248 C284 C309 C247 C214 C315
VDDNB_2 VDD1_26 VSS30 VSS95 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 22U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 180P/50V_4 180P/50V_4
P16 VDDNB_3 B9 VSS31 VSS96 P2
T16 VDDNB_4 VDDIO27 Y25 B11 VSS32 VSS97 P7
+1.8VSUS V16 V25 B13 P9
VDDNB_5 VDDIO26 VSS33 VSS98
2A VDDIO25 V23 B15 VSS34 VSS99 P11
H25 VDDIO1 VDDIO24 V21 B17 VSS35 VSS100 P17
J17 VDDIO2 VDDIO23 V18 B19 VSS36 VSS101 R8
K18 VDDIO3 VDDIO22 U17 B21 VSS37 VSS102 R10
K21 VDDIO4 VDDIO21 T25 B23 VSS38 VSS103 R16
K23 VDDIO5 VDDIO20 T23 B25 VSS39 VSS104 R18
C K25 VDDIO6 VDDIO19 T21 D6 VSS40 VSS105 T7 C
L17 T18 D8 T9
M18
M21
VDDIO7
VDDIO8
VDDIO18
VDDIO17 R17
P25
D9
D11
VSS41
VSS42
VSS106
VSS107 T11
T13
DECOUPLING BETWEEN PROCESSOR AND DIMMs
VDDIO9 VDDIO16 VSS43 VSS108
M23 P23 D13 T15
M25
N17
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21
P18
D15
D17
VSS44
VSS45
VSS109
VSS110 T17
U4
PLACE CLOSE TO PROCESSOR AS POSSIBLE
VDDIO12 VDDIO13 VSS46 VSS111
D19 VSS47 VSS112 U6
D21 U8 +1.8VSUS
SOCKET_638_PIN VSS48 VSS113
D23 VSS49 VSS114 U10
D25 VSS50 VSS115 U12
+1.8VSUS E4 U14
VSS51 VSS116
F2 VSS52 VSS117 U16
F11 U18 C750 C802 C236 C749 C803 C240
VSS53 VSS118 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4
3 CNTR_VREF F13 VSS54 VSS119 V2
F15 VSS55 VSS120 V7
R164 R166 R167 F17 V9
390_4 390_4 1K/F_4 VSS56 VSS121 +1.8VSUS
F19 VSS57 VSS122 V11
2

Q14 H7 W6
MBCLK2 CPU_SIC VSS61 VSS126 C238 C751 C752 C120 C118
18,35 MBCLK2 3 1 CPU_SIC 3 H9 VSS62 VSS127 Y21
H21 Y23 0.22U/6.3V_4 0.22U/6.3V_4 0.01U/16V_4 0.01U/16V_4 180P/50V_4
VSS63 VSS128
2
*BSS138_NL/SOT23 H23 N6
Q15 VSS64 VSS129
J4 VSS65
18,35 MBDATA2 MBDATA2 3 1 CPU_SID
CPU_SID 3
SOCKET_638_PIN
2
*BSS138_NL/SOT23
Q13
B B
SMBALERT# 3 1 CPU_ALERT
CPU_ALERT 3
*BSS138_NL/SOT23
PROCESSOR POWER AND GROUND
+3V +3V
+VCORE0 +VCORE1
R572 +1.8VSUS EC10 0.01U/16V_4 +3VPCU C69 0.01U/16V_4
200/F_6 Update U36 P/N R170 *0_4 SYS_SHDN# C71 0.01U/16V_4

SYS_SHDN# 38,44
R149 R151 R148 on PV +1.8V EC5 0.01U/16V_4 +3VPCU
reserve for C67 0.01U/16V_4
1
10K/F_4 10K/F_4 10K/F_4 power shutdown D34 EC4 0.01U/16V_4 C64 0.01U/16V_4
+1.8V +3V
Del R150, R152 C856 ( if can ) *CH500H
on PV 0.1U/10V_4
+3VPCU EC7 0.01U/16V_4
+3V
2
U36
+1.8VSUS EC3 0.01U/16V_4 +5V
18,35 MBCLK2 8 1 +5V EC1 *0.01U/16V_4
SCLK VCC H_THRMDA 3 +3V
R168 0_4 3920_RST#
3920_RST# 35,44
18,35 MBDATA2 7 2 C855 Q16 EC2 *0.01U/16V_4 +5V EC6 0.01U/16V_4 +3VPCU
SDA DXP 2200P/50V_4
3
MMBT3904 D33
6 ALERT# DXN 3
2 2 1 ECPWROK +VGA_CORE EC8 0.01U/16V_4 +1.8V
H_THRMDC 3 ECPWROK 16,35
13 PM_THERM# 4 OVERT# GND 5
EC9 0.01U/16V_4 For fix HyperTransport nets
1
A MSOP CH501H-40PT A
across plane splits
SI-2 Modified for H/W thermal shutdown G781P8 SMBALERT# R172 10K/F_4
+3V
3
R805 *10K/F_4 +3VS5 +3VS5 +3V +1.8V

PROJECT : QT8
+1.8VSUS
R760 *10K/F_4
+1.8VSUS R806 *300_4 PQ60 2 TEMP_FAIL 18 Quanta Computer Inc.

2
Q71 EC13 EC14 EC11 EC12

*MMBT3904 *2N7002E-G ADD VGA TEMP_ FAIL function
CPU_THERMTRIP_L# SMBALERT# Size Document Number Rev
CPU_THERMTRIP_L#
1 3 M8X is active Hi , M7X acvite Low Custom 1A
S1G2 PWR & GND 3/3
1
*0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 NB5/RD5

5 4 3 2 1
5 4 3 2 1
07
+1.8VSUS +1.8VSUS
103
104
111
112
117
118
103
104
111
112
117
118
81
82
87
88
95
96
81
82
87
88
95
96
4,7 MEM_MA_ADD[0..15] MEM_MA_DATA[0..63] 4 4,7 MEM_MB_ADD[0..15] MEM_MB_DATA[0..63] 4
CN30 CN31
MEM_MA_ADD0 102 5 MEM_MA_DATA0 MEM_MB_ADD0 102 5 MEM_MB_DATA4
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
MEM_MA_ADD1 A0 DQ0 MEM_MA_DATA1 MEM_MB_ADD1 A0 DQ0 MEM_MB_DATA5
101 A1 DQ1 7 101 A1 DQ1 7
99 A3 DQ3 19 99 A3 DQ3 19
97 A5 DQ5 6 97 A5 DQ5 6
92 A7 DQ7 16 92 A7 DQ7 16
D MEM_MA_ADD9 A8 DQ8 MEM_MA_DATA9 MEM_MB_ADD9 A8 DQ8 MEM_MB_DATA12 D
91 A9 DQ9 25 91 A9 DQ9 25
90 A11 DQ11 37 90 A11 DQ11 37
116 A13 DQ13 22 116 A13 DQ13 22
4,7 MEM_MA_BANK[0..2] 84 A15 DQ15 38 4,7 MEM_MB_BANK[0..2] 84 A15 DQ15 38
43 MEM_MA_DATA16 43 MEM_MB_DATA16
MEM_MA_BANK0 107 DQ16 MEM_MA_DATA17 MEM_MB_BANK0 107 DQ16 MEM_MB_DATA17
BA0 DQ17 45 BA0 DQ17 45
MEM_MA_BANK1 106 55 MEM_MA_DATA18 MEM_MB_BANK1 106 55 MEM_MB_DATA18
MEM_MA_BANK2 85 BA1 DQ18 MEM_MA_DATA19 MEM_MB_BANK2 BA1 DQ18 MEM_MB_DATA19
4 MEM_MA_DM[0..7] BA2 DQ19 57 4 MEM_MB_DM[0..7] 85 BA2 DQ19 57
MEM_MA_DM0 DQ20 MEM_MA_DATA21 MEM_MB_DM0 DQ20 MEM_MB_DATA21
10 DM0 DQ21 46 10 DM0 DQ21 46
MEM_MA_DM1 26 56 MEM_MA_DATA22 MEM_MB_DM1 26 56 MEM_MB_DATA22
MEM_MA_DM2 DM1 DQ22 MEM_MA_DATA23 MEM_MB_DM2 DM1 DQ22 MEM_MB_DATA23
52 DM2 DQ23 58 52 DM2 DQ23 58
130 DM4 DQ25 63 130 DM4 DQ25 63
170 DM6 DQ27 75 170 DM6 DQ27 75
DM7 DQ28 MEM_MA_DATA29 DM7 DQ28 MEM_MB_DATA29
DQ29 64 DQ29 64
13 74 MEM_MA_DATA30 13 74 MEM_MB_DATA30
4 MEM_MA_DQS0_P DQS0 DQ30 4 MEM_MB_DQS0_P DQS0 DQ30
C DQ38 MEM_MA_DATA34 DQ38 MEM_MB_DATA39 C
4 MEM_MA_DQS0_N 11 DQS0 DQ39 136 4 MEM_MB_DQS0_N 11 DQS0 DQ39 136
4 MEM_MA_DQS1_N DQS1 DQ40 4 MEM_MB_DQS1_N DQS1 DQ40
DQ47 MEM_MA_DATA52 DQ47 MEM_MB_DATA52
DQ48 157 DQ48 157
4 MEM_MA_CLK1_P CK0 DQ49 4 MEM_MB_CLK1_P CK0 DQ49
4 MEM_MA_CLK1_N CK0 DQ50 4 MEM_MB_CLK1_N CK0 DQ50
4 MEM_MA_CLK7_P CK1 DQ51 4 MEM_MB_CLK7_P CK1 DQ51
4 MEM_MA_CLK7_N CK1 DQ52 4 MEM_MB_CLK7_N CK1 DQ52
4,7 MEM_MA_CKE0 79 CKE0 DQ54 174 4,7 MEM_MB_CKE0 79 CKE0 DQ54 174
80 176 MEM_MA_DATA50 4,7 MEM_MB_CKE1 80 176 MEM_MB_DATA55
4,7 MEM_MA_CKE1 CKE1 DQ55 CKE1 DQ55
4,7 MEM_MA_RAS# 108 RAS DQ57 181 4,7 MEM_MB_RAS# 108 RAS DQ57 181
4,7 MEM_MA_CAS# CAS DQ58 4,7 MEM_MB_CAS# CAS DQ58
4,7 MEM_MA_WE# WE DQ59 4,7 MEM_MB_WE# WE DQ59
MEM_MA_DATA56 MEM_MB_DATA61
SO-DIMM
4,7 MEM_MA0_CS#0 110 S0 DQ60 180 4,7 MEM_MB0_CS#0 110 S0 DQ60 180
4,7 MEM_MA0_CS#1 S1 DQ61 4,7 MEM_MB0_CS#1 S1 DQ61
(Normal)

DQ62 DQ62
(REVERSE)
4,7 MEM_MA0_ODT0 ODT0 DQ63 4,7 MEM_MB0_ODT0 ODT0 DQ63
4,7 MEM_MA0_ODT1 119 ODT1 4,7 MEM_MB0_ODT1 119 ODT1
50 MEMHOT_SODIMM#_1 R106 0_4 50 MEMHOT_SODIMM#_2 R105 0_4 MEMHOT_SODIMM#
NC1 MEMHOT_SODIMM# 7 NC1
SO-DIMM
DIM1_SA0 198 69 MEM_MA_RESET#1 DIM2_SA0 198 69 MEM_MB_RESET#2
SA0 NC2 T155 SA0 NC2 T156
DIM1_SA1 200 83 DIM2_SA1 200 83
SA1 NC3 SA1 NC3
NC4 120 NC4 120
B PDAT_SMB 195 163 MEM_MA_NC5 PDAT_SMB 195 163 MEM_MB_NC5 B
2,7,13,28,36 PDAT_SMB SDA NC/TEST T115 SDA NC/TEST T114
PCLK_SMB 197 PCLK_SMB 197
2,7,13,28,36 PCLK_SMB SCL SCL
+3V 199 VDDspd +3V 199 VDDspd
C701 C702
+0.9VSMVREF_DIMM 0.1U/10V_4 1 196 +0.9VSMVREF_DIMM 0.1U/10V_4 1 196
VREF VSS56 VREF VSS56
VSS55 193 VSS55 193
2 VSS0 VSS54 190 2 VSS0 VSS54 190
3 187 C848 C406 C397 o3 187
C849 VSS1 VSS53 1000P/50V_4 VSS1 VSS53
8 VSS2 VSS52 184 2.2U/6.3V_6 0.1U/10V_4 8 184
C391 1000P/50V_4 oVSS2 VSS52
9 VSS3 VSS51 183 9 VSS3 VSS51 183
C370 0.1U/10V_4 12 178 12 178
VSS4 VSS50 VSS4 VSS50
2.2U/6.3V_6 15 VSS5 VSS49 177 15 VSS5 VSS49 177
18 VSS6 VSS48 172 18 VSS6 VSS48 172
21 171 +1.8VSUS 21 171
24 VSS8 VSS46 168 24 VSS8 VSS46 168
27 VSS9 VSS45 165 27 VSS9 VSS45 165
28 VSS10 VSS44 162 28 VSS10 VSS44 162
33 161 R138 33 161
34 VSS12 VSS42 156 2K/F_4 34 VSS12 VSS42 156
39 155 +0.9VSMVREF_DIMM 39 155
40 VSS14 VSS40 150 40 VSS14 VSS40 150
41 VSS15 VSS39 149 41 VSS15 VSS39 149
42 VSS16 VSS38 145 42 VSS16 VSS38 145
47 VSS17 VSS37 144 47 VSS17 VSS37 144
48 139 R139 *0_4 +0.9VSMVREF_DIMM 48 139
4,41 +0.9VSMVREF
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
53 138 53 138
GND
GND
GND
GND
54 VSS20 VSS34 133 54 VSS20 VSS34 133
DDR SO-DIMM SOCKET 1.8V

201
202
59
60
65
66
71
72
77
78
121
122
127
128
132
201
202
59
60
65
66
71
72
77
78
121
122
127
128
132
A Only for reserved R130
2K/F_4
H=9.2 A
DDR SO-DIMM SOCKET 1.8V

H=5.2
DIM2_SA0
DIM2_SA1
R423
R424
10K/F_4
10K/F_4
+3V PROJECT : QT8
R40
R43
10K/F_4
10K/F_4
DIM1_SA0
DIM1_SA1
SMbus address A2
SMbus address A0 Size Document Number Rev
Custom 1A
DDR2 SODIMMS: A/B CHANNEL
NB5/RD5
5 4 3 2 1
5 4 3 2 1
4,6 MEM_MA_ADD[0..15]
4,6 MEM_MA_BANK[0..2]
MEM_MA_ADD[0..15]
MEM_MA_BANK[0..2]
4,6 MEM_MB_ADD[0..15]
4,6 MEM_MB_BANK[0..2]
MEM_MB_ADD[0..15]
MEM_MB_BANK[0..2]
08
+0.9VSMVTT +0.9VSMVTT
MEM_MA_CKE0 RP40 4 3 47_4P2R_4 MEM_MB_CKE0 RP36 4 3 47_4P2R_4

4,6 MEM_MA_CKE0 4,6 MEM_MB_CKE0
MEM_MA_BANK2 2 1 C176 0.1U/10V_4 +1.8VSUS MEM_MB_BANK2 2 1 C193 0.1U/10V_4 +1.8VSUS
MEM_MA_ADD12 RP35 4 3 47_4P2R_4 MEM_MB_ADD12 RP32 2 1 47_4P2R_4
D D
MEM_MA_ADD9 2 1 C256 0.1U/10V_4 MEM_MB_ADD9 4 3 C245 0.1U/10V_4
MEM_MA_ADD5 4 3 C223 0.1U/10V_4 +1.8VSUS MEM_MB_ADD5 2 1 C154 0.1U/10V_4 +1.8VSUS
MEM_MA_ADD1 4 3 C104 0.1U/10V_4 MEM_MB_ADD1 2 1 C100 0.1U/10V_4
MEM_MA_BANK0 2 1 C217 0.1U/10V_4 +1.8VSUS MEM_MB_BANK0 2 1 C137 0.1U/10V_4 +1.8VSUS
MEM_MA_WE# RP16 4 3 47_4P2R_4 MEM_MB_WE# RP15 4 3 47_4P2R_4
4,6 MEM_MA_WE# 4,6 MEM_MB_WE#
MEM_MA_CAS# 2 1 C96 0.1U/10V_4 MEM_MB_CAS# 2 1 C94 0.1U/10V_4
4,6 MEM_MA_CAS# 4,6 MEM_MB_CAS#
MEM_MA0_ODT1 RP10 4 3 47_4P2R_4 MEM_MB0_ODT1 RP9 4 3 47_4P2R_4
4,6 MEM_MA0_ODT1 4,6 MEM_MB0_ODT1
MEM_MA0_CS#1 2 1 C152 0.1U/10V_4 +1.8VSUS MEM_MB0_CS#1 2 1 C190 0.1U/10V_4 +1.8VSUS
4,6 MEM_MA0_CS#1 4,6 MEM_MB0_CS#1
MEM_MA_ADD15 RP39 4 3 47_4P2R_4 MEM_MB_CKE1 RP38 2 1 47_4P2R_4
4,6 MEM_MB_CKE1
MEM_MA_CKE1 2 1 C271 0.1U/10V_4 MEM_MB_ADD15 4 3 C93 0.1U/10V_4
4,6 MEM_MA_CKE1
MEM_MA_ADD7 RP33 4 3 47_4P2R_4 MEM_MB_ADD7 RP34 4 3 47_4P2R_4 C160 0.1U/10V_4 +1.8VSUS
MEM_MA_ADD14 2 1 C162 0.1U/10V_4 +1.8VSUS MEM_MB_ADD14 2 1
MEM_MA_ADD6 RP29 4 3 47_4P2R_4 C254 0.1U/10V_4
MEM_MA_ADD11 2 1 C101 0.1U/10V_4 MEM_MB_ADD6 RP30 4 3 47_4P2R_4
MEM_MB_ADD11 2 1 C173 0.1U/10V_4 +1.8VSUS
C208 0.1U/10V_4 +1.8VSUS
MEM_MA_ADD2 RP24 4 3 47_4P2R_4 MEM_MB_ADD2 RP22 4 3 47_4P2R_4 C255 0.1U/10V_4
MEM_MA_ADD4 2 1 C102 0.1U/10V_4 MEM_MB_ADD4 2 1
C126 0.1U/10V_4 +1.8VSUS
MEM_MA_BANK1 RP21 2 1 47_4P2R_4 MEM_MB_BANK1 RP19 4 3 47_4P2R_4
MEM_MA_ADD0 4 3 C107 0.1U/10V_4 +1.8VSUS MEM_MB_ADD0 2 1
C253 0.1U/10V_4
4,6 MEM_MA0_CS#0 MEM_MA0_CS#0 RP14 4 3 47_4P2R_4 C270 0.1U/10V_4 4,6 MEM_MB0_CS#0 MEM_MB0_CS#0 RP13 4 3 47_4P2R_4
4,6 MEM_MA_RAS# MEM_MA_RAS# 2 1 4,6 MEM_MB_RAS# MEM_MB_RAS# 2 1 C178 0.1U/10V_4 +1.8VSUS
C146 0.1U/10V_4 +1.8VSUS
C MEM_MA_ADD13 RP12 4 3 47_4P2R_4 MEM_MB0_ODT0 RP11 2 1 47_4P2R_4 C105 0.1U/10V_4 C
4,6 MEM_MB0_ODT0
MEM_MA0_ODT0 2 1 C269 0.1U/10V_4 MEM_MB_ADD13 4 3
4,6 MEM_MA0_ODT0
PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR

WITHIN 1.5 INCH WITHIN 1.5 INCH
+1.8VSUS +1.8VSUS
C239 C121 C241 C242 C117 C235 C122 C119 C237 C115 C116 C745
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
PLACE CLOSE TO SOCKET( PER EMI/EMC) PLACE CLOSE TO SOCKET( PER EMI/EMC)
B B
+3VS5 SI-2 modified --SB internal pull HI to 3vs5
+3V R417
*10K/F_4
R421
CPU_MEMHOT# 3,13
*10K/F_4
3
Close DDR2 socket

+3V
U25 R416 *33_4 2
3
7 8 C706 0.1U/10V_4 Q32

A0 +VS *2N7002E-G
+3V 6 A1
5
1
A2 MEMHOT_SODIMM#
O.S 3 2
PDAT_SMB 1 Q33
2,6,13,28,36 PDAT_SMB SDA
PCLK_SMB 2 4 *2N7002E-G
2,6,13,28,36 PCLK_SMB SCL GND
1
*DS75U+T&R
Address:92h
A R422 10K/F_4 MEMHOT_SODIMM# A

+3V MEMHOT_SODIMM# 6
PROJECT : QT8
Custom 1A
DDR2 SODIMMS TERMINATIONS
NB5/RD5
5 4 3 2 1
5 4 3 2 1
U32A
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
Y25
Y24
V22
V23
V25
V24
U24
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
PART 1 OF 6
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
D24
D25
E24
E25
F24
F25
F23
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
3
3
08
HT_CPU_NB_CAD_L3 HT_RXCAD3P HT_TXCAD3P HT_NB_CPU_CAD_L3 HT_CPU_NB_CLK_L[1..0]
U25 HT_RXCAD3N HT_TXCAD3N F22 HT_CPU_NB_CLK_L[1..0] 3
HT_CPU_NB_CAD_H4 T25 H23 HT_NB_CPU_CAD_H4
HT_CPU_NB_CAD_L4 HT_RXCAD4P HT_TXCAD4P HT_NB_CPU_CAD_L4 HT_CPU_NB_CTL_H[1..0]
T24 HT_RXCAD4N HT_TXCAD4N H22 HT_CPU_NB_CTL_H[1..0] 3
HYPER TRANSPORT CPU I/F

HT_CPU_NB_CAD_H5 P22 J25 HT_NB_CPU_CAD_H5
HT_CPU_NB_CAD_L5 HT_RXCAD5P HT_TXCAD5P HT_NB_CPU_CAD_L5 HT_CPU_NB_CTL_L[1..0]
P23 HT_RXCAD5N HT_TXCAD5N J24 HT_CPU_NB_CTL_L[1..0] 3
HT_CPU_NB_CAD_H6 P25 K24 HT_NB_CPU_CAD_H6
D
HT_CPU_NB_CAD_L6 HT_RXCAD6P HT_TXCAD6P HT_NB_CPU_CAD_L6 HT_NB_CPU_CAD_H[15..0] D
P24 HT_RXCAD6N HT_TXCAD6N K25 HT_NB_CPU_CAD_H[15..0] 3
HT_CPU_NB_CAD_H7 N24 K23 HT_NB_CPU_CAD_H7
HT_CPU_NB_CAD_L7 HT_RXCAD7P HT_TXCAD7P HT_NB_CPU_CAD_L7 HT_NB_CPU_CAD_L[15..0]
N25 HT_RXCAD7N HT_TXCAD7N K22 HT_NB_CPU_CAD_L[15..0] 3
HT_CPU_NB_CAD_H8 AC24 F21 HT_NB_CPU_CAD_H8 HT_NB_CPU_CLK_H[1..0]
HT_CPU_NB_CAD_L8 HT_RXCAD8P HT_TXCAD8P HT_NB_CPU_CAD_L8 HT_NB_CPU_CLK_H[1..0] 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
HT_CPU_NB_CAD_H9 AB25 G20 HT_NB_CPU_CAD_H9 HT_NB_CPU_CLK_L[1..0]
HT_CPU_NB_CAD_L9 HT_RXCAD9P HT_TXCAD9P HT_NB_CPU_CAD_L9 HT_NB_CPU_CLK_L[1..0] 3
AB24 HT_RXCAD9N HT_TXCAD9N H21
HT_CPU_NB_CAD_H10 AA24 J20 HT_NB_CPU_CAD_H10 HT_NB_CPU_CTL_H[1..0]
HT_CPU_NB_CAD_L10 HT_RXCAD10P HT_TXCAD10P HT_NB_CPU_CAD_L10 HT_NB_CPU_CTL_H[1..0] 3
AA25 HT_RXCAD10N HT_TXCAD10N J21
HT_CPU_NB_CAD_H11 Y22 J18 HT_NB_CPU_CAD_H11 HT_NB_CPU_CTL_L[1..0]
HT_CPU_NB_CAD_L11 HT_RXCAD11P HT_TXCAD11P HT_NB_CPU_CAD_L11 HT_NB_CPU_CTL_L[1..0] 3
Y23 HT_RXCAD11N HT_TXCAD11N K17
HT_CPU_NB_CAD_H12 W21 L19 HT_NB_CPU_CAD_H12
HT_CPU_NB_CAD_L12 HT_RXCAD12P HT_TXCAD12P HT_NB_CPU_CAD_L12
W20 HT_RXCAD12N HT_TXCAD12N J19
HT_CPU_NB_CAD_H13 V21 M19 HT_NB_CPU_CAD_H13
HT_CPU_NB_CAD_L13 HT_RXCAD13P HT_TXCAD13P HT_NB_CPU_CAD_L13
V20 HT_RXCAD13N HT_TXCAD13N L18
HT_CPU_NB_CAD_H14 U20 HT_RXCAD14P HT_TXCAD14P M21 HT_NB_CPU_CAD_H14 signals RS780 RX780
HT_CPU_NB_CAD_L14 U21 P21 HT_NB_CPU_CAD_L14
HT_CPU_NB_CAD_H15 HT_RXCAD14N HT_TXCAD14N HT_NB_CPU_CAD_H15
U19 HT_RXCAD15P HT_TXCAD15P P18
HT_CPU_NB_CAD_L15 U18 HT_RXCAD15N HT_TXCAD15N M18 HT_NB_CPU_CAD_L15 HT_TXCALP RES CHIP 1.21K 1/16W +-1%(0402)
R641 R641 P/N : CS21212FB18
HT_CPU_NB_CLK_H0 T22 HT_RXCLK0P HT_TXCLK0P H24 HT_NB_CPU_CLK_H0 SI-2 modified 301 ohm 1% 1.21k ohm 1%
HT_CPU_NB_CLK_L0 T23 HT_RXCLK0N HT_TXCLK0N H25 HT_NB_CPU_CLK_L0 -- follow AMD HT_TXCALN
HT_CPU_NB_CLK_H1 AB23 L21 HT_NB_CPU_CLK_H1
HT_CPU_NB_CLK_L1 HT_RXCLK1P HT_TXCLK1P HT_NB_CPU_CLK_L1 check list to
AA22 HT_RXCLK1N HT_TXCLK1N L20
change part HT_RXCALP RES CHIP 301 1/16W +-1%(0402)
SI-2 modified HT_CPU_NB_CTL_H0 M22 HT_RXCTL0P HT_TXCTL0P M24 HT_NB_CPU_CTL_H0 number 300 ohm R655 R655 P/N : CS13012FB14
-- follow AMD HT_CPU_NB_CTL_L0 M23 M25 HT_NB_CPU_CTL_L0 to 301 ohm 301 ohm 1% 1.21k ohm 1%
HT_RXCTL0N HT_TXCTL0N
check list to
HT_CPU_NB_CTL_H1 R21 HT_RXCTL1P HT_TXCTL1P P19 HT_NB_CPU_CTL_H1 HT_RXCALN
C HT_CPU_NB_CTL_L1 R20 R18 HT_NB_CPU_CTL_L1 C
change part HT_RXCTL1N HT_TXCTL1N
R655 R641
number 300 ohm R533 301/F_4 HT_RXCALP C23 HT_RXCALP HT_TXCALP B24 HT_TXCALP R534 301/F_4
to 301 ohm HT_RXCALN A24 B25 HT_TXCALN
HT_RXCALN HT_TXCALN
RS780(RX780)
U27
SPM_BA0 L2 BA0 DQ15 B9 SPM_DQ15 This block is for UMA RS780 only , RX780 can
SPM_BA1 L3 B1 SPM_DQ14
SPM_A12
BA1 DQ14
DQ13 D9 SPM_DQ9
SPM_DQ12
remove all component
R2 A12 DQ12 D1
SPM_A11 P7 D3 SPM_DQ8
SPM_A10 A11 DQ11 SPM_DQ10
M2 A10/AP DQ10 D7
SPM_A9 P3 C2 SPM_DQ13 +1.8V
SPM_A8 A9 DQ9 SPM_DQ11
P8 A8 DQ8 C8
SPM_A7 SPM_DQ5 +1.8V_MEM_VDDQ
SPM_A6
P2 A7 DQ7 F9
SPM_DQ3 U32D 40mils wdith or more
N7 A6 DQ6 F1
SPM_A5 N3 H9 SPM_DQ4 PAR 4 OF 6 R487 *0_6
SPM_A4 A5 DQ5 SPM_DQ1 SPM_A0 SPM_DQ0
N8 A4 DQ4 H1 AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
SPM_A3 N2 H3 SPM_DQ0 SPM_A1 AE16 AA20 SPM_DQ1
SPM_A2 A3 DQ3 SPM_DQ7 SPM_A2 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) SPM_DQ2 C70 C738 C76
M7 A2 DQ2 H7 V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
SPM_A1 M3 G2 SPM_DQ2 SPM_A3 AE15 Y19 SPM_DQ3 *1U/10V_4 *10U/6.3V_8 *10U/6.3V_8
SPM_A0 A1 DQ1 SPM_DQ6 SPM_A4 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) SPM_DQ4
M8 A0 DQ0 G8 AA12 MEM_A4(NC) MEM_DQ4(NC) V17
SPM_A5 AB16 AA17 SPM_DQ5
SPM_A6 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) SPM_DQ6
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
SPM_CLKN K8 A9 +1.8V_MEM_VDDQ SPM_A7 AD14 Y15 SPM_DQ7
R56 *100_4 SPM_CLKP CK VDDQ1 SPM_A8 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) SPM_DQ8
B
J8 CK VDDQ2 C1 AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20 B
C3 SPM_A9 AD15 AD19 SPM_DQ9
SBD_MEM/DVO_I/F
Within 200mils SPM_CKE VDDQ3 SPM_A10 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) SPM_DQ10
K2 CKE VDDQ4 C7 AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
C9 SPM_A11 AE13 AC18 SPM_DQ11 C87 C77 C74
VDDQ5 T24 MEM_A11(NC) MEM_DQ11/DVO_D7(NC)
E9 SPM_A12 AC14 AB20 SPM_DQ12 *0.1U/10V_4 *0.1U/10V_4 *1U/10V_4
VDDQ6 SPM_A13 MEM_A12(NC) MEM_DQ12(NC) SPM_DQ13
VDDQ7 G1 Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
SPM_CS# L8 G3 AC22 SPM_DQ14
CS VDDQ8 SPM_BA0 MEM_DQ14/DVO_D10(NC) SPM_DQ15
VDDQ9 G7 AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
SPM_WE# K3 G9 SPM_BA1 AE17
WE VDDQ10 SPM_BA2 MEM_BA1(NC) SPM_DQS0P
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
SPM_RAS# K7 A1 W18 SPM_DQS0N
RAS VDD1 L76 SPM_RAS# MEM_DQS0N/DVO_IDCKN(NC) SPM_DQS1P
VDD2 E1 W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
SPM_CAS# L7 CAS VDD3 J9 SPM_CAS# Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21 SPM_DQS1N IOPLLVDD18 - memory PLL
M9 SPM_WE# AD18 not applicable to RX780
SPM_DM0 VDD4 *BLM18PG181SN1D(180,1.5A)_6 SPM_CS# MEM_WEb(NC) SPM_DM0
F3 LDM VDD5 R1 AB13 MEM_CSb(NC) MEM_DM0(NC) W17
SPM_DM1 B3 SPM_CKE AB18 AE19 SPM_DM1
UDM MEM_VDDQ_VDDL SPM_ODT MEM_CKE(NC) MEM_DM1/DVO_D8(NC)
VDDL J1 V14 MEM_ODT(NC)
J7 AE23 +1.8_IOPLLVDD18_NB Del L77, L78
SPM_ODT VSSDL SPM_CLKP IOPLLVDD18(NC) +1.1V_IOPLLVDD
K9 ODT V15 MEM_CKP(NC) IOPLLVDD(NC) AE24
SPM_CLKN W14 MEM_CKN(NC)
for TP on PV
+1.8V_MEM_VDDQ C757 AD23 C762 C763
IOPLLVSS(NC)
SPM_DQS0P F7 LDQS
*1U/10V_4 R502 *40.2/F_4 SPM_COMPP AE12
MEM_COMPP(NC)
*2.2U/6.3V_6 IOPLLVDD- memory PLL
SPM_DQS0N E8 A7 R501 *40.2/F_4 SPM_COMPN AD12 AE18 SPM_VREF1 *2.2U/6.3V_6 not applicable to RX780
LDQS VSSQ1 MEM_COMPN(NC) MEM_VREF(NC)
VSSQ2 B2 +1.8V_MEM_VDDQ
B8 RS780(RX780)
VSSQ3
VSSQ4 D2
SPM_DQS1P B7 D8 R498 *1K_4 R497 *1K_4
C95 R63 SPM_DQS1N UDQS VSSQ5
A8 UDQS VSSQ6 E7
*0.1U/10V_4 *1K_4 F2
VSSQ7
VSSQ8 F8
A SPM_VREF J2 H2 C775 *0.1U/10V_4 C774 *0.1U/10V_4 +1.8V_MEM_VDDQ A
VREF VSSQ9
VSSQ10 H8
A2 NC#A2
C89 R61 E2 A3
*0.1U/10V_4 *1K_4 SPM_BA2 NC#E2 VSS1
L1 NC#L1 VSS2 E3
R3 J3
PROJECT : QT8
NC#R3 VSS3
R7 NC#R7 VSS4 N1

R8 NC#R8 VSS5 P9
*HYB18T512161B2F-25 Size Document Number Rev

Custom 1A
RS740/RS780-HT LINK I/F 1/5
NB5/RD5
5 4 3 2 1
5 4 3 2 1
PEG_RX15
PEG_RX#15
PEG_RX14
PEG_RX#14
PEG_RX13
PEG_RX#13
D4
C4
A3
B3
C2
U32B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
PART 2 OF 6
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
A5
B5
A4
B4
C3
C_PEG_TX15
C_PEG_TX#15
C_PEG_TX14
C_PEG_TX#14
C_PEG_TX13
C_PEG_TX#13
C360
C359
C362
C361
C343
C354
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
PEG_TX15
PEG_TX#15
PEG_TX14
PEG_TX#14
PEG_TX13
PEG_TX#13
17 PEG_RX#[15:0]
17 PEG_RX[15:0]
PEG_RX#[15:0]
PEG_RX[15:0]
Close to North Bridge

PEG_TX#[15:0]
PEG_TX[15:0]
PEG_TX#[15:0] 17
PEG_TX[15:0] 17
9
C1 GFX_RX2N GFX_TX2N B2
PEG_RX12 E5 D1 C_PEG_TX12 C351 0.1U/10V_4 PEG_TX12
PEG_RX#12 GFX_RX3P GFX_TX3P C_PEG_TX#12 C350 0.1U/10V_4 PEG_TX#12
F5 GFX_RX3N GFX_TX3N D2
PEG_RX11 G5 E2 C_PEG_TX11 C814 0.1U/10V_4 PEG_TX11
G6 GFX_RX4N GFX_TX4N E1
PEG_RX10 H5 F4 C_PEG_TX10 C810 0.1U/10V_4 PEG_TX10
H6 GFX_RX5N GFX_TX5N F3
D PEG_RX9 J6 F1 C_PEG_TX9 C811 0.1U/10V_4 PEG_TX9 C_PEG_TX15 D
GFX_RX6P GFX_TX6P C_PEG_TX15 23
PEG_RX#9 J5 F2 C_PEG_TX#9 C813 0.1U/10V_4 PEG_TX#9 C_PEG_TX#15
GFX_RX6N GFX_TX6N C_PEG_TX#15 23
PEG_RX8 J7 H4 C_PEG_TX8 C806 0.1U/10V_4 PEG_TX8
PEG_RX#8 GFX_RX7P GFX_TX7P C_PEG_TX#8 C805 0.1U/10V_4 PEG_TX#8 C_PEG_TX14
J8 H3
PCIE I/F GFX

GFX_RX7N GFX_TX7N C_PEG_TX14 23
PEG_RX7 L5 H1 C_PEG_TX7 C804 0.1U/10V_4 PEG_TX7 C_PEG_TX#14
GFX_RX8P GFX_TX8P C_PEG_TX#14 23
PEG_RX#7 L6 H2 C_PEG_TX#7 C800 0.1U/10V_4 PEG_TX#7
PEG_RX6 GFX_RX8N GFX_TX8N C_PEG_TX6 C798 0.1U/10V_4 PEG_TX6 C_PEG_TX13
M8 GFX_RX9P GFX_TX9P J2 C_PEG_TX13 23
PEG_RX#6 L8 J1 C_PEG_TX#6 C801 0.1U/10V_4 PEG_TX#6 C_PEG_TX#13
GFX_RX9N GFX_TX9N C_PEG_TX#13 23
PEG_RX5 P7 K4 C_PEG_TX5 C791 0.1U/10V_4 PEG_TX5
PEG_RX#5 GFX_RX10P GFX_TX10P C_PEG_TX#5 C795 0.1U/10V_4 PEG_TX#5 C_PEG_TX12
M7 GFX_RX10N GFX_TX10N K3 C_PEG_TX12 23
PEG_RX4 P5 K1 C_PEG_TX4 C792 0.1U/10V_4 PEG_TX4 C_PEG_TX#12
GFX_RX11P GFX_TX11P C_PEG_TX#12 23
PEG_RX#4 M5 K2 C_PEG_TX#4 C796 0.1U/10V_4 PEG_TX#4
PEG_RX3 GFX_RX11N GFX_TX11N C_PEG_TX3 C788 0.1U/10V_4 PEG_TX3
R8 M4
PEG_RX#3 P8
GFX_RX12P
GFX_RX12N
GFX_TX12P
GFX_TX12N M3 C_PEG_TX#3 C785 0.1U/10V_4 PEG_TX#3 To HDMI CONN
PEG_RX2 R6 M1 C_PEG_TX2 C787 0.1U/10V_4 PEG_TX2
R5 GFX_RX13N GFX_TX13N M2
PEG_RX1 P4 N2 C_PEG_TX1 C778 0.1U/10V_4 PEG_TX1
P3 GFX_RX14N GFX_TX14N N1
PEG_RX0 T4 P1 C_PEG_TX0 C771 0.1U/10V_4 PEG_TX0
T3 GFX_RX15N GFX_TX15N P2
PCIE_RXP0 AE3 AC1 PCIE_TXP0_C C158 0.1U/10V_4

33 PCIE_RXP0 GPP_RX0P GPP_TX0P PCIE_TXP0 33
33 PCIE_RXN0
PCIE_RXN0 AD4 GPP_RX0N GPP_TX0N AC2 PCIE_TXN0_C C159 0.1U/10V_4
PCIE_TXN0 33 TO EPRESS CARD
PCIE_RXP1 AE2 AB4 PCIE_TXP1_C C131 0.1U/10V_4
36 PCIE_RXN1
PCIE_RXN1 AD3 GPP_RX1N GPP_TX1N AB3 PCIE_TXN1_C C130 0.1U/10V_4
PCIE_TXN1 36 TO WLAN
PCIE_RXP6_LAN AD1 AA2 PCIE_TXP6_C C149 0.1U/10V_4
31 PCIE_RXP6_LAN GPP_RX2P GPP_TX2P PCIE_TXP6_LAN 31
31 PCIE_RXN6_LAN
PCIE_RXN6_LAN AD2
GPP_RX2N PCIE I/F GPP GPP_TX2N AA1 PCIE_TXN6_C C148 0.1U/10V_4
PCIE_TXN6_LAN 31 TO PCIE-LAN
PCIE_RXP3 V5 Y1 PCIE_TXP3_C C772 0.1U/10V_4
36 PCIE_RXN3
PCIE_RXN3 W6 GPP_RX3N GPP_TX3N Y2 PCIE_TXN3_C C773 0.1U/10V_4
PCIE_TXN3 36 TO TV TUNNER
T223 PCIE_RXP4 U5 Y4 PCIE_TXP4_C
C GPP_RX4P GPP_TX4P T224 C
T225 PCIE_RXN4 U6 Y3 PCIE_TXN4_C
GPP_RX4N GPP_TX4N T226
PCIE_RXP5 U8 V1 PCIE_TXP5_C C139 0.1U/10V_4
26 PCIE_RXN5
PCIE_RXN5 U7 GPP_RX5N GPP_TX5N V2 PCIE_TXN5_C C140 0.1U/10V_4
PCIE_TXN5 26 TO PCIE CARD READER
AA8 AD7 A_TX0P_C C766 0.1U/10V_4 PCIE_NB_SB_TX0P 12
12 PCIE_SB_NB_RX0P SB_RX0P SB_TX0P
Y8 AE7 A_TX0N_C C767 0.1U/10V_4 PCIE_NB_SB_TX0N 12
12 PCIE_SB_NB_RX0N SB_RX0N SB_TX0N
AA7 AE6 A_TX1P_C C765 0.1U/10V_4 PCIE_NB_SB_TX1P 12
Y7 AD6 A_TX1N_C C764 0.1U/10V_4 PCIE_NB_SB_TX1N 12
AA5 PCIE I/F SB AB6 A_TX2P_C C150 0.1U/10V_4 PCIE_NB_SB_TX2P 12
AA6 AC6 A_TX2N_C C151 0.1U/10V_4 PCIE_NB_SB_TX2N 12
W5 AD5 A_TX3P_C C754 0.1U/10V_4 PCIE_NB_SB_TX3P 12
Y5 AE5 A_TX3N_C C755 0.1U/10V_4 PCIE_NB_SB_TX3N 12
AC8 NB_PCIECALRP R491 1.27K/F_4
PCE_CALRP(PCE_BCALRP) NB_PCIECALRN R489 2K/F_4
PCE_CALRN(PCE_BCALRN) AB8 +1.1V
RS780(RX780)
RX780/RS740/RS780 difference table (PCIE LINK) RS780 Display Port Support (muxed on GFX)
RS740 RX780/RS780
GFX_TX0,TX1,TX2 and TX3
NB_PCIECALRP 562R (GND) 1.27K (GND) DP0
AUX0 and HPD0
GPP4 NC GPP4
GFX_TX4,TX5,TX6 and TX7
DP1
B GPP5 NC GPP5 AUX1 and HPD1 B
A A
PROJECT : QT8
Custom 1A
RS740/RS780-PCIE I/F 2/5
NB5/RD5
5 4 3 2 1
5 4 3 2 1
U32C
RX780: Powered from the 1.8-V
and driven by SB600 LDT_RST#,
SB700 LDT_RST# or A_RST#.
RS780: Powered from the 3.3-V
and driven by SB600 LDT_RST#,
rail
or
rail
or
+3V_AVDD_NB
+1.8V_AVDDDI_NB
+1.8V_AVDDQ_NB
F12
E12
F14
G15
H15
H14
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
PART 3 OF 6
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
A22
B22
A21
B21
B20
A20
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
LA_DATAP3
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
23
23
23
23
23
23
10
SB700 LDT_RST# or A_RST#. TXOUT_L3P(NC) A19 T159
S-CD1 E17 B19 LA_DATAN3
CRT/TVOUT
C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) T157
R109 for UAM use 140 ohm F17 Y(DFT_GPIO2) LB_DATAP0
RX780 F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18 LB_DATAP0 23
R157 *0_4 NB_RST#_IN A18 LB_DATAN0
3,12 CPU_LDT_RST# TXOUT_U0N(NC) LB_DATAN0 23
18,24 CRT_R R446 *0_4 CRT_R_1 G18 A17 LB_DATAP1
RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3) LB_DATAP1 23
RS780 R109 *150/F_4 G17 B17 LB_DATAN1
REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) LB_DATAN1 23
R160 0_4 18,24 CRT_G R445 *0_4 CRT_G_1 E18 D20 LB_DATAP2
12 NB_PLTRST# GREEN(DFT_GPIO1) TXOUT_U2P(NC) LB_DATAP2 23
R110 *150/F_4 F18 D21 LB_DATAN2
GREENb(NC) TXOUT_U2N(NC) LB_DATAN2 23
D North Bridge RESET 18,24 CRT_B R444 *0_4 CRT_B_1 E19 D18 LB_DATAP3 D
BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5) T163
R111 *150/F_4 F19 D19 LB_DATAN3
BLUEb(NC) TXOUT_U3N(NC) T160
R549 *0_4 HSYNC_INT A11 B16 LA_CLK
18,19,24 HSYNC_COM DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1) LA_CLK 23
R540 *0_4 VSYNC_INT B11 A16 LA_CLK#
18,19,24 VSYNC_COM DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3) LA_CLK# 23
R133 *0_4 DDCDATA_INT E8 D16 LB_CLK
18,24 DDCDATA DAC_SDA(PCE_TCALRN) TXCLK_UP(PCIE_RESET_GPIO4) LB_CLK 23
R134 *0_4 DDCCLK_INT F8 D17 LB_CLK#
18,24 DDCCLK DAC_SCL(PCE_RCALRN) TXCLK_UN(PCIE_RESET_GPIO1) LB_CLK# 23
R119 *715/F_6 DAC_RSET_NB G14 DAC_RSET(PWM_GPIO1) +1.8V_VDDLTP18_NB
VDDLTP18(NC) A13
+1.1V_PLLVDD A12 B13
+1.8V_PLLVDD18 PLLVDD(NC) VSSLTP18(NC)
D14
LVTM
PLLVDD18(NC) +1.8V_VDDLT_18_NB
B12 A15
PLL PWR
PLLVSS(NC) VDDLT18_1(NC)
VDDLT18_2(NC) B15
+1.8V_VDDA18HTPLL H17 A14 +3V_VDLT33_NB
VDDA18HTPLL VDDLT33_1(NC)
VDDLT33_2(NC) B14
+1.8V_VDDA18PCIEPLL D7 VDDA18PCIEPLL1
E7 VDDA18PCIEPLL2 VSSLT1(VSS) C14
VSSLT2(VSS) D15
NB_RST#_IN D8 C16
NB_PWRGD_IN SYSRESETb VSSLT3(VSS)
16 NB_PWRGD_IN A10 POWERGOOD VSSLT4(VSS) C18
NB_LDT_STOP# C10 C20
PM
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
C12 ALLOW_LDTSTOP VSSLT6(VSS) E20
VSSLT7(VSS) C22
NBHT_REFCLKP C25
2 NBHT_REFCLKP HT_REFCLKP
2 NBHT_REFCLKN
NBHT_REFCLKN C24 HT_REFCLKN I RS780 only
R117 0_4 NB_REFCLK_P E11
2 EXT_NB_OSC REFCLK_P/OSCIN(OSCIN)
CLOCKs
NB_REFCLK_N F11 I E9 R132 *0_4 DISP_ON
REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) DISP_ON 19,23
+1.1V F7 R126 *0_4 LVDS_BLON
LVDS_BLON(PCE_RCALRP) LVDS_BLON 18,23
R125 RS780 RS780 R120 NBGFX_CLKP T2 G12 R118 *0_4 DPST_PWM
GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) DPST_PWM 19,23
4.7K_4 4.7K_4 NBGFX_CLKN T1 I/O
GFX_REFCLKN
2 NBGFX_CLKP
NBGPP_CLKP U1
2 NBGFX_CLKN GPP_REFCLKP
Del NBGPP CLK NBGPP_CLKN U2 I/O R121 *1.27K/F_4
T168 GPP_REFCLKN
C T169 For RX780 only C
SBLINK_CLKP V4 R127 *1.27K/F_4
2 SBLINK_CLKP GPPSB_REFCLKP(SB_REFCLKP)
SBLINK_CLKN V3
2 SBLINK_CLKN GPPSB_REFCLKN(SB_REFCLKN)
+3V R536 4.7K_4 HDTV_DET
18,23 EDIDDATA
R547 *0_4 NB_I2C_DATA A9 I2C_DATA
R545 UMA only
R546 *0_4 NB_I2C_CLK TMDS_HPD0 *0_4
RS780 only R539 4.7K_4 NB_I2C_DATA
18,23 EDIDCLK
R537 *0_4 HDTV_DET
B9
B8
I2C_CLK MIS. TMDS_HPD(NC) D9
D10 TMDS_HPD1
TMDS_HPD 18,23
23 HDMI_DDC_DATA DDC_DATA/AUX0N(NC) HPD(NC) T162
R544 *0_4 RS740_DFT_GPIO0 A8
23 HDMI_DDC_CLK DDC_CLK/AUX0P(NC)
R538 4.7K_4 NB_I2C_CLK RS740_DFT_GPIO1 B7 D12 SUS_STAT#_NB R131 0_4
T161 AUX1P(NC) TVCLKIN(PWM_GPIO5) SUS_STAT# 13
T158 A7 AUX1N(NC)
AE8 R_NB_THRMDA
THERMALDIODE_P T136
R27 0_4 STRP_DATA B10 AD8 R_NB_THRMDC
39 DYN_PWR_EN STRP_DATA THERMALDIODE_N T135
G11 RSVD TESTMODE D13 TEST_EN
selects Loading of straps from RS780_AUX_CAL C8 R541

T164 AUX_CAL(NC)
EPROM 1.82K/F_4
1 : use default vaule , default RS780(RX780)
0 : I2C Master can load strap
values from EEPROM
if connected, or use default
values if not connected BLM18PG181SN1D(180,1.5A)_6
RX780 --RS780_AUX_CAL RX780 RX780 -->NC / RS780 --- ADD +1.1V_PLLVDD
+1.1V
RS780 -- SUS_ATAT +3V L35 +3V_AVDD_NB L82
RS780_AUX_CAL R543 3K_4 BLM18PG181SN1D(180,1.5A)_6 PLLVDD - Graphics PLL +1.8V
not applicable to
AVDD-DAC Analog C842
RX780
BLM18PG181SN1D(180,1.5A)_6
not applicable to RX780 C340 2.2U/6.3V_6 +1.8V_VDDLTP18_NB
2.2U/6.3V_6 L83
C841 VDDLTP18 - LVDS or DVI/HDMI PLL
2.2U/6.3V_6 not applicable to RX780
+1.8V
Enables Debug Bus acess
B through memory T/O pads and GPIO. RS780 +1.8V
B
BLM21PG221SN1D(220,100M,2A)_8
0 : Enable RS780 , Default VSYNC_COM R124 3K_4 L33 +1.8V_PLLVDD18 R107 0_6 +1.8V_AVDDDI_NB AVDDI-DAC Digital +1.8V_VDDLT_18_NB
+3V
1 : Disable RS780 BLM18PG181SN1D(180,1.5A)_6 not applicable to RX780 L85
(RS780 use VSYNC#) VDDLT18 - LVDS or
C321 DVI/HDMI digital
C405 C333 2.2U/6.3V_6 C846 C838
10U/6.3V_8 not applicable to
2.2U/6.3V_6
4.7U/6.3V_6 0.1U/10V_4 RX780
BLM18PG181SN1D(180,1.5A)_6 AVDDQ-DAC Bandgap Reference
PLLVDD18 - Graphics PLL +1.8V_AVDDQ_NB not applicable to RX780
not applicable to RX780 L34
Indicates if memory Side port RS780
is available or not C349
HSYNC_COM R129 3K_4 +3V 2.2U/6.3V_6
0: available RS780 , Default
1: Not available RS780 R136 *3K_4
( RS780 use HSYNC#)
R566 *0_6
RX780 +1.8V +VDDG_NB
+1.8V
VDDA18PCIEPLL -PCIE PLL +1.8V +VDDG_NB
R565 0_6
For extrnal EEPROM Debug only 20mils width
RS780/RX780 L32 +1.8V_VDDA18PCIEPLL RS780 RS780
+3V
Q37 R556 RS780
2
STRP_DATA R548 10K/F_4 +VDDG_NB BLM18PG181SN1D(180,1.5A)_6 BSS138_NL/SOT23 4.7K_4
C358 1 3 NB_LDT_STOP# L84

3,12 CPU_LDT_STOP#
R558 *10K/F_4 2.2U/6.3V_6 +3V +3V_VDLT33_NB
*BLM21PG221SN1D(220,100M,2A)_8 C844
R555 *0_4
VDDA18HTPLL -HT LINK PLL RX780 *2.2U/6.3V_6
A A
20mils width
L31 +1.8V_VDDA18HTPLL +VDDG_NB
Enables Debug Bus acess RX780 +1.8V
RS780 VDDLT33 - LVDS or DVI/HDMI ANALOG
through memory T/O pads and GPIO. BLM18PG181SN1D(180,1.5A)_6 RS780 RS740 only
R557
1 : Enable RX780 , Default S-CD1 R810 *3K_4 C356 Q38 4.7K_4
2
0 : Disable RX780 2.2U/6.3V_6 BSS138_NL/SOT23
Reserved only 3 CPU_LDT_REQ#

R568 0_4 1 3 NB_ALLOW_LDTSTOP
PROJECT : QT8
R564 *0_4 Size Document Number Rev
12 ALLOW_LDTSTOP Custom
RS740/RS780-SYSTEM I/F 3/5 1A
RX780 NB5/RD5
5 4 3 2 1
5 4 3 2 1
11
AE14
AC3
AC4
M11
AA4
AB5
AB1
AB7
AE1
AE4
AB2
D11
E14
E15
K14
L15
J15
J12
W1
W2
W4
W7
W8
M6
G1
G2
G4
G8
D3
D5
H7
R7
N4
R1
R2
R4
U4
A2
B1
E4
P6
V7
V8
V6
Y6
L1
L2
L4
L7
RX780/RS780 POWER DIFFERENCE TABLE
J4
U32F
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
PIN NAME RX780 RS780 PIN NAME RX780 RS780
VDDHT +1.1V +1.1V IOPLLVDD NC +1.1V
VDDHTRX +1.1V +1.1V AVDD NC +3.3V

PART 6/6
D D
GROUND VDDHTTX +1.2V +1.2V AVDDDI NC +1.8V
VDDA18PCIE +1.8V +1.8V AVDDQ NC +1.8V
VDDG18 +1.8V +1.8V PLLVDD NC +1.1V

VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
VDD18_MEM NC +1.8V PLLVDD18 NC +1.8V
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VDDPCIE +1.1V +1.1V VDDA18PCIEPLL +1.8V +1.8V
VDDC +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V

A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VDD_MEM NC +1.8V/1.5V VDDLTP18 NC +1.8V
VDDG33 NC +3.3V VDDLT18 NC +1.8V
IOPLLVDD18 NC +1.8V VDDLT33 NC NC
+1.1V
VDDHT - HT
C LINK digital
+1.1V 2A for RS780M U32E
VDDPCIE - PCIE-E Main power C
I/O for 0.6A L72 +1.1V_VDDHT +1.1V_VDD_PCIE

0.7A R542 0_8
J17 VDDHT_1 VDDPCIE_1 A6 +1.1V
RX780/RS780 BLM21PG221SN1D(220,100M,2A)_8 K16 PART 5/6 B6
VDDHT_2 VDDPCIE_2
L16 VDDHT_3 VDDPCIE_3 C6
C770 C274 C313 C280 M16 D6 C275 C337 C318 C328 C845
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHT_4 VDDPCIE_4 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 4.7U/6.3V_6
P16 VDDHT_5 VDDPCIE_5 E6
VDDHTRX - HT R16 VDDHT_6 VDDPCIE_6 F6
LINK RX I/O for T16 VDDHT_7 VDDPCIE_7 G7
RX780/RS780 0.45A L81 +1.1V_VDDHTRX VDDPCIE_8 H8
H18 VDDHTRX_1 VDDPCIE_9 J9
BLM21PG221SN1D(220,100M,2A)_8 G19 K9
VDDHTRX_2 VDDPCIE_10
F20 VDDHTRX_3 VDDPCIE_11 M9
C847 C323 C843 C839 E21 L9
4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTRX_4 VDDPCIE_12
D22 VDDHTRX_5 VDDPCIE_13 P9
B23 VDDHTRX_6 VDDPCIE_14 R9
A23 VDDHTRX_7 VDDPCIE_15 T9
L12
0.5A +1.2V 2A for RS780M+SB700 +1.2V_VDDHTTX VDDPCIE_16 V9
+1.2V AE25 VDDHTTX_1 VDDPCIE_17 U9
BLM21PG221SN1D(220,100M,2A)_8 AD24 VDDHTTX_2 7A VDDC - Core Logic power
AC23 VDDHTTX_3 VDDC_1 K12 +1.1V_DYN
+1.35V L13 C124 C195 C194 C249 C199 AB22 J14
*BLM21PG221SN1D(220,100M,2A)_8 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDHTTX_4 VDDC_2
AA21 VDDHTTX_5 VDDC_3 U16
+1.35V for VDDHTTX - HT Y20 VDDHTTX_6 VDDC_4 J11 C251 C292 C297 C303 C59
A1-1 chip LINK TX I/O for W19 K15 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8
POWER
VDDHTTX_7 VDDC_5
bug , A1-2 RX780/RS780 V18 VDDHTTX_8 VDDC_6 M12
U17 L14
can remove T17
VDDHTTX_9 VDDC_7
L11
VDDHTTX_10 VDDC_8
R17 VDDHTTX_11 VDDC_9 M13
P17 M15
B +1.8V 1A for RS780M+SB700 M17
VDDHTTX_12
VDDHTTX_13
VDDC_10
VDDC_11 N12
B
L22
600mA +1.8V_VDDA18PCIE VDDC_12 N14
C281 C278 C250 C60
+1.8V J10 VDDA18PCIE_1 VDDC_13 P11
P10 P13 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8
BLM21PG221SN1D(220,100M,2A)_8 VDDA18PCIE_2 VDDC_14
K10 VDDA18PCIE_3 VDDC_15 P14
VDDA18PCIE - C188 C175 C258 C209 C302 C234 M10 VDDA18PCIE_4 VDDC_16 R12
PCIE TX stage 4.7U/6.3V_6 4.7U/6.3V_6 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 L10 R15
VDDA18PCIE_5 VDDC_17
I/O for W9 VDDA18PCIE_6 VDDC_18 T11
RX780/RS780
H9 VDDA18PCIE_7 VDDC_19 T15 VDD_MEM For UMA RS780 only
T10 U12
R10
T14 Not applicable to RX780
Y9 VDDA18PCIE_10 VDDC_22 J16 memory I/O transform
AA9 VDDA18PCIE_11 +1.8V_VDD_MEM
1.8V(0.15A) L23
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10 +1.8V
0.005A AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
VDD18 - RS780 I/O +1.8V R122 0_6 AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11 C192 C179 C172 C216 C153 BLM21PG221SN1D(220,100M,2A)_8
transform U10 AD10 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 4.7U/6.3V_6
C317 VDDA18PCIE_15 VDD_MEM4(NC)
VDD_MEM5(NC) AB10
1U/10V_4 +1.8V_VDDG18_NB F9 AC10
VDDG18_1(VDD18_1) VDD_MEM6(NC) RS780
G9 VDDG18_2(VDD18_2) +3V_VDDG33 R123 0_6
3.3V(0.03A)
R499 0_6
0.005A +1.8V_VDD18_MEM
AE11 VDD18_MEM1(NC) VDDG33_1(NC) H11 +3V
+1.8V AD11 VDD18_MEM2(NC) VDDG33_2(NC) H12
C336 C329 VDD33 - 3.3V I/O
VDD18_MEM For UMA RS780 only C769 RS780(RX780) 0.1U/10V_4 0.1U/10V_4
Not applicable to RX780
1U/10V_4
Not applicable to RX780
memory I/O transform
A A
PROJECT : QT8
Custom 1A
RS740/RS780-POWER5/5
NB5/RD5
5 4 3 2 1
5 4 3 2 1
10
17
NB_PLTRST#
PCIE_RST#
R250
R252
R312
33_4
33_4
33_4 Del R639, R640, R641, R642 on PV
12
26 CARD_PLTRST#
31 LAN_PLTRST# R251 33_4 U37A
R241 33_4
33 EPRESS_PLTRST#
R660 33_4 A_RST#_SB N2
SB700 P4
36 MINI_PLTRST# A_RST# PCICLK0 T108
Part 1 of 5 P3
PCI CLKS
PCICLK1 T214
9 PCIE_SB_NB_RX0P C869 0.1U/10V_4 A_RX0P_C V23 P1 PCI_CLK2_R PCI_CLK_TPM 16
C868 0.1U/10V_4 A_RX0N_C PCIE_TX0P PCICLK2 PCI_CLK3_R
D 9 PCIE_SB_NB_RX0N V22 PCIE_TX0N PCICLK3 P2 PCI_CLK3 16 D
PLACE THESE 9 PCIE_SB_NB_RX1P C865 0.1U/10V_4 A_RX1P_C V24 T4 PCI_CLK4_R PCI_CLK4 16
C864 0.1U/10V_4 A_RX1N_C PCIE_TX1P PCICLK4 PCI_CLK5_R
9 PCIE_SB_NB_RX1N V25 PCIE_TX1N PCICLK5/GPIO41 T3 PCI_CLK5 16
PCIE AC 9 PCIE_SB_NB_RX2P C871 0.1U/10V_4 A_RX2P_C U25 PCIE_TX2P
To RS780
C870 0.1U/10V_4 A_RX2N_C U24
COUPLING CAPS 9 PCIE_SB_NB_RX2N
C867 0.1U/10V_4 A_RX3P_C PCIE_TX2N
9 PCIE_SB_NB_RX3P T23 PCIE_TX3P
CLOSE TO U600 9 PCIE_SB_NB_RX3N C866 0.1U/10V_4 A_RX3N_C T22 PCIE_TX3N PCIRST# N1 PCIRST#_L R643 33_4 PCIRST# PCIRST# 35
PCI EXPRESS INTERFACE

PCIE_NB_SB_TX0P U22
9 PCIE_NB_SB_TX0P PCIE_RX0P
PCIE_NB_SB_TX0N U21 U2
9 PCIE_NB_SB_TX0N PCIE_RX0N AD0
PCIE_NB_SB_TX1P U19 P7
9 PCIE_NB_SB_TX1P PCIE_RX1P AD1
PCIE_NB_SB_TX1N V19 V4
PCIE_NB_SB_TX2P R20 T1 +3V
PCIE_NB_SB_TX2N R21 V3
PCIE_NB_SB_TX3P R18 U1
PCIE_NB_SB_TX3N R17 V1 PE_GPIO1 R294 8.2K_4
AD7 V2
R581 562/F_4 PCIE_CALRP_SB T25 T2 R299 *8.2K_4
R587 2.05K/F_4 PCIE_CALRN_SB PCIE_CALRP AD8
+1.2V_PCIE_VDDR T24 PCIE_CALRN AD9 W1
AD10 T9
+1.2V L44 BLM18PG181SN1D(180,1.5A)_6 +1.2V_PCIE_PVDD P24 R6 SB_GPIO65 R274 *100K/F_4
PCIE_PVDD AD11
40mA AD12 R7
PCIE_PVDD-- PCIE PLL POWER P25 PCIE_PVSS AD13 R5
C485 C503 U8
10U/6.3V_8 1U/10V_4 AD14 R809 8.2K_4
AD15 U5 +3V
AD16 Y7
AD17 W8
AD18 V9
AD19 Y8
AD20 AA8
C
AD21 Y4 C
AD22 Y3
Y2 AD23
AD23 AD23 16
AA2 AD24
AD24 AD24 16
AB4 AD25 change D21, D20 type for PV
AD25 AD25 16
SBSRC_CLKP N25 AA1 AD26
2 SBSRC_CLKP PCIE_RCLKP/NB_LNK_CLKP AD26 AD26 16
SBSRC_CLKN N24 AB3 AD27
2 SBSRC_CLKN PCIE_RCLKN/NB_LNK_CLKN AD27 AD27 16
AB2 AD28
AD28 AD28 16
K23 AC1
PCI INTERFACE
NB_DISP_CLKP AD29
K22 NB_DISP_CLKN AD30 AC2
AD1 D21
AD31
M24 NB_HT_CLKP CBE0# W2 SI-2 mofified for satify -- RB500V-40
+AVBAT
M25 NB_HT_CLKN 100MHZ CBE1# U7 remove R560 , add R796 ,R797 +3VPCU
CBE2# AA7 All the PCI bus has
P17
M18
CPU_HT_CLKP CBE3# Y1
AA6 build-in Pull-UP/Down 20MILR796 499/F_4 +3VRTC_1 R797 10_4 +3VRTC
CPU_HT_CLKN FRAME#
DEVSEL# W5 resistors
RTC_X1 D20
M23 AA5
20MIL 20MIL
+VCCRTC_2
SLT_GFX_CLKP IRDY# RB500V-40
Y8 M22 SLT_GFX_CLKN TRDY# Y5
U6 C906
PAR C907
3 2 J19 GPP_CLK0P STOP# W6
1U/10V_4
J18 GPP_CLK0N PERR# W4
V7 SERR#
SERR# 35
1U/10V_4
20MIL
SERR# R298
L20 GPP_CLK1P REQ0# AC3
4 1 RTC_X2 L19 GPP_CLK1N REQ1# AD4 SI-2 Modified-- for power leakage issue
R632 AB7 Del R783 for 0_4
CLOCK GENERATOR
REQ2# R187 0_4
32.768KHZ M19 GPP_CLK2P REQ3#/GPIO70 AE6 RF_OFF# 36 TP on PV
M20 GPP_CLK2N REQ4#/GPIO71 AB6 D3E GPIO# 26
*20M_6 R626 20M_6 AD2
+BAT
GNT0#
SI-2 Modified-- Add GPIO pin for control D3E wake up ( need low 1ms
B
N22
P22
GPP_CLK3P GNT1# AE4
AD5 for Jmicron request)
20MIL B
C900 C899 GPP_CLK3N GNT2# PE_GPIO1

GNT3#/GPIO72 AC6
18P/50V_4 18P/50V_4 L18 AE5 R631 0_4 LCD_BK 23
25M_48M_66M_OSC GNT4#/GPIO73
1
AD6 CLKRUN#_R R629 0_4
CLKRUN# CLKRUN# 35
V5 BT1
LOCK# T94
R257 0_4 J21 25M_X1 INTE# BAT_CONN
AD3 T213
2
INTE#/GPIO33 INTF#
INTF#/GPIO34 AC4 T110 R589 change to 10 ohm on PV
AE2 INTG#
INTG#/GPIO35 T217
T74 J20 AE3 INTH#
25M_X2 INTH#/GPIO36 INTH# 28
LPC_CLK0 16
LPC_CLK1 16
If CPU have pull Hi ,this LPCCLK0 G22 LPC_CLK0 R243 22_4
PCLK_LPC_DEBUG 36
pin should be not need E22 LPC_CLK1 R589 10_4
LPCCLK1 PCLK_LPC_KB3920 35
RTC_X1 A3 H24 LAD0
RTC XTAL
X1 LAD0 LAD0 35,36

LAD1 H23 LAD1
LAD1 35,36 SI-2
+1.8V R232 *10K/F_4 J25 LAD2 C940 modified
LAD2 LAD2 35,36
PV-1 J24 LAD3
LPC
RTC_X2 LAD3 LFRAME#

LAD3 35,36
5.6P/50V_6 C939 -- for EMI
Modified B3 X2 LFRAME# H25 LFRAME# 35,36 suggestion
H22 LDRQ0#_SB 22P/50V_4
-- change LDRQ0# LDRQ1#_SB
T61
LDRQ1#/GNT5#/GPIO68 AB8 T90
to pull hi AD7 SB_GPIO65
BMREQ#/REQ5#/GPIO65 T107
to 3VS5 +3VS5 R588 10K/F_4
SERIRQ V15 SERIRQ
SERIRQ 35
for power SI-1 Modified - for EMI
ALLOW_LDTSTOP F23
leakage 10 ALLOW_LDTSTOP
CPU_PROCHOT# ALLOW_LDTSTP RTC_CLK
3 CPU_PROCHOT# F24 PROCHOT# RTCCLK C3 RTC_CLK 16
issue 3 CPU_PWRGD CPU_PWRGD F22 C2 INTRUDER_ALERT# R782 *1M/F_4 +AVBAT
RTC
LDT_PG INTRUDER_ALERT#
CPU
3,10 CPU_LDT_STOP# CPU_LDT_STOP# G25 LDT_STP# VBAT B2 +AVBAT +AVBAT SI-2 Modified--reserve
3,10 CPU_LDT_RST# CPU_LDT_RST# G24 LDT_RST#
INTRUDER_ALERT# Left not connected (Southbridge
A
20MIL 1
G3 has 50-kohm internal pull-up to VBAT).
A
SB700 *SHORT_ PAD1 C902

IC CTRL(528P) SB700 A11(218S7EALA11FG) 0.1U/10V_4
P/N : AJALA110T00
2
PROJECT : QT8
Custom 1A
SB700-PCIE/PCI/CPU/LPC 1/4
NB5/RD5
5 4 3 2 1
5 4 3 2 1
+3VSUS
R297
R240
NC only ,Can't be install
*2.2K_4
*2.2K_4
SB_TEST0
SB_TEST1
NEWCARD_DETECT E1
U37D
SB700 Part 4 of 5
13
33 NEWCARD_DETECT PCI_PME#/GEVENT4#
RI# E2 C8 CLK_48M_USB
T211 RI#/EXTEVNT0# USBCLK/14M_25M_48M_OSC CLK_48M_USB 2
R287 *2.2K_4 SB_TEST2 SLP_S2 H7 CLK_48M_USB
T99 SLP_S2/GPM9#
R271 *0_4 SUSB# F5 G8 USB_RCOMP_SB R267 11.8K/F_6
USB MISC
35 SUSB# SLP_S3# USB_RCOMP
R191 *0_4 SUSC# G1
35 SUSC# SLP_S5#
ACPI / WAKE UP EVENTS

R233 *0_4 DNBSWON# H2
+3VSUS 35 DNBSWON# PWR_BTN#
SB_PWRGD_IN H1
D 16 SB_PWRGD_IN PWR_GOOD D
SUS_STAT# K3 C554
10 SUS_STAT# SUS_STAT#
R289 *10K/F_4 SWI# SB_TEST2 H5 E6 USB_FSD13P *2.2P/50V_4
TEST2 USB_FSD13P T101
SI-2 modified add D3E function SB_TEST1 H4 TEST1 USB_FSD13N E7 USB_FSD13N
T199
SB_TEST0 H3 TEST0
USB 1.1
GATEA20 Y15 F7 USB_FDS12P
+3V SCL0/SDATA0 35 GATEA20 GA20IN/GEVENT0# USB_FSD12P T91
is 3V tolerance Clock gen/Robson/TV 35 RCIN# RCIN# W15 KBRST#/GEVENT1# USB_FSD12N E8 USB_FSD12N
T93
AMD datasheet define it tuner SCI# K4
35 SCI# LPC_PME#/GEVENT3#
KBSMI# K24 H11
R245 2.2K_4 PCLK_SMB /DDR2/DDR2 35 KBSMI#
GEVENT5# LPC_SMI#/EXTEVNT1# USB_HSD11P USBP11+ 36
thermal/Accelerometer T109 F1 S3_STATE/GEVENT5# USB_HSD11N J10 USBP11- 36 TV Min-Card
SYS_RST# J2 SYS_RESET#/GPM7#
R253 2.2K_4 PDAT_SMB
31,33,36 PCIE_WAKE#
PCIE_WAKE# H6 WAKE#/GEVENT8# USB_HSD10P E11 USBP10+ 36 for EMI & del R268
R211 *0_4 SWI# F2 F11 WLAN Min-Card
35 SWI#
R786 0_4 SB_THERMTRIP# J6
BLINK/GPM6# USB_HSD10N USBP10- 36 change 2.2P
3 CPU_THERMTRIP# SMBALERT#/THRMTRIP#/GEVENT2#
WD_PWRGD W14 A11
16 WD_PWRGD NB_PWRGD USB_HSD9P USBP9+ 30
+3VS5 USB_HSD9N B11 USBP9- 30 USB Connector
SCL1/SDATA1 is 3V/S5 tolerance 35 RSMRST#
R284 *0_4 RSMRST# D3 RSMRST#
AMD datasheet define it SI-2 modified -- Change lan USB_HSD8P C10 USBP8+ 30
disable control from SB to EC SB USB_HSD8N D10 USBP8- 30 USB Connector
R648 *2.2K_4 SB_SMBCLK1
R649 *2.2K_4 SB_SMBDATA1 reserve
T63 AE18 SATA_IS0#/GPIO10 USB_HSD7P G11 USBP7+ 33
SATA_IS1 AD18 H12 NEW CARD
T194 CLK_REQ3#/SATA_IS1#/GPIO6 USB_HSD7N USBP7- 33
R217 *0_4 LAN_DISABLE#_SB AA19
31,35 LAN_DISABLE# SMARTVOLT/SATA_IS2#/GPIO4
remove pull hi W17 CLK_REQ0#/SATA_IS3#/GPIO0 USB_HSD6P E12 USBP6+ 30
( chip internal SB_NWD_CLK_REQ# V17 E14 FINGERPRINT
T222 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 USB_HSD6N USBP6- 30
have pull hi ) W20 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40
R302 *0_4 ACZ_SPKR W21 C12
USB 2.0
27,28 ACZ_SPKR SPKR/GPIO2 USB_HSD5P USBP5+ 30
PCLK_SMB AA18 D12 BLUETOOTH
2,6,7,28,36 PCLK_SMB SCL0/GPOC0# USB_HSD5N USBP5- 30
PDAT_SMB W18
+3VS5 2,6,7,28,36 PDAT_SMB SDA0/GPOC1#
SCL2/SDATA2 is 3V/S5 tolerance SB_SMBCLK1 K1 SCL1/GPOC2# USB_HSD4P B12 USBP4+ 37
C AMD datasheet define it SB_SMBDATA1 K2 A12 Docking C
GPIO
SDA1/GPOC3# USB_HSD4N USBP4- 37
T69 AA20 DDC1_SCL/GPIO9
R222 *2.2K_4 SB_SCLK2 Y18 G12
T75 DDC1_SDA/GPIO8 USB_HSD3P USBP3+
R227 *2.2K_4 SB_SDATA2 PM_BATLOW# C1 G14 USB card reader or Touch screen
35 PM_BATLOW# LLB#/GPIO66 USB_HSD3N USBP3-
SES_INT Y19
T72 SHUTDOWN#/GPIO5
26 D3E_SCI# G5 DDR3_RST#/GEVENT7# USB_HSD2P H14 USBP2+ 30
+3V H15 Carama USB
USB_HSD2N USBP2- 30
D3E_SCI# from Gevent5# change to Gevent7# on PV
USB_HSD1P A13 USBP1+ 30
R276 4.7K_4 SUS_STAT# SI-2 modified Del D35 USB_HSD1N B13 USBP1- 30 E-SATA and USB Connector
G4
USB_HSD0P B14 USBP0+ 30
2 1 SYS_RST# CPU_MEMHOT#_IN B9 A14 USB Connector
3,7 CPU_MEMHOT# USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USBP0- 30
R275 *0_4 SMBALERT#_1 B8
5 PM_THERM# USB_OC5#/IR_TX0/GPM5#
R279 *10K/F_4 A8 A18
USB OC
*SHORT_ PAD1 +3VS5 USB_OC4#/IR_RX0/GPM4# IMC_GPIO8
SB_JTAG_TDO A9 B18
SB_JTAG_TCK USB_OC3#/IR_RX1/GPM3# IMC_GPIO9
E5 USB_OC2#/GPM2# IMC_PWM0/IMC_GPIO10 F21
+3VS5 SB_JTAG_TDI F8 D21 SB_SCLK2
SB_JTAG_RST# USB_OC1#/GPM1# SCL2/IMC_GPIO11 SB_SDATA2
E4 USB_OC0#/GPM0# SDA2/IMC_GPIO12 F19
R763 2.2K_4 DNBSWON# E20 SB_SCLK3
SCL3_LV/IMC_GPIO13 T64
ACZ_BCLK M1 E21 SB_SDATA3
AZ_BITCLK SDA3_LV/IMC_GPIO14 T70
ACZ_SDOUT M2 E19
ACZ_SDIN0_R AZ_SDOUT IMC_PWM1/IMC_GPIO15 SB_GPIO16
J7 AZ_SDIN0/GPIO42 IMC_PWM2/IMC_GPO16 D19 SB_GPIO16 16
ACZ_SDIN1_R SB_GPIO17 SPI/LPC define
HD AUDIO
J8 E18
To Azalia T98
T209
L8
M3
AZ_SDIN1/GPIO43
AZ_SDIN2/GPIO44
IMC_PWM3/IMC_GPO17
G20
SB_GPIO17 16
ACZ_SDOUT R644 33_4 ACZ_SYNC AZ_SDIN3/GPIO46 IMC_GPIO18

ACZ_SDOUT_AUDIO 27 L6 AZ_SYNC IMC_GPIO19 G21
ACZ_RST# M4 D25
16 ACZ_RST# AZ_RST# IMC_GPIO20
INTEGRATED uC
C908 *10P/50V_4 L5 D24
AZ_DOCK_RST#/GPM8# IMC_GPIO21
B
HD audio IMC_GPIO22 C25 B
interface is IMC_GPIO23 C24
ACZ_SYNC R290 33_4 B25
ACZ_SYNC_AUDIO 27 3.3S5 voltage IMC_GPIO24
IMC_GPIO25 C23
C569 *10P/50V_4
IMC_GPIO26 B24
IMC_GPIO27 B23
ACZ_BCLK R646 33_4 A23
BIT_CLK_AUDIO 27 IMC_GPIO28
IMC_GPIO29 C22
C910 10P/50V_4 A22
IMC_GPIO30 +3VS5
IMC_GPIO31 B22
IMC_GPIO32 B21
ACZ_RST# R296 33_4 A21 +3V
ACZ_RST#_AUDIO 27 IMC_GPIO33
H19 IMC_GPIO0 IMC_GPIO34 D20
INTEGRATED uC
+3VS5 H20 C20 R764
IMC_GPIO1 IMC_GPIO35
2
ACZ_SDIN0_R R295 0_4 ACZ_SDIN0 27 H21 A20 2K/04
R592 22K_4 HDD_AUX_RST# SPI_CS2#/IMC_GPIO2 IMC_GPIO36
F25 IDE_RST#/F_RST#/IMC_GPO3 IMC_GPIO37 B20
B19 3 1 PCLK_SMB
IMC_GPIO38 33,36 SCLK_WLAN
SI-2 Modified --for D22 IMC_GPIO4 IMC_GPIO39 A19
EMI suggestion E24 D18 Q66
To Modem Board E25
D23
IMC_GPIO5
IMC_GPIO6
IMC_GPIO40
IMC_GPIO41 C18 +3VS5 2N7002EPT
ACZ_SDOUT R645 33_4 IMC_GPIO7 +3V

ACZ_SDOUT_AUDIO_MDC 29
C909 *10P/50V_4 R765
2
2K/04
SB700
ACZ_SYNC R292 33_4 3 1 PDAT_SMB
ACZ_SYNC_AUDIO_MDC 29 +3VSUS 33,36 SDATA_WLAN
C577 *10P/50V_4
CN16
C462 SI-2 Modified -- discrete remove RP56
A 10P/50V_4 A
2N7002EPT Q67
ACZ_BCLK R647 33_4 1 SB_JTAG_TCK
BIT_CLK_AUDIO_MDC 29 2
CLOSE TO SB
SB_JTAG_TDO
C911 10P/50V_4 3 SB_JTAG_TDI USBP3-
SB JTAG 4 SB_TEST1 USBP3+
2 1 USBP6_CR- 25
PROJECT : QT8
5 4 3 USBP6_CR+ 25
RP50 *0_4P2R_4
6
ACZ_RST# R293 33_4 SB_JTAG_RST# UMA
ACZ_RST#_AUDIO_MDC 29 7
8
ACZ_SDIN1_R R286 0_4 *S/W JTAG DEBUG Size Document Number Rev
ACZ_SDIN1 29 Custom 1A
SB700-ACPI/GPIO/USB 2/4
NB5/RD5
5 4 3 2 1
5 4 3 2 1
SATA PORT 0,1,2,3

can support AHCI
mode
PLACE SATA AC COUPLING
CAPS CLOSE TO SB600
C559 0.01U/16V_4 SATA_TXP0_C AD9

U37B
SB700 AA24
14
33 SATA_TXP0 SATA_TX0P IDE_IORDY T231
C558 0.01U/16V_4 SATA_TXN0_C Part 2 of 5
SATA1 33 SATA_TXN0 AE9 SATA_TX0N IDE_IRQ AA25
Y22
T232
IDE_A0 T233
C563 0.01U/16V_4 SATA_RXN0_C AB10 AB23
33 SATA_RXN0 SATA_RX0N IDE_A1 T234
C562 0.01U/16V_4 SATA_RXP0_C AC10 Y23
33 SATA_RXP0 SATA_RX0P IDE_A2 T235
IDE_DACK# AB24 T236
C544 0.01U/16V_4 SATA_TXP1_C
D SATA ODD 33 SATA_TXP4
C543 0.01U/16V_4 SATA_TXN1_C
AE10
AD10
SATA_TX1P IDE_DRQ AD25
AC25
T237 D
33 SATA_TXN4 SATA_TX1N IDE_IOR# T238
IDE_IOW# AC24 T239
C535 0.01U/16V_4 SATA_RXN1_C AD11 Y25
33 SATA_RXN4 SATA_RX1N IDE_CS1# T240
C529 0.01U/16V_4 SATA_RXP1_C AE11 Y24 IF THERE IS NO IDE, TEST
33 SATA_RXP4 SATA_RX1P IDE_CS3# T241
R613 4.99/F_4 SATA_TXP2_C AB12 AD24
POINTS FOR DEBUG BUS
30 SATA_TXP2 SATA_TX2P IDE_D0/GPIO15 T242
30 SATA_TXN2
R615 4.99/F_4 SATA_TXN2_C AC12 SATA_TX2N IDE_D1/GPIO16 AD23 T243 IS MANDATORY
ATA 66/100/133
E-SATA SATA_RXN2_C AE12
IDE_D2/GPIO17 AE22
AC22
T244
30 SATA_RXN2 SATA_RX2N IDE_D3/GPIO18 T245
SATA_RXP2_C AD12 AD21
30 SATA_RXP2 SATA_RX2P IDE_D4/GPIO19 T246
IDE_D5/GPIO20 AE20 T247
SATA_TXP3_C AD13 AB20
T197 T248
SERIAL ATA
SATA_TXN3_C SATA_TX3P IDE_D6/GPIO21
T198 AE13 SATA_TX3N IDE_D7/GPIO22 AD19 T249
SATA_RXN3_C AB14 AC20
T88 SATA_RX3N IDE_D9/GPIO24 T251
SATA_RXP3_C AC14 AD20
T85 SATA_RX3P IDE_D10/GPIO25 T252
SATA_TXP4_C AE14 AB22
T227 SATA_TX4P IDE_D12/GPIO27 T254
SATA_TXN4_C AD14 AD22
T228 SATA_TX4N IDE_D13/GPIO28 T255
SATA_RXN4_C AD15 AC23
T229 SATA_RX4N IDE_D15/GPIO30 T257
SATA PORT 4,5 are T230
SATA_RXP4_C AE15 SATA_RX4P
only support IDE SATA_TXP5_C AB16
T89 SATA_TX5P
mode T87
SATA_TXN5_C AC16 SATA_TX5N
SPI_DI/GPIO12 G6 T100
SATA_RXN5_C AE16 D2
T86 SATA_RX5N SPI_DO/GPIO11 T219
SATA_RXP5_C AD16 D1
T82 SATA_RX5P SPI_CLK/GPIO47 T218
R361 F4
SPI ROM
SPI_HOLD#/GPIO31 T111
C R264 1K/F_4 SATA_RBIAS_PN V12 F3 C
SATA_CAL SPI_CS#/GPIO32 T220
SATA_X1 Y12 U15 R265 0_4
SATA_X1 LAN_RST#/GPIO13 BT_OFF# 30
J1 ROM_RST#
ROM_RST#/GPIO14 T215
PLACE SATA_CAL SATA_X2 AA12 SATA_X2 SB_FANOUT0
M8
RES VERY CLOSE SB_SATA_LED# W11
FANOUT0/GPIO3
M5 SB_FANOUT1
T96
SATA_ACT#/GPIO67 FANOUT1/GPIO48 T97
TO BALL OF SB700 PLVDD_SATA-- FANOUT2/GPIO49 M7 CHIPSET_PCIE_SLOW_SB# 2 SI-2 modified -- SB
SATA PLL +3V R382 10K/F_4 internal pull Hi to 3VS5
NOTE: AA11 P5 SB_FANTACH0
SATA PWR
POWER +1.2V_PLLVDD_SATA PLLVDD_SATA FANIN0/GPIO50 SB_FANTACH1
T104 , modified to same power
FANIN1/GPIO51 P8 T92
R361 IS 1K 1% FOR 25MHz +3V_XTLVDD_SATA W12 R8 PORT_80_PWR_DWN rail with SB
XTLVDD_SATA FANIN2/GPIO52 T95
XTAL, 4.99K 1% FOR 100MHz XTLVDD_SATA-- SATA C6 TEMP_COMM
TEMP_COMM T208
INTERNAL CLOCK crystal power TEMPIN0/GPIO61 B6 TEMPIN0
T202 +3VS5 R221 10K/F_4 BOARD_ID0 R229 *10K/F_4
A6 TEMPIN1
TEMPIN1/GPIO62 T203
HW MONITOR
A5 MB_THRMDA_SB
TEMPIN2/GPIO63 T207
C534 B5 R247 *10K/F_4 BOARD_ID1 R248 *10K/F_4
TEMPIN3/TALERT#/GPIO64 T259
SATA_X1 Del R220 for TP on PV
VIN0/GPIO53 A4 ACCLED_EN 29
27P/50V_4 B4 R216 0_4 R225 *10K/F_4 BOARD_ID2 R228 *10K/F_4
VIN1/GPIO54 BT_COMBO_EN# 36
2
Y4 C4
R262 VIN2/GPIO55 BOARD_ID0
VIN3/GPIO56 D4 Del WAN off#
25MHZ 10M_6 D5 BOARD_ID1 and R597 on R230 *10K/F_4 BOARD_ID3 R242 *10K/F_4
VIN4/GPIO57 BOARD_ID2
D6 PV
1
C517 VIN5/GPIO58 BOARD_ID3

VIN6/GPIO59 A7
SATA_X2 B7 BOARD_ID4 R596 *10K/F_4 BOARD_ID4 R600 *10K/F_4
VIN7/GPIO60
27P/50V_4 +3VS5
B 5mA SI-2 modified -- for fix +3V power leakage in S5 mode B
F6 +3V_VDD_HWM L52 0_6
AVDD
SB700
AVSS G7 C571 C572 AVDD--H/W monitor
+3V *0.1U/10V_4 *2.2U/6.3V_6 Analog power
ID4 ID3 ID2 ID1 ID0

C655
+1.2V ( 1.2V @ 60mA) +1.2V_PLLVDD_SATA
0.1U/10V_4 77mA
X X X 0 0 UMA
U20 L47
5
TC7SH08FU BLM18PG181SN1D(180,1.5A)_6
2 SB_SATA_LED#
29 SATA_LED# 4 C524 C550 X X X 0 1 discrete
1 1U/10V_4 0.1U/10V_4
3
X X X X X
+3V 1mA
( 3.3V @ 1.2mA) +3V_XTLVDD_SATA
X X X X X
SI-2 modified for SATA LED fail issue L46
BLM18PG181SN1D(180,1.5A)_6
C539
1U/10V_4
A A
Place near
ball
PROJECT : QT8
Custom 1A
SB700-ACPI/GPIO/USB 2/4
NB5/RD5
5 4 3 2 1
5 4 3 2 1
PLACE ALL THE DECOUPLING CAPS ON For SB700 issue(6/22)

A1-1 chip bug
23
THIS SHEET CLOSE TO SB AS POSSIBLE.
Del R285 for TP on PV R590 use A1-2 chip can remove
VDD-- S/B CORE power 2 1 *0_8 +1.2V_S5
U37C +1.2V_VCC_SB_R
VDDQ--3.3V I/O power 0.8A SB700 604mA R198
+3V L9 VDDQ_1 VDD_1 L15 2 1 0_8 +1.2V U37E
M9 VDDQ_2 Part 3 of 5 VDD_2 M12
1
T15 VDDQ_3 VDD_3 M14 SB700
1
C576 U9 N13 A2
CORE S0
C557 C560 C573 C565 C547 C553 C574 VDDQ_4 VDD_4 C533 C545 C538 C532 C467 VSS_1
U16 P12 A25
PCI/GPIO I/O
100U/6.3V_3528 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 VDDQ_5 VDD_5 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 VSS_2
2 U17 P14 B1
2
D VDDQ_6 VDD_6 VSS_3 D
V8 VDDQ_7 VDD_7 R11 VSS_4 D7
W7 VDDQ_8 VDD_8 R15 T10 AVSS_SATA_1 VSS_5 F20
Y6 VDDQ_9 VDD_9 T16 U10 AVSS_SATA_2 VSS_6 G19
AA4 VDDQ_10 U11 AVSS_SATA_3 VSS_7 H8
AB5 VDDQ_11 U12 AVSS_SATA_4 VSS_8 K9
1.8V : FLASH MEMORY MODE(DEFAULT) AB21 VDDQ_12
CKVDD_1.2V-- Internal V11 AVSS_SATA_5 VSS_9 K11
3.3V: IDE MODE +VDD33_18 +1.2V_CKVDD clock Generator I/O V14 AVSS_SATA_6 VSS_10 K16
power W9 AVSS_SATA_7 VSS_11 L4
VDD33_18--3.3V IDE I/O power Y9 AVSS_SATA_8 VSS_12 L7
1.8V flash memory I/O power 0.45A 286mA Y11 AVSS_SATA_9 VSS_13 L10
+3V R226 2 1 0_8 Y20 L21 L43 +1.2V Y14 L11
VDD33_18_1 CKVDD_1.2V_1 AVSS_SATA_10 VSS_14
AA21 L22 Y17 L12
IDE/FLSH I/O
CLKGEN I/O
R751 2 VDD33_18_2 CKVDD_1.2V_2 AVSS_SATA_11 VSS_15
+1.8V 1 *0_8 AA22 VDD33_18_3 CKVDD_1.2V_3 L24 BLM18PG181SN1D(180,1.5A)_6 AA9 AVSS_SATA_12 VSS_16 L14
1
1
AE25 VDD33_18_4 CKVDD_1.2V_4 L25 AB9 AVSS_SATA_13 VSS_17 L16
C486 C501 C487 C497 C488 C505 C489 C475 C478 AB11 M6
10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 2.2U/6.3V_6 AVSS_SATA_14 VSS_18
AB13 M10
2
2
2.2U/6.3V_6 0.1U/50V_6 0.1U/50V_6 AVSS_SATA_15 VSS_19
AB15 AVSS_SATA_16 VSS_20 M11
AB17 AVSS_SATA_17 VSS_21 M13
AC8 AVSS_SATA_18 VSS_22 M15
AD8 AVSS_SATA_19 VSS_23 N4
AE8 N12
+1.2V_PCIE_VDDR
POWER AVSS_SATA_20 VSS_24
VSS_25 N14
VSS_26 P6
PCIE_VDDR--PCIE I/O power 844mA VSS_27 P9
+1.2V L89 P18 PCIE_VDDR_1
S5_3.3--3.3v standby power VSS_28 P10
P19 +3VALW_R A15 P11
BLM18PG181SN1D(180,1.5A)_6 PCIE_VDDR_2 R604 0_6 AVSS_USB_1 VSS_29
A-LINK I/O
P20 PCIE_VDDR_3 0.01A B15 AVSS_USB_2 VSS_30 P13
1
1
P21 PCIE_VDDR_4 S5_3.3V_1 A17 2 1 +3VS5 C14 AVSS_USB_3 VSS_31 P15
C477 C502 C484 C504 C492 C483 R22 A24 D8 R1
10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 PCIE_VDDR_5 S5_3.3V_2 Change to 0603 AVSS_USB_4 VSS_32
C R24 B17 D9 R2 C
2
2
PCIE_VDDR_6 S5_3.3V_3 AVSS_USB_5 VSS_33
1
3.3V_S5 I/O
R25 PCIE_VDDR_7 S5_3.3V_4 J4 D11 AVSS_USB_6 VSS_34 R4
J5 C875 C570 C876 D13 R9
S5_3.3V_5 AVSS_USB_7 VSS_35
GROUND
L1 0.1U/10V_4 0.1U/10V_4 10U/6.3V_8 D14 R10
2
S5_3.3V_6 AVSS_USB_8 VSS_36
S5_3.3V_7 L2 D15 AVSS_USB_9 VSS_37 R12
+1.2V_AVDD_SATA E15 R14
AVSS_USB_10 VSS_38
AVDD_SATA--SATA phy power 0.2A F12 AVSS_USB_11 VSS_39 T11
+1.2V L92 AA14 AVDD_SATA_1
S5_1.2V--1.2V standby power F14 AVSS_USB_12 VSS_40 T12
AB18 AVDD_SATA_4 G9 AVSS_USB_13 VSS_41 T14
BLM18PG181SN1D(180,1.5A)_6 AA15 0.22A H9 U4
SATA I/O
AVDD_SATA_2 AVSS_USB_14 VSS_42
1
AA17 G2 +1.2V_S5 H17 U14
CORE S5
C888 C880 C884 C883 C881 AVDD_SATA_3 S5_1.2V_1 AVSS_USB_15 VSS_43
AC18 AVDD_SATA_5 S5_1.2V_2 G4 J9 AVSS_USB_16 VSS_44 V6
1
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 AD17 Del R661 J11 Y21
2
AVDD_SATA_6 C903 C901 AVSS_USB_17 VSS_45

AE17 AVDD_SATA_7 J12 AVSS_USB_18 VSS_46 AB1
0.2A 0.1U/10V_4 0.1U/10V_4 for TP on J14 AB19
2
AVSS_USB_19 VSS_47
USB_PHY_1.2V_1 A10 +1.2V_USB_PHY_R PV J15 AVSS_USB_20 VSS_48 AB25
USB_PHY_1.2V_2 B10 K10 AVSS_USB_21 VSS_49 AE1
K12 AVSS_USB_22 VSS_50 AE24
K14 AVSS_USB_23
+3V_AVDD_USB K15 AVSS_USB_24
AVDDTX--USB Phy PCIE_CK_VSS_9 P23
For support USB wakeup-->3V_S5 Analog I/O power V5_VREF--PCI 5V TOLERANCE PCIE_CK_VSS_10 R16
L91
0.2A +5V_VREF
4mA R621 PCIE_CK_VSS_11 R19
+3VS5 A16 AVDDTX_0 V5_VREF AE7 1 2 1K/F_4 +5V PCIE_CK_VSS_12 T17
B16 AVDDTX_1 PCIE_CK_VSS_13 U18
BLM18PG181SN1D(180,1.5A)_6 C16 J16 +3V_AVDDCK 7mA H18 U20
AVDDTX_2 AVDDCK_3.3V PCIE_CK_VSS_1 PCIE_CK_VSS_14
1
D16 AVDDTX_3 1 2 +3V J17 PCIE_CK_VSS_2 PCIE_CK_VSS_15 V18
1
C889 C882 C878 C886 D17 PLL K17 +1.2V_AVDDCK 44mA D36 J22 V20
10U/6.3V_8 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 AVDDTX_4 AVDDCK_1.2V C898 CH501H-40PT PCIE_CK_VSS_3 PCIE_CK_VSS_16
E17 K25 V21
2
AVDDTX_5 PCIE_CK_VSS_4 PCIE_CK_VSS_17

USB I/O
F15 E9 +3V_AVDDC 1U/10V_4 M16 W19
2
B AVDDRX_0 AVDDC PCIE_CK_VSS_5 PCIE_CK_VSS_18 B
F17 AVDDRX_1 M17 PCIE_CK_VSS_6 PCIE_CK_VSS_19 W22
F18 AVDDRX_2 16mA M21 PCIE_CK_VSS_7 PCIE_CK_VSS_20 W24
G15 AVDDRX_3 P16 PCIE_CK_VSS_8 PCIE_CK_VSS_21 W25
G17 AVDDRX_4
G18 AVDDRX_5 F9 AVSSC AVSSCK L17
Part 5 of 5
1
SB700 SB700
C528 C537 C885 C511 C510 C879 C536
1U/10V_4 1U/10V_4 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
2
+3VS5 +3V_AVDDC
+1.2V_S5 +1.2V_USB_PHY_R AVDDC--USB Analog PLL power
L50
R616 0_6 USB_PHY_1.2V--USB Phy BLM18PG181SN1D(180,1.5A)_6
2 1 digital power
1
C546 C540
1
0.1U/10V_4 10U/6.3V_8
2
C890 C891 C892
0.1U/10V_4 0.1U/10V_4 10U/6.3V_8
2
A +1.2V A
+1.2V_AVDDCK +3V +3V_AVDDCK
AVDDCK_1.2--USB Phy AVDDCK_3.3--Analog
digital power system PLL power
L45 L48
BLM18PG181SN1D(180,1.5A)_6 BLM18PG181SN1D(180,1.5A)_6
PROJECT : QT8
1
C509 C516
2.2U/6.3V_6 2.2U/6.3V_6 Quanta Computer Inc.
2

Custom 1A
SB700-PWR/DECOUPLING 4/4
NB5/RD5
5 4 3 2 1
5 4 3 2 1
OVERLAP COMMON PADS WHERE

POSSIBLE FOR DUAL-OP RESISTORS. 16
It must ready
refore RSMRST# REQUIRED STRAPS +3VS5
1
D +3V +3V +3VS5 SI-2 Modified D
-R599 change from

R599
2.2K_4 10kohm to 2.2kohm
for fix system can
2
1
1
intermal have pull not boot
Hi 10K , confirm AMD
R655 R656 R300
10K/F_4 10K/F_4 *10K/F_4 ward this pull Hi
13 SB_GPIO17
not need 13 SB_GPIO16
2
12 PCI_CLK_TPM 12 PCI_CLK4 12 LPC_CLK0 12 RTC_CLK
1
12 PCI_CLK3 12 PCI_CLK5 12 LPC_CLK1 13 ACZ_RST#
GPIO16 R598 R255
*2.2K_4 2.2K_4 GPIO17
2
1
1
1
1
R659
10K/F_4 R291
R658 R654 R657 R231 R595 10K/F_4 TYPE GPIO16 GPIO17
2
10K/F_4 *10K/F_4 *10K/F_4 10K/F_4 10K/F_4
2
2
2
FWH L : 2.2K L : 2.2K
pull down pull down
PCI_CLK_TPM PCI_CLK3 PCI_CLK4 PCI_CLK5 LPC_CLK0 LPC_CLK1 RTC_CLK AZ_RST#
LPC NC L : 2.2K
C
pull down C
PULL BOOTFAIL USE RESERVED RESERVED IMC CLKGEN INTERNAL ENABLE PCI
HIGH TIMER DEBUG ENABLED ENABLED RTC ROM BOOT
L : 2.2K
ENABLED STRAPS SPI NC
pull down
DEFAULT
EXT. RTC
PULL BOOTFAIL IGNORE IMC CLKGEN (PD on X1, DISABLE PCI
LOW TIMER DEBUG DISABLED DISABLED apply ROM BOOT RSVD NC NC
DISABLED STRAPS 32KHz to DEFAULT
DEFAULT DEFAULT DEFAULT DEFAULT RTC_CLK)
NB_PWRGD_IN:
RS780/RX780 = 1.8V; RS740 = 3.3V
DEBUG STRAPS Do NOT share it with SB_PWRGD when use Internal Clk Gen
(Need SB PLL initialize firstly)
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23] SI-2 modified -- confirm AMD R563 need to stuff
+3VS5 R282 10K/F_4 R278 0_4 SB_PWRGD_IN

SB_PWRGD_IN 13
SI-2 modified -- remove
+3V pull Hi resistor . C564
*2.2U/6.3V_6 +1.8V
12 AD28 +1.8V
B
12 AD27 B
12 AD26
12 AD25 U14 R269
12 AD24 1 5 C549 *0.1U/10V_4 10K/F_4
D18 CH501H-40PT NC VCC RX780,RS780
12 AD23
40 VRM_PWRGD 1 2 2 A
1
3 4 R273 *33_4 NB_PWRGD_IN

GND Y NB_PWRGD_IN 10
R651 R636 R652 R638 R637 R653
*2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 *2.2K_4 Use 2.2K PD. D19 CH501H-40PT *NL17SZ17DFT2G
1 2 SOT-353
5,35 ECPWROK
2
R266 *10K/F_4 +1.8V
NB/SB POWER GOOD CIRCUIT 0_4 R272

WD_PWRGD 13
PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23
USE USE PCI USE ACPI USE IDE USE DEFAULT RESERVED
PULL LONG PLL BCLK PLL PCIE STRAPS
HIGH RESET
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT
PULL USE BYPASS BYPASS BYPASS IDE USE EEPROM

AL17SZ17000 IC(5P) NL17SZ17DFT2G(SOT-353) SOT-353
LOW SHORT PCI PLL ACPI PLL PCIE STRAPS
A RESET BCLK ALUC1G17000 IC OTHER(5P) SN74AUC1G17DBVR(SOT23-5) SOT23-5 A
PROJECT : QT8
Custom 1A
SB700-STRAPS
NB5/RD5
5 4 3 2 1
5 4 3 2 1
IC CTRL(632P) 216-0707001-00(BGA)
VGA P/N : AJ070700T00
17
PART 1 OF 6
2.5Gb/s bit rate POWER
PEG_TX0 AC30 AA28 C_PEG_RXP0 C163 0.1U/10V_4 +PCIE_VDDR=1.2V
9 PEG_TX0 PCIE_RX0P PCIE_TX0P PEG_RX0 9
PEG_TX#0 AC31 AA27 C_PEG_RXN0 C156 0.1U/10V_4
D 9 PEG_TX#0 PCIE_RX0N PCIE_TX0N PEG_RX#0 9 +VDD_MEM1.8V=1.8V D
+VGA_CORE=1.0~1.1V - M62S,M71S
9 PEG_TX1
PEG_TX1 AC29 PCIE_RX1P P PCIE_TX1P AA25 C_PEG_RXP1 C167 0.1U/10V_4
PEG_RX1 9 0.95~1.1V - M72S
PEG_TX#1 AB29 AA24 C_PEG_RXN1 C170 0.1U/10V_4
9 PEG_TX#1 PCIE_RX1N C PCIE_TX1N PEG_RX#1 9
I
PEG_TX2 AB31 Y28 C_PEG_RXP2 C180 0.1U/10V_4
9 PEG_TX2
PEG_TX#2 AB30
PCIE_RX2P - PCIE_TX2P
Y27 C_PEG_RXN2 C196 0.1U/10V_4
PEG_RX2 9
9 PEG_TX#2 PCIE_RX2N PCIE_TX2N PEG_RX#2 9
E
PEG_TX3 AA31
X Y25 C_PEG_RXP3 C164 0.1U/10V_4
9 PEG_TX#3
PEG_TX#3 AA30 PCIE_RX3N
P PCIE_TX3N Y24 C_PEG_RXN3 C157 0.1U/10V_4
PEG_RX#3 9
R
9 PEG_TX4
PEG_TX4 W30 PCIE_RX4P
E PCIE_TX4P V28 C_PEG_RXP4 C218 0.1U/10V_4
PEG_RX4 9
PEG_TX#4 C_PEG_RXN4 C204 0.1U/10V_4
9 PEG_TX#4 W31 PCIE_RX4N S PCIE_TX4N V27 PEG_RX#4 9
S
PEG_TX5 W29 V25 C_PEG_RXP5 C203 0.1U/10V_4
PEG_TX#5 V29 V24 C_PEG_RXN5 C187 0.1U/10V_4
9 PEG_TX#5 PEG_RX#5 9
PCIE_RX5N I PCIE_TX5N
PEG_TX6
N C_PEG_RXP6 C220 0.1U/10V_4
V31 T28
9
9
PEG_TX6
PEG_TX#6
PEG_TX#6 V30
PCIE_RX6P T PCIE_TX6P
T27 C_PEG_RXN6 C224 0.1U/10V_4
PEG_RX6 9
PEG_RX#6 9
PCIE_RX6N PCIE_TX6N
E
9 PEG_TX7
PEG_TX7 U31 R T25 C_PEG_RXP7 C243 0.1U/10V_4
PEG_RX7 9
PCIE_RX7P PCIE_TX7P
9 PEG_TX#7
PEG_TX#7 U30 PCIE_RX7N F PCIE_TX7N T24 C_PEG_RXN7 C252 0.1U/10V_4
PEG_RX#7 9
C A C
9 PEG_TX8
PEG_TX8
PEG_TX#8
P30 PCIE_RX8P C PCIE_TX8P P28 C_PEG_RXP8
C_PEG_RXN8
C276 0.1U/10V_4
PEG_RX8 9
P31 P27 C268 0.1U/10V_4
9 PEG_TX#8 PCIE_RX8N E PCIE_TX8N PEG_RX#8 9
PEG_TX9 P29 P25 C_PEG_RXP9 C259 0.1U/10V_4

PEG_TX#9 N29 P24 C_PEG_RXN9 C246 0.1U/10V_4
PEG_TX10 N31 M28 C_PEG_RXP10 C289 0.1U/10V_4

PEG_TX#10 N30 M27 C_PEG_RXN10 C277 0.1U/10V_4
PEG_TX11 M31 M25 C_PEG_RXP11 C290 0.1U/10V_4

PEG_TX#11 M30 M24 C_PEG_RXN11 C296 0.1U/10V_4
PEG_TX12 K30 L28 C_PEG_RXP12 C288 0.1U/10V_4

PEG_TX#12 K31 L27 C_PEG_RXN12 C295 0.1U/10V_4
PEG_TX13 K29 L25 C_PEG_RXP13 C330 0.1U/10V_4

PEG_TX#13 J29 L24 C_PEG_RXN13 C324 0.1U/10V_4
PEG_TX14 J31 J28 C_PEG_RXP14 C325 0.1U/10V_4

PEG_TX#14 J30 J27 C_PEG_RXN14 C331 0.1U/10V_4
PEG_TX15 H31 G28 C_PEG_RXP15 C304 0.1U/10V_4

B 9 PEG_TX15 PCIE_RX15P PCIE_TX15P PEG_RX15 9 B
PEG_TX#15 H30 G27 C_PEG_RXN15 C316 0.1U/10V_4
Clock Calibration
EXT_GFX_CLKP AD29
2 EXT_GFX_CLKP PCIE_REFCLKP
EXT_GFX_CLKN AD30 AF25 M72_PCIE_CALRN R74 2K/F_4 +1.1V_PCIE_VDDC
2 EXT_GFX_CLKN PCIE_REFCLKN PCIE_CALRN
100MHz (+/-300ppm) input frequency, SM BUS
PCIE_CALRP AE25 M72_PCIE_CALRP R70 1.27K/F_4
0-0.7V single-ended swing AC28 NC_SMBCLK
AC27 NC_SMBDATA 1.27K for M82-S
NC_1 AE23
R71 0_4 AG25 AH30
12 PCIE_RST# PERSTB NC_2
M72-S/M82-S
U29A
VGA Core BPP

VGA Core VDDC
+1.8V PCIE_VDDR
A A
+1.8V PCIE_PVDD
+1.8V VDDR1
PROJECT : QT8
3.3V_Delay VDDR3
20ms 20ms Custom
M7X/M8X_PCIE_Interface 1A
NB5/RD5
5 4 3 2 1
5 4 3 2 1
U29B
R100
R522
1K/F_4
10K/F_4
GPIO_24_JMODE
ROMCS#
NA- M62S,M71S
PD 1K- M72S AJ4
AJ5
AL5
AK5
TXCM_DPA0P
TXCP_DPA0N
TX0M_DPA1P
TX0P_DPA1N
PART 2 OF 6
INTEGRATED TXCM_DPB0P
TMDS/DP PORT TXCP_DPB0N
TX0M_DPB1P
TX0P_DPB1N
AK9
AL9
AJ9
AJ10
TXC_HDMI_L-
TXC_HDMI_L+
TX0_HDMI_L-
TX0_HDMI_L+
Remove 180R
SHUNT RESISTOR
for M82-S
from AMD Jackson
TXC_HDMI_L- 23
TXC_HDMI_L+ 23
TX0_HDMI_L- 23
TX0_HDMI_L+ 23
18
AL6 TX1M_DPA2P TX1M_DPB2P AL10 TX1_HDMI_L- confirm TX1_HDMI_L- 23
GPIO22(ROMCS#) AK6 AK10 TX1_HDMI_L+
TX1P_DPA2N TX1P_DPB2N TX1_HDMI_L+ 23
PD without external VBIOS ROM
AK8 AL11 TX2_HDMI_L-
TX2M_DPA3P TX2M_DPB3P TX2_HDMI_L- 23
AL8 AK11 TX2_HDMI_L+
TX2P_DPA3N TX2P_DPB3N TX2_HDMI_L+ 23
NA - M64/M62, M71
R87 10K/F_4 BBEN AL7 +1.8V_TPVDD DPA_PVDD / DPB_PVDD
BBEN- M66 DPA_PVDD +1.8V_TPVDD
BBEN(10K PD)- M76 AD9 DVALID DPA_PVSS AK7 DP/TMDS PLL Power (Link A)
PSYNC DPB_PVDD DP/TMDS PLL Power (Link B)
D AE7 AE11 DPB_PVDD D
19 PSYNC PSYNC_NEW DPB_PVDD
AF11 1.8 V ± 3%
R95 10K/F_4 TEMP_FAIL DPB_PVSS
NA- M62S,M71S
PU to 3.3V- M72S AK4 DVPCNTL_MVP_0 DPA_VDDR_1 AJ12 DPA_B_VDDR DPA_B_VDDR DPA_VDDR / DPB_VDDR
AL3 DVPCNTL_MVP_1 DPA_VDDR_2 AJ13 DP/TMDS Transmitter Power (Link A)
DPA_B_VDDR DP/TMDS Transmitter Power (Link B)
V2 AK13 DPA_B_VDDR
V1
DVPCNTL_0 DPB_VDDR_1
AL13 1.1 V ± 3%
DVPCNTL_1 DPB_VDDR_2
MEM_ID[3:0] Vendor Type Vendor P/N W3 DVPCNTL_2
DPB_VSSR_5 AL12
0000 Qimonda (Infineon) 16*16 HYB18T256161BF-25 W1 DVPCLK DPB_VSSR_4 AK12 ENABLE HD AUDIO ( M8X-M )
0001 Qimonda (Infineon) 32*16-500MHZ HYB18T512161B2F-20 DPB_VSSR_3 AJ11
0010 Hynix 16*16 HY5PS561621AFP-25 Y1 DVPDATA_0 DPB_VSSR_2 AH9
0011 Hynix 32*16-500MHZ H5PS5162FFR-20L Y2 DVPDATA_1 DPB_VSSR_1 AH11 R488 *0_4 VIP_3
VIP_3 19
0100 Samsung 16*16 K4N56163QG-ZC25 Y3 DVPDATA_2
0101 Samsung 32*16-500MHZ K4N51163QG-HC20 AA2 DVPDATA_3 DPA_VSSR_5 AJ8
0110 Reserved AA3 DVPDATA_4 DPA_VSSR_4 AF7 M82-S 0_4
0111 Reserved AB1 DVPDATA_5 DPA_VSSR_3 AG7 R476
1000 Reserved AB2 DVPDATA_6 DPA_VSSR_2 AJ7 DPA_VSSR_2
1001 Reserved AB3 DVPDATA_7 DPA_VSSR_1 AH7
1010 Reserved AC1 DVPDATA_8
150 OHM
1011 Reserved AC3 DVPDATA_9 DP_CALR AG11 TMDS_HPD
TMDS_HPD 10,23
1100 Reserved AD1 DVPDATA_10
1101 Reserved AD2 DVPDATA_11 EXT TMDS HPD1 AA8 TMDS_HPD R65 *100K/F_4
1110 Reserved AD3 DVPDATA_12 DVO
L_CRT_R R463 150/F_4
1111 Reserved AF3 DVPDATA_13 R AL28 L_CRT_R R449 0_4
CRT_R 10,24 Del R481, R482, R483,
AG3 AK28
AH3
DVPDATA_14
DVPDATA_15
RB L_CRT_G R462 150/F_4 R68, R464, R486 for TP
AG1 AL27 L_CRT_G R448 0_4
AH2
DVPDATA_16 G
AK27
CRT_G 10,24 on PV
+VDDR4 DVPDATA_17 GB
PWRCNTL1 PWRCNTL0 V-CORE Memory ID AH1 DVPDATA_18
L_CRT_B R461 150/F_4
AJ3 AL26 L_CRT_B R447 0_4
R495 DVPDATA_19 B CRT_B 10,24
10K/F_4 MEM_ID0 AJ1 AK26
R496 *10K/F_4 MEM_ID1 DVPDATA_20 DAC1 / CRT BB
AJ2 DVPDATA_21
H 0 0 1.1V R493
R492
*10K/F_4
*10K/F_4
MEM_ID2
MEM_ID3
AK2
AK3
DVPDATA_22
DVPDATA_23
HSYNC
VSYNC
AK29
AK30
HSYNC_COM 10,19,24
VSYNC_COM 10,19,24
C AJ28 R484 499/F_4 C

RSET
M 0 1 1.0V 19
19
GPIO0
GPIO1
GPIO0
GPIO1
Y4
V3
GPIO_0
GPIO_1 AVDD AL29 +1.8V_A2VDD_Q +1.8V_A2VDD_Q AVDD
GPIO2 V4 C111 DAC1 Analog Power
T151 GPIO_2
GPIO3 V5 GENERAL AH28
T18 GPIO_3 AVSSQ Dedicated power for DAC1.
M 1 0 1.0V 19
T152
GPIO5
GPIO4
GPIO5
U3
U2
GPIO_4
GPIO_5
PURPOSE
I/O
VDD1DI AJ27 +VDDD1 +VDDD1
0.1U/10V_4
1.8 V ± 5%
T4 C127
GPIO_6
10,23 LVDS_BLON R93 0_4 EXT_LVDS_BLON T5 GPIO_7_BLON VSS1DI AJ26 VDD1DI
+1.8V_A2VDD_Q
L 1 1 0.9V 19
19
GPIO8
GPIO9
GPIO8
GPIO9
T7
T8
GPIO_8_ROMSO
GPIO_9_ROMSI R2 AL17
0.1U/10V_4 DAC1 Digital Power.
1.8 V ± 5% 1.8V(65mA)
GPIO10 R1 AK17
T153 GPIO_10_ROMSCK R2B
19 GPIO11 GPIO11 R2 +1.8V_A2VDD_Q L16
GPIO_11 +1.8V
19 GPIO12 GPIO12 R3 GPIO_12 G2 AL15 A2VDD
BBEN BBP 19 GPIO13
T154
GPIO13
HDMI_HP2
P1
P3
GPIO_13
GPIO_14_HPD2
G2B AK15 DAC2 Analog Power.
3.3 V ± 5%
C129 C168
BLM18PG181SN1D(180,1.5A)_6
C98
42 GFX_CORE_CNTRL0 R526 0_4 N1 AL14 10U/6.3V_8
GPIO_15_PWRCNTL0 DAC2 (TV/CRT2) B2
2 OSC_SPREAD
OSC_SPREAD N2 GPIO_16_SSIN B2B AK14 A2VDDQ 0.1U/10V_4 1U/10V_4
L 0 V-CORE T37
HPD3
VGA_ALERT P4
P7
GPIO_17_THERMAL_INT
GPIO_18_HPD3 C AJ17 Del R470, R478,
DAC2 Band Gap (clean) power supply.
1.8 V ± 5%
5 TEMP_FAIL TEMP_FAIL P8 R450, R472, R471,
R99 0_4 PWRCNTL_1 GPIO_19_CTFB
42 GFX_CORE_CNTRL1 P5 GPIO_20_PWRCNTL1 Y AJ15 R469, R451 for TP on
VDD2DI DPB_PVDD
H 1 +1.8V 20 BBEN BBEN
ROMCS#
V7
N3
GPIO_21_BB_EN
GPIO_22_ROMCSB COMP AJ14
PV
DAC2 Digital Power. 1.8V(20mA)
R91 10K/F_4 GPIO_23_CLKREQb Y5 DPB_PVDD L24
+3V
GPIO_24_JMODE GPIO_23_CLKREQB DAC2_VSY 1.8 V ± 5% C165 C182
+1.8V
M4 GPIO_24_JMODE V2SYNC AE16 T13
DPLL_PVDD BLM18PG181SN1D(180,1.5A)_6 1.8V(40mA) T36 M5 GPIO_25_TDI H2SYNC AF16 DAC2_HSY BLM18PG181SN1D(180,1.5A)_6
Phase Lock Loop +1.8V M7 T10 0.1U/10V_4 1000P/50V_4 C145
T34 GPIO_26_TCK
L17 M8 AH14 10U/6.3V_8
Power T35 GPIO_27_TMS A2VDD +3V_DELAY
T38 L8
Dedicated analog C114 C147 GPIO_28_TDO
AH16 +1.8V_A2VDD_Q C136 Del L25 for
A2VDDQ +1.8V_A2VDD_Q
power pin for 10U/6.3V_8 0.1U/10V_4 Y8 GEN_A
0.1U/10V_4 TP on PV
+VDDD1
display PLLs. +1.8V 1.8V+R6043(249R)=1.8V/3=0.6V
Y7 GEN_B A2VSSQ AG16
1.8 V ± 3% V8 GEN_C
GENERICC AH6 AF18 +VDDD1
T123 GEN_D_HPD4 VDD2DI
R75 499/F_4 AG6 GEN_E C171
VSS2DI AE18
B BLM18PG181SN1D(180,1.5A)_6 1.8V(40mA) R76 249/F_4 +0.6V_M72_VREFG AC11 B
VREFG
PCIE_PVDD +1.8V R2SET AG14 R69 715/F_4 0.1U/10V_4
PCI-E PLL power. L71
+1.8V_DPLL_PVDD AH12
1.8 V ± 5% C743 C747 C746 DPLL_PVSS DPLL_PVDD
AG12 DPLL_PVSS SCL AA5 EDIDCLK 10,23
AA4 Del R84, R85, +VDDD1
10U/6.3V_8 1U/10V_4 0.1U/10V_4 +1.8V_VPCIE_PVDD AH31 SDA EDIDDATA 10,23
PCIE_PVDD R466, R467 1.8V(100mA)
SERIAL AJ29
BUSES DDC1DATA DDCDATA 10,24 for TP on PV
BLM18PG181SN1D(180,1.5A)_6 VDDC(345mA) AH29 +VDDD1 L15
DDC1CLK DDCCLK 10,24 +1.8V
+VGA_CORE +VGACORE_MPVDD A9 PLL & R511 *4.7K_4 +3V_DELAY
L79 MPVSS MPVDD XTAL VTHM_DAT BLM18PG181SN1D(180,1.5A)_6
B9 MPVSS DDC2DATA AC5
MPVDD C822 C823
DDC2CLK AC4 VTHM_CLK C110 C135 C97
Memory Phase Lock Loop Power 10U/6.3V_8 C824 +1.1V_DPLL_VDDC AE12 R510 *4.7K_4 +3V_DELAY 10U/6.3V_8
1U/10V_4 0.1U/10V_4 DPLL_VDDC 0.1U/10V_4 1U/10V_4
Same as VDDC DDC3DATA_DP3_AUXN AF4 T12
2 EVGA-XTALI
EVGA-XTALI AJ31 XTALIN DDC3CLK_DP3_AUXP AH4 T11 DDC 3V tolerance
--DDC1,DDC2,SDA/SCL
EVGA-XTALO AJ30 AF9
BLM18PG181SN1D(180,1.5A)_6 XTALOUT DDC4DATA_DP4_AUXN HDMI_SDA 23 DDC 5V tolerance
1.1V(100mA) AG9 HDMI_SCL 23
L18 DDC4CLK_DP4_AUXP --DDC3,DDC4 +1.8V_TPVDD 1.8V(20mA)
+1.1V
TS_FDO AE14
C106 C169 C161 1K/F_4 R67 AH26 TEST +1.8V_TPVDD L20 +1.8V
10U/6.3V_8 1U/10V_4 0.1U/10V_4 TESTEN THERMAL VGATHRM+ C113 C108
DPLUS AE5
AD12 AE4 VGATHRM- BLM18PG181SN1D(180,1.5A)_6
PLLTEST DMINUS 0.1U/10V_4 1000P/50V_4 C134
DPLL_VDDC 10U/6.3V_8
Phase Lock Loop Power M72-S/M82-S
Dedicated digital power pin for display PLLs. DPA_B_VDDR
1.1 V ± 5%
Thermal Sensor
5,35 MBCLK2 R524 0_4 1.1V(S100,D200mA)
5,35 MBDATA2 R525 0_4 781-1_3V R509 200/F_6 +3V_DELAY DPA_B_VDDR L70 +1.1V
U30 C790 0.1U/10V_4 BLM18PG181SN1D(180,1.5A)_6
C741 *22P/50V_4 EVGA-XTALI VTHM_CLK R518 *0_4 MBCLK2 8 1 C740 C742 C737
SMCLK VCC VGATHRM+ 10U/6.3V_8
1
VTHM_DAT R519 *0_4 MBDATA2 7 2 0.1U/10V_4 1000P/50V_4

SMDATA DXP
A CL=20PF *27MHZ
Y7 R468
*10M_6
For Int Clk 27Mhz
+3V_DELAY
R516 10K/F_4 VGA_ALERT 6 -ALT DXN 3
C793
2200P/50V_4 w/s 10 / 10 A
2
5 4 VGATHRM-
C735 EVGA-XTALO GND -OVT
*22P/50V_4 G781-1P8@EV
-VGATHRM +3V_DELAY
I2C ADDRESS: 9AH R513 10K/F_4
PROJECT : QT8
Custom 1A
M7X/M8X_Main
NB5/RD5
5 4 3 2 1
5 4 3 2 1
1.8V -(300mA)
L14 BLM18PG181SN1D(180,1.5A)_6 +LVDDR_1-2 U29F
19
+1.8V
U29E C109 C123 PART 6 OF 6 R83 10K/F_4
Part 5 of 6 C103
1U/10V_4 1U/10V_4 0.1U/10V_4 AF20 AA7 0_4 R89
LVDDR_1 VARY_BL DPST_PWM 10,23
VSS_33 B25 AG20 LVDDR_2
AA26 J8 Control AC6 0_4 R80
PCIE_VSS_1 VSS_34 DIGON DISP_ON 10,23
AA29 PCIE_VSS_2 VSS_35 B5 1.8V(100mA)
AC26 D11 L19 BLM18PG181SN1D(180,1.5A)_6 +1.8V_LVDDC AJ18 LVDS channel
PCIE_VSS_3 VSS_36 +1.8V LVDDC_1
AD31 PCIE_VSS_4 VSS_37 C17 AH20 LVDDC_2 TXCLK_UP AD21 EXT_TXUCLKOUT+ 23
AE29 PCIE_VSS_5 VSS_38 C22 TXCLK_UN AE21 EXT_TXUCLKOUT- 23
AE30 C27 C133 C125 C144 AJ24
PCIE_VSS_6 VSS_39 TXOUT_U0P EXT_TXUOUT0+ 23
AE31 D29 1U/10V_4 1U/10V_4 1U/10V_4 AJ23
PCIE_VSS_7 VSS_40 TXOUT_U0N EXT_TXUOUT0- 23
D
F28 PCIE_VSS_8 VSS_41 C3 AF23 LVSSR_1 TXOUT_U1P AK24 EXT_TXUOUT1+ 23 D
G26 PCIE_VSS_9 VSS_42 C6 AF21 LVSSR_2 TXOUT_U1N AL24 EXT_TXUOUT1- 23
G29 PCIE_VSS_10 VSS_43 D3 AL18 LVSSR_3 TXOUT_U2P AG21 EXT_TXUOUT2+ 23
PCI-Express GND
G30 PCIE_VSS_11 VSS_44 D28 LVDDR AJ22 LVSSR_4 TXOUT_U2N AH21 EXT_TXUOUT2- 23
G31 PCIE_VSS_12 VSS_45 F29 LVDS Output Driver Analog Power Supply AJ25 LVSSR_5 TXOUT_U3P AG23
H29 PCIE_VSS_13 VSS_46 D4 1.8 V ± 3% AK18 LVSSR_6 TXOUT_U3N AH23
J25 PCIE_VSS_14 VSS_47 F11 AK23 LVSSR_7
J26 PCIE_VSS_15 VSS_48 F12 AK25 LVSSR_8 TXCLK_LP AL19 EXT_TXLCLKOUT+ 23
L26 PCIE_VSS_16 VSS_49 F14 LVDDC AJ21 LVSSR_9 TXCLK_LN AK19 EXT_TXLCLKOUT- 23
L29 PCIE_VSS_17 VSS_50 F16 LVDS Output Driver Digital Power Supply AL23 LVSSR_10 TXOUT_L0P AJ20 EXT_TXLOUT0+ 23
L30 PCIE_VSS_18 VSS_51 F18 1.8 V ± 3% AL25 LVSSR_11 TXOUT_L0N AJ19 EXT_TXLOUT0- 23
L31 PCIE_VSS_19 VSS_52 F20 TXOUT_L1P AK20 EXT_TXLOUT1+ 23
M26 PCIE_VSS_20 VSS_53 F21 TXOUT_L1N AL20 EXT_TXLOUT1- 23
M29 F23 LPVDD +1.8V_TPVDD AK21
PCIE_VSS_21 VSS_54 TXOUT_L2P EXT_TXLOUT2+ 23
P26 PCIE_VSS_22 VSS_55 F25 Analog Power for 1.8V(40mA) TXOUT_L2N AL21 EXT_TXLOUT2- 23
R29 PCIE_VSS_23 VSS_56 F7 transmitter PLL. It should AG18 LPVDD TXOUT_L3P AK22
R30 F9 AH18 AL22
R31
PCIE_VSS_24 VSS_57
G3 be a power for the PLL C155 LPVSS TXOUT_L3N
PCIE_VSS_25 VSS_58
T26 PCIE_VSS_26 VSS_59 G6 block of the macro. C143 C132
U29 H23 1.8 V ± 3% 100P/50V_4 1U/10V_4 0.1U/10V_4
PCIE_VSS_27 VSS_60 M72-S/M82-S
V26 PCIE_VSS_28 VSS_61 J3
Y26 PCIE_VSS_29 VSS_62 J4
Y29 PCIE_VSS_30 VSS_63 J6
Y30 K1 +3V_DELAY
PCIE_VSS_31 VSS_64
Y31 PCIE_VSS_32 VSS_65 L12
VSS_66 L15
VSS_67 L18
L21 GPIO0 R92 *10K/F_4
VSS_68
VSS_69 L6 CONFIGURATION STRAPS 18 GPIO0
A13 M11 18 GPIO1 GPIO1 R514 *10K/F_4
VSS_1 VSS_70
C A2 VSS_2 VSS_71 M14 C
C18 M17 18 GPIO5 GPIO5 R517 *10K/F_4
VSS_3 VSS_72
A24 VSS_4 VSS_73 M20
A30 M6 PIN DESCRIPTION OF DEFAULT SETTINGS M82-S 18 VIP_3 VIP_3 R475 *10K/F_4
VSS_5 VSS_74
AA1 VSS_6 VSS_75 P12
AA11 P15 18 GPIO8 GPIO8 R94 10K/F_4
VSS_7 VSS_76
AA14 VSS_8 VSS_77 P18 GPIO0 PCIE FULL TX OUTPUT SWING 0 R465 10K/F_4
AA17 VSS_9 VSS_78 P21 10,18,24 HSYNC_COM
AA20 VSS_10 VSS_79 P6
AA6 AC21 GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED 0 10,18,24 VSYNC_COM R485 *10K/F_4
VSS_11 VSS_80
AC2 VSS_12 VSS_81 R14
AC7 R17 18 PSYNC R79 *10K/F_4
VSS_13 VSS_82
AE3 VSS_15 VSS_83 R20 GPIO5 Allows eitherPCIe 2.5GT/s or 5GT/s operation REV
AL4 VSS_16 VSS_84 T6
AD14 VSS_17 VSS_85 U1
AF12 VSS_18 VSS_86 U12 VIP3 ENABLE HD AUDIO ( M8X-M ) 1
AF14 VSS_19 VSS_87 U15
AD16 VSS_20 VSS_88 U18
AD18 VSS_21 VSS_89 U21 GPIO8 ENABLE HD AUDIO ( M82-S ) 1
AE6 VSS_22 VSS_90 AE20
AG2 VSS_23 VSS_91 V14
AE9 VSS_24 VSS_92 V17 HSYNC ENABLED HDMI 1
AH25 VSS_25 VSS_93 V20
AK1 VSS_26 VSS_94 P2
AK31 VSS_27 VSS_95 V6
AJ6 VSS_28 VSS_96 W2
AL2 VSS_29 VSS_97 Y12
AL30 Y15
B1
VSS_30
VSS_31
VSS_98
VSS_99 Y18 Memory Aperture size SI-1 Modified -- follow AMD
B
C13 VSS_32 VSS_100 Y21 reference schematic change for B
VSS_101 Y6 reduce leakage to VDDR3 BUS
M9
VSS_102
GPIO9 GPIO13 GPIO12 GPIO11
CORE GND BIOSROM ROMIDCFG2 ROMIDCFG1 ROMIDCFG0
M72-S/M82-S 0 128M 0 0 0
0 256M 0 0 1
0 64M 0 1 0 +3V_DELAY
0 32M 0 1 1 GPIO9 R90 *10K/F_4

18 GPIO9
0 512M 1 0 0 18 GPIO13 GPIO13 R523 *10K/F_4
GPIO12 R521 *10K/F_4

0 1G 1 0 1 18 GPIO12
GPIO11 R520 10K/F_4
18 GPIO11
0 2G 1 1 0
A
0 4G 1 1 1 A
It is a shared pin strap with CONFIG[2:0] if BIOS_ROM_EN is set to 0.
PROJECT : QT8
Custom 1A
M7X/M8X_GND / LVDS/ Straps
NB5/RD5
5 4 3 2 1
5 4 3 2 1
20
PCIE_VDDR--PCI-E I/O power. 1.8 V ± 5%
U29D
VDDR1-- I/O power for the memory interface on M82 1.8 V ± 5% +1.8V_PCIE_VDDR
D D
PART 4 OF 6 1.8V(400mA)
1.8V(1.1A)
A15 AF30 +1.8V_PCIE_VDDR L74
+1.8V VDDR1_1 PCIE_VDDR_1 +1.8V
A22 VDDR1_2 PCIE_VDDR_2 AF31
A28 AF29 C759 BLM18PG181SN1D(180,1.5A)_6
C820 C438 C339 C312 VDDR1_3 PCIE_VDDR_3 C760 C761
A4 VDDR1_4 PCIE_VDDR_4 AF27
C263 C300 C305 A8 AF28 *0.1U/10V_4 1U/10V_4 10U/6.3V_8
1U/10V_4 1U/10V_4 1U/10V_4 VDDR1_5 PCIE_VDDR_5 +1.1V
10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 10U/6.3V_8 B8 AG29
VDDR1_6 PCIE_VDDR_6
C9 VDDR1_7 PCIE_VDDR_7 AG30
+1.1V_PCIE_VDDC
Memory I/O
D1 VDDR1_8 PCIE_VDDR_8 AG31 1.1V(1.0A)
H1 VDDR1_9
H11 AA23 +1.1V_PCIE_VDDC L21
VDDR1_10 PCIE_VDDC_1 BLM18PG181SN1D(180,1.5A)_6
H12 VDDR1_11 PCIE_VDDC_2 AC24
H14 AC25 C244 C219 C138
VDDR1_12 PCIE_VDDC_3
C311 C326 C298 C327 H16 VDDR1_13 PCIE_VDDC_4 AE26 C186 C207 PCIE_VDDC--PCI-E
H18 AE27 0.1U/10V_4 0.1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 Digital Power
PCI-Express
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 VDDR1_14 PCIE_VDDC_5
H20 VDDR1_15 PCIE_VDDC_6 AE28 Supply (Either 1.0
VDD_CT -- Level H21 L23
translation between B31
VDDR1_16 PCIE_VDDC_7
M23 V or 1.1 V) 1.0 V
+1.8V_VDD_CT VDDR1_17 PCIE_VDDC_8
core and I/O, 1.8V(110mA) M1 VDDR1_18 PCIE_VDDC_9 P23 -5% to 1.1 V +5%
T23
excluding memory L28 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDD_CT AA9
PCIE_VDDC_10
V23
+1.8V VDD_CT_1 PCIE_VDDC_11
receivers.1.8 V ± 5% Y9 VDD_CT_2 PCIE_VDDC_12 Y23 VDDC+VDDCI
C314 C257 V9 +VGA_CORE
VDD_CT_3 0.95~1.1V(15A peak )( Ripple < 87.2mV)
C291 T9 VDD_CT_4
VDDC--Dedicated core
10U/6.3V_8 1000P/50V_4 J11 L11 power, provides power
Q34 VDD_CT_5 VDDC_1
P-MOS,2.6A Gated 3.3V 0.1U/10V_4 J20 VDD_CT_6 VDDC_2 L14 to the internal
AO3409 +3V_DELAY C222 C232 C73
50mA by J21 VDD_CT_7 VDDC_3 L17
logic. 0.9 V - 1.2 V
L9 L20 C227 C215
VDDC +3V_DELAY VDD_CT_8 VDDC_4 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4 10U/6.3V_8 (± 5%)
C +3V 1 3 VDDC_5 M12 C
M72-S/M82-S M15
VDDC_6
VDD_R3 --IO power for C174 C191
I/O Internal
AC18 VDDR3_1 VDDC_7 M18
3.3 V pins (e.g. C184 AC16 M21
2
R443 1U/10V_4 1U/10V_4 0.1U/10V_4 VDDR3_2 VDDC_8

GPIO’s). 3.3 V ± 5% AC14 VDDR3_3 VDDC_9 AC20
100K/F_4 +VDDR4 AC12 P14
VDDR3_4 VDDC_10 C210 C262 C261 C86
VDDC_11 P17
+1.8V L94
BLM18PG181SN1D(180,1.5A)_6 C937
AF1
AF2
VDDR4_1 P VDDC_12 P20
R12 1U/10V_4 1U/10V_4 1U/10V_4
C266
1U/10V_4 10U/6.3V_8
VDDR4_2 VDDC_13
SI-1 Modified -- follow AMD C935 C936 O R15
Core
reference schematic change *10U/6.3V_8 1U/10V_4 0.1U/10V_4 VDDC_14
AE1 R18
D8 CH501H-40PT AE2
VDDR5_1
VDDR5_2
W VDDC_15
VDDC_16 R21
1 2 AD20
1.8/3.3V 150mA +VDDR5 E VDDC_17
VDDC_18 U14
L95 C233 C198 C228 C91
27,35,39,42,43,44 MAINON
+1.8V
C780 C779 M2
R VDDC_19 U17
U20 C200
R42 68.1K_4 BLM18PG181SN1D(180,1.5A)_6 C938 C781 RSVD_1 VDDC_20 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
M3 V12 10U/6.3V_8
*10U/6.3V_8 1U/10V_4 1U/10V_4 0.1U/10V_4 RSVD_2 VDDC_21
L4 RSVD_3 VDDC_22 V15
Q8 AD11 V18
RSVD_4 VDDC_23
3
2N7002E V21
D9 VDDC_24
VDDC_25 Y11
L30 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDDRH_1 A10 Y14
+1.8V VDDRH_1 VDDC_26
1 2 2 C347 A19 Y17 C181 C265 C211 C90
23,35,38,39,41,42 HWPG VDDRH_2 VDDC_27
Clock
I/O
Memory
C346 Y20 C229
*CH501H-40PT L-F 10U/6.3V_8 0.1U/10V_4 VDDC_28 1U/10V_4 1U/10V_4 1U/10V_4 1U/10V_4
AA12 10U/6.3V_8
VDDC_29
B10 VSSRH_1 VDDC_30 AA15
B19 AA18
1
L80 BLM18PG181SN1D(180,1.5A)_6 +1.8V_VDDRH_2 VSSRH_2 VDDC_31

+1.8V VDDC_32 AA21
R45 *75K/F_4 C58 P9
VDDC_33
B
C826 C825 BBN -0.75V 100mA B
10U/6.3V_8 V11 BBN_1
Back Bias
0.1U/10V_4 0.1U/10V_4 U11 J12 +VDDCI L27
+VBBP BBN_2 VDDCI_1 +VGA_CORE
J14 BLM18PG181SN1D(180,1.5A)_6
VDDCI_2
1.5/1.8V 120mA VDDCI_3 J16 C294 C282 C293
R11 BBP_1 VDDCI_4 J18 C283 VDDCI--Isolated (clean)
P11 0.1U/10V_4 0.1U/10V_4 1U/10V_4 10U/6.3V_8 core power for the l/O
C212 BBP_2
C260 logic. Voltage level
1U/10V_4 0.1U/10V_4 should match that of
VDDC. POWER Same as VDDC
VDD_R4 -- Power for DVPDATA_[23:12] - external
TMDS or GPIO; corresponds to +VBBP
DVOA_MSB_VMODE register bit; '1' - 3.3 V(default); *BLM18PG181SN1D(180,1.5A)_6 BBP -- Connect to VBBP back bias regulator / generator.
'0' - 1.8 V; 1.8 V ± 5% or 3.3 V ± 5% If back bias is not used, connect directly to VDDC.
+VGA_CORE L93 SI-1 modified -- ADD
power play function Back Bias Enabled:
VDD_R5 -- Power for DVP control pins Q61
(GPIO_21_BB_EN = 3.3 V):
(DVPCNTL_[0-2] and DVPCLK) and 2N7002E 1.5 V or 1.8 V
Q62
DVPDATA_[11:0] - external TMDS or GPIO; ME2303T1
corresponds to DVOA_LSB_VMODE register bit; 3 1 3 1 +1.8V
Back Bias Disabled:
+VGA_CORE
'1' - 3.3 V(default); '0' - 1.8 V; 1.8 V (GPIO_21_BB_EN = 0 V):
± 5% or 3.3 V ± 5% VDDC
2
R752 100K/F_4
VDDRH_1 & VDDRH_2 --Dedicated power 1 2 +5V
A pins for memory clock pads for each A
3
channel. Should have the same

voltage level as VDDR1.
2 Q63
18 BBEN
2N7002E
PROJECT : QT8
1

Custom 1A
M7X/M8X_Power_and_NC
NB5/RD5
5 4 3 2 1
5 4 3 2 1
22 ODTA0 ODTA0
ODTA1
MDA0
MDA1
E29
U29C
DQ_0
Part 3 of 6
MA_0 B14 MAA0

MAA1
21
22 ODTA1 E30 DQ_1 MA_1 A14
MDA2 E31 B13 MAA2
RASA0# MDA3 DQ_2 MA_2 MAA3
22 RASA0# D31 DQ_3 MA_3 E14
RASA1# MDA4 MAA4
D 22 RASA1#
MDA5
C29
B29
DQ_4 MEMORY MA_4 B17
A17 MAA5 D
CASA0# MDA6 DQ_5 MA_5 MAA6
22 CASA0#
CASA1# MDA7
B30
A29
DQ_6 INTERFACE MA_6 C15
G16 MAA7
22 CASA1# DQ_7 MA_7
MDA8 E26 E16 MAA8
WEA0# MDA9 DQ_8 MA_8 MAA9
22 WEA0# D26 DQ_9 MA_9 C14
22 WEA1# WEA1# MDA10 E25 A12 MAA10
MDA11 DQ_10 MA_10 MAA11
D25 DQ_11 MA_11 B12
22 CSA0#_0 CSA0#_0 MDA12 G23 C12 A_BA0
MDA13 DQ_12 MA_BA0 A_BA1
G21 DQ_13 MA_BA1 D14
MDA14 E21 B15 MAA12
CSA1#_0 MDA15 DQ_14 MA_A12 A_BA2
22 CSA1#_0 D21 DQ_15 MA_BA2 G14 A_BA2 22
MDA16 C28
MDA17 DQ_16 DQMA#0
B28 DQ_17 DQMb_0 D30
22 CKEA0 CKEA0 MDA18 B27 DQ_18 DQMb_1 G25 DQMA#1 SI-1 modified --
22 CKEA1 CKEA1 MDA19 A27 C26 DQMA#2 for support
MDA20 DQ_19 DQMb_2 DQMA#3
C25 DQ_20 DQMb_3 C21 1Gbit VRAM ( 64M
22 CLKA0 CLKA0 MDA21 A25 C5 DQMA#4
22 CLKA0# CLKA0# MDA22 C24
DQ_21 DQMb_4
D6 DQMA#5 X 16 )
MDA23 DQ_22 DQMb_5 DQMA#6
B24 DQ_23 DQMb_6 D2
22 CLKA1 CLKA1 MDA24 C23 K3 DQMA#7
CLKA1# MDA25 DQ_24 DQMb_7
22 CLKA1# B23 DQ_25
MDA26 A23 C30 QSA0
QSA#[7..0] MDA27 DQ_26 QS_0 QSA1
22 QSA#[7..0] B22 DQ_27 QS_1 D23
MDA28 C20 B26 QSA2
C DQ_28 QS_2 C
QSA[7..0] MDA29 B20 B21 QSA3
22 QSA[7..0] DQ_29 QS_3
MDA30 A20 B6 QSA4
read strobe
DQMA#[7..0] MDA31 DQ_30 QS_4 QSA5
22 DQMA#[7..0] C19 DQ_31 QS_5 E7
MDA32 C8 E2 QSA6
MDA[63..0] MDA33 DQ_32 QS_6 QSA7
22 MDA[63..0] C7 DQ_33 QS_7 J2
MDA34 B7
MAA[12..0] MDA35 DQ_34 QSA#0
22 MAA[12..0] A7 DQ_35 QS_0B C31
MDA36 A5 E23 QSA#1
MDA37 DQ_36 QS_1B QSA#2
write strobe
C4 DQ_37 QS_2B A26
MDA38 B4 A21 QSA#3
A_BA0 MDA39 DQ_38 QS_3B QSA#4
22 A_BA0 A3 DQ_39 QS_4B A6
22 A_BA1 A_BA1 MDA40 G9 D7 QSA#5
MDA41 DQ_40 QS_5B QSA#6
E9 DQ_41 QS_6B E1
MDA42 D9 J1 QSA#7
MDA43 DQ_42 QS_7B
G7 DQ_43
MDA44 G5 E20 ODTA0
MDA45 DQ_44 ODT0 ODTA1
F5 DQ_45 ODT1 C11
MDA46 G4
MDA47 DQ_46 CLKA0
F4 DQ_47 CLK0 A18
MDA48 B3 A11 CLKA1
MDA49 DQ_48 CLK1
B2 DQ_49
MDA50 C2 B18 CLKA0#
MDA51 DQ_50 CLK0b CLKA1#
C1 DQ_51 CLK1b B11
B MDA52 E3 B
MDA53 DQ_52 RASA0#
F3 DQ_53 RAS0b G20
MDA54 F2 D12 RASA1#
MDA55 DQ_54 RAS1b
F1 DQ_55
MDA56 G2 D20 CASA0#
+1.8V MDA57 DQ_56 CAS0b CASA1#
G1 DQ_57 CAS1b E12
MDA58 H3
MDA59 DQ_58 CSA0#_0
H2 DQ_59 CS0b_0 E18
MDA60 K2 G18
R116 MDA61 DQ_60 CS0b_1
L3 DQ_61
100/F_4 MDA62 L2 G11 CSA1#_0
MDA63 DQ_62 CS1b_0
L1 DQ_63 CS1b_1 E11
MVREFD F30 D18 CKEA0

+1.8V MVREFD CKE0 CKEA1
F31 MVREFS CKE1 G12
D16 WEA0#
R113 R98 4.7K_4 WE0b WEA1#
L5 TEST_MCLK WE1b C10
C338 100/F_4 R532 R102 4.7K_4 L7
0.1U/10V_4 100/F_4 R97 240/F_4 TEST_YCLK
J7 MEMTEST DRAM_RST J5 +1.8V
R101 4.7K_4
MVREFS Change MEMTEST to 240 1% M72-S/M82-S
ohm to GND , AMD update
A A
R529
C817
0.1U/10V_4
100/F_4
PROJECT : QT8
B 1A
M7X/M8X/MEM_Interface
NB5/RD5
5 4 3 2 1
5 4 3 2 1
A_BA0
A_BA1
MAA12
MAA11
L2
L3
R2
P7
U5
BA0
BA1
A12
DQ15
DQ14
DQ13
DQ12
B9
B1
D9
D1
D3
MDA9
MDA13
MDA10
MDA15
MDA14
DDR2 BGA
MEMORY A_BA0
A_BA1
MAA12 R2
L2
L3
U35
BA0
BA1
DQ15
DQ14
DQ13
B9
B1
D9
D1
MDA6
MDA0
MDA7
MDA1
21 QSA[7..0]
QSA[7..0]
QSA#[7..0]
22
A11 DQ11 A12 DQ12 21 QSA#[7..0]
MAA10 M2 D7 MDA8 MAA11 P7 D3 MDA2
MAA9 A10/AP DQ10 MDA12 MAA10 A11 DQ11 MDA5 DQMA#[7..0]
P3 A9 DQ9 C2 M2 A10/AP DQ10 D7 21 DQMA#[7..0]
MAA8 P8 C8 MDA11 MAA9 P3 C2 MDA3
MAA7 A8 DQ8 MDA17 MAA8 A9 DQ9 MDA4 MDA[63..0]
P2 A7 DQ7 F9 P8 A8 DQ8 C8 21 MDA[63..0]
MAA6 N7 F1 MDA22 MAA7 P2 F9 MDA28
MAA5 A6 DQ6 MDA16 MAA6 A7 DQ7 MDA25 MAA[12..0]
N3 A5 DQ5 H9 N7 A6 DQ6 F1 21 MAA[12..0]
MAA4 N8 H1 MDA21 MAA5 N3 H9 MDA30
MAA3 A4 DQ4 MDA23 MAA4 A5 DQ5 MDA27
N2 A3 DQ3 H3 N8 A4 DQ4 H1
MAA2 M7 H7 MDA18 MAA3 N2 H3 MDA26
MAA1 A2 DQ2 MDA20 MAA2 A3 DQ3 MDA29 A_BA0
D
M3 A1 DQ1 G2 M7 A2 DQ2 H7 21 A_BA0 D
MAA0 M8 G8 MDA19 MAA1 M3 G2 MDA24 21 A_BA1 A_BA1
A0 DQ0 MAA0 A1 DQ1 MDA31
M8 A0 DQ0 G8
CLKA0# K8 A9
CLKA0 CK VDDQ1 CLKA0#
J8 CK VDDQ2 C1 K8 CK VDDQ1 A9
C3 CLKA0 J8 C1
CKEA0 VDDQ3 CK VDDQ2
K2 CKE VDDQ4 C7 VDDQ3 C3
C9 CKEA0 K2 C7
VDDQ5 CKE VDDQ4
VDDQ6 E9 VDDQ5 C9
G1 +1.8V E9
CSA0#_0 VDDQ7 VDDQ6 +1.8V
L8 CS VDDQ8 G3 VDDQ7 G1
G7 CSA0#_0 L8 G3
WEA0# VDDQ9 CS VDDQ8
K3 WE VDDQ10 G9 VDDQ9 G7
WEA0# K3 G9
RASA0# WE VDDQ10 CLKA0
K7 RAS VDD1 A1 21 CLKA0
E1 RASA0# K7 A1
CASA0# VDD2 RAS VDD1 CLKA0#
L7 CAS VDD3 J9 VDD2 E1 21 CLKA0#
M9 CASA0# L7 J9
DQMA#2 VDD4 CAS VDD3
F3 LDM VDD5 R1 VDD4 M9
DQMA#1 B3 DQMA#3 F3 R1 R155 R156
UDM DQMA#0 LDM VDD5 56.2/F_4 56.2/F_4
VDDL J1 B3 UDM
VSSDL J7 VDDL J1
ODTA0 K9 C432 J7
ODT ODTA0 VSSDL C345
K9 ODT
0.1U/10V_4
+1.8V QSA2 F7 0.1U/10V_4 C440
QSA#2 LDQS QSA3
E8 LDQS VSSQ1 A7 F7 LDQS
B2 +1.8V QSA#3 E8 A7 470P/50V_4
VSSQ2 LDQS VSSQ1
VSSQ3 B8 VSSQ2 B2
VSSQ4 D2 VSSQ3 B8
R115 QSA1 B7 D8 D2
4.99K/F_4 QSA#1 UDQS VSSQ5 QSA0 VSSQ4
A8 UDQS VSSQ6 E7 B7 UDQS VSSQ5 D8
F2 R159 QSA#0 A8 E7
VSSQ7 4.99K/F_4 UDQS VSSQ6 ODTA0
VSSQ8 F8 VSSQ7 F2 21 ODTA0
M_VREF1 (SSTL-1.8) VREF = .5*VDDQ J2 H2 F8
VREF VSSQ9 (SSTL-1.8) VREF = .5*VDDQ M_VREF2 VSSQ8 RASA0#
VSSQ10 H8 J2 VREF VSSQ9 H2 21 RASA0#
A2 NC#A2 VSSQ10 H8
C C341 E2 A3 A2 21 CASA0# CASA0# C
R114 NC#E2 VSS1 C425 NC#A2
21 A_BA2 L1 BA2 VSS2 E3 E2 NC#E2 VSS1 A3
4.99K/F_4 0.1U/10V_4 R3 J3 R161 L1 E3 21 WEA0# WEA0#
NC#R3 VSS3 21 A_BA2 BA2 VSS2
R7 N1 4.99K/F_4 0.1U/10V_4 R3 J3
A15 VSS4 NC#R3 VSS3
SI-1 modified -- R8 A13 VSS5 P9 R7 A15 VSS4 N1 21 CSA0#_0 CSA0#_0
for support R8 A13 VSS5 P9
1Gbit VRAM ( 64M SI-1 modified -- 21 CKEA0 CKEA0
+1.8V X 16 ) for support

HYB18T512161B2F-20
1Gbit VRAM ( 64M +1.8V HYB18T512161B2F-20
X 16 )
C418 C431 C423 C437 C436 C821 C422
C439 C433 C427 C426 C413 C407 C434 21 ODTA1 ODTA1
10U/6.3V_8 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.01U/16V_4
*10U/6.3V_8 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.01U/16V_4 21 RASA1# RASA1#
21 CASA1# CASA1#
21 WEA1# WEA1#
U34 U4
A_BA0 L2 B9 MDA60 A_BA0 L2 B9 MDA43 21 CSA1#_0 CSA1#_0
A_BA1 BA0 DQ15 MDA59 A_BA1 BA0 DQ15 MDA47
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 MDA61 D9 MDA41 21 CKEA1 CKEA1
MAA12 DQ13 MDA58 MAA12 DQ13 MDA46
R2 A12 DQ12 D1 R2 A12 DQ12 D1
MAA11 P7 D3 MDA56 MAA11 P7 D3 MDA44
M2 A10/AP DQ10 D7 M2 A10/AP DQ10 D7
MAA9 P3 C2 MDA57 MAA9 P3 C2 MDA45
P8 A8 DQ8 C8 P8 A8 DQ8 C8
MAA7 P2 F9 MDA52 MAA7 P2 F9 MDA35
MAA6 A7 DQ7 MDA50 MAA6 A7 DQ7 MDA37 CLKA1
N7 A6 DQ6 F1 N7 A6 DQ6 F1 21 CLKA1
MAA4 A5 DQ5 MDA49 MAA4 A5 DQ5 MDA38 CLKA1#
N8 A4 DQ4 H1 N8 A4 DQ4 H1 21 CLKA1#
M7 A2 DQ2 H7 M7 A2 DQ2 H7
MAA1 M3 G2 MDA51 MAA1 M3 G2 MDA39 R576 R575
MAA0 A1 DQ1 MDA55 MAA0 A1 DQ1 MDA34 56.2/F_4 56.2/F_4
M8 A0 DQ0 G8 M8 A0 DQ0 G8
B B
CLKA1# K8 A9 CLKA1# K8 A9
CLKA1 CK VDDQ1 CLKA1 CK VDDQ1
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1
C3 C3 C857
CKEA1 VDDQ3 CKEA1 VDDQ3
K2 CKE VDDQ4 C7 K2 CKE VDDQ4 C7
C9 C9 470P/50V_4
VDDQ5 VDDQ5
VDDQ6 E9 VDDQ6 E9
G1 +1.8V G1 +1.8V
CSA1#_0 VDDQ7 CSA1#_0 VDDQ7
L8 CS VDDQ8 G3 L8 CS VDDQ8 G3
VDDQ9 G7 VDDQ9 G7
WEA1# K3 G9 WEA1# K3 G9
WE VDDQ10 WE VDDQ10
RASA1# K7 A1 RASA1# K7 A1
RAS VDD1 RAS VDD1
VDD2 E1 VDD2 E1
CASA1# L7 J9 CASA1# L7 J9
CAS VDD3 CAS VDD3
VDD4 M9 VDD4 M9
DQMA#6 F3 R1 DQMA#4 F3 R1
DQMA#7 LDM VDD5 DQMA#5 LDM VDD5
B3 UDM B3 UDM
VDDL J1 VDDL J1
VSSDL J7 VSSDL J7
ODTA1 K9 C365 ODTA1 K9 C435
ODT ODT
0.1U/10V_4 0.1U/10V_4
QSA6 F7 QSA4 F7
+1.8V QSA#6 LDQS +1.8V QSA#4 LDQS
E8 LDQS VSSQ1 A7 E8 LDQS VSSQ1 A7
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
VSSQ4 D2 VSSQ4 D2
QSA7 B7 D8 QSA5 B7 D8
R530 QSA#7 UDQS VSSQ5 R162 QSA#5 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
4.99K/F_4 F2 4.99K/F_4 F2
VSSQ7 VSSQ7
VSSQ8 F8 VSSQ8 F8
M_VREF3 J2 H2 M_VREF4 J2 H2
(SSTL-1.8) VREF = .5*VDDQ VREF VSSQ9 (SSTL-1.8) VREF = .5*VDDQ VREF VSSQ9
VSSQ10 H8 VSSQ10 H8
A2 NC#A2 A2 NC#A2
C816 E2 A3 C424 E2 A3
R531 NC#E2 VSS1 R158 NC#E2 VSS1
21 A_BA2 L1 BA2 VSS2 E3 21 A_BA2 L1 BA2 VSS2 E3
A 4.99K/F_4 0.1U/10V_4 R3 J3 4.99K/F_4 0.1U/10V_4 R3 J3 A
NC#R3 VSS3 NC#R3 VSS3
R7 A15 VSS4 N1 R7 A15 VSS4 N1
R8 A13 VSS5 P9 SI-1 modified -- R8 A13 VSS5 P9
SI-1 modified -- for support
for support 1Gbit VRAM ( 64M
1Gbit VRAM ( 64M HYB18T512161B2F-20 X 16 ) HYB18T512161B2F-20
X 16 ) DDR2 BGA MEMORY
+1.8V +1.8V
PROJECT : QT8
C357 C393 C428 C335 C322 C429 C371 C444 C348 C421 C342 C430 C404 C395 Quanta Computer Inc.
10U/6.3V_8 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.01U/16V_4 10U/6.3V_8 1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.01U/16V_4
C 1A
NB5/RD5
M7X/M8X/VRAM_A0,A1
5 4 3 2 1
1 2 3 4 5 6 7 8
+12VALW
23
+3V
1. If LCD connector near GPU, then place these series Resistors near GPU
2. If LCD connector near N/B, then place these series Resistors near N/B +3V R8 2.2K_4 EDIDCLK
2
C16
OPTION SIGNAL FROM NB to LVDS for UMA R19 AO3404 ID 0.1U/10V_4 R7 2.2K_4 EDIDDATA
current
LA_CLK RP3 1 2 *0_4P2R_4 TXLCLKOUT+ 330K_6 R401 75R/F_6 +LOGO_PWR
10 LA_CLK 5.8A +5V
3
10 LA_CLK# LA_CLK# 3 4 TXLCLKOUT- +5VSUS N-MOS,5.8A
1
LA_DATAP0 RP1 1 2 *0_4P2R_4 TXLOUT0+ Q1 +3VLCD
10 LA_DATAP0
LA_DATAN0 3 4 TXLOUT0- AO3404 L1 +3VLCD_CON
10 LA_DATAN0 RP4 *0_4P2R_4 TXLOUT1+ +3VLCD
LA_DATAP1 1 2 LCDONG 2 PBY201209T-4A_8 C12 10U/6.3V_8
10 LA_DATAP1
1
10 LA_DATAN1
LA_DATAN1 3 4 TXLOUT1- SI-2 modified-delete R402 and C10 0.1U/10V_4
1
LA_DATAP2 RP5 1 2 *0_4P2R_4 TXLOUT2+ R14 R401 from 0ohm to 75ohm C13 0.01U/16V_4
10 LA_DATAP2
3
LA_DATAN2 3 4 TXLOUT2- R10
A 10 LA_DATAN2 A
100K/F_4 +VIN_BLIGHT +VIN_BLIGHT
1
10 LB_CLK LB_CLK RP2 3 4 *0_4P2R_4 TXUCLKOUT+ 22_8 +3VLCD_CON
2
10 LB_CLK# LB_CLK# 1 2 TXUCLKOUT- 2 +3VLCD_CON 41
2
1
LB_DATAP0 RP6 1 2 *0_4P2R_4 TXUOUT0+ C6 1000P/50V_4
10 LB_DATAP0 1 2
LB_DATAN0 3 4 TXUOUT0- Q3 Q4 C22 LCDDISCHG
10 LB_DATAN0 3 4
3
10 LB_DATAP1
LB_DATAP1 RP8 1 2 *0_4P2R_4 TXUOUT1+ PDTC144EU 2N7002E 0.1U/10V_4
2
LB_DATAN1 TXUOUT1- 5 6
10 LB_DATAN1 3 4 +3V EDIDCLK 10,18
1
7 8
3
LB_DATAN2 RP7 3 4 *0_4P2R_4 TXUOUT2- 10,19 DISP_ON 2 EDIDDATA VADJ1
10 LB_DATAN2 10,18 EDIDDATA 9 10
LB_DATAP2 1 2 TXUOUT2+ +LOGO_PWR
10 LB_DATAP2 11 12
LCDON# Q2 BLONCON 13 14
2 Camera Pin
1
R17 2N7002E C678 1000P/50V_4 15 16
2.2K_4 TXLCLKOUT+ 17 18 TXUCLKOUT+
OPTION SIGNAL FROM M8X to LVDS for discrete TXLCLKOUT- 19 20 TXUCLKOUT-
EXT_TXLCLKOUT- RP59 1 0_4P2R_4 TXLCLKOUT- 21 22
19 EXT_TXLCLKOUT- 2
1
EXT_TXLCLKOUT+ TXLCLKOUT+ TXLOUT0+ 23 24 TXUOUT0+
19 EXT_TXLCLKOUT+ 3 4 25 26
EXT_TXLOUT0- RP57 1 2 0_4P2R_4 TXLOUT0- TXLOUT0- TXUOUT0-
19 EXT_TXLOUT0- 27 28
EXT_TXLOUT0+ 3 4 TXLOUT0+
19 EXT_TXLOUT0+ 29 30
EXT_TXLOUT1- RP60 1 2 0_4P2R_4 TXLOUT1- D5 CH501H-40PT TXLOUT1+ TXUOUT1+
EXT_TXLOUT1+ 3 4 TXLOUT1+ PN_BLON 2 1 BLONCON C28 22P/50V_4 TXLOUT1- TXUOUT1-
19 EXT_TXLOUT1+ RP61 3 0_4P2R_4 33 34
EXT_TXLOUT2+ 4 TXLOUT2+
19 EXT_TXLOUT2+ 35 36
EXT_TXLOUT2- 1 2 TXLOUT2- +3VPCU R24 33K_6 TXLOUT2+ TXUOUT2+
R22 100K/F_4 TXLOUT2- TXUOUT2-
EXT_TXUCLKOUT- RP58 3 0_4P2R_4 TXUCLKOUT- D6 CH501H-40PT 39 40
19 EXT_TXUCLKOUT- 4 41 42
19 EXT_TXUCLKOUT+ EXT_TXUCLKOUT+ 1 2 TXUCLKOUT+ LVDS_BLON R23 1K/F_4 PN_BLON 2 1 LID_EC#
RP62 3 0_4P2R_4 10,18 LVDS_BLON LID_EC# 34,35 42
EXT_TXUOUT0+ 4 TXUOUT0+ CN1
19 EXT_TXUOUT0+
EXT_TXUOUT0- 1 2 TXUOUT0-
19 EXT_TXUOUT0-
EXT_TXUOUT1- RP64 1 2 0_4P2R_4 TXUOUT1- 2 1 LCD CONN
19 EXT_TXUOUT1- HWPG 20,35,38,39,41,42
EXT_TXUOUT1+ 3 4 TXUOUT1+ 10,19 DPST_PWM DPST_PWM R88 *0_4
19 EXT_TXUOUT1+
3
B EXT_TXUOUT2- RP63 1 2 0_4P2R_4 TXUOUT2- D7 CH501H-40PT B
19 EXT_TXUOUT2-
EXT_TXUOUT2+ 3 4 TXUOUT2+ PWM_VADJ R96 0_4 VADJ1
19 EXT_TXUOUT2+ 35 PWM_VADJ
LCD_BK 2
12 LCD_BK
Q5 Del R21 and Pull hi R259 to
+3VS5, add D7 to HWPG on PV C5 C7
R259 PDTC144EU PV del logo light
1
*10K/F_4 *4.7U/6.3V_6 0.1U/10V_4
+3VS5
UMA/DISCRETE select for HDMI HDMI HPD SENSE

TMDS_HPD R66 20K/F_4 HDMI_DET
10,18 TMDS_HPD
for Layout
From RS780M for Layout concern check 3v or 5v
1
concern +VIN_BLIGHT
,placement close D10 R64
,placement close HDMI conn L2 FBM2125 HM330-T(4A,0.015)_8 100K/F_4
north bridge +VIN
UDZS2.7BTE-17
RP31
2
9 C_PEG_TX#15 C_PEG_TX#15 C386 *0.1U/10V_4 TX2_HDMI-L TX2_HDMI+L 3 4 *0_4P2R_4 TX2_HDMI+ C15 C11 C9 C14 C8
9 C_PEG_TX15 C_PEG_TX15 C387 *0.1U/10V_4 TX2_HDMI+L TX2_HDMI-L 1 2 TX2_HDMI- 0.1U/50V_6 0.01U/50V_4 0.1U/50V_6 *10U/25V_12 0.1U/50V_6
RP23
9 C_PEG_TX#14 C_PEG_TX#14 C388 *0.1U/10V_4 TX1_HDMI-L TX1_HDMI-L 3 4 *0_4P2R_4 TX1_HDMI-
9 C_PEG_TX14 C_PEG_TX14 C389 *0.1U/10V_4 TX1_HDMI+L TX1_HDMI+L 1 2 TX1_HDMI+
RP37
9 C_PEG_TX#13 C_PEG_TX#13 C355 *0.1U/10V_4 TX0_HDMI-L TX0_HDMI+L 3 4 *0_4P2R_4 TX0_HDMI+
+5V_HDMVCC +5V_HDMVCC
C 9 C_PEG_TX13 C_PEG_TX13 C344 *0.1U/10V_4 TX0_HDMI+L TX0_HDMI-L 1
RP17
2 TX0_HDMI-
UMA AND DISCRETE HDMI I2C SELECT C
C_PEG_TX#12 C827 *0.1U/10V_4 TXC_HDMI-L TXC_HDMI-L 3 4 *0_4P2R_4 TXC_HDMI-

9 C_PEG_TX#12
Close to HDMI Connector
2
9 C_PEG_TX12 C_PEG_TX12 C828 *0.1U/10V_4 TXC_HDMI+L TXC_HDMI+L 1 2 TXC_HDMI+
D31 D32
CH501H-40PT RP65 0_4P2R_4
1 2 HDMI_SDATA
18 HDMI_SDA 3 4 HDMI_SCLK
1
CH501H-40PT Change R494, 18 HDMI_SCL
From M82-S R503 to 4.7K for
18 TX2_HDMI_L- TX2_HDMI_L-
TX2_HDMI_L+
C794
C789
0.1U/10V_4
0.1U/10V_4
TX2_HDMI-
TX2_HDMI+
R494
4.7K_4
R503
4.7K_4
AMD on PV Discrete DDC4 is 5V DIS
18 TX2_HDMI_L+ tolerance , the MOSFET Change 2N7002
+3V +5V
18 TX1_HDMI_L- TX1_HDMI_L- C782 0.1U/10V_4 TX1_HDMI- for Layout HDMI_SCLK HDMI_SDATA level shifter no need to FDV301N for
TX1_HDMI_L+ C786 0.1U/10V_4 TX1_HDMI+ concern
18 TX1_HDMI_L+ UMA DDC is 3V AMD on PV
18 TX0_HDMI_L-
18 TX0_HDMI_L+
TX0_HDMI_L-
TX0_HDMI_L+
C799
C797
0.1U/10V_4
0.1U/10V_4
TX0_HDMI-
TX0_HDMI+
,placement close
HDMI conn HDMI PORT CN29
tolerance,the MOSFET
level shifter is need
R680
*2K/04
2
SHELL1 20
18 TXC_HDMI_L- TXC_HDMI_L- C768 0.1U/10V_4 TXC_HDMI- TX2_HDMI+ 1 22
TXC_HDMI_L+ C776 TXC_HDMI+ D2+SHELL3
18 TXC_HDMI_L+ 0.1U/10V_4 2 D2 Shield 1 3HDMI_SCLK
TX2_HDMI- 3 10 HDMI_DDC_CLK
TX1_HDMI+ D2- Q59
4 D1+
5 +3V *FDV301N
TX1_HDMI- D1 Shield +5V
6
R507 499/F_4 TX2_HDMI+
Del C748, C756 for
TX0_HDMI+ 7
8
D1-
D0+
HDMI_DDC_CLK R753 *0_4 HDMI_SCLK
R681
UMA
R508 499/F_4 TX2_HDMI- TX0_HDMI- D0 Shield HDMI_DDC_DATA R755 *0_4 HDMI_SDATA Q60
HDMI on PV 9 D0- *2K/04
2
+5V
UMA RS780M TXC_HDMI+ 10 CK+
*FDV301N
3
R506 499/F_4 TX1_HDMI+ 11 CK Shield

D Q36
2N7002E R505 499/F_4 TX1_HDMI-
上 750 ohm CS17502FB19 TXC_HDMI- 12 CK- 10 HDMI_DDC_DATA
1 3 HDMI_SDATA D
13 CE Remote
2 14 NC
R512 499/F_4 TX0_HDMI+
DIS M82-S HDMI_SCLK
HDMI_SDATA
L73 1
L75 1
2 0_6
2 0_6
HDMISCL
HDMISDA
15
16
DDC CLK
DDC DATA
R515 499/F_4 TX0_HDMI- 上 499 ohm CS14992FB24 17
PROJECT : QT8
+5V_HDMVCC GND
18
1
R528 R504 499/F_4 TXC_HDMI+ FUSE1A6V_POLY +5V

19 HP DET
SHELL4 23
1 2 2 1 21
100K/F_4
R500 499/F_4 TXC_HDMI- Close to HDMI Connector +5V
F1
C128 *0.1U/10V_4
SHELL2
HDMI CONN
Custom 1A
LCD CONN,HDMI CONN
HDMI_DET NB5/RD5
1 2 3 4 5 6 7 8
5 4 3 2 1
CRT PORT
2
F2 40 mils
1
+5VCRT
+5VCRT
C670
0.1U/10V_4
40 MIL
SI-2 modified --Change Layout footprint 12/27
24
+5V
16
FUSE1A6V_POLY
6
CRT_R_1_L L61 BLM18BA470SN1(47,300MA)_6 CRT_R1 1 11 +3V
D
7 D
CRT_G_1_L L60 BLM18BA470SN1(47,300MA)_6 CRT_G1 2 12 D28 *BAV99W
8 1
CRT_B_1_L L59 BLM18BA470SN1(47,300MA)_6 CRT_B1 3 13 CRT_R1
3
9
4 14 2
10
R400 R399 R398 C677 C675 C672 C671 C674 C676 5 15
D27 *BAV99W
150/F_4 150/F_4 150/F_4 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6
1 CRT_G1
EMI
17
3
CRT CONN
close conn CN20 2
R400 for UAM use 140 ohm within 600mils

D26 *BAV99W
on PV(AMD) +5V R1 0_4 CRTDDCCLK2 1 CRT_B1
3
R3 33_4 CRTVSYNC
+5V 2
R4 33_4 CRTHSYNC
D1 *BAV99W
5
1
C673 0.1U/10V_4 R5 0_4 CRTDDCDAT2
U21 1 DDCCLK2
3
10,18,19 VSYNC_COM 2 4 PR_VSYNC 37 2

AHCT1G125DCH C1 C2 C3 C4
D2 *BAV99W
C *470P/50V_4 *47P/50V_4 *47P/50V_4 *47P/50V_4 C
1
5
CRTVSYNC
U22 AHCT1G125DCH 3
2
10,18,19 HSYNC_COM 2 4 PR_HSYNC 37
D3 *BAV99W
+3V_DELAY R761 4.7K_4 +3V
1
follow AMD 3
CRTHSYNC
reference +3V R25 *4.7K_4
2
schematic change 2
for reduce DDCCLK 1 3 DDCCLK2 DDCCLK2 37
leakage to VDDR3 10,18 DDCCLK D4 *BAV99W
BUS Q6
2N7002E 1 DDCDAT2
R762 4.7K_4 +3V 3
+3V_DELAY
R26 *4.7K_4 2
+3V
2
DDCDATA 1 3 DDCDAT2 DDCDAT2 37

10,18 DDCDATA
Q7
2N7002E
R2 R6
6.81K_4 6.81K_4
B B
+5VCRT 2 1 +5V_CRT2
+5VCRT
CH501H-40PT D25
PR_RED
U23
37 PR_RED 2 IA0 inputs function
CRT_R_1_L 3
PR_GEN IA1 CRT_R
37 PR_GEN 5 IB0 YA 4 CRT_R 10,18
CRT_G_1_L 6 7 CRT_G
IB1 YB CRT_G 10,18
PR_BLU 11 9 CRT_B /E SET
37 PR_BLU IC0 YC CRT_B 10,18
CRT_B_1_L 10 12
IC1 YD
14 ID0
13 ID1 L L Y - port 0
1 16 +5V_SW R403 0_6 +5V
35,37 PR_INSERT# SEL VCC
15 8 R404 L H Y - port 1
/E GND
1
10K/F_4
74CBT3257 C679 H X Disconnect
0.1U/10V_4
2
EMI
A CRT SWITCH A
PROJECT : QT8
Custom 1A
CRT
NB5/RD5
5 4 3 2 1
8 7 6 5 4 3 2 1
For 5158
25
For 5158E
2 CLK_48M_CR R397 *0_4 XTLO UMA BOM need to add
SP6 R339 *0_4 SD_DAT1
Note: SP7 R315
R316
*0_4
*0_4
MS_DATA0_SD_DAT0
XD-D6
SP6 R334 *0_4 MS_DATA1
SP4 R333 *0_4 SD/MMC MS XD R338 *0_4 XD-D3
+3VSUS R321 *100K/F_4 U19 SP8 R345 *0_4 MS_DATA2_XD_D2
43 SP19 For 5158E SP1 XD_CD# SP16 R666 *0_4 SD_DAT2
XD_CLE/CF_D3 SP18 SP2 SD_WP R676 *0_4 XD-RE#
XD_CE#/CF_D11 42
13 41 SP17 SP3 SD_CD# SP5 R327 *0_4 MS_BS
R320 *0_4 CARD_LEDO CF_CD# XD_ALE/CF_D4 SP4 SD_DAT1 XD_D4 R335 *0_4 XD-D5
26,29 CARD_LED# 14 GPIO0
15 40 SP16 SP5 MS_BS XD_D5 SP15 R675 *0_4 SD_DAT3
CF_D10 SD_DAT2/XD_RE#/CF_D12 SP15 SP6 SD_DAT1 MS_D1 XD_D3 R390 *0_4 XD_WE
16 CF_D9 SD_DAT3/XD_WE#/CF_D5 39 AL005158B10 -->RTS5158E
17 38 SP14 SP7 SD_DAT0 MS_D0 XD_D6 SP11 R354 *0_4 SD_CLK_MS_CLK
CF_D2 XD_RDY/CF_D13 SP13 SP8 SD_DAT7 MS_D2 XD_D2 R358 *0_4 XD-D1
D XD_CD#
18 CF_D8/SM_CD# SD_DAT4/XD_WP#/CF_D6 37 AL005158B00 -->RTS5158 SP2 SD_WP D
19 SP9 MS_INS# R319 *0_4
SP2 CF_D1/XD_CD# SD_CMD_R SP10 SD_DAT6 MS_D3 XD_D7 SP13 R677 *0_4 XD-WP#
20 CF_D0/SM_WPM#/SD_WP SD_CMD 36
SD_CD# 21 35 SP12 SP11 SD_CLK MS_SCLK XD_D1 SP19 R393 *0_4 XD-CLE
CF_A0/SD_CD# SD_DAT5/XD_D0/CF_D14 SP11 SP12 SD_DAT5 XD_D0 SP4 R317 *0_4 XD-D4
22 CF_DMACK# SD_CLK/XD_D1/MS_CLK/CF_D7 34
SP4 23 31 SP10 SP13 SD_DAT4 XD_WP# SP10 R351 *0_4 MS_DATA3
CF_A1/XD_D4 SD_DAT6/XD_D7/MS_D3/CF_D15
SI-2 modified --Fix 24 CF_DMARQ CF_CS0# 30 SP14 XD_R/B# R348 *0_4 XD-D7
Y5 layout footprint 29 MS_CD# SP15 SD_DAT3 XD_WE# SP14 R389 *0_4 XD-RB#
R362 *6.19K/F_4 RREF MS_INS#/CF_IORD# SP8 SP16 SD_DAT2 XD_RE# SP12 R369 *0_4 XD-D0
2 28
to XTAL-5X3_2-3_8 RREF SD_DAT7/XD_D2/MS_D2/CF_IOWR#
27 SP7 SI-2 remove R673 not SP17 XD_ALE SP17 R391 *0_4 XD-ALE
(ME placement) SD_DAT0/XD_D6/MS_D0/CF_RST# SP6 SP18 XD_CE# SP18 R392 *0_4 XD-CE#
SD_DAT1/XD_D3/MS_D1/CF_IORDY 26 need -- UMA BOM remove
25 SP5 SP19 XD_CLE SD_CMD_R R372 *0_4 SD_CMD
XD_D5/MS_BS/CF_A2
13 USBP6_CR- 4 DM
13 USBP6_CR+ 5 DP AV_PLL_IN 1
C647 C918
C665 *5.6P/50V_4 XTLO

*0.1U/10V_4
*1U/10V_4 JMB 380 Note:
48 XTLO SD/MMC MS XD
2
*12MHz 10 VREG CH501H-40PT

R395 VREG_OUT +3VSUS_RTS R323 *0_6 D23
5V_IN 8 +3VSUS 1 2 MS_CD# MDID0 SD_DAT0 XD_D0 MS_D0
*270K_4 Y5 3 MDID1 SD_DAT1 XD_D1 MS_D1
A3V3_ IN C634 C593 C598 XD_CD# SD_CD# MDID2 SD_DAT2 XD_D2 MS_D2
33 1 2
1
XTLI D3V3_ IN *0.1U/10V_4 *0.1U/10V_4 *4.7U/6.3V_6 MDID3 SD_DAT3 XD_D3 MS_D3

47 XTLI
C668 *5.6P/50V_4 *0.1U/10V_4 C633 CH501H-40PT MDID4 SD_CMD XD_WE# MS_BS
BG612000717 MDID5 SD_CLK XD_CE# MS_SCLK
For 5158 C873 MDID6 SD_WP XD_WP#
D3V3_OUT 11 +3VSUS
270P/25V_4 MDID7 XD_CLE
MODE_SEL 45 *0.1U/10V_4 C612 C589 MDID8 SD_DAT4 XD_D4
MODE_SEL *4.7U/6.3V_6 RTS5158 need to remove MDID9 SD_DAT5 XD_D5
R394 C667 D23/D24/C873 MDID10 SD_DAT6 XD_D6
7 +3VSUS +3VCARD MDID11 SD_DAT7 XD_D7
C *10K/F_4 *47P/50V_4 A3V3_OUT MDID12 XD_RE# C
9 +3VCARD MDID13 XD_R/B#
For 5158 CARD_3V3_OUT MDID14 XD_ALE
6 C624 C917 CR1_LEDN SD1_LED# MS1_LED# XD_LED#
AG33 C629 C628 C618 C617 CR1_PCTLN SD1_PCTL#MS1_PCTL#XD1_PCTL#
AG_PLL 46
32 *0.1U/10V_4 CR1_CD0 SD1_CD# XD_CV#
R667 *100K/F_4 5158_RST# 44 DGND2 *1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 CR1_CD1 MS1_CD# XD_CD#
+3VSUS RST# DGND1 12
C925
If SD_DAT1 connect to *RTS5158
SP4 , MOD_SEL need to *1U/10V_4
let it to N.C
PAD8 PAD9 PAD10 PAD11
*H-S315D110P2
H31
*H-S315D110P2 H2
H32
+3VCARD +3VCARD MDC_SPRING MDC_SPRING MDC_SPRINGMDC_SPRING
5 IN1 CARD READER SI-2 for 台端Conn
1
CN42
*H-O173X118D173X118N
H13
XD,MMC/SD,MS/MSP XD-RB# 1 37
1
C905 XD-RE# xD-R/B GND
2 xD-RE GND 38
XD-CE# 3 41
1
xD-CE GND PAD7
*H-S315D110P2
*270P/25V_4 XD-CLE 4 42
xD-CLE GND
*H-C256D157P2
H3
XD-ALE 5 1
+3VCARD +3VCARD +3VCARD XD_WE xD-ALE
6 40
1
xD-WE NC
*H-S315D110P2
H22
*H-C244D181P2
H23
*H-C217D157P2
H6
*H-C217D157P2
H9
*H-C217D157P2
H8
XD-WP# 7 39
1
CN36 XD-D0 xD-WP NC *MDC_SPRING
8 xD-D0
XD-RB# 1 37 XD-D1 9 36 SD_CD#
1
R678 XD-RE# XD-R/B GND SD_DAT2 xD-D1 SD-CD SD_WP
2 XD-RE GND 38 10 SD-DAT2 SD-WP 35
XD-CE# 3 40 SD_DAT3 11 34 XD_CD#
B *10K/F_4 XD-CLE XD-CE GND SD_CMD SD-DAT3 xD-CD PAD4 B
4 XD-CLE GND 42 12 SD-CMD xD-VCC 33 Del PAD1
XD-ALE 5 43 13 32 XD-D7 1 for TP
XD_WE XD-ALE GND GND xD-D7 XD-D6
6 XD-WE 14 MS-VCC xD-D6 31 on PV
*H-C315D118P2
*H-S315D110P2
H7
*H-C315D118P2
H25
*H-C256D217P2
H18
*H-C256D217P2
H17
XD-WP# 7 39 SD_CD# SD_CLK_MS_CLK 15 30 XD-D5
XD-WP SD-C/D SD_CD# 26 MS-SDLK xD-D5
H12
XD-D0 8 36 SD_CD# MS_DATA3 16 29 SD_DAT1 MDC_SPRING
XD-D1 XD-DATA0 SD-CD-SW SD_WP MS_CD# MS-DATA3 SD-DAT1 XD-D4
9 41 17 28
1
SD_DAT2 XD-DATA1 SD-W/P SD_WP MS_DATA2_XD_D2 MS-INS xD-D4 XD-D3 PAD5 PAD2
Del R625 10 SD-DATA2 SD-WP-SW 35 18 MS-DATA2 xD-D3 27
for TP SD_DAT3 11 34 XD_CD# MS_DATA0_SD_DAT0 19 26 MS_DATA2_XD_D2 1 1
SD_CMD SD-DAT3 XD-CD MS_DATA1 MS-DATA0 xD-D2 MS_DATA0_SD_DAT0
on PV 12 SD-CMD XD-VCC 33 20 MS-DATA1 SD-DAT0 25
13 32 XD-D7 MS_BS 21 24 SD_CLK_MS_CLK
GND XD-DATA7 XD-D6 MS-BS SD-CLK MDC_SPRING *MDC_SPRING
14 MS-VCC XD-DATA6 31 22 GND SD-VCC 23 K/B SCREW HOLE VGA Hole
SD_CLK_MS_CLK 15 30 XD-D5
MS-SDLK XD-DATA5 PAD6 PAD3
*H-C315d118p2
H1
MS_DATA3 16 29 SD_DAT1
MS-DATA3 SD-DATA1
*H-S315D110P2
H5
*H-S315D110P2
H11
*H-C217D181P2
H4
*H-C217D181P2
H10
MS_CD# 17 28 XD-D4 *TAI TWUM 5IN1 CARD READER SOCKET 1 1
26 MS_CD# MS-INS XD-DATA4
MS_DATA2_XD_D2 18 27 XD-D3
1
MS_DATA0_SD_DAT0 MS-DATA2 XD-DATA3 MS_DATA2_XD_D2
19 26
1
MS_DATA1 MS-DATA0 XD-DATA2 MS_DATA0_SD_DAT0 R611 0_4 MS_DATA0_SD_DAT0 *MDC_SPRING *MDC_SPRING
20 MS-DATA1 SD-DATA0 25 26 MDIO00
MS_BS 21 24 SD_CLK_MS_CLK R623 0_4 XD-D0
MS-BS SD-CLK
22 GND SD-VCC 23 26 MDIO01
R608 0_4 SD_DAT1 for MDC cable
+3VCARD R610 0_4 MS_DATA1 routing
R622 0_4 XD-D1
5IN1 CARD READER SOCKET R612 0_4 MS_DATA2_XD_D2
26 MDIO02
R620 0_4 SD_DAT2
C872 R607 R614 0_4 MS_DATA3 Mini Card Hole
26 MDIO03
2.2U/6.3V_6 150K/F_4
Q25
R619 0_4 SD_DAT3 SI-2 for CN37
+3V +3VCARD
*H-C256D217P2
H26
*H-C256D217P2
H27
R606 0_4 XD-D3
*AO3409
H20
*H-C256D217P2
H14
*H-C236D87P2
H28
*H-C236D87P2
H29
*H-C236D87P2
H30
R618 0_4 SD_CMD
26 MDIO04
*H-C256D217P2
R609 0_4 MS_BS
1
CLOSE CONN 1 3 R627 0_4 XD_WE
1
+5V R617 47/F_4 SD_CLK_MS_CLK
A 26 MDIO05 A
R634 47/F_4 XD-CE#
R593 0_4 SD_WP
26 MDIO06
2
R591 0_4 XD-WP#

+3VCARD XD_PWON R387 *10K/F_4 R633 0_4 XD-CLE
26 MC_PWR_CTRL_0# 26 MDIO07
R605 0_4 XD-D4
+3VCARD 26 MDIO08
R603 0_4 XD-D5
PROJECT : QT8
26 MDIO09
R602 0_4 XD-D6
26 MDIO10 PAD12
C887 C894 C874 R332 0_8 R601 0_4 XD-D7
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
RESERVED for JMicron -- after
26
26
MDIO11
MDIO12
R679
R635
0_4
0_4
XD-RE#
XD-RB#
1 Quanta Computer Inc.
26 MDIO13
programming can out-put +3.3V R628 0_4 XD-ALE
26 MDIO14
MDC_SPRING Size Document Number Rev
throught MC_PWR_CTRL_0# signal SI-2 modified - for Custom 1A
RTS5158 & CR SOCKET &HOLE
Jmicron updae NB5/RD5
8 7 6 5 4 3 2 1
5 4 3 2 1
+3V
C615
C609
0.1U/10V_4
0.1U/10V_4
TPBIAS0
R586
56.2/F_4
R585
56.2/F_4
C862 0.33U/16V_4
26
C636 0.1U/10V_4 TPB0N
*WCM-2012-900T(400mA)
D TPB0P D
C657 10U/6.3V_8 TPA0N 4 3
5
6
7
8
TPA0N TPA0P 1 2
5
6
7
8
+1.8V TPA0P L87 TPA0P 4
+1.8V_CARD 4
*BLM18PG181SN1D(180,1.5A)_6 TPBIAS0 TPA0N 3
L53 3
MDIO08 25 L88 TPB0P 2
C578 10U/6.3V_8 TPB0P 2
MDIO09 25 1 2
+3V TPB0N TPB0N
1
MDIO10 25 4 3 1 1
C610 0.1U/10V_4 12K %1 MDIO11 25
:CS31202FB15 MDIO12 25 1394_CONN
C613 0.1U/10V_4 R361 *WCM-2012-900T(400mA)
or 12K/F_4 CN34
C580 1000P/50V_4 CS31202FB07
C635 0.1U/10V_4 R580 56.2/F_4 R583 4.99K/F_4
R582 56.2/F_4
C579 0.1U/10V_4 C863
36
35
34
33
32
31
30
29
28
27
26
25
U16 220P/50V_4
TPBIAS_1
TPA1P
TPB1P
TAV33
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
TREXT
TPA1N
TPB1N
C C
R359 10K/F_4 D3E :
+1.8V_CARD 37 24 mode 1 : when card device insert can wake up card reader chip
DV18 TCPS
mode 2 : need to use pin16 to wake up card reader device
38 TXIN MDIO13 23 MDIO13 25
39 TXOUT MDIO14 22 MDIO14 25
R364 +3V
25 MDIO07 40 MDIO7 CR_LEDN 21 CARD_LED# 25,29
D3E _WAKEN pin :out put low 1ms can wake up
1M/F_4 25 MDIO06 41 20 +3V system when system into D3E mode 2
MDIO6 DV33
Y6 25 MDIO05 42 MDIO5 DV33 19
25 MDIO04 43
JMB380 18 +1.8V_CARD R324 R313 RB501V-40 D39 SI-2 modified - for
MDIO4 DV18 4.7K_4 4.7K_4 2 1 D3E GPIO# 12 Jmicron updae
+3V 44 DV33 CR1_PCTLN 17 MC_PWR_CTRL_0# 25
24.576MHZ
C641 C642 25 MDIO03 45 16 SD_CD# 25 D3E_SCI# 13
22P/50V_4 MDIO3 CR1_CD0N
27P/50V_4
25 MDIO02 46 MDIO2 CR1_CD1N 15 MS_CD# 25
3
Q69 R795 2.2K_4 +3VS5
25 MDIO01 47 14 T113 2N7002E-G
MDIO1 NC
B 25 MDIO00 48 MDIO0 D3E_WAKEN 13 D3E_WAKEUP 2 Q69 for power B
leakage
APCLKN
APREXT
APCLKP
D3E _WAKEN pin :out put Hi into D3E mode

APGND
49
APVDD
APRXN
XRSTN
APRXP concern
APTXN
APTXP
XTEST
APV18
EPAD
out put low normal mode
1
1
10
11
12
+3VCARD
R301
MDIO06 R594 10K/F_4

12 CARD_PLTRST#
MDIO13 R318 10K/F_4

8.2K/F_4
+3V
+1.8V_CARD
+1.8V_CARD
2 CLK_PCIE_CARD#
MDIO07 R342 10K/F_4
2 CLK_PCIE_CARD
A MDIO12 R360 2 1 200K/F_4 A

9 PCIE_TXP5
9 PCIE_TXN5
C583 0.1U/10V_4 PCIE_RXN5_C
PROJECT : QT8
9 PCIE_RXN5
C582 0.1U/10V_4 PCIE_RXP5_C
9 PCIE_RXP5
MDIO14 R630 1 200K/F_4
2

B 1A
JMB380 Controller/1394
NB5/RD5
5 4 3 2 1
A B C D E
+4.75VAVDD +5V +5V

SI-2 Modified -- change
footrint QFN48-7X7-5-49P-1H
for datasheet update
SI-2 Modified
EAPD#--DEFAULT is Hi
+4.75VAVDD
C626
10U/6.3V_8
1
C645
L56
0.1U/10V_4
2
*0_8
C644
1U/10V_4
5
2
U15
Vout
BYP
GND
Vin
EN
1
3
C587
0.1U/10V_4
C586
0.047U/25V_4
1
C581
L55
1U/10V_4
0_8
2
C646
0.1U/10V_4
C584
27
10U/6.3V_8
37 SPDIF EAPD# 28
TPS793475
DIGITAL_CLK 30 C608
+3V +3V_DVDD C946 AGND AGND AGND 1U/10V_4 R325 0_4 MAINON 20,35,39,42,43,44
C947 22P/50V_4
L54 0_8 *.1U/10V_4 C625 C643
1 2 10U/6.3V_8 0.1U/10V_4 C924 100U/6.3V_3528 AGND AGND
EARPO_R EARP_R
+
R78 C923 100U/6.3V_3528
C590 C604 C588 Del R672 22_6 EARPO_L EARP_L TO Headphone jack
+
AGND BIT_CLK_AUDIO ACZ_SDIN0_ADC
direct
1U/10V_4 0.1U/10V_4 10U/6.3V_8 on PV AGND Change C923, 924
footprint
C596 C595
49
48
47
46
45
44
43
42
41
40
39
38
37
U17 +4.75VAVDD *27P/50V_4 *27P/50V_4
+3V_DVDD AGND
GPIO 7 / SPDIF OUT1

EAPD
SPDIF0
EAPD
GPIO 6
GPIO 5
DMIC_CLK
AVSS2**
PORTA_R
NC
PORTA_L
AVDD2**
NC
SI-2 for EMI C602 0.01U/16V_4
R385 FOR EMI
C961 *22P/50V_4
1 2
TO Internal Speakers
1 DVDD_CORE PORT-D_R 36 HP-R 28
5.11K/F_4
30 DIGITAL_D1 R787 0_6
C597 0.1U/10V_4
2 VOL_UP/DMIC_0 PORT-D_L 35 HP-L 28 Audio JACK: Normal Open
+3V_DVDD R306 0_6 3 DVDD_IO SENSE_B / NC 34 SENSE_B R384 39.2K/F_4 SB_E#
SA_A# -->EXT HP
T221 DIGITAL_D2 4 VOL_DN/DMIC_1 CAP2 33 C663 1U/10V_4 AGND C664 1U/10V_4 AGND SA_B# -->EXT MIC
3 ACZ_SDOUT_AUDIO 5 SDO MONO_OUT 32
SB_E#-->DOCK MIC
BIT_CLK_AUDIO 6 31 MIC1-VREFO-E
13 BIT_CLK_AUDIO BITCLK VREFOUT-E / GPIO 4
IDT_GPIO3# Del R686,
Change to SHORT-1A for EMI on PV
7 DVSS GPIO 3 30 IDT_GPIO3# 28
13 ACZ_SDIN0 R305 22_4 ACZ_SDIN0_ADC 8
92HD71B7 29 MIC1-VREFO-C
R356, R349
direct on PV R788 *0_6
SDI_CODEC VREFOUT-C
9 28 MIC1-VREFO-B R789 *0_6
DVDD_CORE VREFOUT-B
13 ACZ_SYNC_AUDIO ACZ_SYNC_AUDIO 10 27 VREF_FLT R368 *0_6

SYNC VREFFILT
ACZ_RST#_AUDIO 11 26 CDC_AVSS R331 *0_6
13 ACZ_RST#_AUDIO RESET# AVSS1
R309 47K_4 C594 12 25 +4.75VAVDD C662 C620 C639 C931 R353 *0_6
13,28 ACZ_SPKR PCBEEP AVDD1 10U/6.3V_8 1U/10V_4 1U/10V_4 1U/10V_4
PORTC_R
PORTE_R
PORTB_R
PORTF_R
SENSE_A
PORTC_L
PORTE_L
PORTB_L
PORTF_L
C661 R674 *0_6

0.1U/10V_4 0.1U/10V_4
+3V_DVDD
NC
NC
NC
R314 C600 AGND AGND AGND

AGND AGND AGND AGND
13
14
15
16
17
18
19
20
21
22
23
24
10K/F_4 0.01U/16V_4
+4.75VAVDD
1 C601 C585 MIC1-VREFO-B R363 4.7K_4 1
0.1U/10V_4 10U/6.3V_8
recommand use X7R /10V R357 4.7K_4
R328 AGND SHIELD
MIC1_R1 C640 2.2U/6.3V_6 EXT_MIC_R
AGND SHIELD
TO EXTERNAL MIC
AGND 5.11K/F_4 MIC1_L1 C630 2.2U/6.3V_6 EXT_MIC_L
AGND SHIELD
JACK_SEN# R330 39.2K/F_4 SENSE_A R687 4.7K_4 R344 1.21K/F_4 AGND
AGND SHIELD
SA_B# R329 20K/F_4 DOCK_MIC_R1 C616 2.2U/6.3V_6 R343 10K/F_4
DOCK_MIC_R 37
AGND SHIELD
DOCK_MIC_L1 C611 2.2U/6.3V_6 R336 10K/F_4
C599 DOCK_MIC_L 37 AGND SHIELD TO DOCK MIC
1000P/50V_4 MIC1-VREFO-E R688 4.7K_4 R337 1.21K/F_4 AGND
AGND
SB_E# R807 change to 330K +12VALW EARPO_R
3
CN19 for HP on PV Q73
C614 0.1U/10V_4 AUDIO CONN +5V 2N7002E
13 37 JACK_SEN# Change C962, 963
+5VPCU 2 R811 footprint
1 R807
35,37 CIR_IN 2 330K/F_4 *0_4
EARP_L 3
EARP_R 4 R371 R367 +3V
1
5
3
3
SA_A# 47K_4 47K_4
6 Q29
7
3
SA_B# 2N7002E Q72 R668 47/F_6 C962 100U/6.3V_3528
+
8
2
Q28 2 R812 2 2N7002E RSPK_DK 37
EXT_MIC_L 9 R808
10
3
C922 MMBT3904 2
*180P/50V_4 C921 EXT_MIC_R 11 *0_4 100K/F_4 EARPO_L
12 DOCK MIC DETECT 2
3
Q74
1
1
*180P/50V_4 14 R366 2N7002E Del R814, R815 on PV
1
3
10K/F_4
1
C920 DOCK_MIC_L DKMIC_SEN 2 Q27 AGND AGND 2 R813 TO DOCK Headphone
C919 AGND
*180P/50V_4 *180P/50V_4 TO AUDIO/B CON. MMBT3904
3
C660 R396 Q75 *0_4
1
AGND SI-2 modified 1U/10V_4 47K_4 2N7002E

for EMI AGND -- Change AGND
1
AGND AGND SA_A# Q76 C141 R669 C963 100U/6.3V_3528
+
2
footprint for 2N7002E .01U/25V_4 LSPK_DK 37
ME request , R816 100K/F_4 Add C141 47/F_6
TO Headphone jack pin 13,14 are +3V 2 1 for
固定pin 1 soft-star AGND
on PV
AGND
PROJECT : QT8
Custom 1A
Azalia AD1883
NB5/RD5
A B C D E
1 2 3 4 5 6 7 8
AUDIO AMPLIFIER
LIN-,RIN- and LIN+,RIN+ swap for BOBO noise on PV
SI-2 Modified -- remove C621/C623
+5VAMP
6
15
PVDD1
U18
ROUT+ 18
14
R_SPK+4
R_SPK-3
L6
L7
BK1608HM241
BK1608HM241
C34
R_SPK+
R_SPK- CN5
4
28
PVDD2 ROUT- C37 3
16 VDD 470P/50V_4 2
4 470P/50V_4
LOUT+ 1
27 HP-L
R383 20K/F_4 HP_L_C C659 1 2 0.047U/16V_6 C_SPKR_L 5 LIN- LOUT- 8 DC impedance 0.35ohm
R373 20K/F_4 HP_R_C 1 2 0.047U/16V_6 C_SPKR_R 17 INT SPEAKER CONN
27 HP-R RIN-
C656 19
A
PC_BEEP SHUTDOWN AGND A
9 LIN+
INT. SPEAKER
C619
C651
C622
C637
7 12 L_SPK+2 L11 BK1608HM241 L_SPK+
RIN+ NC
EPAD 21
2
AGND C650 2 1 0.47U/10V_6 AMP_BYPASS 10 1 L_SPK-1 L10 BK1608HM241 L_SPK-
BYPASS GND1
PV-1 Modified --R383 , R373 GND2 11 Vrms = Vpp / 2 √2
100P/50V_4
100P/50V_4
100P/50V_4
100P/50V_4
change from 20Kohm to 0 ohm AUDIO_G0 2 13
1
AUDIO_G1 GAIN0 GND3
for Volume too low issue 3 GAIN1 GND4 20
+5VAMP SI-2 modified -- Power = (Vrms) 2/ R
TPA6017A2/FAN7031/LM4874 C53 C52
for EMI 470P/50V_4
suggestion
470P/50V_4 QT8 speaker -- 3.2ohm / 2W
AGND AGND AGND AGND AGND
6017A2 Gain Table R346 R340

AGND
+3V
GAIN0 GAIN1 AV RIN 100K/F_4 100K/F_4
+5VAMP
AUDIO_G0 SI-2 modified -- +5V
0 0 6dB 90K
2
remove D22 , add
0 1 10dB 70K AUDIO_G1 R322
D40 R376 0_6 R386 *0_6
2
1 0 15.6dB 45K 2 100K/F_4
35 VOLMUTE#
R347 R341 R310 *0_6
1
1 1 21.6dB 25K 3 C649 C638 C632 C631
1K_4 *1K/F_4 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.047U/25V_4
1 AGND
1 27 EAPD#
2
D40 R386, R310 change
BAT54A to SHORT-1A on PV
B AGND B
AGND
PC-BEEP MUTE_LED SI-2 Modified

+5VPCU
Low -->un-MUTE
+5VAMP SI-2 modified -- remove
2
High-->Mute R307,Q24 , add SI-2 Modified --
C942 *.1U/16V/04 R311 R311 change from
R781,D41,Q70
AGND SI-2 modified - from Hp suggestion 10k to 100k
100K/F_4
1
35,37 MUTE_LED
5
1 C943 *0.1UF/06 TO AMP +3V R781 10K/F_4

35 KEY_BEEP
3
4 R771 *1K/04 PC_BEEP
13,27 ACZ_SPKR 2 2 Q70
35 VOLMUTE#
ME2N7002E
U38 R772
TO CODE 3 2
3
2
*NC7SZ86 *1K/04
C944 C945 1
27 IDT_GPIO3#
*.47U/10V_6 *.47U/10V_6
1
D41
1
AGND BAT54A
AGND
R773 *0_4
AMP_GND
C C
Acceleration sensor
+3V +3V
U6
1 Vdd_IO reserved second source
6 VDD
C449 C448 C450 3 C443 C442
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 Reserved *0.1U/10V_4 *0.22U/6.3V_4 U7
11 Reserved
2 VDD Reserved 1
9 VDD_IO Reserved 10
Del R768
Del R767 12 INTH# 8 INT1
9 INT2 12 INTH# 4 INT
12 2 PDAT_SMB 8
SDO GND 2,6,7,13,36 PDAT_SMB SDI
PDAT_SMB 13 4 PCLK_SMB 6 7
2,6,7,13,36 PDAT_SMB SDA/SDI/SDO GND 2,6,7,13,36 PCLK_SMB SCK SDO
PCLK_SMB 14 5 5 3
2,6,7,13,36 PCLK_SMB SCL/SPC GND CSB GND
R169 10K/F_4 7 10
+3V CS GND
D *BOSCH BMA150 D
SGT-LIS302DLTR
SGT-LIS302DLTR interrupt pin default

is low / active Hi , BIOS need to
programming 22h to change status
from active Hi to low PROJECT : QT8
Custom 1A
AMP_TPA6017/INT SPK
NB5/RD5
1 2 3 4 5 6 7 8
A B C D E
Modem CONN
29
FBSA1017
H21
FBSA1017
H19
1
1
+3V
MDC
CN18
4 4
1 2 C653 C654 C658
ACZ_SDOUT_AUDIO_MDC GND REV 0.1U/10V_4 2.2U/6.3V_6 1000P/50V_4
13 ACZ_SDOUT_AUDIO_MDC 3 A_SDO REV 4
5 GND VCC 6
ACZ_SYNC_AUDIO_MDC 7 8
13 ACZ_SYNC_AUDIO_MDC AC_SDIN1_MDC A_SYNC GND
13 ACZ_SDIN1 9 A_SDI GND 10
R326 33_4 11 12 R377 0_4
A_RST# A_BCLK BIT_CLK_AUDIO_MDC 13
C603 *10P/50V_4 MDC CONN
13 ACZ_RST#_AUDIO_MDC For EMI
C652
*10P/50V_4
+3V
SI-2 modified -- LED4
change footprint
R750
*10K/F_4
(White)
2
LED
SATA_R_LED1 R381 100F_6 3
3 +3V
3
LED4
1 LED 3P WHITE/AMBER + 1 2 -
2 Q26 (Amber)
3
R766
Q65 Q64 0_6 SI-1 modified -- Single Color ,Right angle
LTW-110TLA
3
35 LEDVCC_EN# 2 14 ACCLED_EN 2 for fix SATA LED 3
1
*PDTC144EU *PDTC144EU
no support LED
light control
1
1
PDTC144EU
14 SATA_LED#
SI-1 modified --
change LED part
number
Del R380
LED PWR CONTROL R817 0_8
Change R381 to 100
Add R766, R817, R818,
Q18 R819
+12VALW *2N7002E 20~40mils LED PWR control no-stuff
on PV LED6 2P WHITE LED
+3V 3 1 +3V_LED +3V_LED 1 2 PWR_R_LED1 R378 20_6
34,35 PWR_LED# +3VPCU_LED
SI-2 change R180
from 100k to
R180
1Mohm for current
2
*1M_4
limit C457 C460 LED5 2P WHITE LED
10U/6.3V_8 0.1U/10V_4 1 2 MBAT_R_LED1 R379 20_6
35 MBATLED0# +3VPCU_LED
R178 *1M/F_4 LED_CTL
3 White
3
2P WHITE LED
C451 C932 C933 LED7 Anode 2 1 Amber
1 2 CARD_LED1 R584 20_6
2 *2N7002E 25,26 CARD_LED# +3V 2
LEDVCC_EN# 2 *1U/25V_8 *.22U/25V_6 *.22U/25V_6
35 LEDVCC_EN# Q17 Dual Color ,Right angle
LTW-326DSKF-5A
LED1 2P WHITE
1
35 CAPSLED# 1 2 CAP_LED R185 20_6

+3V_LED
add LED auto dim
function
R818 0_8
Q23
*2N7002E
20~40mils
+3VPCU 3 1 +3VPCU_LED +3VPCU_LED
I = Vcc -Vf / R
LED Vf
2
LED_CTL (Amber) R Amber
C566
10U/6.3V_8
C568
0.1U/10V_4
35 TP_LED1#
TP_LED1#
4 2
TPLD3 R183 200/F_6
+3V_LED Vcc 4 2 +
Anode
TP_LED2# TPLD4 R182 20_6 3 1 +
35 TP_LED2# 3 1 +3V_LED
(White) White
LED3 LED 4P WHITE/AMBER
For PA
R819 0_8
1 1
Q12
*AO3404
20~40mils
+5V 3 1 +5V_LED
PROJECT : QT8
2
C410 C556
0.1U/10V_4 *10U/6.3V_8
LED_CTL Size Document Number Rev
Custom 1A
MDC1.5 Con Accelerometer/lLED
NB5/RD5
A B C D E
5 4 3 2 1
BLUETOOTH +3VPCU +3VSUS

LEFT SIDE USBX1 and E-SATA/USB COMBO
R181
4.7K_4
+5VSUS
U33 80 mils (Iout=2A) 30
1
2 8 USB0PWR
VIN1 OUT3
3 VIN2 OUT2 7
1
Q19 4 6 C850
ME2303T1 EN OUT1 C853 C852 +
Del R179 on PV 2 1 GND OC 5
100UF_16V
*470P/50V_4 0.1U/10V_4
C819 G545B2PU8
2
1U/10V_4 (TPS2061D)
3
3
D D
C459 AL000545017
2 Q20 0.1U/10V_4
14 BT_OFF#
PDTC144EU 24mil IC(8P)G545B2P8U(MSOP-8) - 1.5A
BTV AL000545000 USB 0
IC OTHER(8P) G545A2P8U(MSOP-8) - 2A
1
CN33
C454 C447 C452
CN15 10U/6.3V_8 0.1U/10V_4 *WCM-2012-900T(400mA) USB0PWR 1 8
BLUE TOOTH CONN *100U/6.3V_3528 USBP0- 1 GND
13 USBP0- 4 3 2 7
2
87213-0600-6P-L USBP0+ 2 GND
13 USBP0+ 1 2 3 3 GND 6
4 4 GND 5
BTCON_P1 L37 C415 C419
6 T258
BLUELED *47P/50V_4 *47P/50V_4
5 BLUELED 35,36
SI-2 Modified footprint -- 4
USBP5-
USBP5- 13
USBP1+ USB CONN
for ME change pitch for USBP5+ USBP1-
3 USBP5+ 13
1.25mm to 1.0mm
1
2 BTV
1
2
C414
*Clamp-Diode_6
*Clamp-Diode_6 C420
1
*Clamp-Diode_6
2
SI-2 modified -- Change
C334
C319 Connector layout type
*Clamp-Diode_6
from SMD PAD to Dip as
For Discrete Touch-Screen SMT request
1
C812
C + C808 C807 C
*100UF_16V
0.1U/10V_4 *470P/50V_4
2
USB & ESATA
CN32
SI-2 Modified -- remove touch-screen function
*WCM-2012-900T(400mA) USB0PWR 1
USBP1- USB Vcc
13 USBP1- 4 3 2 D-
1 2 USBP1+ 3
13 USBP1+ D+
4 GND
L29
*47P/50V_4
*47P/50V_4
C320
C332
5 GND Shield 14
C352 0.01U/16V_4 6
14 SATA_TXP2 A+
1. ESD GND C353 0.01U/16V_4 7 15
USB CAMERA CONNECT USB Fingerprint CON 14
14
SATA_TXN2
SATA_RXN2
C310
C299
0.01U/16V_4
0.01U/16V_4
8
9
A-
GND
B-
Shield
Shield 12
2. SYSTEM GND 14 SATA_RXP2 10 B+
11 GND Shield 13
CN10
CAMERA-BOARD 3. USB-
6
Close to ESATA USB_ESATA_COMBO
27 DIGITAL_D1 DIGITAL_D1 4. USB+ CON from AMD
DIGITAL_CLK 5
27 DIGITAL_CLK
+3.9V-CAMARA 4 recommend
L26 4 USBP2- 3
13 USBP2- 3
USBP2+ 2 5. USB PWR(+3V)
13 USBP2+ 1 2 1
B +3V B
*WCM-2012-900T(400mA)
C92
0.1U/10V_4 SI-2 Modified RIGHT SIDE USBX2
Del R154 on PV
SI-2
+5VSUS
Add for EMI solution C412 0.1U/10V_4
DIGITAL_CLK +5VSUS
CN13 1
2
L40 3
USBP6+ 5 4
13 USBP6+ 1 2 4 13 USBP8+ 5
C951 4 3 USBP6- C56
+3V 13 USBP6- 3 13 USBP8- 6
*27P/50V_4 0.1U/10V_4
+3.9V-CAMARA 2 7
1 13 USBP9+ 8
*WCM-2012-900T(400mA)
13 USBP9- 9
R86 10
+5V *0_6 CN7
FINGER PRINTER CONN DUAL USB CONN
U3 PCB footprint
3 VIN VOUT 4 PCB footprint BL123-10R-10P-L-QT6
BL123-05R-5P-L-QT6
C221
C166 1 SHDN R1 R73 4.7U/6.3V_6
1U/10V_4 *215K/F_4
A A
2 GND SET 5
IC(5P) G913C (SOT23-5)EP R73 and R72

no-stuff for
R2 R72
*100K/F_4
fix Vout on PV
PROJECT : QT8
Vout=1.25(1+R1/R2) NB5/RD5
Custom
BT/WEBCAM/FT/USBX4/ESATA 1A

5 4 3 2 1
5 4 3 2 1
32 +FB12 R41 0_6 +LAN_A1.8_FB12

+3VLANVCC R425 0_6
C713
0.1U/10V_4
+CTRL15_E
C700
10U/6.3V_8
C703
10U/6.3V_8
31
Stuffed for 8101E/8102E/RTL8111C
+3VLANVCC R426 0_6 +3V_GVDD
D Del R50 on PV LAN_TX# D
+LAN_D1.5 R38 0_6 +LAN_D1.5_RVD Stuffed for RTL8111C(10/100/1000)

+3V_A_LAN +3V_A_LAN LAN_LED_100# R30 0_4 LAN_GLINK100#
XTAL1 LAN_GLINK10#
R418 *0_6 +CTRL15_E
Y1 32 +CTRL15
LAN_GLINK1000#
1 2 XTAL2 Stuffed for 8102E/RTL8101E
+3V_LAN +3V_LAN
+3V_GVDD
25MHZ
LAN CABLE DETECT 35
+CTRL15_E
Del R36, C712, +LAN_D1.5
C45 C44 C710 on PV R37 2.49K/F_4 LANRSET +LAN_D1.5
30P/50V_4 30P/50V_4 Del R766 for TP on PV use BIOS to programming
+LAN_D1.5 EEPROM , EEDI should be
+3V_LAN
pull Hi
U2
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
2
R427 R46
EPAD
GVDD
CKTAL2
CKTAL1
NC
NC
VCTRL15
AVDD33
VDD15
LED_TX#
LED_100#
LED_10#
LED_1000#
VDD33
VDD15
VDD15
RSET
3.6K_6 Del U1, R46 on PV
only for 8111B,
32 +CTRL18 1 48 8101E&8102E&8111C can
1
+3V_A_LAN VCTRL18 EESK EEDI
2 AVDD33 EEDI 47 remove
+3V_A_LAN MDI0+ 3 46 +3V
MDIP0 VDD33 +3V_LAN
MDI0- 4 45
+LAN_A1.8_FB12 MDIN0 EEDO
5 44 Remove R456 and Add D42 on PV if ISOLATEB pin
MDI1+ AVDD18 EECS +LAN_D1.5 LAN_YLED
6 MDIP1 VDD15 43 pull-low,the LAN
MDI1- 7 42 chip will not drive
+LAN_A1.8 MDIN1 NC LAN_GLED
+LAN_A1.8 8 AVDD18 VDD15 41 it's PCI-E outputs
C MDI2+ C
MDI2-
9 MDIP2 RTL8111C-VB-GR NC 40 R456
( excluding EMI
10 MDIN2 NC 39 *1K/F_4
+LAN_A1.8 11 38 +LAN_D1.5 PCIE_WAKE# pin ) C88 C40
MDI3+ AVDD18 VDD15 +3V_LAN +3V_LAN
12 MDIP3 VDD33 37 *0.1U/50V_6 *0.1U/50V_6
MDI3- 13 36 ISOLATEB R457 100_4
MDIN3 ISOLATEB# LAN_DISABLE# 13,35
+LAN_A1.8 14 35
AVDD18 NC
LANWAKEB#
+LAN_D1.5 +LAN_D1.5 R778 *0_4 15 34 2 1
PDAT_SMB
PCLK_SMB
VDD15 NC
REFCLK_N
2
REFCLK_P
+3V_LAN 16 33
PERSTB#
+3V_LAN VDD33 VDD15
EVDD18
EVDD18
R441
VDD15
VDD15
*RB501V-40
HSON
AGND
AGND
HSOP
RJ45
HSIN
HSIP
R778 15K/F_4 D42
SI-2 modified --
1
CN27
RTL8111C remove ,
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
R58 330_4 LAN_GLED 12
RTL8111B,8101E,8102E +3V_LAN
LAN_GLED# 10 LED_GRE_P
need to stuff T5 +LAN_D1.5 LED_GRE_N
T6
LAN_MX3- 8
PCIE_WAKE# PCIE_RXN6_LAN_L C82 0.1U/10V_4 LAN_MX3+ RX1-
13,33,36 PCIE_WAKE# PCIE_RXN6_LAN 9 7 RX1+
PCIE_RXP6_LAN_L C81 0.1U/10V_4 LAN_MX1- 6
PCIE_RXP6_LAN 9 RX0-
+LAN_D1.5 +LAN_D1.5 +LAN_E1.8 LAN_MX2- 5
+LAN_E1.8 TX1-
+LAN_E1.8 +LAN_E1.8 PCIE_LAN_CLKN PCIE_LAN_CLKN 2 LAN_MX2+ 4
PCIE_LAN_CLKP LAN_MX1+ TX1+
PCIE_LAN_CLKP 2 3 RX0+
Del R429, R431, R433, R435, PCIE_TXP6_LAN LAN_MX0- 2 14
9 PCIE_TXP6_LAN TX0- GND1
C718, C726 for 8111B on PV PCIE_TXN6_LAN LAN_MX0+ 1
9 PCIE_TXN6_LAN TX0+
GND 13
R460 *0_4 LAN_REST_R# R34 330_4 LAN_YLED 9

35 LAN_REST# +3V_LAN LED_YEL_P
LAN_YLED# 11 LED_YEL_N
B AL08111C001 IC CTRL(64P) RTL8111C-VB-GR(QFN)

Del R428 on PV RJ45_CONN B
AL08101E005 IC(64P)RTL8101E-GR(QFN) U26

C709 0.01U/16V_4 V_DAC 1 24 LAN_MCT0 C927 0.01U/100V_6 R39 75/F_4
TCT1 MCT1
MDI0+ 2 23 LAN_MX0+
TD1+ MX1+ LAN_MX0+ 37
MDI0- 3 22 LAN_MX0-
TD1- MX1- LAN_MX0- 37
C68 0.01U/16V_4 V_DAC 4 21 LAN_MCT1 C928 0.01U/100V_6 R44 75/F_4
+3V_LAN TCT2 MCT2
MDI1+ 5 20 LAN_MX1+
C733 0.1U/10V_4
MDI1- 6 19 LAN_MX1-
LAN_GLINK10# 2 U28 C62 0.01U/16V_4 V_DAC 7 18 LAN_MCT2 C929 0.01U/100V_6 R47 75/F_4
TCT3 MCT3
5
3 LAN_PLTRST# 2 MDI2+ 8 17 LAN_MX2+

12 LAN_PLTRST# TD3+ MX3+ LAN_MX2+ 37
4 LAN_REST_R#
LAN_GLINK100# 1 1 MDI2- 9 16 LAN_MX2-
D37 BAT54A TC7SH08FU C65 0.01U/16V_4 V_DAC 10 15 LAN_MCT3 C930 0.01U/100V_6 R51 75/F_4
3
TCT4 MCT4
LAN_GLINK1000# D38 1 2 RB501V-40 LAN_GLED# MDI3+ 11 14 LAN_MX3+
LAN_TX# R55 0_4 LAN_YLED# MDI3- 12 13 LAN_MX3-
R785 *0_4 C708
Link NS892402
C39 C85 1000P/3KV_1808
SI-2 modified --
A
*0.01U/16V_4 *0.01U/16V_4 LAN_PLTRST# is 3VS5 power NS892402:GIGABIT DB0AT9LAN05 A
rail , Maybe can remove
NAND GATE NS892405:10/100 DB0ZB1LAN04
PROJECT : QT8
Custom 1A
RTL8111C/8101E/RJ11-RJ45 CN
NB5/RD5
5 4 3 2 1
5 4 3 2 1
LANVCC
1.2W
+3V_LAN
Power trace Layout 寬度> 30mil
32
364mA
>30mil
+3VLANVCC
C719 C722 C716 C729 these CAP are for LAN CHIP LANVCC
D D
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
Del L68, L69 direct C720 pins--16, 37, 46 and 53.placement close lan
on PV C723 chip
10U/6.3V_8 0.1U/10V_4
+3V_A_LAN
placement close to lan chipset
>30mil
C715 C714 these CAP are for LAN CHIP LAN_A3.3

0.1U/10V_4 0.1U/10V_4
pins-- 2 and 59.placement close lan chip
L8
RTL8111C ( Gaga lan ) use 4.7uH +FB12 31
power choke A>500mA tolerance L9
±15% RTL8111C stuff
C C
RTL8101E & RTL8102E stuff 0ohm RTL8102E need to remove L9
+LAN_A1.8
Power trace Layout 寬度> 30mil Power domain chart
L8 L9
L8
4.7UH,+-20%,580MA_8 L9 0_8
>30mil +LAN_A1.8
31 +CTRL18 RTL8111B / RTL8111C
RTL8101E RTL8102E
C51 C57
these cap are for lan
10U/6.3V_8
0.1U/10V_4
C728 C727 C721 C730 chip LAN_A1.8 LANVCC 3.3V 3.3V
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 pins--5, 8, 11 and 14.
C50
*10U/6.3V_8 C46 placement close chip LAN_D1.8 1.8V 1.2V
10U/6.3V_8
C46 1.8V 1.2V
RTL 8101E /8102E stuff , LAN_A1.8
placement close to lan chipset R220
RTL 8111C need to remove +LAN_E1.8
8102E need to remove LAN_D1.5 1.5V 1.2V
R442 0_8 8101E use 0 ohm
C46
RTL8111C stuff R220 8111C use 4.7uH
RTL8101E / 8102E can remove
C731 C732 C732 change to 1U on PV
0.1U/10V_4 1U/10V_4
B B
these cap are for lan chip

L66 LAN_D1.8 pins, such as 22 and 28.
0_8
placement close lan chip
L66
RTL8111C used 0ohm
L66
RTL 8101E/8102E need to
remove
Power trace Layout 寬度> 30mil

C705
RTL8111C stuff
RTL8101E / 8102E can remove +LAN_D1.5
L67 L67 *0_8
>30mil
31 +CTRL15
L67 & C704

8101E/8102E stuff
C705
C704 8111C need to remove C705 C711 C49 C79 C84 C83 C61 C63 C48 C47 C80 C55 C66
C704 10U/6.3V_8 10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
0.1U/10V_4
*10U/6.3V_8
A A
these cap are for lan chip LAN_D1.5 pins-- 15,

21, 32, 33, 38, 41, 43, 49, 52 and 58.placement PROJECT : QT8
close lan chip Quanta Computer Inc.
Custom 1A
LAN Power
NB5/RD5
5 4 3 2 1
A B C D E
NEWCARD (PCIEXPRESS*1 + USB*1)

SATA CD-ROM SI-2 Modified footprint -- Modify 12/27
1
2
CN37
GND1
S1
NEWCARD SI-1 modified -- change
footprint CN17 #31,32 as
ME request for Hole pad
change
+3V_NEWCARD
CN17
EXPCARD-48303-0042-26P-L-QT6
1 GND_1
+3V
+3V
33
+3VS5
14 SATA_TXP4 TXP
1
3 14 USBP7- R209 0_4 USB7-1 2 USB- C567 C561
14 SATA_TXN4 TXN 14 13 USBP7-
4 USBP7+ R212 0_4 USB7+1 3 USB+
GND2 13 USBP7+
5 NEWCARD_DETECT R214 0_4 CPUSB# 4 CPUSB# 0.1U/10V_4 0.1U/10V_4 C575 C520
14 SATA_RXN4 13 NEWCARD_DETECT
2
RXN
14 SATA_RXP4 6 RXP 5 RSV_0
7 6 RSV_1 10U/6.3V_8 0.1U/10V_4
R624 1K/F_4 GND3 S7 SCLK_WLAN
D 13,36 SCLK_WLAN 7 SMBCLK D
1 2 8 P1 SDATA_WLAN 8 SMBDATA
DP 13,36 SDATA_WLAN +3VAUX
9 +5V +1.5V_NEWCARD 9 +1.5V_0
ODD_5V 10 +5V 10 +1.5V_1
11 15 PCIE_WAKE# 11 WAKE#
MD 15 13,31,36 PCIE_WAKE# +3V_NEWCARD
12 GND +3VAUX 12 +3.3VAUX
1
13 PERST# 13 PERST# C507 C506
GND P6 14 +3.3V_1
SATA ODD 15 +3.3V_2 0.1U/10V_4 0.1U/10V_4
1
CLK_NEW_OE# 16 CLKREQ# C519 C513
NEWCARD_DETECT R260 0_4 CPPE# 17 CPPE#
PCIE_NEW_CLKN 18 REFCLK- 0.1U/10V_4 0.1U/10V_4
2 PCIE_NEW_CLKN
2
Del L90 direct on PV PCIE_NEW_CLKP 19 REFCLK+
2 PCIE_NEW_CLKP +3VS5
L96 *WCM2012-110 20 GND_2
ODD_5V PCIE_RXN0 1 2 PCIE_RXN0 21 PERn0
9 PCIE_RXN0
120 mils PCIE_RXP0 4 3 PCIE_RXP0 22 PERp0
9 PCIE_RXP0
+5V 23 GND_3 NC5 31
1
PCIE_TXN0 1 2 PCIE_TXN0 24 PETn0 C531 C530
9 PCIE_TXN0 PCIE_TXP0 PCIE_TXP0 NC5 32 +1.5V_NEWCARD
4 3 25 PETp0
NC1
NC2
NC3
NC4
C877 C896 C893 C897 C895 9 PCIE_TXP0 0.1U/10V_4 0.1U/10V_4
26 GND_4
2
10U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 L97 *WCM2012-110
27
28
29
30
1
C498 C499
0.1U/10V_4 0.1U/10V_4
2
R258 SI-2 remove --internal pull hi +3VS5
CPUSB# R218 *10K/F_4

CPPE# R258 *10K/F_4
C 2231_SHDN# R280 *10K/F_4 C
2231_STBY# R281 *10K/F_4
SI-2 Modified footprint -- Modify 固定孔 Size as SMT request
For HP request to
SI Build U13 SI-2 reserve
2231_STBY# 0.7A
21
22
23
24
1 STBY# 3.3VIN 2 +3V

CN40 SATA HDD(1ST) +3VS5 17 4 PCIE_RXN0
+3VAUX AUXIN 3.3VIN
15 AUXOUT
N_PLTRST# 6 12 PCIE_RXP0
SYSRST# 1.5VIN +1.5V
Main HDD +5V: 2 A(4 Pin) NEWCARD_DETECT 10 14
CPPE# 1.5VIN PCIE_TXN0
9 CPUSB#
+3V: 2 A(4 Pin) PERST# 8 3
PERST# 3.3VOUT +3V_NEWCARD
2A
20
2231_SHDN# 20 5 PCIE_TXP0
1
NEWCLKEN SHDN# 3.3VOUT

Gnd : (5 Pin) 18 RCLKEN
NEW_OC# OC# 19 11 Del R790,
+1.5V_NEWCARD
1A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OC# 1.5VOUT
1
R270 0_6 7 13 R791, C957 C958 C959 C960
GND 1.5VOUT
SI-2 R792,
modified for *.1U/10V_4 *.1U/10V_4 *.1U/10V_4 *.1U/10V_4
2
R5538D001-TR-F R793 for
add Pin RF on PV
SATA_TXP0 14 21~25 as U25
SATA_TXN0 14 R5538 NEW CARD POWER SWITCH Thermal pad
+3V_HDD1 tied to Gnd
SATA_RXN0 14
+5V_HDD1 SATA_RXP0 14 pin name pull hi/low
+1.5V
CPPE# internal pull up to AUXIN
+5V_HDD1 +5V
B +3V_HDD1 +3V B
1
SYSRST# internal pull up to AUXIN C525 C526
R754 *0_8 0.1U/10V_4 0.1U/10V_4
2
CPUSB## internal pull up to AUXIN
+3VS5
Del R578 direct on PV
PERST# a logic level power good 2 EXT_NWD_CLK_REQ#
R224 0_6
+5V_HDD1 +3V_HDD1
R223
3
SHDN# internal pull up to AUXIN *22K_4
RCLKEN internal pull up to AUXIN 2 NEWCLKEN
C33 C31 C697 C32 Q21

C858 C860 C861 C859 *10U/6.3V_8 *4.7U/6.3V_6 *0.1U/10V_4 *10U/6.3V_8 OC# over current status 2N7002E
10U/6.3V_8 4.7U/6.3V_6 0.1U/10V_4 10U/6.3V_8
1
STBY# internal pull up to AUXIN CLK_NEW_OE#
follow AMD schematic

+3VS5
C514 0.1U/10V_4
U11
5
A A
EPRESS_PLTRST# 2
12 EPRESS_PLTRST# N_PLTRST#
4
1
SI-2 modified -- *TC7SH08FU

PROJECT : QT8
3
EPRESS_PLTRST# is
3VS5 power rail , Quanta Computer Inc.
Maybe can remove NAND
GATE Size Document Number Rev
Custom 1A
NEW CARD/SATA ODD/SATA HDD
R784 0_6 NB5/RD5
A B C D E
5 4 3 2 1
POWER BUTTON CONNECT

MY5
MY6
MY3
C379
C833
C375
220P/50V_4
220P/50V_4
220P/50V_4
MY1
MY2
MY4
C836
C835
C377
220P/50V_4
220P/50V_4
220P/50V_4
MX7
MX0
MX5
C384
C378
C382
220P/50V_4
220P/50V_4
220P/50V_4
34
MY7 C834 220P/50V_4 MY0 C381 220P/50V_4 MX1 C385 220P/50V_4
NBSWON1# MY8 C376 220P/50V_4 MX4 C402 220P/50V_4 MY12 C832 220P/50V_4
+PWLEDVCC MY9 C403 220P/50V_4 MX6 C383 220P/50V_4 MY13 C374 220P/50V_4
MY10 C830 220P/50V_4 MX3 C837 220P/50V_4 MY14 C831 220P/50V_4
D D
MY11 C373 220P/50V_4 MX2 C380 220P/50V_4 MY15 C372 220P/50V_4
1
G2
1
C36 C38 C481 *SHORT_ PAD1
0.1U/10V_4 0.1U/10V_4 0.1U/10V_4
2
SI-2 Modified
-- net swap for
layout concern
KEYBOARD PULL-UP CN11
MX1
+3VPCU MX7 1
RP42
C699 0.1U/10V_4 MY0 MX6 2
10 1 3
Add R36 for +5VPCU 1. +3VPCU(LIDSWITCH PWR) MY15 9 2 MY5 MY9
MY11 MY4 MX4 4
8 3 5
CN4 2. LEDVCC(+3VPCU) MY13 7 4 MY8 MX5
R36 *39_6 PWR BTN CONN MY3 MY0 6
6 5 7
+5VPCU 1 2 3. LIDSWITCH MX2
MX3 8
+3VPCU 10K_10P8R
R33 39_6 MY5 9
+PWLEDVCC 1 4.POWERON# MY1 10
+3VPCU_LED 1 2 RP41
2 MY10 MX0 11
23,35 LID_EC# 3 5. PWRLED# MY9
10 1
MY14 MY2 12
35 NBSWON1# 4 9 2 13
PWR_LED# 6. GND MY1 8 3 MY12 MY4
29,35 PWR_LED# 5 14
MY2 7 4 MY6 MY7
6 MY7 MY8 15
6 5 16
MY6
10K_10P8R MY3 17
C C
MY12 18
MY13 19
MY14 20
MY[0..15] MY11 21
35 MY[0..15] 22
MY10
MY15 23
MX[0..7] 24
35 MX[0..7]
KB CONN
gb1rf240-1253-7f-24p-l
Del R770 on PV
SI-2 Modified 12/27
CAP SW CONNECT +5V_LED 140 mA

CN12
1.LEDVCC
4 2.LEDVCC SI-2 Modified
3
2 3. NC
C394 1
0.1U/10V_4 BL123-04R-TAND
4. GND
BL123-04R-4P-L-QT6
+3VPCU
B B
C75
0.1U/10V_4
CN8 1. +3VPCU
CAP SW BOARD
2. MBCLK
1
35,44 MBCLK 2 3. MBDATA
35,44 MBDATA 3
35 IC2_INT 4 4. CAP_INT
5
35 NUMLED# 6 5. GND
+5V_LED 7
8 6. NUM LOCK LED
C934 9
0.1U/10V_4
7. +5V
8. ESB_CLK
9. ESB_DAT
L77 BK1608HS470 ESB_CLK

35 CAP_ESB_CLK
PV modified:
L57 BK1608HS470 ESB_DAT CN8 update type
35 CAP_ESB_DAT
Add L57, L77, C904, C621 for ESB
A A
Del R104, R103
C904
C621
10P/50V_4 10P/50V_4
PROJECT : QT8
Custom 1A
LED/KEYBOARD/SW
NB5/RD5
5 4 3 2 1
5 4 3 2 1
Change U9 layout footprint

+3VPCU +3VPCU +3VPCU_EC +5VPCU
12 SERIRQ
SERIRQ
LFRAME#
3
4
to LQFP128-16X16-4-AA1
U9
SERIRQ VCC1 9
22
C456
C472
C463
4.7U/6.3V_6
0.1U/10V_4
0.1U/10V_4
L41
1
U8
*GMT_G910T21U
Vout Vin 3
+5VSUS R153
R163
4.7K_4
4.7K_4
TPCLK
TPDATA
35
GND
12,36 LFRAME# LFRAME VCC2
LAD0 10 33 C491 0.1U/10V_4 BLM18BA470SN1(47,300MA)_6 C458 close conn
12,36 LAD0 LAD0 VCC3
LAD1 8 96 C495 0.1U/10V_4
12,36 LAD1 LAD1 VCC4
LAD2 7 111 C490 0.1U/10V_4 1U/10V_4
12,36 LAD2
2
LAD3 LAD2 VCC5 C455 0.1U/10V_4
5 125
12,36 LAD3
PCLK_LPC_KB3920 12
LAD3 VCC6
67 C461 4.7U/6.3V_6 Del L86 on PV TOUCH PAD CONNECTOR
12 PCLK_LPC_KB3920 PCICLK AVCC
R208 0_4 13
12 PCIRST# PCIRST/GPIO5
CLKRUN# 38 +3VPCU_EC 25 mils
D 12 CLKRUN# CLKRUN D
C851 0.1U/10V_4
+5VSUS
SCI1# 20
GATEA20 SCI/GPIOE TEMP_MBAT C411 0.1U/10V_4
13 GATEA20 1 GA20/GPIO0 AD0/GPI38 63 TEMP_MBAT 44 +3V_LED
13 RCIN# RCIN# 2 64 AD_TYPE
3920_RST# KBRST/GPIO1 AD1/GPI39 AD_AIR
37 ECRST AD2/GPI3A 65
SYS_I
AD_AIR 44 SI-2 for fix cpu vcore
AD3/GPI3B 66 SYS_I 44 12
MX0 55
34 MX0 KSI0/GPIO30 11
MX1 56 68 CC-SET R794 0_4 TPCLK L38 BLM18BA470SN1(47,300MA)_6 TPCLK-1
34 MX1 KSI1/GPIO31 DA0/GPO3C CC-SET 44 10
MX2 57 70 CELL_SLT TPDATA L39 BLM18BA470SN1(47,300MA)_6 TPDATA-1
34 MX2 KSI2/GPIO32 DA1/GPO3D CPU_SVID 40 9
MX3 58 71 FAN1ON TP_LED1#
34 MX3 KSI3/GPIO33 DA2/GPO3E FAN1ON 37 8
MX4 59 72 D/C# C417 TP_LED2#
34 MX4 KSI4/GPIO34 DA3/GPO3F D/C# 44 7
MX5 60 C441
34 MX5 KSI5/GPIO35 6
MX6 61 21 PWM_VADJ *10P/50V_4 *10P/50V_4 TP_L
34 MX6 KSI6/GPIO36 PWM1/GPIOF PWM_VADJ 23 5
MX7 62 23 KEY_BEEP (1KHz) TP_R
34 MX7 KSI7/GPIO37 PWM2/GPIO10 KEY_BEEP 28 4
SI-2 Modified for hp request 3
MY0 39 26
34 MY0 KSO0/GPIO20 FANPWM1/GPIO12 T54 2
MY1 40 27 FAN2ON
34 MY1 KSO1/GPIO21 FANPWM2/GPIO13 T53 1
MY2 41 28 FAN1SIG
34 MY2 KSO2/GPIO22 FANFB1/GPIO14 FAN1SIG 37
MY3 42 29 CIR_IN Del R249 on PV
34 MY3 KSO3/GPIO23 FANFB2/GPIO15 CIR_IN 27,37
MY4 43 CN14
34 MY4 KSO4/GPIO24
34 MY5
MY5 44 KSO5/GPIO25 SCL1/GPIO44 77 MBCLK
MBCLK 34,44 Battery charge/discharge TOUCH PAD CONN
34 MY6
MY6 45 KSO6/GPIO26 SDA1/GPIO45 78 MBDATA
MBDATA 34,44 Cap button SW2 PCB footprint
MY7 46 79 MBCLK2 3 1 BL121-12R-12P-L-QT6
34 MY7 KSO7/GPIO27 SCL2/GPIO46 MBCLK2 5,18
34 MY8
MY8 47 KSO8/GPIO28 SDA2/GPIO47 80 MBDATA2
MBDATA2 5,18 VGA thermal MY7 4 2 MX4
MY9 48 system thermal 6 5
34 MY9 KSO9/GPIO29
34 MY10
MY10
MY11
49
50
KSO10/GPIO2A PA Update SW2, SW4, SW6
34 MY11 KSO11/GPIO2B
MY12 51 TMG-533-S-V-TR P/N on PV
34 MY12 KSO12/GPIO2C
MY13 52
34 MY13 KSO13/GPIO2D
C MY14 53 6 SUSB# C
34 MY14 KSO14/GPIO2E GPIO4 SUSB# 13
MY15 54
34 MY15
81
KSO15/GPIO2F
KSO16/GPIO48 GPIO7 14 HWPG
HWPG 20,23,38,39,41,42
TOUCH PAD ON/OFF
82 KSO17/GPIO49 GPIO8 15 PM_BATLOW1# Pin 17 (GPIO0B) ==> assigned for
ESB_CLK / Pull high 4.7K
IC2_INT 83 16 SUSC#
34 IC2_INT
SLPBTN# PSCLK1/GPIO4A GPIOA SUSC# 13 Pin 18 (GPIO0C) ==> assigned for SW4
84 17 CAP_ESB_CLK 34
R200 10K/F_4 85
PSDAT1/GPIO4B GPIOB
18 CAP_ESB_DAT 34
ESB_DAT / Pull high 4.7K TP_L R352 1K/F_4 TP_L_CONN 3 1
+3VPCU PSCLK2/GPIO4C GPIOC
ACIN 86 19 NBSWON1# 4 2
44 ACIN PSDAT2/GPIO4D GPIOD NBSWON1# 34
TPCLK 87 25 LAN_RESET# move to Pin 25 6 5
PSCLK3/GPIO4E GPIO11 LAN_REST# 31
2
TPDATA 88 30
PSDAT3/GPIO4F GPIO16 SWI#1
EC_DEBUG1 36 pin 18 (SWI#1) move to Pin 31 C445
GPIO17 31
BIOS_RD# 119 32 KBSMI#1 0.1U/10V_4 TMG-533-S-V-TR
1
BIOS_WR# RD GPIO18
120 WR
BIOS_CS# 128 34 VRON
SELMEM/SPICS GPIO19 VRON 39,40
R234 0_4 SERR#_1 89 36 NUMLED#
12 SERR# SELIO/GPIO50 GPIO1A NUMLED# 34
76 AD5/GPI43
37 VOLME_UP#
VOLME_UP# 109 D0/GPXD0
reserved for H/W CIR Del R256 for TP SI-2 ADD R256 SW6
VOLME_DN# 110 on PV for H/W CIR TP_R R365 1K/F_4 TP_R_CONN 3 1
37 VOLME_DN# D1/GPXD1
PR_INSERT# 112 4 2
24,37 PR_INSERT# D2/GPXD2
MUTE_LED 114 73 6 5
28,37 MUTE_LED D3/GPXD3 GPIO40 CIR_IN 27,37
2
RF_LINK# 115 74
36 RF_LINK# D4/GPXD4 GPIO41 T56
BLUELED 116 75 C446
D5/GPXD5 AD4/GPI42 T57
LAN CABLE DETECT 117 90 DNBSWON#1 0.1U/10V_4 TMG-533-S-V-TR
31 LAN CABLE DETECT
1
D6/GPXD6 GPIO52 CAPSLED# +3V R199 *10K/F_4 HWPG
T60 118 D7/GPXD7 GPIO53 91 CAPSLED# 29
92 PWR_LED#
R235 *4.7K_4 BIOS_A0 97 A0/GPXA0
GPIO54
GPIO55 93 ECPWROK
PWR_LED# 29,34
ECPWROK 5,16
TOUCH PAD L/R
SUSON 98 95 RSMRST# R244 100K/F_4 CIR_IN
41,43 SUSON A1/GPXA1 GPIO56 RSMRST# 13 +3VPCU
MAINON 99 121 VOLMUTE# R188 10K/F_4 NBSWON1#
20,27,39,42,43,44 MAINON A2/GPXA2 GPIO57 VOLMUTE# 28
LAN_POWER 100 126 SPI_CLK R236 10K/F_4 VOLME_UP#
B 43 LAN_POWER A3/GPXA3 GPIO58 B
S5_ON 101 127 LID_EC# R237 10K/F_4 VOLME_DN#
42,43 S5_ON A4/GPXA4 GPIO59 LID_EC# 23,34
41 VR2.5_ON
VR2.5_ON 102 A5/GPXA5
R207 10K/F_4 SLPBTN# Blue LED change to 100K ohm
103 R190 4.7K_4 MBCLK pull low on PV
13,31 LAN_DISABLE# A6/GPXA6
LEDVCC_EN# 104 123 CRY2 C479 18P/50V_4 R197 4.7K_4 MBDATA
29 LEDVCC_EN# A7/GPXA7 XCLKO
MBATLED0# 105 R210 *8.2K_4 PM_BATLOW#
29 MBATLED0# A8/GPXA8
4
106 R175 *8.2K_4 CLKRUN# BLUELED R268 100K/F_4

A9/GPXA9 30,36 BLUELED
TP_LED1# 107 122 CRY1 Y3 R213 *8.2K_4 SERIRQ +3VPCU
29 TP_LED1# A10/GPXA10 XCLKI
TP_LED2# 108 32.768KHZ R256 4.7K_4 CAP_ESB_CLK
29 TP_LED2# A11/GPXA11 R220 4.7K_4 CAP_ESB_DAT
11
1
GND1
GND2 24 SB780 internal have pull hi
35 +3VPCU
GND3
124 V18R GND4 94 C480 18P/50V_4 SI-1
113 modified C542
GND5
2
69 Del R246, R254 direct on PV 0.1U/10V_4

C493 C494 AGND
change D11 type D11 -- change
0.1U/10V_4 4.7U/6.3V_6 for PV RB500V-40 vaule U12 R263
1
KB3926 UMA BOM missing BIOS_CS# 1 CE# VDD 8

SPI_CLK R239 33_4 6 10K/F_4
For KB3926 C version BIOS_WR# SCK
5 SI
AD_TYPE R174 100/F_4 BIOS_RD# 2 7 SPI_7P
AD_ID 44 SO HOLD#
SI-2 Add Pin 117,103 for DSM,116 for Bluetooth,Pin 23 for Key Beep to Amplifier
+3VPCU R238 10K/F_4 SPI_3P 3 4
WP# VSS
SI-2 modified 64.9K -->65W
2
for avoid AD-_ID R173 MX25L8005

SCI1# D13 1 2 CH501H-40PT C941 33.2K/F_4 33.7K -->90W
SCI# 13 noise 0.1U/10V_4 SST AKE5GFK0Z09 1M byte
1
SB internal pull Hi 10k CS36492FB17 RES CHIP 64.9K 1/16W +-1%(0402) WINBOND AKE3GFP0N08 SPI
A PM_BATLOW1# D15 1 2 CH501H-40PT PM_BATLOW# 13 to 3v_s5 BIOS A
CS33322FB13 RES CHIP 33.2K 1/16W +-1% (0402) PME AKE3GZP0500
DNBSWON#1 D16 RB500V-40 3920_RST#

EON AKE3GZP0Q00
DNBSWON# 13 Change D12, D16 to RB500 3920_RST# 5,44
for current loss
R176 47K_4
C453 0.1U/10V_4
PROJECT : QT8
+3VPCU 2 1
KBSMI#1 D12 RB500V-40
KBSMI# 13
SLPBTN# R206 0_4
SB internal pull Hi Size
Custom
Document Number Rev
SWI#1 D14 1 2 *CH501H-40PT L-F NBSWON1# R205 *0_4 KB3926/ROM/TP 1A
SWI# 13 10k to 3v_s5 SLP_BTN# 37
NB5/RD5
5 4 3 2 1
A B C D E
Mini PCI-E Card 1 WLAN

SI-2 modified --Change Library to MIPCI-C-1775861-52P-LDV-QT6
+3V
+3VSUS
R57 *10K/F_4
+1.5V
36
Del R419
2
C78 C72 C35
0.01U/16V_4 0.1U/10V_4 10U/6.3V_8
+3V_WLAN +1.5V
D D
3 1 MINICAR_PME#
13,31,33 PCIE_WAKE#
CN25 Q9
51 52 *PDTC144EU
Reserved +3.3V
49 Reserved GND 50
47 Reserved +1.5V 48
45 46 MINI_BLED R277 *0_4 +3V_WLAN
Reserved LED_WPAN# BLUELED 30,35
43 44 RF_LINK#
Reserved LED_WLAN# RF_LINK# 35
41 42 R288 10K/F_4
Reserved LED_WWAN# +3V
39 Reserved GND 40
37 Reserved USB_D+ 38 USBP10+ 13
35 36 Del R48, R49 C30 C707
GND USB_D- USBP10- 13
PCIE_TXP1 33 34 for USB 0.1U/10V_4 10U/6.3V_8
9 PCIE_TXP1 PETp0 GND
PCIE_TXN1 31 32 DAT_SMB SDATA_WLAN 13,33 power shape
9 PCIE_TXN1 PETn0 SMB_DATA
29 30 CLK_SMB SCLK_WLAN 13,33
GND SMB_CLK
27 GND +1.5V 28
PCIE_RXP1 25 26 Change +3VSUS to +3V
9 PCIE_RXP1 PERp0 GND
PCIE_RXN1 23 24 Del R35 on PV
9 PCIE_RXN1 PERn0 +3.3Vaux
21 22 MINI_PLTRST#
GND PERST# MINI_PLTRST# 12
PCLK_LPC_DEBUG 19 20
12 PCLK_LPC_DEBUG Reserved W_DISABLE# RF_OFF# 12
MINI_PLTRST# 17 18 INTEL WLAN
Reserved GND +3V
CARD PIN 20
15 16 LAD0_1 R434 0_4 LAD0 LAD0 12,35 W_DISABLE#
PCIE_MINI1_CLKP GND Reserved LAD1_1 R436 0_4 LAD1
2 PCIE_MINI1_CLKP 13 REFCLK+ Reserved 14 LAD1 12,35 have
2 PCIE_MINI1_CLKN PCIE_MINI1_CLKN 11 12 LAD2_1 R437 0_4 LAD2 LAD2 12,35
REFCLK- Reserved LAD3_1 R438 0_4 LAD3 internal
9 GND Reserved 10 LAD3 12,35
T3 CLK_MINI_OE# 7 8 LFRAME#_1 R440 0_4 LFRAME# LFRAME# 12,35
pull-up 110k
CLKREQ# Reserved C42 C41
14 BT_COMBO_EN# 5 BT_CHCLK +1.5V 6 ohm
3 4 0.1U/10V_4 1U/10V_4
T4 MINICAR_PME# BT_DATA GND
1 WAKE# +3.3V 2
C C
MINI PCIE H=4.0
BT_DATA,BT_CHCLK,CLKREQ# R579
internal pull-DOWN 100k *10K/F_4
ohm
PCLK_LPC_DEBUG R432 *0_4 C717 *27PF/50V_4
for EMI request
Mini PCI-E Card 2 TV tuner card

+3V
Del R308
Del EC_debug2 for
CAP board update
on PV
B B
MINIEC_5V +1.5V
FOR KBC DEBUG C605 C592
CN39 0.1U/10V_4 10U/6.3V_8
R350 *0_6 51 52
+5V COMP VIDEO IN +3.3Vaux
49 Therm Trip out GND 50
47 AUD_R_IN +1.5V 48
35 EC_DEBUG1 45 AUD_L_IN NC 46
43 GND NC 44
41 +3.3Vaux NC 42
39 +3.3Vaux GND 40
37 GND NC(USB_D+) 38 USBP11+ 13
35 GND NC(USB_D-) 36 USBP11- 13
PCIE_TXP3 33 34
9 PCIE_TXP3 PETp0 GND
PCIE_TXN3 31 32 PDAT_SMB PDAT_SMB 2,6,7,13,28
9 PCIE_TXN3 PETn0 NC(SMB_DATA)
29 30 PCLK_SMB PCLK_SMB 2,6,7,13,28
GND NC(SMB_CLK)
27 GND +1.5V 28
PCIE_RXP3 25 26 R304 0_6 +3V
9 PCIE_RXP3 PERp0 GND
PCIE_RXN3 23 24 R303 *0_6 +3VSUS
9 PCIE_RXN3 PERn0 NC(+3.3Vaux)
21 22 MINI_PLTRST#
GND PERST#
19 S-Video Y/in NC 20
17 S-Video C/in GND 18 Del WAN off#
15 16 +1.5V
PCIE_MINI2_CLKP GND NC
2 PCIE_MINI2_CLKP 13 REFCLK+ NC 14
2 PCIE_MINI2_CLKN PCIE_MINI2_CLKN 11 12
REFCLK- NC
9 GND NC 10
7 CLKREQ# NC 8
5 6 C606 C607 C591
NC +1.5V 0.01U/16V_4 0.1U/10V_4 10U/6.3V_8
3 NC GND 4
A 1 NC +3.3Vaux 2 A
MINIPCIE H=7.0
67910-0002
PROJECT : QT8
SI-2 modified --Change Library to MIPCIE-P04-FJ504-170-52P-QT6 Quanta Computer Inc.
Custom 1A
Mini CARD X 3
NB5/RD5
A B C D E
A B C D E
CABLE DOCK
37
support 6A 200mils
CX000480005
+DOCK_VA CN21
L5
48/6A_12 VA_P VA_P 44 43 VA_P
44 +DOCK_VA VDD VDD
SI-2 modified follow QT6 schematic CRT_GDK 38 38 39 39

remove R671,R670,C916,Q30,L65,C669,R388 C29 C17 CRT_RDK 40 37
40 37
0.1U/50V_6 0.1U/50V_6 24 DDCDAT2 34 34 35 35
CRT_BDK 36 33
4
R779 221/F_4 C949 .1U/50V_6 SPDIF_DOCK R18 33_6 PR_HSYNC_D 36 33 4
27 SPDIF 24 PR_HSYNC 30 30 31 31
24 DDCCLK2 32 32 29 29 CIR_IN 27,35
USBP4- 26 27 PWR_ON
26 27
R780 C950 R20 33_6 PR_VSYNC_D 28 25 MUTE_LED
24 PR_VSYNC 28 25 MUTE_LED 28,35
100/F_4 220P/50V_4 22 23 SLP_BTN#
22 23 SLP_BTN# 35
USBP4+ 24 21 JACK_SEN#
24 21 JACK_SEN# 27
18 19 VOLME_UP#
31 LAN_MX3+ 18 19 VOLME_UP# 35
4 3 USBP4- 20 17 VOLME_DN#
13 USBP4- 31 LAN_MX3- 20 17 VOLME_DN# 35
1 2 USBP4+ 15 SPDIF_DOCK
13 USBP4+ 15 Remove R410, R411
31 LAN_MX2+ 14 14
L4 *WCM-2012-900T(400mA) 16 13
31 LAN_MX2- 16 13 AGND
10 11 RSPK_DK_L
31 LAN_MX1+ 10 11 RSPK_DK 27
12 9 LSPK_DK_L
31 LAN_MX1- 12 9 LSPK_DK 27
31 LAN_MX0+ 6 6 7 7
8 5 DOCK_MIC_R 27
31 LAN_MX0- 8 5 DOCK_MIC_L 27
SI-2 modified -- +3V +3VPCU 2 2 3 3 AGND
for power leakage +VIN 4 1 DOCK_PRESENT
4 1
concern
1
C698 42 41
VSS VSS
46 46 45 45
R413 0.1U/50V_6
100K/F_4 R415 DOCKING CONN
*100K_4
2
PR_INSERT#
PR_INSERT# 24,35
docking
insert is HI
3 voltage 3
Q31
3
MMBT3904
DOCK_PRESENT 1 2 DKPR# 2
R412 1K/F_4
1
R414
2K/F_4 PR_GEN R12 0_6 CRT_GDK
24 PR_GEN
Change D29, D30 to RB500 PR_RED R11 0_6 CRT_RDK
24 PR_RED
D29 for current loss on PV
PR_BLU R15 0_6 CRT_BDK
24 PR_BLU
+5V RB500V-40
D30
+5VSUS R409 1 2 10K/F_4 DK_PWRON RB500V-40 PWR_ON R16 R9 R13
C25 C19 C23 C24 C20 C21
1
S0: 4V *Check 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6 5.6P/50V_6

S3: 2.5V voltage on R408 150/F_4 150/F_4 150/F_4
DB 15K/F_4
S4/S5:
2
0V
filter for docking CRT
2 2
+3V DOCK_MIC_R
DOCK_MIC_L
CPU FAN R177
4.7K_6 RSPK_DK_L
LSPK_DK_L
VOLME_DN#
35 FAN1SIG
JACK_SEN#
CIR_IN
CN26
20 mil
+5VFAN1 1 PR_HSYNC_D
1
2 2
3 PR_VSYNC_D
C725 C724 3
FAN CONN
2.2U/6.3V_6 0.1U/10V_4 C27 C26
C688 C692 C691 C693 C694 C696 C695
*47P/50V_4
*47P/50V_4 *100P/50V_4 *100P/50V_4 *270P/25V_4 *180P/50V_4 *180P/50V_4 *180P/50V_4 *180P/50V_4
+5V
G955 /FON
signal have C687 1U/10V_4
internal AGND AGND AGND AGND AGND
pull Hi to
VIN , R420 R420 SI-2 modified
maybe can
1 10K/F_4 U24 1
remove +5VFAN1
2 VIN VO 3
5 8 7 6 5 G995 layout notice
FAN_SMBALERT# GND
1 /FON GND 6
GND 7 Gnd shape
PROJECT : QT8
35 FAN1ON 4 VSET GND 8

FANPWR = 1.6*VSET G995
1 2 3 4

Custom 1A
CABLE DOCKING/FAN
NB5/RD5
A B C D E
5 4 3 2 1
+3V 2,3,5,6,7,10,11,12,13,14,15,16,18,20,23,24,25,26,27,28,29,30,31,33,35,36,37,39,43
DC/DC +3VPCU/+ 5VPCU/ +12VALW

TON: 5V / 3.3V
38
GND = 400 / 500KHz
+5VPCU 27,28,34,35,39,40,41,42,43 REF = 400 / 300KHz
VCC = 200 / 300KHz
+3VPCU 5,12,23,29,30,34,35,37,40,41,42,44
+VIN
D +3VSUS 13,25,30,36,39,41,43 D
+VIN_6237
+3VS5 5,7,12,13,14,15,16,23,26,33,43
+5VAL +5V_VCC1
+5VSUS 23,30,35,37,43
2200P/50VB_4
0.1U/50VB_6
10U/25VD_1206
PR160
PC94
PC93
PC98
+VIN PR163 2 1
+5V 5,15,20,23,24,25,27,28,29,30,33,36,37,39,42,43 PR164
390K_4
4.7U/6.3VC_6
2 1 *47_6
+LANVCC +
PC110
0_8
PR162 Place these CAPs 3.3 Volt +/- 5%
6237ONLDO
150K/F_4
close to FETs
5 Volt +/- 5%
+3VPCU
C/C:8A
Place these CAPs Del PR159 for TP on PV
10U/25VD_1206
0.1U/50VB_6
2200P/50VB_4
6237VIN PC107
close to FETs
PC157
PC76
PC79
+5VPCU P/C:10A
PC108 PC106 1U/10VC_4
5
6
7
8
0.1U/50VB_6
0.1U/10VC_4
PC109
REF
C/C:8A
1
*1U/10VC_4 6236AGND
P/C:10A
6236AGND 4
TON
PQ58
8
7
6
5
PR158 SI4800BDY
0_4
2
8
7
6
5
4
3
2
1
4 6236AGND
6236AGND PL13 +3VPCU
LDOREFIN
LDO
IN
RTC
ONLDO
VCC
TON
REF
3
2
1
PC105 REFIN2 2.5uH/7.5A_10
Vout=0.7(Ra+Rb)/Rb 3V_LX
6236AGND
C PQ53 *0.1U/10VC_4 C
SI4800BDY PR217
5
6
7
8
2
SI-1 Modified
330U/6.3V_ESR25_6X5.8
+5VPCU 309K/F_4
+5VPCU Rb around 49.9k 9 BYP REFIN2 32
6236AGND
0.1U/10VC_4
PL12 10 31 1 2 -ECAP6_3X6_1-7_2-QT8
1
2
3
OUT1 ILIM2
1
2.5uH/7.5A_10 6236FB1 11 PU8 30 PR214
FB1 OUT2
PC182
PC181
+5V_ALWP PR153 1 2 12 29 4 *2.2_6 +
309K/F_4 PGOOD1 ILIM1 ISL6237 SKIP PGOOD2 PR157
13 28
1
PGOOD1 PGOOD2
2
6237ON1 14 27 0_4
2
ON1 ON2
2
8
7
6
5
330U/6.3V_ESR25_6X5.8
PR208 5V_DH 15 26 3V_DH PC174
1
DH1 DH2
0.1U/10VC_4
Ra *2.2_6 5V_LX 16 25 *100P/50VA_6

LX1 LX2
1
PC179
PC177
+ PR155 4 5V_DL
SECFB
1
3
2
1
AGND
PGND
+3VPCU
0.1U/50VB_6
PC102
*0_4
BST1
BST2
VDD
PAD
1
DL1
DL2
PC103 PQ59
2
2
PC161 PQ54 0.1U/50VB_6 FDS6690AS
2
*100P/50VA_6 FDS6690AS
5VBST1R
Rb
33
17
18
19
20
21
22
23
24
5
6
7
8
Rds(on) 15m ohm PR154
PR156 PR149 1_6 *0_4
3VBST2R
1
2
3
0_4 5VBST1
3VBST2
Rds(on) 15m ohm 1 2
1
43 MAIND 4
1
PR148 PC104 PQ34

SI-1 Modified - +5VAL 1 2 *0.1U/10VC_4 6236AGND SI4800BDY
ECAP6_3X6_1-7_2-QT8 6236AGND PD18 1_6 3V_DL
1 6236AGND
PC101 6236AGND
2
I_lim*MOSFET(RDSON)=V_ILIM(mV)/10 CHN217PT 3 PR216 PR183
+3V
3
2
1
PC180 0_4
V_ILIM(mV)=5uA*R_ILIM 2 0.1U/50VB_6 1U/10VC_4 PR152 PGOOD2
+3V
*SHORT-1A 0_4
PGOOD1
6.76A
HWPG 20,23,35,39,41,42
1
B B
PC97 1
0.1U/50VB_6 PC100
PD17 3 6236AGND 6236AGND S0-S1
CHN217PT
PR147 2 0.1U/50VB_6 +3VPCU
0_6
+12V_ALWP
+12VALW
2
5
PR151 PC96
PR161
100K_4
0_4 2.2U/50VB_8 SI2 +3VS5 PQ35
+3VSUS
1
AP4228
+5VAL
PR150
6237ON2
0.5A 1.84A
5,44 SYS_SHDN# 2 1
0_4
S0-S5 +3VS5 +3VSUS S0-S3
4
+5VPCU +5VPCU
+3VSUS
5,7,12,13,14,15,16,23,26,33,43 +3VS5 +3VSUS 13,25,30,36,39,41,43
5
6
7
8
5
6
7
8
+5VSUS SUSD
43 S5_OND SUSD 43
MAIND4 PQ24 4 PQ23
43 MAIND
SI4800BDY
+5V 43 SUSD
SI4800BDY 4.5A +3VPCU
A A
4.31A S0-S3
1
2
5
6
For EMI-SI +5V For EMI-SI +5VSUS PQ51 +LANVCC
3
2
1
3
2
1
S0-S1 3 SI3456
PROJECT : QT8
43 LAN_ON
0.27A
4
PC195 PC194 +3VLANVCC

+5V 5,15,20,23,24,25,27,28,29,30,33,36,37,39,42,43 +5VSUS 23,30,35,37,43
0.1U/10VC_4 0.1U/10VC_4
+3VLANVCC 31,32,43 Size Document Number Rev
Custom 1A
+5V/+3V(ISL6237)
NB5/RD5
5 4 3 2 1
5 4 3 2 1
+1.1V & +1.2V 39

PD1
+5VPCU CH501H-40PT L-F
D +VIN D
2 1 RTBST
1U/10VC_4
PC23
2200P/50VB_4
10U/25VD_1206
*10U/25VD_1206
PR32
+VIN +1.2V
0.1U/50VB_6
10_6
PC127
PC128
PC126
PC131
Ton=3.85p*R_TON*VOUT/(VIN-0.5) +3VSUS PC15 PR8
12A (4.3A+7.0A)
5
6
7
8
Frequency=Vout/(VIN*TON) 8204VDD BST
PR7 1U/10VC_4 0_6
13
2
9
604K_4 PC4 4
PR51 0.1U/50VB_6 S0-S1
VDDP
VDD
BST
47K_4 RTTON 16 12 RTDH PQ42
TON DH SI4800BDY
RTPG 4 11 RTLX
PR53 PGD LX +1.2V
PU1
RTLPPG 5 PL7
20,23,35,38,41,42 HWPG PR38
3
2
1
PR1 LPGD ILIM
0_4 RTEN 15
RT8204 ILIM 10
35,40 VRON EN/DEM
5
6
7
8
10.7K/F_4 1.5uH/10A_10
DL 8
1
0_4 17 PAD
*100P/50VA_4
0.1U/10VC_4
VOUT
3 +
LDRI
LEN
FB
LFB
PC2
PC160
RTDL 4 PR200 PC150
C 20,27,35,42,43,44 MAINON C
PQ41 *2.2_6 390U/2.5V_6X5.8ESR10
RTFB
2
PR13 *0_4 FDS6690AS
14
1
PR45
PR50
reserved for pwr seq -- andrew 6.04K/F_6 10K/F_4 PC140
RTLEN
*100P/50VA_6
3
2
1
PR52 R1 R2
3.82A RTPG
RDSon=15m-ohm
0_4
PQ57
S0-S1 PC3
PC19
*100P/50VA_4
SI3456 *100P/50VA_4
+1.2V +1.1V
6 Vo=0.75(R1+R2)/R2
5 4
2 +1.2V R_ILIM=I_LIMIT*Rsense/20uA +1.1V 9,10,11,18,20,43
.1U/10V/04
1
+1.2V 2,3,11,12,14,15
PC170
PC168 PC169 PC173 Keep R2 higher than 10Kohm

10U/4VD_8 .1U/10V/04 10U/4VD_8 RTLDRI
+1.1V_DYN 11
9338DRV 3
PC26
5
6
7
8
22P/50VA_4 PC90
B 10U/4VD_8 B
PR215 PR211 PC175 PR54
*0_4 PU11 47/F_4 0.033U/25VB_6 0_6 4
20,23,35,38,41,42 HWPG 3 6 PQ56
PGD DRV SI4856
RTPG 9338EN 4 EN 9338ADJ +1.1V PC37
+1.1V 7.0A
G9338 ADJ 5
PR213 +5V 22P/50VA_4
0_4 PR210 +1.1V_DYN
1 2 R1
3
2
1
VCC GND
PC176
*.1U/10V/04
127/F_6
S0-S1
PR212
PC178 R2 100/F_4
0.1U/10VC_4
PC162
10U/4VD_8
10U/4VD_8
.1U/10V/04 R1
+3V
*22P/50VA_4
PC163
PC165
PC32
PR223 PR58
Vout1= 0.5 * ( 1 + R1/R2 ) 13.7K/F_4 5.11K/F_6
RTLFB
3
PR222
*10K/F_4
DYN_PWR_EN High Low PR224 Vo=0.75(R1+R2)/R2
10 DYN_PWR_EN 2
PQ5 R2 PR49
A 0_4 2N7002E-G 10K/F_4 A
+1.1V_DYN 1.0 1.1 PC189
PROJECT : QT8
1
PR225 *0.1U/10VC_4
2K_4
PR31 for UMA only

B 1A
+1.2V & +1.1V(RT8204)
NB5/RD5
5 4 3 2 1
A B C D E F G H
3A +CPUVDDNB
UGATE_NB 8 G1
7 S1/D2
PQ50
D1 1
D1 2
+VIN_CPU_NB
+VIN
40
2200P/50VB_4
0.1U/50VB_6
10U/25VD_1206
PR93
1
390U/2.5V_ESR10_6X5.8
3 CPU_VDDNB_RUN_FB_H PL10 G2 3 LGATE_NB
ISL6265 Pin1 OFS VFIXEN 6
PC144
PC149
PC142
2.5UH/7.5A_10
47/F_4 + 5 S2 4
2
PC171
1.2V
V X SI4914DY
0.1U/10VC_4
PR92
PC167
3.3V 3 CPU_VDDNB_RUN_FB_L
X V 47/F_4
1 1
5V 6265AGND
X X
SI-1 Modified -
+5VPCU PR100 ECAP6_3X6_1-7_2-QT8
1000P/50VB_4
10_6
PC44
PR94
VFIXEN VID Codes 22.1K/F_4
2
PC45
SVC SVD Output 1U/10VC_4
1
+VIN +VIN
PR101
1
10_6 6265AGND
1200P/50VB_6
0 0 1.4 PR80
PC137
0_4
2200P/50VB_4
0.1U/50VB_6
10U/25VD/1206
10U/25VD/1206
1
1
PC139
PC134
0 1 1.2
2
2
PC27
PC36
PR193
44.2K/F_6
PR197
0_4
PR81
PC46 LGATE_NB
2
5
1 0 1.0 0.01U/50VB_4 PR198
33P/10VB_4
PC141
*short 12.1K/F_4 PHASE_NB
2
6265AGND
1 1 0.8 4
+5VPCU PR96 UGATE_NB PQ43
1
0_4
2
6265AGND PC136
0.1U/50VB_6
SI7686DP
36A
+3VPCU
49
48
47
46
45
44
43
42
41
40
39
38
37
PR82 PU3
3
2
1
+3VPCU *0_4 PL8 +VCORE0
FB_NB
COMP_NB
FSET_NB
VSEN_NB
RTN_NB
OCSET_NB
PGND_NB
LGATE_NB
PHASE_NB
UGATE_NB
GND
VIN
VCC
1 2 PR196 0.36uH/25A_11
PR83 6265AGND 1_6
10K_4 PR95 1 2
PR84 1 OFS/VFIXEN BOOT_NB 36 BOOT_NB
3 4
5
PR73 PC42
330U/2V_ESR9_7
2 0_4 *10K_4 2
1
330U/2V_ESR9_7
16 VRM_PWRGD 1 2 2 PGOOD BOOT_0 35 BOOT_0 PR207
*2.2_8
PC85
PC84
PR69 *0_4 1_6 0.22U/25VB_6 4
3 CPU_PWRGD_SVID_REG 1 2 3 34 UGATE_0
2
PWROK UGATE_0
*100P/50VA_6
PC158
35 CPU_SVID PR66 0_4
3 CPU_SVD 1 2 4 33 PHASE_0
SVD PHASE_0
SI-2 for fix cpu vcore PR60 0_4 ISP_0
3
2
1
3 CPU_SVC 1 2 5 32 PQ46
SVC PGND_0 SI7636DP ISN_0
PR226 PR55 0_4
1 2 6 31 LGATE_0 +5VPCU +VIN
35,39 VRON ENABLE LGATE_0
6265AGND
PC135
PC30
PR194 180P/50VA_4 Pin 49 is GND Pin
7 RBIAS PVCC 30 2 1
10K_4
2200P/50VB_4
0.1U/50VB_6
10U/25VD/1206
10U/25VD/1206
22K/F_4 PR195
ISL6265HRTZ-T 4.7U/6.3VC_6
1
PC132
PC133
PC29
PC22
PR44 100K/F_4 8 29 LGATE_1
OCSET LGATE_1
5
255/F_4
PC28
2
4700P/25VB_4 9 28
VDIFF_0 PGND_1
PR46
4 36A
1K/F_4 10 27 PHASE_1
FB_0 PHASE_1 +VCORE1
PR17 PC8 PQ44
11 26 UGATE_1 SI7686DP
COMP_0 UGATE_1 PL9
3
2
1
54.9K/F_4 1200P/50VB_6 PR40 PR37 PC20 0.36uH/25A_11 PC86 PC87
12 VW_0 BOOT_1 25 1 2
COMP_1
VDIFF_1
VSEN_0
VSEN_1
PC18 6.81K/F_4 1_6 0.22U/25VB_6 3 4
RTN_0
RTN_1
5
ISN_0
ISN_1
VW_1
ISP_0
ISP_1
180P/50VA_4
FB_1
1
330U/2V_ESR9_7
330U/2V_ESR9_7
PR205
PC17 4 *2.2_8
13
14
15
16
17
18
19
20
21
22
23
24
3 3
1000P/50VB_4
2
*100P/50VA_6
PR25
Close to
PC146
ISP_0
CPU
3
2
1
16.2K/F_4 PQ47
2
socket SI7636DP
1
1
PR29
PR28
1000P/50VB_4
PR6 PR24 PC9
4.02K/F_4 0.1U/50VB_6
+VCORE0
1
2
10_4 ISN_0 PC11 PC13 PR10
0.1U/50VB_6 4.02K/F_4
2
1
0_4 0_4
3 CPU_VDD0_RUN_FB_H ISP_1
PR26
6.81K/F_4
PR23
3 CPU_VDD0_RUN_FB_L PR9
1
16.2K/F_4 ISN_1
+VCORE0 +VCORE1
PR5 Parallel 0_4
PR209
2 1
2
10_4 PR189 2 1
+1.8VSUS *0.001_2512
Close to *1K/F_4
1
Reserve for uni-plane

1200P/50VB_6
CPU socket
PC5
PR4 PR27
0_4
Reserve for uni-plane
4700P/25VB_4
10_4
2
PC6
180P/50VA_4
1K/F_4
PR33
3 CPU_VDD1_RUN_FB_L
PC1
3 CPU_VDD1_RUN_FB_H +VCORE0 5
4 4
+VCORE1 5
54.9K/F_4
PR3
PR2
PR16
+VCORE1
255/F_4 +CPUVDDNB5
10_4
PROJECT : QT8
C 1A
NB5/RD5
CPU_CORE(ISL6265)
A B C D E F G H
A B C D E
41
+2.5V 3
+1.8VSUS 3,4,5,6,7,40,42,43
+VIN
4 4
*100U/25V_6.3X7.7
*100U/25V_6.3X7.7
*10U/25VD_1206
10U/25VD_1206
1
PC47
PC48
I_lim(Valley)=10uA*R_ILIM/RDS_ON
PC159
PC164
+ +
+5VPCU
PR39
For OCP set.
2
51116_V5FILT
2
10_6
PC25 PC16
0.1U/50VB_6
2200P/50VB_4
2.2U/6.3VC_6 1U/10VC_4
+1.8VSUS
1
+3VSUS
PC34
PC33
15
14
PU2
5
23.65A Ra=(Vout-0.75)/0.75*Rb PC39
PR71
PR48
V5IN
V5FILT
BST 22 16 CS PR31
VBST CS 10K_4
4
S0~S3 0.1U/50VB_6 0_6 8.45K/F_6
Rb value from 100K to 300K ohm PQ39
PGOOD 13 HWPG 20,23,35,38,39,42
AOL1426
1.8V_DH 21 DRVH
+1.8VSUS 11 S5ON PR18
SUSON 35,43
1
2
3
PL6 S5 0_4
+1.8VSUS_J 1.8V_LX 20 10 S3ON PR19
LL TI51116 S3 0_4
1
*100P/50VA_4
1.5uH/10A_10 23 +1.8VSUS
VLDOIN
0.1U/10VC_4
*100P/50VA_4
+
PC7
3 PC143 3
PC153
PC14
4 1.8_DL 19 PC40
2
DRVL 1U/10VC_4
2
Ra PQ48 1
AOL1412 VTTGND
390U/2.5V_6X5.8ESR10 PR21 PR22 4
147/F_4 0_4 1.8V_OUT MODE PC41 PC38 +0.9VSMVTT
8
+0.9VSMVT
1
2
3
PC10 VDDQSNS 10U/4VD_8 10U/4VD_8
*100P/50VA_4 9 24
VDDQSET VTT +0.9VSMVTT 4,7
COMP 6
VTTSNS 2 VTTSNS PR56
0_4
2.25A
COMP
Fix 1.8V Output 18
S0~S3
CS_GND
PGND
VTTREF
PR36 7 PR57 CPU_VTT_SENSE 4
51116_V5FILT NC *0_4
12 25
GND
PR41 NC PAD
*0_4 0_4 PR47
MODE +1.8VSUS
17
3
51116_V5FILT
PR30 0_4
Rb *0_4
PR43
VDDIO_FB_H 3 EC:1108 SI
PR20 0_6
100K/F_4 PR15 Differential Pair
*0_4
4,6 +0.9VSMVREF
VDDIO_FB_L 3 Mode Discharge Mode
PC35
0.033U/25VB_6
2 V5IN No discharge 2
VDDQ Tracking discharge

+2.5V
0.25A +1.8VSUS
Gnd Non-tracking discharge
Close to CPU For EMI-SI
SI power S0~S1
PC196
5
6
7
PU9 8 0.1U/10VC_4
V_TRIP(mV)=R_TRIP(Kohm)*10(uA)
PR167 +2.5V
10K_4
PQ27
35 VR2.5_ON 1 SHDN VOUT 4 43 1.8V_OND 4
SI4856
I_OCP=V_trip/Rds_on+I_Ripple/2
+1.8V
PC112
+3VPCU 3 VIN R1 PR166
+
PC111 10.4A VDDQSET VDDQ(V) VTTREF and Vtt Note
0.1U/10VC_4 100K/F_4 4.7U/6.3VC_6
1
2 5SET
S0~S1
3
2
1
PC113 GND SET

1U/10VC_4 +1.8V GND 2.5 V_ vddqsns/2 DDR
2
G913C Vout=1.25(1+R1/R2)
PR165
+1.8V 3,5,8,10,11,12,15,16,18,19,20,21,22,26,43 V5IN 1.8 V _vddqsns/2 DDR2
R2 100K/F_4 For EMI-SI PC197
0.1U/10VC_4
FB adjustable V_VDDQSNS/2 1.5V<VDDQ<3V
1 1
Discrete:SI4856 PROJECT : QT8

UMA:SI4800 Quanta Computer Inc.
Custom 1A
1.8VSUS/DDR_VTER/+1.8V/2.5V
NB5/RD5
A B C D E
5 4 3 2 1
ATI M82-SE
PWRCNTL1 PWRCNTL0 V-CORE
+VGA_CORE5,18,20
+1.2V_S5 15
+1.5V 33,36
42
H 0 0 1.1V
+5VPCU +VIN
D M 0 1 1.0V PR91
20_6 D
CH501H-40PT L-F
2
2
1 0 1.0V
10U/25VD_1206
*10U/25VD_1206
M
8118VDDA
PD9
2200P/50VB_4
0.1U/50VB_6
PR105 PC55 PC83
+VGA_CORE
PC154
PC155
PC89
PC88
1K_4 1U/10VC_4 1U/10VC_4
5
6
7
8
+5VPCU
L 1 1 0.9V 9.4A
1
8118AGND PR121
16
5
PC65 0_6 4
S0~S1
8118AGND
PR117 8118VIN 2 8 8118BST
VDDA
VDDP
10K_4 VIN BST
0.01U/50VB_4
HDR 9 8118HDR DCR=8.1m-ohm (max)
PD10 PQ52
PR125 8118PG 4 SI4800BDY PL11 +VGA_CORE
20,23,35,38,39,41 HWPG PGD
0_4 PC72
3
2
1
SW1010CPT 0.1U/50VB_6 +VGA_CORE 5,18,20
43 VCORE_PG
5
6
7
8
PR118 10 8118LX 1.5UH/16A_PCMC104T-1R5MN
LX
1
8118EN 3
20,27,35,39,43,44 MAINON ON/SKIP PU6 PR206 PR103 +
*100P/50VA_4
15K_4 7 8118LDR 4 *2.2_6 191K/F_4 PR99 PC172 PC166

8118VSET 13 LDR 51.1/F_4 0.1U/10VC_4 390U/2.5V_ESR10_6X5.8
OZ8119
2
VSET
PC75
*100P/50VA_6
PR119
10K_4 +8118VREF 14 PQ55
VREF
PC151
FDS6690AS PR104 PC60
11 8118CSP
CSP
8118TSET 15 SI-1 Modified -ECAP6_3X6_1-7_2-QT8
3
2
1
PR74 PR79 TSET 11K/F_4 33N/10VB_4
C C
162K/F_6 63.4K/F_4
GNDA1
GNDP
8118AGND
OCT
12 8118CSN
CSN
1000P/50VB_4
3
0.1U/50VB_6
PR65 PR89
17
6
PC54
PC56
PR116 665K/F_6 *49.9K/F_4
1000P/50VB_4
1000P/50VB_4
22P/50VA_4
0_4
0.022U/25VB_6
PC49
PC63
18 GFX_CORE_CNTRL0 2 PR75 PR78
PC57
110K/F_6 130K/F_6
PC53
PQ10
2N7002E-G PR70
665K/F_6
1
PR98
0_4
18 GFX_CORE_CNTRL1 2 PR76
8118AGND
PQ8
2N7002E-G *short
8118AGND
1
+1.8VSUS
+1.5V
PC114 PC115 PU10
B
10U/4VD_8 0.1U/10VC_4 5 VIN POK 7 2.0A B
9 VIN1 GND 1 S0~S1

PR220 PR174 +1.5V
10K_4
S5EN_G966
+1.2V_S5 +5V
10K_4
5913EN 8
APL5913
3
35,43 S5_ON
+5V EN VOUT +1.5V 33,36
0.5A
6 VCNTL VOUT 4
PC186 PC116 PC119 PC121
FB
*0.1U/10VC_4 S0~S5 0.1U/10VC_4
PR176
0.1U/10VC_4 10U/4VD_8
PU12 PC117 R1
2
+3VPCU 1 8 +1.2V_S5 0.1U/10VC_4 5913FB
POK GND
2 VEN ADJ 7
3 6 +1.2V_S5 15 41.2K/F_6
VIN VO
4 VPP NC 5
+5VPCU
9
R1 Sequence control ?? PR172 R2 PC118

966ADJ
G966 47K/F_4 1 2
9
PC188 PC187 PR218 PC183 PC184

10U/4VD_8 0.1U/10VC_4 51.1K/F_6 10U/4VD_8 0.1U/10VC_4 56P/50VA_6
PC185
0.1U/10VC_4 Vo=0.8(1+R1/R2)
R2
PR219
100K/F_4 Vo=0.8(R1+R2)/R2
A A
R2<120Kohm
PROJECT : QT8
Custom 1A
VGA PWR OZ8118/1.2V_S5/+1.5
NB5/RD5
5 4 3 2 1
1 2 3 4 5
PR109
*10K_4
SI-1 Modified - can remove +1.35V for AMD update
PC66
0.5A +12VALW
43
+5V +3V +1.1V
20,27,35,39,42,44 MAINON
*0.1U/10VC_4 S0-S1
+VIN PR180
PU5 1M_4
+1.8VSUS 1 8 +1.35V PR178 PR182 PR175
A POK GND *22_8 *22_8 *22_8 A
2 VEN ADJ 7
3 6 PR179
VIN VO MAIND 38
4 VPP NC 5
+5VPCU
9
R1 1M_4 PQ31
1
PC58 *G966 *2N7002E-G PQ33 PQ29
9
PC67 *0.1U/10VC_4 PC68 PC73 *2N7002E-G *2N7002E-G PC122
*10U/4VD_8 PR106 *10U/4VD_8 *0.1U/10VC_4 *2200P/50VB_4
2
*69.8K/F_6 MAINON_G 2 2 2 2
PC51
*0.1U/10VC_4 PQ32
3
R2 2N7002E-G
PR113
1
*100K/F_4 2 PR181
20,27,35,39,42,44 MAINON
Vo=0.8(R1+R2)/R2 1M_4
R2<120Kohm PQ30
1
PDTC144EU
+3VSUS +5VSUS +12VALW
+12VALW
+3VLANVCC
PR88 PR114
+VIN PR188 *22_8 1M_4
*22_8 PR111
+VIN 1M_4
PR129
B SUSD *22_8 B
SUSD 38
PR90 LAN_ON
LAN_ON 38
3
3
1M_4 PQ3 PQ7 PR124
1
*2N7002E-G *2N7002E-G 1M_4
1
PC74 PQ12
SUSON_G 2 2 2 *2200P/50VB_4 *2N7002E-G PC70
2
*2200P/50VB_4
2
PQ9 2 2
2N7002E-G
3
3
PR87 PQ13
1
1
1M_4 2N7002E-G
2 35 LAN_POWER 2
1
35,41 SUSON PR123
1M_4
PQ4 PQ14
1
1
PDTC144EU PDTC144EU LAN_POWER_G
For Discrete Only

C C
+12VALW +1.8V
+3VS5
+VIN
PR184 PR173 +12VALW
1M_4 *22_8
+VIN
PR185
3
*22_8 S5_OND PR171
S5_OND 38
1M_4 PR177
PR186 PQ37 PR170 1M_4
3
1M_4 *2N7002E-G *0_4 2

PC123
*2200P/50VB_4 20,27,35,39,42,44 MAINON PQ26
1.8V_OND 41
2
3
2 2 *2N7002E-G
1
PR168
3
2 1M_4 PC120
42 VCORE_PG
3
PQ36 *2200P/50VB_4
2
PR187 PR169
1
2 1M_4 2N7002E-G 0_4 PQ25 2

35,42 S5_ON
1
PDTC144EU
PQ28
PQ38 S5_ONG 2N7002E-G
1
PDTC144EU
1
D D
PROJECT : QT8
Custom 1A
DISCHARGE
NB5/RD5
1 2 3 4 5
5 4 3 2 1
TOP DC_JACK
65W/90W 37
PL3
+DOCK_VA
+VA
PD8
S10P40CPT/40V/10A
2
1
3
+VAD
PQ45
IRFR3707ZCTRPBF
+VAD
PC198
0.1U/50VB_6
+VAD
PC199
0.1U/50VB_6
EC:SI2 PQ6 +BATCHG
PL1
HI0805R800R-00/5A_8
PL2
44
AD_ID 35 +PRWSRC
HI0805R800R_5A/08 PD20 EC:11/05_SI For VAD noise FDS6679AZ HI0805R800R-00/5A_8 CN23
2 1 8 +BATT 7 8
CN3 7 8
3 4 3 2 7
J1-1 1 3 6 SMD 6 10
3 5 PL4 6 10
4 6 4 5
HI0805R800R_5A/08 S10P40CPT/40V/10A EC:11/05_SI +VIN PR203 SMC 5 9
1
PR190 PR61 100K/F_4 5 9
D D
PC124 PC156 100_4 PC138 RC7520WT-R020 4 2
BATDIS_G
9 2 0.1U/50VB_6 0.1U/50VB_6 ACOK_IN 1U/25VC_8 4 2
10 1 1 2 MBATV
+3VPCU 3 1
DC-IN CONN PR192 3 1
+BATCHG
+VH28 100K/F_4 BATDIS_G PR202 11
PC145 14K/F_4 11
CSIN_1
CSIP_1
PR12 0.01U/50VB_4 12
JACK-LED 0_6 J1-1 +6251_VDD PR35 PR34 PR14 12
PD19 330_4 330_4 10K/F_4
3
PR11 PD4 *SW1010CPT BP07061-BA015

10K_6 PD6 SW1010CPT PC129 PC130 PC31 PC24
2 1 PC200 1000P/50V_4 TEMP_MBAT 35
5,35 3920_RST#
2
ACOK# 2 PQ18 34,35 MBDATA
2N7002E-G *UDZS5.6BTE-17 PC77
10U/25VD_1206
*10U/25VD_1206
PR59 PR107 2.2U/6.3VC_6 PC12
5,38 SYS_SHDN#
1
SI-2 modified -- EMI *100K/F_4 20_4
34,35 MBCLK
0.01U/50VB_4
2200P/50VB_4
0.1U/50VB_6
PR102 +6251_VDD +6251_VDD
1
1
2_6
1
2 PR67
+VAD2 CSIP CSIN 4.7_6
VREF = 5.075V
PD15 PC61 PD3 PD2
*UDZS5.6BTE-17 6251_ACIN PQ2 PR201 UDZS5.6BTE-17 UDZS5.6BTE-17
PR140 2N7002E-G +6251_VDDP
2
470_4 PTC
+VH28 1 2
3
2
PR136 0.1U/50VB_6 PC43 PD7
5
6
7
8
*200K_4 *200K_4 PQ19 Close to AC soft start MOSFET CH501H-40PT L-F
19
20
15
1
1
*2N7002E-G
1
PR135 2 +VAD 4.7U/6.3VC_6
CSIP
VDDP
CSIN
VDD
+VAD2 2 PR110 20_4 4
1
3
C CSOP_1 CSOP PR86 PC52 PQ40 C

3 21 CSOP
2
1
*0_4 PQ11 16 6251_BOOT SI4800BDY
BOOT
2
PQ20 PR141 IMD2 PC69
3
*2SB1197K 2 *200K_4 1_6 0.1U/50VB_6

0.047U/25VB_4 17 6251_UGATE
1
CSON_1 CSON UGATE PR199 +VAD2
22
3
2
1
CSON PL5 RL3720WT-R020
PR146 PQ21 PR115 20_4 ACOK# 23 18 6251_PHASE 2 1 +VAD2
1
*680K/F_6 *2N7002E-G ACPRN PHASE
5
6
7
8
10UH/4.4A_10
2P
1P
10U/25VD/1206
10U/25VD/1206
PR126 +DCIN 24 14 6251_LGATE PR145 PD16
DCIN LGATE
PC148
PC147
10_6 PR191 *10K_4
ISL6251A 4 *2.2_8 1
PC80 PC99
20,27,35,39,42,43 MAINON PGND 13
+DOCK_VA +VA 1U/25VC_8 +6251_VREF 3 *CHN217PT
EC:11/05_SI
12 CSOP_1
GND
2
PD13 PC125 2
4
SW1010CPT PD11 *0.01U/50VB_4
*100P/50VA_4
2 1 +VAD2 PR122 100K/F_4 11 PR72 PR63 CSON_1 +VH28
3
2
1
6251_ACIN VADJ 7.5K/F_4 *100K/F_4
2 ACSET PQ49 PQ22
1
2 1 SW1010CPT Setting the Vin PC78 10 6251_VADJ SI4800BDY *IMZ2
min to 11.42V 6251_EN 3 ACLIM
EN
0.1U/10VC_4
PD12 PR131 PR128 For ACSET PR130 6251_ACLIM VADJ =
VCOMP
ICOMP
CELLS
3
CHLIM
2
VRFE
CH501H-40PT L-F 75K/F_4 1.26V VERF >> 4.2V +5%
100K/F_4
ICM
12.4K/F_4 Float >> 4.2V PR142
Setting the Vin min to 15.88V PR62 GND >> 4.2 -5% *100K_4 PC95
For EN = 1.06V PR68 *100K/F_4 PR138 *0.1U/50VB_6
9
35 AD_AIR PU4 10K/F_4 *47K_4
1
V ACLIM = VREF *
+6251_VREF
VREF = 2.39V
6251_CHLIM (Rhi // 152K) / (Rhi // 152K + Rlow// 152K)
6251_VCOMP1
6251_ICM
B 6251_CELLS Input curretn = 2.9A (71.5K , 10K) PR144 B
PR132 PR120 PR77 100K_4 (0.05/Vref * Vaclim + 0.05 ) / Rsense
PC82 12.4K/F_4 7.15K/F_6 CC-SET 35
0.1U/10VC_4 6251_ICOMP *47K_4
PR85 Charging Curret setting =
2
PC50 I chg = 165mV / Rsense * (Vchlim / 3.3V)

PR112 PC64 100P/50VA_4 100K_4
0_4 6800P/25VB_4 +VAD2
1
Input Current monitor ADP TYPE PR72 Value P/N PC91

ACOK 3 1 +6251_VDD V icm = 19.9 * (Vcsip - Vcsin) *0.1U/50VB_6
PC62 PR97
100P/50VA_4 SYS_I 35 65W 102K/F CS41022FB19
PR133 PQ15 ONLY for 3S battery pack
10K_4 PDTA124EU 90W 7.5K/F CS27502FB11
PR108 100_4
2
10K_4
5
PC59
35 ACIN 3300P/25VB_4 + 3
2
ACOK# EC:11/05_SI 4
PR134 PC71 - 1
15K_4 0.01U/50VB_4 PU7
1
+VAD2 PR227 PU13 +VH28 PR139 *TL331
2
6251_ACIN PR137 22_6 PR143
BATDIS_G 1 8 *22K_4 *10K_4
VIN Vout
3
1
*100_4 ACOK_IN PR42 2
*0_4 PC190 GND 6251_ACIN PC191
PC81
P2805 PG 6
PD14 .1U/50V_6 4 .1U/50V_6
2
NC PC92
2 2
CP
3 CN D_CAP 5
1
*220P/50VB_4
A A
1
PQ16 *1U/25VC_8 PQ17 PD5
*CH501H-40PT L-F
7
*2N7002E-G PR127 *2N7002E-G 2 PC192
D/C# 35
1
PQ1 1U/50V_6
2
*1M_4 *PDTC144EU 2 1
2
*CH501H-40PT L-F
1
PC193
PC21
*10U/10VD_8
0.01U/50V_6
PROJECT : QT8
Custom 1A
CHARGER ( ISL6251)
NB5/RD5
5 4 3 2 1
5 4 3 2 1
CPU Power 1
CPU Power 2
EC Pin98
SUSON HWPG VRM_PWRGD
+VCORE0
+1.8VSUS
D D
EC Pin99
EC Pin34 MAINON
+VCORE1
VDDA_EN
+0.9VSMVTT
+CPUVDDNB
+2.5V
HWPG
+1.2V
EC Pin101
HWPG
C S5_ON S5_OND +1.1V C
Delay +3VS5
EC Pin101 VCORE_PG
S5_ON
+1.2VS5 +VGACORE
HWPG
+5VSUS EC Pin99
MAINON
EC Pin98 Option 1.8V_OND

Delay +1.8V
SUSON SUSD
Delay +3VSUS VCORE_PG
B B
+5V
+5V
+1.5V
EC Pin99
MAINON MAIND
Delay +3V
1 2 3 4 EC Pin76
A A
S5_ON SUSON MAINON HWPG ECPWROK SB_PWRGD_IN NB_PWRGD_IN
S5_OND SUSD MAIND VCORE_PG Delay 600ms 3.3V 1.8V
RSMRST# VRM_PWRGD
PROJECT : QT8
Custom 1A
Power control
NB5/RD5
5 4 3 2 1

HP Pavilion DV5 - AMD (QT8)

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HP Pavilion DV5 - AMD (QT8)

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1 2 3 4 5 6 7 8

Headphone Jack (10/100/GagaLAN)

SMBUS TABLE Capacitive Sense PAGE 35

to NB for VGA reference clock 02

CLK_VGA_27M_SS R653,R656,R612 R653,R656,R612 To M82-S 27Mhz - RX780 only

6 GNDDOT SRC4C_LPRS 9 SBSRC_CLKN 2 1 SBSRC_CLKN

100 MHz non-spreading differential SRC clock

SEL_27 1* 27MHz non-spreading singled clock PROJECT : QT8

BLM21PG221SN1D(220,100M,2A)_8 CPU_THERMDC R569 0_4

+1.8VSUS R59 10K/F_4

+1.8VSUS R62 300_4 Q11 CPUTEST20 R798 *300/F_4

+1.8VSUS R453 10K/F_4 CPU_DBREQ# 7 8

+1.8VSUS R452 300_4 Q10 CPU_TMS 13 14

Q35 MMBT3904 CPU_TDI 15 16

PLACE THEM CLOSE TO

MEM_MB_DM2 MB_DM1 MA_DM1 MEM_MA_DM2

6 MEM_MB_DQS0_P C12 MB_DQS_H0 MA_DQS_H0 G13 MEM_MA_DQS0_P 6

+VCORE0 U31E +VCORE1

F25 VSS60 VSS125 V17

R572 +1.8VSUS EC10 0.01U/16V_4 +3VPCU C69 0.01U/16V_4

200/F_6 Update U36 P/N R170 *0_4 SYS_SHDN# C71 0.01U/16V_4

R805 *10K/F_4 +3VS5 +3VS5 +3V +1.8V

+1.8VSUS R806 *300_4 PQ60 2 TEMP_FAIL 18 Quanta Computer Inc.

Q71 EC13 EC14 EC11 EC12

*0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 *0.1U/10V_4 NB5/RD5

192 MEM_MA_DATA58 192 MEM_MB_DATA62

DDR SO-DIMM SOCKET 1.8V

DDR SO-DIMM SOCKET 1.8V

MEM_MA_CKE0 RP40 4 3 47_4P2R_4 MEM_MB_CKE0 RP36 4 3 47_4P2R_4

PLACE CLOSE TO PROCESSOR PLACE CLOSE TO PROCESSOR

+3VS5 SI-2 modified --SB internal pull HI to 3vs5

Close DDR2 socket

7 8 C706 0.1U/10V_4 Q32

A R422 10K/F_4 MEMHOT_SODIMM# A

HYPER TRANSPORT CPU I/F

Quanta Computer Inc.

*HYB18T512161B2F-25 Size Document Number Rev

Close to North Bridge

PCIE I/F GFX

PCIE_RXP0 AE3 AC1 PCIE_TXP0_C C158 0.1U/10V_4

selects Loading of straps from RS780_AUX_CAL C8 R541

STRP_DATA R548 10K/F_4 +VDDG_NB BLM18PG181SN1D(180,1.5A)_6 BSS138_NL/SOT23 4.7K_4

C358 1 3 NB_LDT_STOP# L84

0 : Disable RX780 2.2U/6.3V_6 BSS138_NL/SOT23

Reserved only 3 CPU_LDT_REQ#

VDDHTRX +1.1V +1.1V AVDD NC +3.3V

VDDA18PCIE +1.8V +1.8V AVDDQ NC +1.8V

VDDG18 +1.8V +1.8V PLLVDD NC +1.1V

VDDC +1.1V +1.1V VDDA18HTPLL +1.8V +1.8V

VDDG33 NC +3.3V VDDLT18 NC +1.8V

IOPLLVDD18 NC +1.8V VDDLT33 NC NC

I/O for 0.6A L72 +1.1V_VDDHT +1.1V_VDD_PCIE

PCI EXPRESS INTERFACE

C900 C899 GPP_CLK3N GNT2# PE_GPIO1

X1 LAD0 LAD0 35,36

RTC_X2 LAD3 LFRAME#

SB700 *SHORT_ PAD1 C902

ACPI / WAKE UP EVENTS

ACZ_SDOUT R644 33_4 ACZ_SYNC AZ_SDIN3/GPIO46 IMC_GPIO18

ACZ_SDOUT R645 33_4 IMC_GPIO7 +3V

SATA PORT 0,1,2,3

C559 0.01U/16V_4 SATA_TXP0_C AD9

C517 VIN5/GPIO58 BOARD_ID3

ID4 ID3 ID2 ID1 ID0

0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 NB5/RD5

10K/F_4 10K/F_4 10K/F_4 10K/F_4 10K/F_4

C_PEG_TX#12 C827 0.1U/10V_4 TXC_HDMI-L TXC_HDMI-L 3 4 0_4P2R_4 TXC_HDMI-

XTLI D3V3_ IN 0.1U/10V_4 0.1U/10V_4 *4.7U/6.3V_6 MDID3 SD_DAT3 XD_D3 MS_D3