DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF AKRON,OHIO, USA.

NOVEMBER 29 2010

Design and Simulation of Semi-Controlled Single

Phase Full Bridge Rectifier
Krishna Ram Budhathoki
Department of ECE, UA

Abstract—this paper is dealing with the single phase semi
controlled full wave rectifiers operating at the fourth quadrant. It
deals with finding the optimum value of series inductance to limit
the peak-to-peak ripple at the output voltage to 10% of its
average. It is shown next that a parallel capacitor can be added to
the load resistor to minimize the size of series inductance for
maintain the output voltage ripple to 10% of its average. In both
of these cases, only the fundamental components of the ripple are
considered. The next part of the paper consists of the control
circuit design for firing the thyristor at the specified angle.. The
delay angle alpha is calculated by varying the resistor(R) and
capacitor(C) values of 555 timer operated at the mono stable
mode and triggered by the pulse generated at the zero crossing of
the input voltage.
Index Terms—rectifier, zero crossing detection, firing angle,
Total harmonic distortion, Power Factor.
average. Using Parametric Sweep in the PSPICE, the values of
L and C could be found for the 10 percent ripple in the output
voltage of the rectifier. The values of L and C could also be
found out using the Fourier series expansion of the average
output voltage of the full wave rectifiers [4].The design of
control circuit could be done like Pulse Width Modulation
(PWM). In this paper, the different approach of control circuit
design is shown using 555 timer and OPAMPS.
IV. CONVETER OPERATION AND DESIGN
The basic full wave rectifier circuit to be implemented is
shown in Fig 1.

I. INTRODUCTION

The semi-controlled rectifier’s circuit is different to that of

full controlled rectifier circuit in the sense that it contains both
the diodes and thyristors as the uncontrolled and controlled
elements. Due to the presence of diodes in the semi-controlled
rectifiers, freewheeling operation takes place restricting the
rectifier operation to only one quadrant [3].
II. APPLICATION
The primary purpose of the rectifier circuit is to produce
dc power from the ac supply. Therefore, it finds users in
almost all the electronic equipments. Using the Semi-
controlled rectifiers, the variable dc output is produced from
the constant ac source [1]. The output voltage is varied by
controlling the delay (or firing angle) of the thyristor. A phase-
controlled thyristor is turned on by applying a short pulse to its
gate and turned off due to natural or line commutation; and in
case of highly inductive load, it is turned off by firing another
thyristor of the rectifier during its negative half cycle [2]. It is
also used for detecting the amplitude-modulated wave.
Controlled rectifiers are used in the generation of polarized
voltage for welding.
Fig 1: Basic Circuit Diagram for the full wave rectifier
The rectifier circuit consists of two diodes in the upper half
and two thyristors in the lower half. The circuit is operated by
the 120V(rms), 60Hz supply. The firing of thyristors T1 and
T1 are controlled by the control circuit. The load is of 10Ω
resistor and the output at the load is filtered by the second
order LC filter so as to limit the output peak-peak ripple in V o
( voltage across resistor) to approximately 10% of
<V0>(average value of Vo).
i. Positive half cycle (0 ≤ wt ≤ π ¿
Diode D2 and thyristor T1 are forward biased while D1 and
T2 are reversed biased. So when T1 is fired at an angle α,
negative voltage waveform would be found at load R.

ii. During negative half cycle( π ≤wt ≤ 2 π ¿

III. LITERATURE REVIEW
Diode D1 and thyristor T2 would be forward biased and T1
Different techniques can be used to find the L and C values for and D2 would be reversed biased. Since T2 would not conduct
the rectifier to limit the output voltage ripple to 10 % of its before α, the current at the inductor is freewheeled by D2 and
T1. So when T2 is fired at an angle α, current starts building
through already forward biased D1 and T2. Output at the B. Design of second order filter
resistor would be negative for this cycle also. The inductor in
the output would filter ripples in the output current while the
Second order filter was designed with L and C in the hope to
capacitor would filter ripples in the output voltage.
reduce the size of L in order to limit the output voltage ripple
A. Design of Inductive Filter to 10% of the average.

Design of inductive filter was made for α=0, C=0 and Since the average voltage across the inductor in the steady
R=10Ω .The value of series inductance is to be calculated for state is zero, the average output voltage for continuous
the peak to peak ripple to be 10% of the average output
inductor current from eqn (1.2) is,
voltage (v0).
2Vm
Vo 
For the full wave rectifier, sinusoidal voltage across the load 
can be expressed as a Fourier series consisting of a dc term
Average inductor current must equal the average resistor
and the even harmonics [6].
current because the average capacitor current is zero.
 Vo 2Vm
IL  IR  
vo  t  Vo  V
n  2,4..
n cos(not   ) (1.1) R R
(1.4)

where, Considering the second harmonics,

2vm 2Vm  1 1 
V2    72.052Volt
Vo 

(1.2)
  1 3 
2V  1 1  Assuming the capacitor is short circuited to ac terms, the
Vn  m   (1.3)
  n  1 n  1 
harmonics voltage V2 exists across the inductor.
If V02 be the output voltage at load R for the second harmonic,
then using voltage division rule,
For the given supply voltage, average output voltageV 0 is
given by  1 
 R  j 2wc 
2vm 2 2  120  
Vo    108.037volt V02  72.052  (1.5)
   1 
V  R  j 2 wc  j 2 wL 
I o  0  10.80amp  
Average current , R
For n=2 and 4 , from eqn (1.3) Since average voltage across the inductor is zero, the average
2vm  1 1  voltage across the resistor is,
V2    72.025volt
  1 3  VoR 
2Vm
 108.03volt

2vm  1 1 
V4    14.405volt For the peak to peak ripple at the load to be 10% of its average
  3 5  value,
For output voltage ripple to be within 10% of Vo 10
∆ V =10 % of V o=10.8037Volt VR   VoR  10.80volt
100 and
∆V
∆ i= =1.08 Amp
R VR
The current amplitude at each frequency is calculated by io   1.08amp
R
Vn Vn V2
In    (1.4) And the current in resistor due to the second harmonic voltage
Z n R  jnwL  10  j 2  377  L  is,
2V2 144.05
io  2 I 2    1.08 V02
10  j 2  377 L 10  j 2  377 L I 02  (1.6)
R
which gives L=0.176H
But,
 2V02
io  2 I 02   1.08amp
R
Putting R=10Ω ,
V02  5.4volt
Vi in equation (1), and choosing
Putting the value of
L  110mH arbitrarily and solving for C , we get
C  150  F
V. CONTROL CIRCUIT DESIGN
The design of the control circuit is the most important part of
the project. The control circuit should be such that it is
possible to send the control signal for firing the thyristor at the
specified firing angle (α). We can design the control circuit
from different ways. The goal of all the circuit should be to
produce the periodic pulse at the specified angle taking input
signal as the reference.
The control circuit that is used here uses the 555 timer to
calculate the delay angle (α) for firing the thyristor. 555 timer
would produce a pulse at certain delay at each zero crossing of
the input signal.
A. Block Diagram of Control circuit
The general block diagram of control circuit is shown if Fig 2.
Fig 2: Block diagram of the control circuit
1. Reference Signal
The reference signal is the same input supply voltage of 120V
(rms), 60Hz.
2. Zero crossing detection
The zero crossing detectors consists of two parts. The first is
step down transformer and the second is the comparator.
Transformer is used for down converting the 170 Peak-Peak
ac voltage to about 17 peak-peak voltage. The conversion is
chosen in by selecting the values of L1 and L2 according to
equation (2.1)[5].
L1  N1 
   (2.1)
L2  N2 
Where L1,N1 and L2,N2 are the inductance and turns of the
primary and secondary respectively.
For the transformer with V1 as input and V2 as output,
N1 V 1
 (2.2)
N2 V 2
So, transformer is designed with L1=240H and L2=20H to
keep the output voltage to nearly 17 peak to peak.
For the zero crossing detection, two separate circuits are
designed for the positive edge and negative edge zero crossing
of the input voltage waveform.
i. Positive edge zero crossing detection.
The positive edge zero crossing detection of the input voltage
waveform is shown in Fig 3.
Fig 3: Circuit diagrams for the positive edge zero crossing detection of the
input voltage waveform.
The transformer input voltage is the supply voltage which is
170 volt peak to peak at 60 Hz. The transformer inductances
L1 and L2 are chosen as 260 and 2 henry respectively in
order to get 17 volt peak to peak at the secondary.
For the simulation of transformer, XFRM_LINEAR of the
Analog Library, in pspice is used. The coupling factor K is
chosen to be 1 .Since the secondary circuit needs a DC
connection to ground, it is done by adding a large resistor of
100MΩ.
The ua741OPAMP is used as a comparator. The output
voltage of the transformer is directly fed to the Opamp ua741
which is biased to +5volt at +Vcc and and 0Volt to –Vcc,
produces the output pulses as shown in Fig 4.
Fig 4: Positive edge, zero crossing detection of the input voltage waveform
(out1)
As shown in Fig 4, the pulse generated by the opamp starts at
the positive edge zero crossing point of the input voltage
wave. These pulses are later used for the firing of first
Thyrisotr(T1), which becomes forward biased during the
positive half cycle of the input voltage wave.
ii. Negative edge zero crossing detection of the
input voltage waveform
For the zero crossing detection of the input voltage wave
while going from negative value to positive value (i.e for the
negative edge zero crossing detection), the signal from the
transformer is inverted using the an opamp as an inverter
whose gain is adjusted to 1 by keeping the values of R1 and Rf
equal.This inverted signal is sent to the another opamp as a
comparator as shown in Fig 5 to generate the pulse at the
negative zero crossing edge.
Fig 5: Circuit for the negative zero-crossing detection of the input voltage
wave.
This method could detect the zero crossing of the negative
edge of input wave(pulse generated starts from the negative
zero crossing), but it could not detect the positive edge
crossing of input wave( which is already determined ).
Negative edge detection is used for firing the second
thyristor(T2) since it gets forward biased only in the negative
half cycle of the input wave. The negative edge zero crossing
circuit is shown in fig(8) and the corresponding waveform is
shown in fig(10).
Fig 6: Negative edge zero crossing detection of the input voltage waveform.
3. Phase Control Circuit
There are two separate phase control circuits for the two
thyristors. It consists of 555 timers and MOSFET as a switch.
The MOFET used is the IRF540. The 555 timer is operated in
monostable mode. In the monostable mode of the 555 timer,
the output pulse of duration equivalent to 1.1RC second is
produced at the output pin 2 when a negative edge transition
occurs at the trigger pin 2
i. Operation of phase control circuit
In the monostable mode of operation, pins 6(threshold) and
7(discharge) are shorted and connected to the Vcc(+12V) via a
resistor(R) and connected to the ground via a capacitor(C2) as
shown in Fig 7.These values of R and C determines the period
of the output pulse given by 1.1RC sec. Pin 5(control) is
grounded via a capacitor(C1). Pin 4(reset output) is connected
to the Vcc. Pin2(trigger) input to the 555 timer is connected to
the source terminal of the MOSFET(M2) which his connected
to the source via a resistor.
The MOSFET(IRF(540) is used as a switch which is driven by
the pulse generated at the zero crossing of the input voltage
waveform. When there is no input pulse at the gate terminal of
the MOSFET, MOSFET behaves as an open circuit thus a
trigger input of the 555 timer remains at the high voltage level.
As soon as the gate of the MOSFET receives the input pulse
from the zero crossing detection circuit, it behaves as a short
circuit thus shorting trigger pin of 555 timer. This result in the
transition from a high voltage to low( 0 volt) in the trigger
input of timer, which triggers the timer. The output voltage at
pin3 of timer remains high for the time interval of 1.1RC
second. Fig 7shows the output pulse of the 555 timer used for
firing the Q1 thyristor. The ON time is 3.3mS as estimated by
1.1*R*C ( R=500Ω and C=6µF). Similarly Fig 8 shows the
phase control circuit diagram for firing thyristor Q2. Fig 10
shows the output voltage waveform of 555 timer which has
the ON time of 3.3ms as calculated by 1.1RC.

Fig 10: Output of the 555 timer for firing the Q2 thyristor

Since duration of output pulse of the 555 timer depends on the

R and C values of the 555 timer, one can vary them to get the
firing pulse at the desired angle.

4. Gate Drive Circuit

The gate drive circuit uses pulse transformers for the isolation
of control signal from input voltage signal. It is shown in Fig
11. The gate drive circuit is designed for the thryristor 2N3899
Fig 7: Phase control circuit for the firing Thyristor (Q1) which requires 4 to 5.2mA triggering current at its gate for
firing. The MOSFETS at the first stage of the gate drive
circuit (M11 and M14) invert the pulse obtained from the
respective 555 timer. These inverted pulses are used as
controls for the second stage MOSFETS(M8 and M12). The
corresponding second stage voltage waveforms at terminal n1
and n2 of MOSFETS (M8 and M12) are shown in Fig 12 and
Fig 13 respectively. When input to the second stage MOSFET
is low( corresponding to the high voltage at 555 timer output),
the primary side of the transformer would not be grounded and
thus no current flows at the primary loop. Now when input to
the second stage MOSFET is high( corresponding to the high
voltage at 555 timer output), the MOSFET behaves as a short
Fig 8: Output of the 1st 555 timer for firing the thyristor Q1 circuit connecting the primary of the transformer to the +12V
supply. The diode across the primary is needed to circulate the
magnetizing current of the transformer[7].By this method, the
primary is connected to the +12V supply during period when
the value of output pulse of 555 timer goes low. In the
secondary side of the transformer, one end is connected to the
gate of the thryster via a diode and a resistor while the other
side is connected to the common ground of the bridge rectifier.
As soon as the primary of the pulse transformer gets
connected to the +12V supply, an impulse of short duration at
the secondary terminal would be produced as shown in Fig
14and Fig 15. The diode in the secondary would allow the
unidirectional flow of impulse current to the gate. The resistor
values are chosen such that the impulse current would be
sufficient to fire the thyristors as shown in Fig 16and Fig 17.

Fig 9: Control circuit for firing thyristor (Q2)

Fig 11: Semi controlled full wave rectifier along with the control circuitry

Fig 12: voltage pulse found at n1 Fig 14: Voltage pulse found at m1

Fig 13: Voltage pulse found at n2 Fig 15: Voltage pulse found at m2
 
Case II:   0 and inductive filter (L=180mH)

waveform Vs(source voltage)Fig 19, Vd(Diodes voltage)Fig

20, inductor current (I0)Fig 21, source current (Is)Fig 22 and
output voltage (V0)Fig 23 are as shown.

Fig 16: Current pulse found at g1

Fig 19: Source voltage Vs

Fig 17: current pulse found at g2

VI. SIMULATION RESULT Fig 20: Voltage( Vd)

The full wave rectifier circuit of Fig 11 is simulated using
PSPICE.

Case I:   71.26 ,C=0 and L=0

For R and C values of 555 timers as 500Ω and 6µF, pulse

delay from 555 timer becomes,
Delay  1.1 R  C (3.1)
Delay  1.1 500  6  3.3ms , Fig 21: Inductor current (I0)
For 60Hz source frequency, T=16.67ms
360
  3.3ms  71.26
16.67 ms
Corresponding output waveform at 10Ω load of full bridge
rectifier for   71.26 , C=0 and L=0 is shown in Fig 18.

Fig 22: Source current Is

Fig 18: Output voltage waveform

Fig 23: Output voltage(Vo)

Calculation of power factor(pf) and THD
P watt
pf   (3.2)
S Vs ,rms I s ,rms
From the plot of output current (Fig 25) ,
I rms  102.22amp
V I2
Vrms  s  120.2V watt  rms  1.045kw
2 and R
From eqn (3.2),
Fig 25: Source current (Is)
1.045 KW
pf   0.845
120.20 10.28
Now,
2
I rms  I1,2rms
THD  (3.3)
I1,2rms
But the fundamental source rms current calculated from FFT
of current(Is) from PSPICE, Fig 22 is
I1,rms  0.4895 A
Fig 26: Inductor current (I0)
Putting the values in eqn(3.3) , we get
THD  0.4895
Output voltage ripple calculated from the simulation, Fig 23
v0, pp
vo   100% (3.4)
vo
109.54  99.03
vo   100%  10.16%
103.8
Fig 27: Capacitor voltage ( v0)

Case III:   0 and second order filter (L=110mH and


Power factor and THD calculation for case III
C=150 μF)
From eqn (3.2),
For   0 and second order filter (L=110mH and C=150 μ

P watt
F), source voltage (vs), diode voltage (vd)Fig 24, source pf  
S Vs ,rms I s ,rms
current (Is)Fig 25, inductor current(Io)Fig 26 and capacitor
voltage(vo)Fig 27 are as shown. From Fig(27),
Vo ,rms  103.44 volt
Vo2,rms
P  1.07 KW
R
V
Vsrms  s  120.2V
2
From Fig 25,
I s ,rms  10.288 amp
1.07 KW
pf   0.865
So 120.2  10.288

Fig 24: Source voltage (Vs) and diode voltage (vd)

Case IV:   30 and inductive filter (L=180mH)

Vs
Vsrms   120.2V
2
From Fig(28) and Fig(29),
I srms  2.37 A
I orms  2.38 A
P  I orms
2
 R  56.56watt
Again,
3.2
I1rms   2.26 A
2
P watt 56.56
pf     0.198
S Vs ,rms I s ,rms 120.2  2.37
Fig 30: waveform for (Vs) and load voltage(Vo)
From eqn(3.3),
2
I srms  I1,2srms
THD   0.31
I1,2srms

Fig 31: waveform of inductor current(I0)

Fig(30) shows the output voltage waveform and Fig(31)

shows the waveform form the inductor current.

Fig 28: Source current(Is)   30

Case V: and second order filter(L=110mH and
C=150µF.

The waveforms of source current (Is) Fig(32), FFT of source

current (Fig(33), voltage across capacitor(Fig(34) and
capacitor current(Fig(35) are as shown.

Power factor and THD calculation:

From Fig(33), Fig(34) and Fig(35)
4.5
I1rms   3.18 A
2
I srms  3.74 A
Fig 29:FFT of source current(Is)
Vorms  32.82volt
 2
Vorms
P  107.71watt
R
From eqn(3.2)
107.71
pf   0.23
170
 3.74
2
From eqn(3.3),

2
I srms  I1,2srms
THD   0.619
I1,2srms
Fig(35) shows that average current across capacitor is 0.

Fig 34: Waveform for the voltage across capacitor

Fig 32: waveform of source current ( Is) Fig 35: waveform for the capacitor current

VII. CONCLUTION

The semi-controlled rectifier circuit uses both the diodes and

Fig 33: FFT of source current(Is)
thyristors by which we can get one quadrant output. In this
way, a variable dc output voltage could be obtained from the
constant ac source by varying the firing angle. The simulation
was done is cadence 16.3 and the result came as expected. The
first and second order filters were designed to limit the output
voltage ripple to 10% of its average. For the firning of
thyristor, control circuit was designed using 555 timer in
monostble mode. The output waveforms were generated for
different values of firing angle and the corresponding power
factor and THD were calculated and average inductor voltage
and average capacitor current were found zero. The designed
circuit now could be implemented in hardware.
 VIII. REFERENCES

[1] http://www.scribd.com/doc/18667041/Controlled-Rectifiers-Sharifah-
Azma-Syed-Mustaffa
[2] Power Electronics,Circuits ,devices and application,second
edition,Muhammad H. Rashid pg 323,345
[3] http://www.services.eng.uts.edu.au/~venkat/pe_html/ch06s1/ch06s1p1.h
tm
[4] Power Electronics, Daniel W.Hart, McGRAW HILLpg, 135,136
[5] http://www.seas.upenn.edu/~jan/spice/PSpicePrimer.pdf
[6] Power Electronics, Daniel W.Hart pg 120
[7] http:// www.engr.siu.edu/staff1/hatz/EE483/LABS/Exp3.html