Text

// another check if test is using full program, disable unnecessary PR_SAE check
ing in memory_array.v
// uncomment the following when you want to check performance:
// `define CHECK_PERFORMANCE
//
//
//
//
//
//
// Define smore clock period
`define smore_clk 50
reg full_prog;
initial full_prog = 1'b0;
////////////////////////////////////////////////////////////////////
// Helper function to check whether a value is within range
////////////////////////////////////////////////////////////////////
// mainly used for time comparison
function in_range(
input time value,
input time margin,
input time reference,
input int direction,
input bit debug); // only smaller/bigger than, or both
time difference;
begin
// the display statements are for debug only
difference = value > reference ? value - reference : ref
erence - value;
if (debug) $display("val = %0t, margin = %0t, ref = %0t,
dir = %0d", value, margin, reference, direction);
if (direction==-1) begin // value can only be smaller th
an reference
if ((difference <= margin) && (value <= referenc
e))
in_range = 1'b1;
else
in_range = 1'b0;
end
else if(direction==1) begin // value can only be larger
if ((difference <= margin) && (value >= referenc
e))
in_range = 1'b1;
else
in_range = 1'b0;
end
else if(direction==0) begin // value can be both smaller
/bigger than reference
if (difference <= margin)
in_range = 1'b1;
else
in_range = 1'b0;
end
else if(direction==2) begin // value can only be larger,
but without upper bound
if (value < reference)
in_range = 1'b0;
else
in_range = 1'b1;
end
if (debug) $display("diff = %0t, result=%0d", difference
, in_range);
end
endfunction
// many SA checkers are only valid for certain modes
// this function checks if SMORE is in a valid mode
function check_set_mode(
input [15:0] valid_mode);
begin
for(int i=0; i<16; i++) begin
if (valid_mode[i] && TF_SA_SET_TB == i && !SMI_R
CXSC && !SMI_RXW)
return 1;
end
return 0;
end
endfunction
function check_form_mode(
begin
if (valid_mode[i] && TF_SA_FORM_TB == i && SMI_F
ORM && !SMI_RXW)
return 1;
end
return 0;
end
endfunction
// only 8 reset modes, 3 bits

function check_reset_mode(
begin
if (valid_mode[i] && TF_SA_RST_TB == i && SMI_RC
XSC && !SMI_RXW)
return 1;
end
return 0;
end
endfunction
////////////////////////////////////////////////////////////////////
// Check that clocks are not glitching.
////////////////////////////////////////////////////////////////////
time rwc_rise, rwc_fall, last_rwc_rise;
time memc_rise, memc_fall, last_memc_rise;
time memca_rise, memca_fall, last_memca_rise;
time memcb_rise, memcb_fall, last_memcb_rise;
parameter tRWC_PER_MIN = 22;
ìfdef GATE_SIM
parameter tRWC_PWLO_MIN = 8;
parameter tRWC_PWHI_MIN = 8;
parameter tMEMC_PER_MIN = 20;
parameter tMEMC_PWLO_MIN = 20;
parameter tMEMC_PWHI_MIN = 1;
èlse
parameter tRWC_PWLO_MIN = 10;
parameter tRWC_PWHI_MIN = 10;
parameter tMEMC_PER_MIN = 20;
parameter tMEMC_PWLO_MIN = 20;
parameter tMEMC_PWHI_MIN = 1;
èndif
time smi_stdby_fedly_falling;
time smi_stdby_fedly_rising;
always @ (negedge smore0.SMI_STDBY_FEDLY)
begin
smi_stdby_fedly_falling = $time;
@ (posedge smore0.SMI_STDBY_FEDLY)
smi_stdby_fedly_rising = $time;
if ((smi_stdby_fedly_rising - smi_stdby_fedly_falling) < 10)
error_pkg::error("POTENTIAL Glithch for SMI_STDBY_FEDLY");
end
reg ignore_clock_checker;
initial ignore_clock_checker = 1'b0;
always @(posedge smore0.rw_clock) begin
last_rwc_rise = rwc_rise;
rwc_rise = $time;
if ((rwc_rise - last_rwc_rise) < tRWC_PER_MIN &&
!(SMI_IOP_HSI_CLKEN || SMI_IOP_HSI_IN_EN || smore0.ifc_smi_cmd_bi_all)
&&
!(ignore_clock_checker || !SMI_CHPSEL) && SP_XPOR_GLOBAL) begin
error_pkg::error("rw_clock period not correct");
$display ("rw_clock period is only %0d ns", (rwc_rise - last_rwc_rise));
end
if ((rwc_rise - rwc_fall) < tRWC_PWLO_MIN &&
&&
error_pkg::error("rw_clock low pulse width not correct");
$display ("rw_clock low pulse width is only %0d ns", (rwc_rise - rwc_fal
l));
end
end
always @(negedge smore0.rw_clock) begin
rwc_fall = $time;
if ((rwc_fall - rwc_rise) < tRWC_PWHI_MIN &&
!(SMI_IOP_HSI_CLKEN|| SMI_IOP_HSI_IN_EN || smore0.ifc_smi_cmd_bi_all)&
&
error_pkg::error("rw_clock high pulse width not correct");
$display ("rw_clock high pulse width is only %0d ns", (rwc_fall - rwc_ri
se));
end
end
always @(posedge smore0.mem_clock_a) begin
last_memc_rise = memc_rise;
memc_rise = $time;
if ((memc_rise - last_memc_rise) < tMEMC_PER_MIN &&
!ignore_clock_checker) begin
error_pkg::error("mem_clock period not correct");
$display ("mem_clock period is only %0d ns", (memc_rise - last_memc_rise
));
end
if ((memc_rise - memc_fall) < tMEMC_PWLO_MIN &&
error_pkg::error("mem_clock low pulse width not correct"
);
$display ("mem_clock low pulse width is only %0d ns", (m
emc_rise - memc_fall));
end
end
always @(negedge smore0.mem_clock_a) begin
memc_fall = $time;
if ((memc_fall - memc_rise) < tMEMC_PWHI_MIN &&
error_pkg::error("mem_clock high pulse width not correct
");
$display ("mem_clock high pulse width is only %0d ns", (
memc_fall - memc_rise));
end
end
always @(posedge smore0.mem_clock_a) begin
last_memca_rise = memca_rise;
memca_rise = $time;
if ((memca_rise - last_memca_rise) < tMEMC_PER_MIN &&
error_pkg::error("mem_clock_a period not correct");
$display ("mem_clock_a period is only %0d ns", (memca_rise - last_memca_
rise));
end
if ((memca_rise - memca_fall) < tMEMC_PWLO_MIN &&
error_pkg::error("mem_clock_a low pulse width not correct");
$display ("mem_clock_a low pulse width is only %0d ns", (memca_rise - me
mca_fall));
end
end
always @(negedge smore0.mem_clock_a) begin
memca_fall = $time;
if ((memca_fall - memca_rise) < tMEMC_PWHI_MIN &&
error_pkg::error("mem_clock_a high pulse width not correct");
$display ("mem_clock_a high pulse width is only %0d ns", (memca_fall - m
emca_rise));
end
end
always @(posedge smore0.pipe_clock) begin
last_memcb_rise = memcb_rise;
memcb_rise = $time;
if ((memcb_rise - last_memcb_rise) < tMEMC_PER_MIN &&
!(SMI_IOP_HSI_CLKEN| SMI_IOP_HSI_IN_EN || smore0.ifc_smi_cmd_bi_all) &
&
!ignore_clock_checker && SP_XPOR_GLOBAL) begin
error_pkg::error("pipe_clock period not correct");
$display ("pipe_clock period is only %0d ns", (memcb_rise - last_memcb_r
ise));
end
if ((memcb_rise - memcb_fall) < tRWC_PWLO_MIN &&
&&
error_pkg::error("pipe_clock low pulse width not correct");
$display ("pipe_clock low pulse width is only %0d ns", (memcb_rise - mem
cb_fall));
end
end
always @(negedge smore0.pipe_clock) begin
memcb_fall = $time;
if ((memcb_fall - memcb_rise) < tMEMC_PWHI_MIN &&
!(SMI_IOP_HSI_CLKEN|| SMI_IOP_HSI_IN_EN || smore0.ifc_smi_cmd_bi_all)
&&
error_pkg::error("pipe_clock high pulse width not correct");
$display ("pipe_clock high pulse width is only %0d ns", (memcb_fall - me
mcb_rise));
end
end
////////////////////////////////////////////////////////////////////
// Check that RXBOUT is not glitching.
////////////////////////////////////////////////////////////////////
time rxbout_rise, rxbout_fall;
time xwe_rise, xre_rise;
always @(posedge YYXWE)
xwe_rise = $time;l
always @(posedge YYXRE)
xre_rise = $time;
parameter tRXB_PW_MIN = 45;
always @(posedge SMI_RXBOUT) begin
rxbout_rise = $time;
if (((rxbout_rise - rxbout_fall) < tRXB_PW_MIN) && !`HOST.rxb_ignored) beg
in
error_pkg::error("RXBOUT low pulse width not correct");
$display ("RXBOUT low pulse width is only %0d ns",(rxbou
t_rise - rxbout_fall));
end
end
always @(negedge SMI_RXBOUT) begin
rxbout_fall = $time;
if (((rxbout_fall - rxbout_rise) < tRXB_PW_MIN/2) && !`HOST.rxb_ignored) b
egin
error_pkg::error("RXBOUT high pulse width not correct");
$display ("RXBOUT high pulse width is only %0d ns", (rxb
out_fall - rxbout_rise));
end
if (xwe_rise > xre_rise) begin
if ((rxbout_fall - xwe_rise) > `HOST.tWB && !`HOST.tWB_exception)
error_pkg::error("RXBOUT did not go low within tWB");
else // sequential read case
if ((rxbout_fall - xwe_rise) > `HOST.tRB && !`HOST.tWB_exception)
error_pkg::error("RXBOUT did not go low within tRB");
end
end
////////////////////////////////////////////////////////////////////
// Check that ifc_wake_osc is not glitching.
////////////////////////////////////////////////////////////////////
time wakeosc_rise;
always @(posedge smore0.ifc_wake_osc)
wakeosc_rise = $time;
parameter tWAKEOSC_PW_MIN = 50;
always @(negedge smore0.ifc_wake_osc) begin
if ($time - wakeosc_rise < tWAKEOSC_PW_MIN) begin
error_pkg::error("ifc_wake_osc pluse too narrow");
$display("ifc_wake_osc pluse (%t)", $time - wakeosc_rise);
end
end
////////////////////////////////////////////////////////////////////
// Check that cenc_clear_cmd is not glitching.
////////////////////////////////////////////////////////////////////
time cenc_clrcmd_rise;
always @(posedge smore0.cenc_clear_cmd)
cenc_clrcmd_rise = $time;
parameter tCLRCMD_PW_MIN = 50;
always @(negedge smore0.cenc_clear_cmd) begin
if ($time - cenc_clrcmd_rise < tCLRCMD_PW_MIN) begin
$display ("ifc_wake_osc pluse (%t)", $time - cenc_clrcmd_rise);
end
end
////////////////////////////////////////////////////////////////////
// Check that bist_clear_cmd is not glitching.
////////////////////////////////////////////////////////////////////
time bist_clrcmd_rise;
always @(posedge smore0.bist_clear_cmd)
bist_clrcmd_rise = $time;
always @(negedge smore0.bist_clear_cmd) begin
if ($time - bist_clrcmd_rise < tCLRCMD_PW_MIN) begin
$display ("ifc_wake_osc pluse (%t) too narrow", $time - bist_cl
rcmd_rise);
end
end
////////////////////////////////////////////////////////////////////
// make sure each page write has only 1 RBW
////////////////////////////////////////////////////////////////////
reg rbw_rose;
reg rbw_exception;
initial rbw_exception = 1'b0;
ìfdef GATE_SIM
always @(posedge smore0.central_ctrl0.cenc_do_prog_page_reg.Q)
èlse
always @(posedge smore0.cenc_do_prog_page)
èndif
rbw_rose = 1'b0;
ìfdef GATE_SIM
always @(posedge smore0.ifc_pgbf_prog)
rbw_exception = 1'b1;
èlse
always @(negedge smore0.central_ctrl0.cenc_state[16])
rbw_rose = 1'b0;
èndif
always @(posedge SMI_RBW) begin
if (rbw_rose && !rbw_exception)
error_pkg::error("SMI_RBW rose more than once");
else
rbw_rose = 1'b1;
end
////////////////////////////////////////////////////////////////////
// make sure each page write has only 1 VAW - in most cases
////////////////////////////////////////////////////////////////////
reg vaw_rose;
reg vaw_exception;
initial vaw_exception = 1'b0;
always @(posedge `TB.TF_SMI_DOUBLEVAW_EN_TB)
vaw_exception = 1'b1;
always @(negedge YYRXB)
vaw_rose = 1'b0;
always @(posedge SMI_SHRDR_COPY_TOP)
vaw_rose = 1'b0;
always @(posedge SMI_VAW) begin
if (vaw_rose && !vaw_exception && !`TB.TF_SMI_DOUBLEVAW_EN_TB)
error_pkg::error("SMI_VAW rose more than once");
else
vaw_rose = 1'b1;
end
////////////////////////////////////////////////////////////////////
// make sure each page has only 1 CR_CAMOP, plus one more in RAW
// exceptions for 4-page erase
////////////////////////////////////////////////////////////////////
reg camop_rose;
reg camop_exception, raw_enabled;
initial camop_exception = 1'b0;
initial raw_enabled = 1'b0;
always @(negedge YYRXB)
camop_rose = 1'b0;
always @(SMI_RAW) begin
camop_rose = 1'b0;
raw_enabled = 1'b0;
end
ìfdef GATE_SIM
èlse
èndif
begin
if (smore0.cenc_full_prog && TF_SMI_FULLPGM_RAW_EN_TB ||
smore0.cenc_dw && TF_SMI_DW_RAW_EN_TB)
raw_enabled = 1'b1;
end
ìfdef GATE_SIM
always @(posedge smore0.ifc_pgbf_prog)
camop_exception = 1'b1;
èlse
always @(negedge smore0.central_ctrl0.cenc_state[16])
camop_rose = 1'b0;
èndif
always @(posedge SMI_CR_CAMOP) begin
if (camop_rose && !camop_exception && !raw_enabled)
error_pkg::error("SMI_CR_CAMOP rose more than once");
else
camop_rose = 1'b1;
end
////////////////////////////////////////////////////////////////////
// make sure each CR_CAMOP polls each SMI_CR_ENTRY once and only once
////////////////////////////////////////////////////////////////////
reg [15:0] cr_entry_polled;
initial cr_entry_polled = 4'h0;
always @(negedge SMI_CR_CAMOP) begin
if (cr_entry_polled != 16'hFFFF && ($time > 200) &&
!smore0.cenc_do_reset && !smore0.bec_page_timeout)
error_pkg::error("some cr entries were not polled during CAMOP");
cr_entry_polled = 4'h0;
end
always @(posedge SMI_CR_CAMOP) begin
#3;
cr_entry_polled[SMI_CR_ENTRY] = 1'b1;
end
always @(SMI_CR_ENTRY) begin
#3;
if (SMI_CR_CAMOP) begin
if (cr_entry_polled[SMI_CR_ENTRY]) //begin
error_pkg::error("cr entry polled more than once");
/*
$display("cr entry %0d", SMI_CR_ENTRY);
end
*/
cr_entry_polled[SMI_CR_ENTRY] = 1'b1;
end
end
////////////////////////////////////////////////////////////////////
// make sure during form, SMI_RCXSC is low
////////////////////////////////////////////////////////////////////
always @(posedge SMI_SA_ENABLE)
if (SMI_FORM && !SMI_RXW)
if (SMI_RCXSC)
error_pkg::error("SMI_RCXSC polarity is wrong during FORM");
////////////////////////////////////////////////////////////////////
// check RBW-->STDBY-->RXW timing sequence
////////////////////////////////////////////////////////////////////
reg rxw_exception;
initial rxw_exception = 1'b0;
ìfdef GATE_SIM
èlse
always @(posedge SMI_RBW) begin
fork
begin: check_stream
wait (!SMI_RBW);
wait (SMI_STDBY);
wait (!SMI_STDBY);
// 4VL is tricky, we expect another pulse of RBRC/RBSC
// To correctly differentiate 4VL from other operations,
// need to tap on a signal directly from backend_ctrl
if (smore0.backend_ctrl0.lv4_en) begin
if (`TB.TF_SMI_RBSC_EN_TB) begin
wait (SMI_RBSC);
wait (!SMI_RBSC);
end
else begin
wait (SMI_RBRC);
wait (!SMI_RBSC);
end
wait (SMI_STDBY);
wait (!SMI_STDBY);
end
#100;
if (SMI_RXW && !SMI_RBW && !`HOST.reset_busy && !rxw_exception &
&
!smore0.cenc_do_reset && !smore0.bec_page_timeout)
error_pkg::error("SMI_RXW is supposed to go low within 100ns
after SMI_STDBY goes low");
disable reset_stream;
end
begin: reset_stream
wait ((smore0.cenc_do_reset || smore0.bec_page_timeout) == 1'b1)
;
disable check_stream;
end
join
end
èndif
////////////////////////////////////////////////////////////////////
// make sure each bay is only activated once in each write, RBW, VAW
////////////////////////////////////////////////////////////////////
reg [7:0] baye_rose;
reg baye_exception;
initial baye_exception = 1'b0; // turn this on if you expect SW retries
wire SMI_BAYE_0 = SMI_BAYE[0];
always @(negedge SMI_RXW)
baye_rose = 8'h0;
always @(posedge SMI_RBW)
baye_rose = 8'h0;
always @(posedge SMI_VAW)
baye_rose = 8'h0;
always @(posedge SMI_FINAL_RTR)
baye_rose = 8'h0;
always @(SMI_RCXSC) // this is important in non-concurrent DW
baye_rose = 8'h0;
always @(posedge SMI_BAYE_0) begin
if ((!SMI_RXW || SMI_RBW || SMI_VAW) && ! baye_exception) begin
if (baye_rose[0])
error_pkg::error("SMI_BAYE[0] rose more than once");
baye_rose[0] = 1'b1;
end
end
if (baye_rose[1])
end
end
if (baye_rose[2])
end
end
if (baye_rose[3])
end
end
if (baye_rose[4])
end
end
if (baye_rose[5])
end
end
if (baye_rose[6])
end
end

if (baye_rose[7])
end
end
//wire [7:0] #100 SMI_BAYE_delay = SMI_BAYE;
reg [7:0] SMI_BAYE_delay;
reg [7:0] SMI_BAYE_delay0;
always @ (posedge smore0.mem_clock_a)
begin
SMI_BAYE_delay0 <= SMI_BAYE;
SMI_BAYE_delay <= SMI_BAYE_delay0;
end
wire[7:0] baye_change = SMI_BAYE_delay ^ SMI_BAYE;
wire [2:0] baye_change_cnt = {2'b00, baye_change[0]} + {2'b00, baye_change[1]
} +
{2'b00, baye_change[2]} + {2'b00, baye_change[3]
} +
} +
};
always @(baye_change_cnt) begin
if ($time > `MA.tPOWERON && baye_change_cnt > 3'h2) begin
error_pkg::error("BAYE switching more than 2 bays within a clock");
$display("clock (%d) ", baye_change_cnt);
end
end
time baye_3_0_change, baye_7_4_change;
always @(SMI_BAYE[3:0]) begin
baye_3_0_change = $time;
if ((($time - baye_7_4_change) < 975ns) && ($time > `MA.tPOWERON))
error_pkg::error("BAYE [7:4] to [3:0] timing constraint violated");
end
always @(SMI_BAYE[7:4]) begin
baye_7_4_change = $time;
if ((($time - baye_3_0_change) < 975ns ) &&
($time > `MA.tPOWERON))
error_pkg::error("BAYE [3:0] to [7:4] timing constraint violated");
end
////////////////////////////////////////////////////////////////////
// make sure each SAD has at most one SAE shift in
////////////////////////////////////////////////////////////////////
reg [63:0] adrcnt_clk_sae_sad;
always @(SMI_RXW or SMI_CAD_ARYOP)
adrcnt_clk_sae_sad = 64'h0;
reg adrcnt_clk_sae_sad_exception;
initial adrcnt_clk_sae_sad_exception = 1'b0;
time SMI_ADRCNT_CLK_rise;
always @(posedge SMI_ADRCNT_CLK) begin
SMI_ADRCNT_CLK_rise = $time;
if (!SMI_RXW && SMI_SAEXWDATA && !SMI_TL_RXW && !adrcnt_clk_sae_sad_excepti
on) begin
if (adrcnt_clk_sae_sad[SMI_SAD_ARYOP]) begin
error_pkg::error("SMI_ADRCNT_CLK rose more than once for SMI_SAD_ARY
OP, SAE_XWDATA=1");
$display("SMI_SAD_ARYOP = %h", SMI_SAD_ARYOP);
end else
adrcnt_clk_sae_sad[SMI_SAD_ARYOP] = 1'b1;
end
end
////////////////////////////////////////////////////////////////////
// make sure each SAD has at most one WDATA shift in
////////////////////////////////////////////////////////////////////
reg [63:0] adrcnt_clk_wdata_sad;
always @(SMI_RXW or SMI_CAD_ARYOP)
adrcnt_clk_wdata_sad = 64'h0;
always @(posedge SMI_ADRCNT_CLK)
if (!SMI_RXW && !SMI_SAEXWDATA && !SMI_TL_RXW) begin
if (adrcnt_clk_wdata_sad[SMI_SAD_ARYOP]) begin
error_pkg::error("SMI_ADRCNT_CLK rose more than once for SMI_SAD_ARY
OP, SAE_XWDATA=0");
$display("SMI_SAD_ARYOP = %h", SMI_SAD_ARYOP);
end else
adrcnt_clk_wdata_sad[SMI_SAD_ARYOP] = 1'b1;
end
////////////////////////////////////////////////////////////////////
// HV checkers
////////////////////////////////////////////////////////////////////
wire expect_hv = SMI_RXW ? 1'b0 :
SMI_FORM ? 1'b1 :
(`TB.TF_SMI_CONCUR_DW_EN_TB && SMI_DIRECT_WR) ?
(!`TB.TF_SMI_LVSET_TB || !`TB.TF_SMI_LVRST_TB) :
SMI_RCXSC ? !`TB.TF_SMI_LVRST_TB :
!`TB.TF_SMI_LVSET_TB;
always @(posedge SMI_SA_ENABLE) begin
if (SMI_RXW) begin
if (SMI_HVOP)
error_pkg::error("SMI_HVOP is high but not expected during read");
if (SMI_COL_HV_ON)
error_pkg::error("SMI_COL_HV_ON is high but not expected during read
");
if (SMI_ROW_HV_ON)
error_pkg::error("SMI_ROW_HV_ON is high but not expected during read
");
end
else begin
if (!expect_hv && SMI_COL_HV_ON)
error_pkg::error("SMI_COL_HV_ON is high but not expected when `TB.TF
_SMI_COLHVON_EN_TB is low");
if (!SMI_COL_HV_ON && expect_hv)
error_pkg::error("SMI_COL_HV_ON is low but expected when `TB.TF_SMI_
COLHVON_EN_TB is high");
if (!SMI_ROW_HV_ON && expect_hv)
error_pkg::error("SMI_ROW_HV_ON is low but expected when high voltag
e is expected");
if (SMI_ROW_HV_ON && !expect_hv)
error_pkg::error("SMI_ROW_HV_ON is high when high voltage is not exp
ected");
if (!SMI_HVOP && expect_hv)
error_pkg::error("SMI_HVOP is low but expected when high voltage is
expected");
if (SMI_HVOP && !expect_hv)
error_pkg::error("SMI_HVOP is high when high voltage is not expected
");
end
end
reg pchgcol_fell_on_cad;
initial pchgcol_fell_on_cad = 1'b0;
always @(negedge SMI_PCHGCOL)
pchgcol_fell_on_cad = 1'b1;
reg pchgcol_rose_on_cad;
initial pchgcol_rose_on_cad = 1'b0;
always @(negedge SMI_PCHGCOL)
pchgcol_rose_on_cad = pchgcol_fell_on_cad;
always @(SMI_SPARE_EN or SMI_CAD) begin
#10;
if (!SMI_PCHGCOL)
error_pkg::error("SMI_PCHGCOL is low when switching CAD");
if (!expect_hv && SMI_COL_HV_ON)
error_pkg::error("SMI_COL_HV_ON is on when switching CAD but NOT expect
ing HV");
if (`TB.TF_SMI_COLHVON_EN_TB && SMI_COL_HV_ON)
error_pkg::error("SMI_COL_HV_ON is on when switching CAD and TF_SMI_COL
HVON_EN_TB is high");
if (!`TB.TF_SMI_COLHVON_EN_TB && expect_hv && !SMI_COL_HV_ON && pchgcol_ro
se_on_cad)
error_pkg::error("SMI_COL_HV_ON is low when switching CAD and TF_SMI_CO
LHVON_EN_TB is low");
pchgcol_fell_on_cad = 1'b0;
pchgcol_rose_on_cad = 1'b0;
end
always @(SMI_BAYE) begin
#10;
if (SMI_ROW_HV_ON)
error_pkg::error("SMI_ROW_HV_ON is on when switching BAYE");
if (SMI_COL_HV_ON && `TB.TF_SMI_COLHVON_EN_TB)
error_pkg::error("SMI_COL_HV_ON is on when switching BAYE");
end
////////////////////////////////////////////////////////////////////
// Make sure the SMI_COL_HV_ON is low when SMI_PCHGCOL is high
////////////////////////////////////////////////////////////////////
always @(posedge SMI_PCHGCOL)
if (SMI_COL_HV_ON && (!expect_hv || expect_hv && `TB.TF_SMI_COLHVON_EN_TB)
)
error_pkg::error("SMI_PCHGCOL went high when SMI_COL_HV_ON is high");
////////////////////////////////////////////////////////////////////
// Make sure the SMI_ROW_HV_ON is low when SMI_PCHGROW is high
////////////////////////////////////////////////////////////////////
always @(posedge SMI_PCHGROW)
if (SMI_ROW_HV_ON)
error_pkg::error("SMI_PCHGROW went high when SMI_ROW_HV_ON is high");
///////////////////////////////////////////////////////////////////
// For each SMI_ADRCNT_CLK, (SMI_SAEXWDATA=1), at most one
// SMI_SA_ENABLE and at most one SMI_TL_CPY rise
// ////////////////////////////////////////////
reg adrcnt_rose, sa_enable_rose, adrcnt_to_sa_exception, tl_cpy_rose, ad
rcnt_to_tl_cpy_exception;
initial begin
adrcnt_rose = 0;
sa_enable_rose = 0;
adrcnt_to_sa_exception = 0;
tl_cpy_rose = 0;
adrcnt_to_tl_cpy_exception = 0;
end
always @( negedge SMI_ADRCNT_CLK) begin
#10 adrcnt_rose = 1;
if ($time - SMI_ADRCNT_CLK_rise < 100ns && $time > 200ns)
error_pkg::error("SMI_ADRCNT_CLK pulse width less than 100ns");
end
always @(posedge SMI_ADRCNT_CLK) begin
#10 adrcnt_rose = 0;
sa_enable_rose = 0; // reset it for next sa_enable
tl_cpy_rose = 0;
end
/*always @(posedge SMI_SA_ENABLE) begin
if (!SMI_RXW && !adrcnt_to_sa_exception && !`HOST.reset_busy) be
gin
if (adrcnt_rose && sa_enable_rose)
error_pkg::error("SMI_SA_ENABLE should only go h
igh at most once for each SMI_ADRCNT_CLK.");
else
sa_enable_rose = 1;
end
end */
always @(posedge SMI_TL_CPY) begin
if (!SMI_RXW && !adrcnt_to_tl_cpy_exception ) begin
if (!SMI_ADRCNT_CLK && tl_cpy_rose) // !smi_adrcnt_clk c
an be used to indicate the period in between each smi_adrcnt_clk pulse
error_pkg::error("SMI_TL_CPY should only go high
at most once for each SMI_ADRCNT_CLK.");
else
tl_cpy_rose = 1;
end
end
always @(negedge `HOST.disable_checkPW) begin // reset the two flags dur
ing a host reset
tl_cpy_rose = 0;
sa_enable_rose = 0;
end
////////////////////////////////////////////////////////////////////////
/////
// Follow up the previous checker and check for the one-to-one relation
// between SMI_TL_CPY and SMI_SA_ENABLE
////////////////////////////////////////////////////////////////////////
/////
reg [`NUM_COL-1:0] tlcpy_cad_aryop;
initial tlcpy_cad_aryop = `NUM_COL'h0;
always @(SMI_FLOAT)
tlcpy_cad_aryop = `NUM_COL'h0;
reg sae_rose_tlcpy, tlcpy_rose_sae;
reg sae_rose_tlcpy_exception, tlcpy_rose_sae_exception;
initial begin
sae_rose_tlcpy = 1'b0;
tlcpy_rose_sae = 1'b0;
sae_rose_tlcpy_exception = 1'b0;
tlcpy_rose_sae_exception = 1'b0;
end
always @(negedge `HOST.disable_checkPW) begin
end
always @(posedge SMI_TL_CPY) begin
tlcpy_cad_aryop[SMI_CAD_ARYOP] = 1'b1;
if (!SMI_RXW && !`HOST.disable_checkPW &&
tlcpy_rose_sae && !tlcpy_rose_sae_exception)
error_pkg::error("There is no SAE_ENABLE after the last
TL_CPY pulses.");
end
if (!SMI_RXW && !`HOST.disable_checkPW &&
sae_rose_tlcpy && !sae_rose_tlcpy_exception)
error_pkg::error("There is no TL_CPY after the last SA_E
NABLE pulses.");
end
///////////////////////////////////////////////////////////////////
// make sure during read or SWRTR_FLOW, SA_ENABLE is always followed by
// SMI_TL_RXW within a SMI_CAD
///////////////////////////////////////////////////////////////////
reg sa_rose_cad;
reg tlrxw_rose_cad;
initial begin
sa_rose_cad = 1'b0;
tlrxw_rose_cad = 1'b0;
end
if (SMI_RXW || SMI_SWRTR_FLOW)
sa_rose_cad = 1'b1;
always @(posedge SMI_TL_RXW[0]) begin
if (SMI_RXW || SMI_SWRTR_FLOW)
if (SMI_SWRTR_FLOW && !SMI_RXW) begin
if (tlcpy_cad_aryop[{SMI_SPARE_EN, SMI_CAD}+1] &&
({SMI_SPARE_EN, SMI_CAD} < `NUM_COL-2) &&
!smore0.cenc_do_reset) begin
error_pkg::error("TL_CPY for CAD_ARYOP happened a little early"
);
$display("CAD_ARYOP = %0d", {SMI_SPARE_EN, SMI_CAD}+1);
end
if (tlcpy_cad_aryop[0] && ({SMI_SPARE_EN, SMI_CAD} == `NUM_COL-1)
&&
!smore0.cenc_do_reset)
error_pkg::error("TL_CPY for CAD_ARYOP 0 happened a little earl
y");
end
end
always @(SMI_CAD) begin
if ((sa_rose_cad != tlrxw_rose_cad) && sa_rose_cad &&
!`HOST.reset_busy && !`HOST.disable_checkPW) begin
if (!SMI_RXW)
error_pkg::error("SMI_SA_ENBALE rose for last CAD SW, but SMI_T
L_RXW didn't");
end
ìfdef CHECK_PERFORMANCE
if ((sa_rose_cad != tlrxw_rose_cad) && !sa_rose_cad)
error_pkg::error("SMI_SA_ENBALE didn't rise for last CAD read, but
SMI_TL_RXW did");
èndif
#10;
sa_rose_cad = 1'b0;
end
always @(`HOST.reset_busy or `HOST.disable_checkPW or SMI_RXW) begin
sa_rose_cad = 1'b0;
end
////////////////////////////////////////////////////////////////////
// Make sure the SMI_RL_INIT is pulsed for every bec_do_rl_init.
////////////////////////////////////////////////////////////////////
reg RL_INIT_rose;
initial RL_INIT_rose = 1'b0;
always @(posedge SMI_RL_INIT)
if (RL_INIT_rose && $time > `MA.tPOWERON)
error_pkg::error("duplicate SMI_RL_INIT for last bec_do_rl_init");
else
RL_INIT_rose = 1'b1;
always @(negedge smore0.bec_do_rl_init) begin
#10;
if (RL_INIT_rose !== 1'b1 && !SMI_4VLX2VL && !smore0.cenc_do_reset &&
$time > `MA.tPOWERON)
error_pkg::error("SMI_RL_INIT didn't rise for last bec_d
o_rl_init");
RL_INIT_rose = 1'b0;
end
reg sae_rose_cad, rl_init_cad;
initial sae_rose_cad = 1'b0;
initial rl_init_cad = 1'b0;
always @(SMI_SPARE_EN or SMI_CAD) begin
#10;
if (sae_rose_cad && !rl_init_cad &&
(SMI_SWRTR_FLOW||SMI_RBRC||SMI_RBSC) && !smore0.cenc_do_reset)
error_pkg::error("SMI_SA_ENABLE rose but not SMI_RL_INIT");
sae_rose_cad = 1'b0;
rl_init_cad = 1'b0;
end
sae_rose_cad = 1'b1;
always @(posedge SMI_RL_INIT)
rl_init_cad = 1'b1;
////////////////////////////////////////////////////////////////////
// Make sure the SMI_CHECK is not high during read - there is no
// SAD switching for read
////////////////////////////////////////////////////////////////////
always @(posedge SMI_CHECK)
if (SMI_RXW && !SMI_FLOAT && !SMI_VAW && !SMI_RBSC && !SMI_RBRC &&
!`HOST.reset_busy && !`HOST.disable_checkPW )
error_pkg::error("SMI_CHECK went high during read - you're wasting cycl
es");
////////////////////////////////////////////////////////////////////
// Make sure the SMI_CHECK is always high during read skip polling -
// there is no SAD switching for read
////////////////////////////////////////////////////////////////////
always @(SMI_CAD_ARYOP) begin
#10;
if (!SMI_CHECK && !SMI_FLOAT &&
(SMI_VAW || SMI_RBSC || SMI_RBRC) && (SMI_CAD_ARYOP != 6'h22) &&
error_pkg::error("SMI_CHECK should be high during read skip polling");
end
////////////////////////////////////////////////////////////////////
// Make sure WDATA shift in happens only once for each CAD
////////////////////////////////////////////////////////////////////
reg wdata_shiftin_happened;
initial wdata_shiftin_happened = 1'b0;
always @(SMI_CAD_ARYOP[0])
wdata_shiftin_happened = 1'b0;
always @(posedge SMI_ADRCNT_CLK[0])
if (!SMI_TL_RXW[0] && !SMI_SAEXWDATA[0]) begin
if (wdata_shiftin_happened &&
error_pkg::error("WDATA shift in cycle happened more than once for c
urrent CAD_ARYOP - you're wasting cycles");
else
wdata_shiftin_happened = 1'b1;
end
////////////////////////////////////////////////////////////////////
// DETECT checkers
////////////////////////////////////////////////////////////////////
reg detect_rst_rose, detect_set_rose;
initial begin
detect_rst_rose = 1'b0;
detect_set_rose = 1'b0;
end
always @(posedge SMI_DETECT_RST) begin
detect_rst_rose = 1'b1;
if (!memory_array0.detect_rst)
error_pkg::error("SMI_DETECT_RST rise unexpected");
end
always @(posedge SMI_DETECT_SET) begin
detect_set_rose = 1'b1;
if (!memory_array0.detect_set)
error_pkg::error("SMI_DETECT_SET rise unexpected");
end
always @(posedge SMI_DETECT_SET or posedge SMI_DETECT_RST) begin
#10;
if (smore0.bec_cdw &&
!(SMI_DETECT_RST && SMI_DETECT_SET) && !smore0.cenc_do_reset)
error_pkg::error("SMI_DETECT_RST/SET should be both high during CD
W");
end
always @(negedge SMI_SA_ENABLE) begin
#10;
if (memory_array0.detect_set && !detect_set_rose)
error_pkg::error("SMI_DETECT_SET did not rise as expected");
if (memory_array0.detect_rst && !detect_rst_rose)
error_pkg::error("SMI_DETECT_RST did not rise as expected");
if (SMI_DETECT_RST || SMI_DETECT_SET)
error_pkg::error("SMI_DETECT_RST and/or SMI_DETECT_SET are/is stil
l high after SAE");
end
///////////////////////////////////////////////////////////////
// BLP to DETECT timing
///////////////////////////////////////////////////////////////
time tBLP_to_DETECT_SET,tBLP_to_DETECT_RST,tBLP_to_DETECT_CDW, tBLP_to_D
ETECT_FORM;
time blp_fall_time;
always @(negedge SMI_BLP)
blp_fall_time = $realtime;
always @(`TB.TF_SMI_BLP2DETECT_FORM_TB)
case (`TB.TF_SMI_BLP2DETECT_FORM_TB)
0: tBLP_to_DETECT_FORM = `smore_clk * 0;
endcase
always @(`TB.TF_SMI_BLP2DETECT_SET_TB)
case (`TB.TF_SMI_BLP2DETECT_SET_TB)
0: tBLP_to_DETECT_SET = `smore_clk * 0;
endcase
always @(`TB.TF_SMI_BLP2DETECT_RST_TB)
case (`TB.TF_SMI_BLP2DETECT_RST_TB)
0: tBLP_to_DETECT_RST = `smore_clk * 0;
endcase
time tBLP_to_WLDV;
always @(*)
case (TF_SMI_BLP_WLDV_DLY_TB)
0: tBLP_to_WLDV = `smore_clk * 0;
endcase
assign tBLP_to_DETECT_CDW = tBLP_to_DETECT_RST > tBLP_to_DETECT_SET ? tB
LP_to_DETECT_RST : tBLP_to_DETECT_SET;
if (check_set_mode(16'h000f) && !SMI_FORM) begin
if (`TB.TF_SMI_CONCUR_DW_EN_TB && SMI_DIRECT_WR) begin /
/ concurrent direct write, check RST against SET timing requirements
#1; // delay 1ns so blp_fall_time is updated
if (`MA.wll) begin
if (!in_range($realtime-1, 0, blp_fall_time+t
BLP_to_WLDV+tBLP_to_DETECT_CDW, 1,0)) begin
èlse
BLP_to_WLDV+tBLP_to_DETECT_CDW, 0,0)) begin
èndif
error_pkg::error("During CDW, BL
P fall to DETECT_SET rise is out of range");
$display("%0t while parameter requires %
0dns", $realtime-1-blp_fall_time, tBLP_to_DETECT_SET);
end
end
else begin
BLP_to_DETECT_CDW, 1,0)) begin
èlse
BLP_to_DETECT_CDW, 0,0)) begin
èndif
error_pkg::error("During CDW, BLP fall t
o DETECT_SET rise is out of range:");
0dns", $realtime-1-blp_fall_time, tBLP_to_DETECT_SET);
end
end
end
else begin
if (!in_range($realtime-1, 0, blp_fall_time+tBLP
_to_DETECT_SET, 1,0)) begin
èlse
if (!in_range($realtime-1, 5, blp_fall_time+tBLP
_to_DETECT_SET, 0,0)) begin
èndif
error_pkg::error("BLP fall to DETECT_SET
rise is out of range:");
0dns",$realtime-1-blp_fall_time, tBLP_to_DETECT_SET);
end
end
end
else if(check_form_mode(16'h000f)) begin // check form
if (!in_range($realtime-1, 0, blp_fall_time+tBLP_to_DETE
CT_FORM, 1,0)) begin
èlse
CT_FORM, 0,0)) begin
èndif
error_pkg::error("During form, BLP fall to DETEC
T_SET rise is out of range:");
$display("%0t while parameter requires %0dns", $
realtime-1-blp_fall_time, tBLP_to_DETECT_FORM);
end
end
end
always @(posedge SMI_DETECT_RST) begin
if (`TB.TF_SMI_CONCUR_DW_EN_TB && SMI_DIRECT_WR) begin // concur
rent direct write, check RST against SET timing requirements
if (`MA.wll) begin
ìfdef GATE_SIM
if (!in_range($realtime-1, 5, blp_fall_time+tBLP_to_W
LDV+tBLP_to_DETECT_CDW, 0,0)) begin // both larger and smaller
èlse
if (!in_range($realtime-1, 5, blp_fall_time+tBLP_to_W
LDV+tBLP_to_DETECT_CDW, 1,0)) begin
èndif
error_pkg::error("During CDW, BLP fall to DETECT
_RST rise is out of range:");
$display("%0t while parameter requires %0dns",$r
ealtime-1-blp_fall_time, tBLP_to_DETECT_SET);
end
end
else begin
ìfdef GATE_SIM
if (!in_range($realtime-1, 5, blp_fall_time+tBLP_to_D
ETECT_CDW, 0,0)) // both larger and smaller
èlse
if (!in_range($realtime-1, 5, blp_fall_time+tBLP_to_D
ETECT_CDW, 1,0))
èndif
error_pkg::error("During CDW, BLP fall to DETECT
_RST rise is out of range:");
end
end
else if (SMI_SA_ENABLE && !SMI_BLP && !SMI_RXW && SMI_RCXSC && `
MA.wll) begin
ìfdef GATE_SIM
CT_RST+tBLP_to_WLDV, 0,0)) begin // both larger and smaller
èlse
CT_RST+tBLP_to_WLDV, 1,0)) begin
èndif
error_pkg::error("BLP fall to DETECT_RST rise is
out of range:");
realtime-1-blp_fall_time, tBLP_to_DETECT_RST);
end
end
else begin
ìfdef GATE_SIM
CT_RST, 0,0)) begin // both larger and smaller
èlse
CT_RST, 1,0)) begin
èndif
error_pkg::error("BLP fall to DETECT_RST rise is
out of range:");
realtime-1-blp_fall_time, tBLP_to_DETECT_RST);
end
end
end
////////////////////////////////////////////////////////////////////////
///////////////
// BLP pulse width variable declaration
// They are used for SA checkers as well
////////////////////////////////////////////////////////
wire [3:0] blpw_pw = SMI_FORM ? `TB.TF_SMI_BLPFORM_PW_TB : SMI_RCXSC ? `
TB.TF_SMI_BLPRST_PW_TB : `TB.TF_SMI_BLPSET_PW_TB;
time tBLPW_PW_min, tBLPW_PW_max,tBLPR_PW_min, tBLPR_PW_max;
////////////////////////////////////////////////////////////////
// A group of timing checkers for SA
///////////////////////////////////////////////////////////////
// According to SA spec, these are minimum delays
// For now, default these checkers to set_mode >= 4 if set_mode is not
// specified on specs
`define Tdly_SMI_SAENOFF_MUXSWON 135
`define Tdly_SMI_MUXSWOFF_SAENON 135
`define Tdly_SMI_SAENOFF_BLSWON 135
`define Tdly_SMI_BLSWOFF_SAENON 135
`define Tpw_SMI_MUX_SWON_DCHG 225
`define Tpw_SMI_BLDV_SWON_DCHG 225
time timing_margin;
initial timing_margin = 5;
èlse
initial timing_margin = 15;
èndif
time timing_margin_min; // for timing parameters that only have minimum
requirement and no maximum requirement
initial timing_margin_min = 100000;
time saenoff_time, muxswon_time, muxswoff_time, saenon_time, blswon_time

, blswoff_time;
time blpon_time, blpoff_time;
always @(posedge SMI_SA_ENABLE) saenon_time = $realtime;
always @(negedge SMI_SA_ENABLE) saenoff_time = $realtime;
always @(posedge SMI_MUX_SWON) muxswon_time = $realtime;
always @(negedge SMI_MUX_SWON) muxswoff_time = $realtime;
always @(posedge SMI_BLDV_SWON) blswon_time = $realtime;
always @(negedge SMI_BLDV_SWON) blswoff_time = $realtime;
always @(posedge SMI_BLP) blpon_time = $realtime;
always @(negedge SMI_BLP) blpoff_time = $realtime;
always @(posedge SMI_MUX_SWON) begin // Same as bldv_swon, skipping migh
t make this delay very very long
#1;
// Margin for this timer should be 30 to cover the variance of
// clock cycle time, 3 cycles = [135, 165]
if (!in_range(muxswon_time, timing_margin_min, saenoff_time+`Tdl
y_SMI_SAENOFF_MUXSWON,1,0)
&& !SMI_RXW && !SMI_SA_ENABLE && check_set_mode(16'hfff0
) && !SMI_RCXSC)
error_pkg::error("Tdly_SMI_SAENOFF_MUXSWON is out of ran
ge of minimum value.");
end
always @(negedge SMI_MUX_SWON) begin // mode = 4, 6, 7, 8

if (check_set_mode(16'h01d0) && !SMI_RCXSC && !SMI_RXW && !SMI_S
A_ENABLE) begin
wait (SMI_SA_ENABLE);
#1; // time variables will be updated
if (!SMI_RXW && !in_range(saenon_time, timing_margin_min
, muxswoff_time+`Tdly_SMI_MUXSWOFF_SAENON,1,0))
error_pkg::error("Tdly_SMI_MUXSWOFF_SAENON is ou
t of range of minimum value.");
end
end
// BLDV_SWON heavily depends on column skipping, so it might have multip
le pulses when SA_EN is low
// and thus Tdly_SMI_SAENOFF_BLSWON should be taken strictly as a minimu
m delay
always @(posedge SMI_BLDV_SWON) begin // mode = 5, 6
#1;
if (!in_range(blswon_time, timing_margin_min, saenoff_time+`Tdly
_SMI_SAENOFF_BLSWON,1,0)
&& !SMI_RXW && !SMI_SA_ENABLE && check_set_mode(16'h0060
) && !SMI_RCXSC)
error_pkg::error("Tdly_SMI_SAENOFF_BLSWON is out of rang
e of minimum value.");
end
always @(posedge SMI_SA_ENABLE) begin // mode = 5, 6
#1;
if (!in_range(saenon_time, timing_margin_min, blswoff_time+`Tdly
_SMI_BLSWOFF_SAENON,1,0)
&& !SMI_RXW && check_set_mode(16'h0060) && !SMI_RCXSC) b
egin
error_pkg::error("Tdly_SMI_BLSWOFF_SAENON is out of rang
e of minimum value.");
$display("saenon = %0t, blswoff_time = %0t, timing_margi
n_min = %0t", saenon_time, blswoff_time, timing_margin_min);
end
end
// SA on to first BLP on delay is controlled by `TB.TF_SMI_SAEN_BLP_DLY_
TB[1:0]
// ONLY FOR TF_SA_SET_TB == 4 or 5
time Tdly_SMI_SAEN_BLP;
wire no_concur_dw = !(SMI_DIRECT_WR && `TB.TF_SMI_CONCUR_DW_EN_TB);
always @(`TB.TF_SMI_SAEN_BLP_DLY_TB)
case (`TB.TF_SMI_SAEN_BLP_DLY_TB)
0: Tdly_SMI_SAEN_BLP = `smore_clk * 0;
endcase
reg check_blp_rise;
if (check_set_mode(16'h0030) && no_concur_dw && !SMI_RCXSC && !S
MI_RXW) begin
//$display("enter %0t", $realtime);
check_blp_rise = 0;
fork
begin
wait (SMI_BLP);
//$display("%0t: blp found, should disab
le blp_check.", $realtime);
end
begin
wait (!SMI_SA_ENABLE) if (blpon_time < s
aenon_time && !check_blp_rise) // blp never goes high during sa_enable is high
error_pkg::error("Expected SMI_B
LP never assserted.");
end
join_any
check_blp_rise = 1;
ìfdef GATE_SIM
if (!in_range(blpon_time, timing_margin, saenon_time+Tdl
y_SMI_SAEN_BLP,0,0)) begin
èlse
if (!in_range(blpon_time, timing_margin, saenon_time+Tdl
y_SMI_SAEN_BLP,1,0)) begin
èndif
error_pkg::error("Tdly_SMI_SAEN_BLP violated");
$display("`TB.TF_SMI_SAEN_BLP_DLY_TB=%0d",`TB.TF
_SMI_SAEN_BLP_DLY_TB);
end
end
end
time Tdly_SMI_BLP_MUXSW, Tdly_SMI_MUXSW_BLP; // controlled by trimbits
always @(`TB.TF_SMI_BLP_MUXSW_DLY_TB)
case (`TB.TF_SMI_BLP_MUXSW_DLY_TB)
0: Tdly_SMI_BLP_MUXSW = `smore_clk * 0;
endcase
// mode = 6
time Tdly_SMI_SAEN_MUXSW;
time real_saen_muxsw; // pick the larger one between saen_muxsw and blp_
muxsw
always @(`TB.TF_SMI_SAEN_MUXSW_DLY_TB)
case (`TB.TF_SMI_SAEN_MUXSW_DLY_TB)
0: Tdly_SMI_SAEN_MUXSW = `smore_clk * 0;
endcase
real_saen_muxsw = Tdly_SMI_SAEN_MUXSW > Tdly_SMI_BLP_MUXSW ? Tdl
y_SMI_SAEN_MUXSW : Tdly_SMI_BLP_MUXSW;
if (check_set_mode(16'h0040) && !SMI_RXW && !SMI_RCXSC) begin
fork
wait (SMI_MUX_SWON);
wait (!SMI_SA_ENABLE) if ( real_saen_muxsw == 0
? muxswon_time + 5 < saenon_time : muxswon_time < saenon_time) // blp never goes
high during sa_enable is high
error_pkg::error("Expected SMI_MUX_SWON
never assserted.");
join_any
ìfdef GATE_SIM
if (!in_range(muxswon_time, timing_margin, saenon_time+r
eal_saen_muxsw,0,0)) begin
èlse
if (!in_range(muxswon_time, timing_margin, saenon_time+r
eal_saen_muxsw,1,0)) begin
èndif
error_pkg::error("real_saen_muxsw violated");
$display("`TB.TF_SMI_SAEN_MUXSW_DLY_TB=%0d, BLP_
MUXSW_DLY_TB=%0d", `TB.TF_SMI_SAEN_MUXSW_DLY_TB, `TB.TF_SMI_BLP_MUXSW_DLY_TB);
end
end
end
// mode = 6,7
time Tdly_SMI_MUXSW_BLDVSW;
always @(`TB.TF_SMI_MUXSW_BLDVSW_DLY_TB)
case (`TB.TF_SMI_MUXSW_BLDVSW_DLY_TB)
0: Tdly_SMI_MUXSW_BLDVSW = `smore_clk * 0;
endcase
always @(posedge SMI_BLDV_SWON) begin
ìfdef GATE_SIM
#4;
èlse
#1;
èndif
ìfdef GATE_SIM
if (check_set_mode(16'h00c0) && !SMI_RXW && SMI_SA_ENABLE && !SM
I_RCXSC
&& !in_range(blswon_time, timing_margin, muxswoff_time+T
dly_SMI_MUXSW_BLDVSW,0,0)) begin
èlse
if (check_set_mode(16'h00c0) && !SMI_RXW && SMI_SA_ENABLE && !SM
I_RCXSC
&& !in_range(blswon_time, timing_margin, muxswoff_time+T
dly_SMI_MUXSW_BLDVSW,1,0)) begin
èndif
error_pkg::error("Tdly_SMI_MUXSW_BLDVSW violated");
$display("`TB.TF_SMI_MUXSW_BLDVSW_DLY_TB=%0d", `TB.TF_SM
I_MUXSW_BLDVSW_DLY_TB);
end
end
// mode = 7,8, mux to detect_set
time Tdly_SMI_MUXSW_DETECT;
always @(`TB.TF_SMI_MUXSW_DETECT_DLY_TB)
case (`TB.TF_SMI_MUXSW_DETECT_DLY_TB)
0: Tdly_SMI_MUXSW_DETECT = `smore_clk * 0;
endcase
#1;
ìfdef GATE_SIM
#5;
èndif
if (check_set_mode(16'h0080) && !SMI_RXW && SMI_SA_ENABLE && !SM
I_RCXSC
&& !in_range($realtime-1, timing_margin, muxswon_time+Td
ly_SMI_MUXSW_DETECT,1,0)) begin
error_pkg::error("mode 7 Tdly_SMI_MUXSW_DETECT violated"
);
$display("Tdly_SMI_MUXSW_DETECT=%0t, `TB.TF_SMI_MUXSW_DE
TECT_DLY_TB=%0d",Tdly_SMI_MUXSW_DETECT, `TB.TF_SMI_MUXSW_DETECT_DLY_TB);
end
I_RCXSC && `TB.TF_SMI_MUXSW_MUXSW_DLY_TB!=0
&& !in_range($realtime-1, timing_margin, muxswon_time+Td
ly_SMI_MUXSW_DETECT,1,0)) begin
error_pkg::error("mode 8 Tdly_SMI_MUXSW_DETECT violated"
);
$display("Tdly_SMI_MUXSW_DETECT=%0t, `TB.TF_SMI_MUXSW_DE
TECT_DLY_TB=%0d", Tdly_SMI_MUXSW_DETECT, `TB.TF_SMI_MUXSW_DETECT_DLY_TB);
end
end
always @(`TB.TF_SMI_MUXSW_BLP_DLY_TB)
case (`TB.TF_SMI_MUXSW_BLP_DLY_TB)
0: Tdly_SMI_MUXSW_BLP = 0;
endcase
always @(posedge SMI_MUX_SWON) begin
#5;
ìfdef GATE_SIM
if (!in_range(muxswon_time, timing_margin, blpoff_time+Tdly_SMI_
BLP_MUXSW,0,0)
&& check_set_mode(16'h0050) && !SMI_RXW && SMI_SA_ENABLE
&& !SMI_RCXSC
&& blpoff_time > saenon_time)
èlse
if (!in_range(muxswon_time, timing_margin, blpoff_time+Tdly_SMI_
BLP_MUXSW,1,0)
&& !SMI_RCXSC
&& blpoff_time > saenon_time)
èndif
error_pkg::error("Tdly_SMI_BLP_MUXSW violated");
end
always @(posedge SMI_BLP) begin
#1;
ìfdef GATE_SIM
#5; // for overlapping signal transitions to settle down
if (!in_range(blpon_time+5, timing_margin, muxswoff_time+Tdly_SM
I_MUXSW_BLP,0,0)
&& !SMI_RCXSC
&& muxswon_time > saenon_time)
èlse
if (!in_range(blpon_time, timing_margin, muxswoff_time+Tdly_SMI_
MUXSW_BLP,1,0)
&& !SMI_RCXSC
&& muxswon_time > saenon_time)
èndif
error_pkg::error("Tdly_SMI_MUXSW_BLP violated");
end
// Controlled by `TB.TF_SMI_BLP_BLDVSW_DLY_TB, `TB.TF_SMI_BLDV_BLP_DLY_T
B;
// mode = 5
time Tdly_SMI_BLP_BLDVSW, Tdly_SMI_BLDV_BLP;
time Tpw_SMI_DETECT,detect_set_on_time,detect_set_off_time;
always @(`TB.TF_SMI_BLP_BLDVSW_DLY_TB)
case (`TB.TF_SMI_BLP_BLDVSW_DLY_TB)
0: Tdly_SMI_BLP_BLDVSW = `smore_clk * 0;
endcase
always @(`TB.TF_SMI_BLDV_BLP_DLY_TB)
case (`TB.TF_SMI_BLDV_BLP_DLY_TB)
0: Tdly_SMI_BLDV_BLP = 0;
endcase
#1;
ìfdef GATE_SIM
if (!in_range(blswon_time, timing_margin, blpoff_time+Tdly_SMI_B
LP_BLDVSW,0,0)
&& !SMI_RCXSC) begin
èlse
if (!in_range(blswon_time, timing_margin, blpoff_time+Tdly_SMI_B
LP_BLDVSW,1,0)
&& !SMI_RCXSC) begin
èndif
error_pkg::error("Tdly_SMI_BLP_BLDVSW violated");
$display("`TB.TF_SMI_BLP_BLDVSW_DLY_TB=%0d", `TB.TF_SMI_
BLP_BLDVSW_DLY_TB);
end
end
reg check_blp_5;
always @(negedge SMI_BLDV_SWON) begin
if (check_set_mode(16'h0020) && !SMI_RXW && SMI_SA_ENABLE && !PR
_WRITE_OK && !SMI_RCXSC) begin
check_blp_5 = 0;
fork
wait (SMI_BLP);
wait (!SMI_SA_ENABLE) if (blpon_time <= saenon_t
ime && !check_blp_5) // blp never goes high during sa_enable is high
error_pkg::error("Expected SMI_BLP never
assserted.");
join_any
check_blp_5 = 1;
#1;
if (!in_range(blpon_time, timing_margin, blswoff_time+Td
ly_SMI_BLDV_BLP,1,0))begin
error_pkg::error("Tdly_SMI_BLDV_BLP violated");
$display("`TB.TF_SMI_BLDV_BLP_DLY_TB=%0d", `TB.T
F_SMI_BLDV_BLP_DLY_TB);
end
end
end
always @(negedge SMI_SA_ENABLE) begin // when loop is complete,check Tho
ld for SA_ENABLE
#1;
if (check_set_mode(16'h0020) && !SMI_RXW && !SMI_RCXSC) // mode
5
if (!in_range(saenoff_time, timing_margin, blswoff_time-
5,2,0)) // give it a 5ns margin
error_pkg::error("Thold loop over to SA_ENABLE f
alls violoated");
else if (check_set_mode(16'h0010) && !SMI_RXW && !SMI_RCXSC) //
mode 4
if (!in_range(saenoff_time, timing_margin, muxswoff_time
-5,2,0)) // give it a 5ns margin
alls violoated");
mode 6
if (!in_range(saenoff_time, timing_margin, blswoff_time-
5,2,0)) // give it a 5ns margin
alls violoated");
mode 7
if (!in_range(saenoff_time, timing_margin, detect_set_of
f_time-5,2,0)) // give it a 5ns margin
alls violoated");
mode 8
if (!in_range(saenoff_time, timing_margin, muxswoff_time
-5,2,0)) // give it a 5ns margin
alls violoated");
end
// mode = 6,7
time Tdly_SMI_BLDVSW_MUXSW;
initial Tdly_SMI_BLDVSW_MUXSW = 0;
reg check_bldvsw_muxsw;
initial check_bldvsw_muxsw = 0;
always @(`TB.TF_SMI_BLDVSW_MUXSW_DLY_TB)
case (`TB.TF_SMI_BLDVSW_MUXSW_DLY_TB)
0: Tdly_SMI_BLDVSW_MUXSW = 0;
endcase
ìfdef GATE_SIM
#5;
èlse
#1;
èndif
if (check_set_mode(16'h00C0) && !SMI_RXW && SMI_SA_ENABLE && !SM
I_RCXSC) begin
ìfdef GATE_SIM
if (check_bldvsw_muxsw && !in_range(muxswon_time, timing
_margin, blswoff_time+Tdly_SMI_BLDVSW_MUXSW,0,0)) begin
èlse
if (check_bldvsw_muxsw && !in_range(muxswon_time, timing
_margin, blswoff_time+Tdly_SMI_BLDVSW_MUXSW,1,0)) begin
èndif
error_pkg::error("Tdly_SMI_BLDVSW_MUXSW violated
");
$display("`TB.TF_SMI_BLDVSW_MUXSW_DLY_TB=%0d", `
TB.TF_SMI_BLDVSW_MUXSW_DLY_TB);
end
check_bldvsw_muxsw = 0;
end
end
if (check_set_mode(16'h00C0) && !SMI_RXW && SMI_SA_ENABLE)
check_bldvsw_muxsw = 1;
end
always @(negedge SMI_SA_ENABLE) check_bldvsw_muxsw = 0;
// DETECT pulse width, right now for mode == 7,8
/*
always @(`TB.TF_SMI_DETECT_PW_TB)
case (`TB.TF_SMI_DETECT_PW_TB)
0: Tpw_SMI_DETECT = 100;
endcase */
always @(posedge SMI_DETECT_SET)
detect_set_on_time = $realtime;
always @(negedge SMI_DETECT_SET)
detect_set_off_time = $realtime;
// Tdly_SMI_DETET_BLP, mode == 7
time Tdly_SMI_DETECT_BLP;
always @(`TB.TF_SMI_DETECT_BLP_DLY_TB)
case(`TB.TF_SMI_DETECT_BLP_DLY_TB)
0: Tdly_SMI_DETECT_BLP = `smore_clk * 0;
endcase
always @(negedge SMI_DETECT_SET) begin
I_RCXSC && !PR_WRITE_OK) begin // loop continues, so check this delay
wait (SMI_BLP);
#1;
if (!in_range(blpon_time, timing_margin, detect_set_off_
time+Tdly_SMI_DETECT_BLP-5,2,0)) begin
error_pkg::error("Tdly_SMI_DETECT_BLP violated")
;
$display("Tdly_SMI_DETECT_BLP=%0t", Tdly_SMI_DET
ECT_BLP);
end
end
end
// mode = 4, 6, 7
// `TB.TF_SMI_MUX_SWON_PW_TB
// VERY TRICKY, this only applies when SA_ENABLE is high,
// when column changes, mux pulse width is a constant: Tpw_SMI_MUX_SWON_
DCHG
// for mode 7, the pulse width is the sum of delays + detect_set pulse w
idth + blp pulse width
time tMUX_SWON_PW;
initial tMUX_SWON_PW = 0;
`define Tpw_SMI_MUX_SWON_DCHG 225
always @(`TB.TF_SMI_MUX_SWON_PW_TB)
case (`TB.TF_SMI_MUX_SWON_PW_TB)
0: tMUX_SWON_PW = 50;
endcase
always @(negedge SMI_MUX_SWON) begin // when SA_ENABLE is high, mode !=
7
#1;
if (check_set_mode(16'h0050) && !SMI_RXW && muxswon_time>memory_
array0.tPOWERON && SMI_SA_ENABLE
&& !in_range(muxswoff_time, 10, muxswon_time+tMUX_SWON_P
W,0,0)) begin // 10ns within the pulse width requirement
error_pkg::error("SMI_MUX_SWON pulse width viola
ted tMUX_SWON_PW");
$display(" SMI_MUX_SWON pulse width:%0t, tMUX_SW
ON_PW:%0t", muxswoff_time-muxswon_time, tMUX_SWON_PW);
end
end
// mode = 7,8, detect_set pw determined by MUX_SWON_PW_TB
always @(negedge SMI_DETECT_SET) begin //
#1;
if (check_set_mode(16'h0180) && !SMI_RXW && detect_set_on_time>m
emory_array0.tPOWERON && SMI_SA_ENABLE && `TB.TF_SMI_MUXSW_MUXSW_DLY_TB!=0
&& !in_range(detect_set_off_time, 10, detect_set_on_time
+tMUX_SWON_PW,0,0)) begin// 10ns within the pulse width requirement
error_pkg::error("Mode 8 DETECT_SET pulse width
violated tMUX_SWON_PW");
$display("Mode 8 DETECT_SET pulse width:%0t, tMU
X_SWON_PW:%0t", detect_set_off_time-detect_set_on_time, tMUX_SWON_PW);
end
end
// mode = 7, mux pulse width checker moved down to use the loop counter
always @(posedge SMI_MUX_SWON) begin : muxsw_pulse_3// when SA_ENABLE is

LOW, excludes 5,7
wait (!SMI_MUX_SWON);
#1;
if (check_set_mode(16'h0050) && !SMI_RCXSC && !SMI_RXW && muxswo
n_time>memory_array0.tPOWERON && !SMI_SA_ENABLE
&& !in_range(muxswoff_time, 30, muxswon_time+`Tpw_SMI_MU
X_SWON_DCHG,0,0)) begin
error_pkg::error("SMI_MUX_SWON pulse width viola
ted Tpw_SMI_MUX_SWON_DCHG");
$display("SMI_MUX_SWON pulse width:%0t, Tpw_SMI_
MUX_SWON_DCHG:%0t", muxswoff_time-muxswon_time,`Tpw_SMI_MUX_SWON_DCHG);
end
end
always @(SMI_CAD) disable muxsw_pulse_3;
// mode = 5, 6, 7
// `TB.TF_SMI_BLDV_SWON_PW_TB
time tBLDV_SWON_PW;
initial tBLDV_SWON_PW = 0;
`define Tpw_SMI_BLDV_SWON_DCHG 225
always @(`TB.TF_SMI_BLDV_SWON_PW_TB)
case (`TB.TF_SMI_BLDV_SWON_PW_TB)
0: tBLDV_SWON_PW = 50;
endcase
always @(negedge SMI_BLDV_SWON) begin // when SA_EN is high
#1;
if (check_set_mode(16'h00d0) && !SMI_RCXSC && !SMI_RXW && blswon
_time > memory_array0.tPOWERON && SMI_SA_ENABLE
&& !in_range(blswoff_time, timing_margin, blswon_time+tB
LDV_SWON_PW,0,0)) begin // 10ns within the pulse width requirement
error_pkg::error("SMI_BLDV_SWON pulse width viol
ated tBLDV_SWON_PW");
$display("SMI_BLDV_SWON pulse width:%0t, tBLDV_S
WON_PW:%0t",blswoff_time-blswon_time, tBLDV_SWON_PW);
end
end
always @(posedge SMI_BLDV_SWON) begin : bldv_pulse_2// when SA_EN is low
wait (!SMI_BLDV_SWON);
#1;
if (check_set_mode(16'h00d0) && !SMI_RCXSC && !SMI_RXW && blswon
_time > memory_array0.tPOWERON && !SMI_SA_ENABLE
&& !in_range(blswoff_time, timing_margin, blswon_time+`T
pw_SMI_BLDV_SWON_DCHG+25,0,0)) begin // 10ns within the pulse width requirement,
+25 to make it a multiple of 50
error_pkg::error("SMI_BLDV_SWON pulse width viol
ated Tpw_SMI_BLDV_SWON_DCHG");
$display("SMI_BLDV_SWON pulse width:%0t, Tpw_SMI
_BLDV_SWON_DCHG:%0t", blswoff_time-blswon_time, `Tpw_SMI_BLDV_SWON_DCHG);
end
end
always @(SMI_CAD) disable bldv_pulse_2;
// mode = 8, SMI_EQVREF related checkers
time eqvrefon_time, eqvrefoff_time;
always @(posedge SMI_EQVREF) eqvrefon_time = $realtime;
always @(negedge SMI_EQVREF) eqvrefoff_time = $realtime;
time Tdly_SMI_MUXSW_EQVREF;
always @(`TB.TF_SMI_MUXSW_EQVREF_DLY_TB)
case (`TB.TF_SMI_MUXSW_EQVREF_DLY_TB)
0: Tdly_SMI_MUXSW_EQVREF = `smore_clk * 0;
endcase
time Tdly_SMI_EQVREF_MUXSW;
always @(`TB.TF_SMI_EQVREF_MUXSW_DLY_TB)
case (`TB.TF_SMI_EQVREF_MUXSW_DLY_TB)
0: Tdly_SMI_EQVREF_MUXSW = `smore_clk * 0;
endcase
always @(posedge SMI_EQVREF) begin
#1;
ìfdef GATE_SIM
#5; // wait for mux_swon to rise in certain cases
if( check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE
&& !in_range(eqvrefon_time, timing_margin, muxswon_time+
Tdly_SMI_MUXSW_EQVREF,0,0)) begin
èlse
if( check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE
&& !in_range(eqvrefon_time, timing_margin, muxswon_time+
Tdly_SMI_MUXSW_EQVREF,1,0)) begin
èndif
error_pkg::error("SMI_EQVREF violated Tdly_SMI_MUXSW_EQV
REF");
$display("Tdly_SMI_MUXSW_EQVREF:%0t", Tdly_SMI_MUXSW_EQV
REF);
end
end
always @(negedge SMI_EQVREF) begin : eqvref_to_mux
#1;
if ( check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE && `T
B.TF_SMI_MUXSW_MUXSW_DLY_TB!=0) begin
if (!SMI_MUX_SWON && Tdly_SMI_EQVREF_MUXSW != 0) error_p
kg::error("SMI_MUX_SWON should be high while SMI_EQVREF is high.");
#1;
ìfdef GATE_SIM
#5;// wait for mux
if (!in_range(muxswoff_time, timing_margin, eqvrefoff_ti
me+Tdly_SMI_EQVREF_MUXSW,0,0)) begin
èlse
if (!in_range(muxswoff_time, timing_margin, eqvrefoff_ti
me+Tdly_SMI_EQVREF_MUXSW,1,0)) begin
èndif
error_pkg::error("SMI_MUX_SWON violated Tdly_SMI
_EQVREF_MUXSW");
$display("Tdly_SMI_EQVREF_MUXSW:%0t", Tdly_SMI_E
QVREF_MUXSW);
end
end
end
always @(negedge SMI_SA_ENABLE) disable eqvref_to_mux;
time tEQVREF_PW;
initial tEQVREF_PW = 0;
always @(`TB.TF_SMI_EQVREF_PW_TB)
case (`TB.TF_SMI_EQVREF_PW_TB)
0: tEQVREF_PW = 50;
1: tEQVREF_PW = 100;
endcase
always @(negedge SMI_EQVREF) begin
#1;
if (check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE
&& !in_range(eqvrefoff_time, 5, eqvrefon_time+tEQVREF_PW
, 0, 0)) begin
error_pkg::error("SMI_EQVREF pulse width violate
d `TB.TF_SMI_EQVREF_PW_TB");
$display("SMI_EQVREF pulse width:%0t, `TB.TF_SMI
_EQVREF_PW_TB:%0t", eqvrefoff_time-eqvrefon_time, tEQVREF_PW);
end
end
// mode = 8, MUX_2_MUX
time Tdly_SMI_MUXSW_MUXSW;
always @(`TB.TF_SMI_MUXSW_MUXSW_DLY_TB)
case (`TB.TF_SMI_MUXSW_MUXSW_DLY_TB)
0: Tdly_SMI_MUXSW_MUXSW = 0;
endcase
#1;
ìfdef GATE_SIM
if (check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE && mux
swoff_time > saenon_time && blpon_time+5 < muxswoff_time
&& !in_range(muxswon_time, timing_margin, muxswoff_time+
Tdly_SMI_MUXSW_MUXSW,0,0)) begin
èlse
if (check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE && mux
swoff_time > saenon_time && blpon_time < muxswoff_time
&& !in_range(muxswon_time, timing_margin, muxswoff_time+
Tdly_SMI_MUXSW_MUXSW,1,0)) begin
èndif
error_pkg::error("SMI_MUX_SWON violated Tdly_SMI_MUXSW_M
UXSW");
$display("Tdly_SMI_MUXSW_MUXSW:%0t", Tdly_SMI_MUXSW_MUXS
W);
end
end
// mode = 8,
time Tdly_SMI_DETECT_MUXSW;
always @(`TB.TF_SMI_DETECT_MUXSW_DLY_TB)
case (`TB.TF_SMI_DETECT_MUXSW_DLY_TB)
0: Tdly_SMI_DETECT_MUXSW = `smore_clk * 0;
endcase
always @(negedge SMI_DETECT_SET) begin : detect_to_muxsw
if (check_set_mode(16'h0100) && !SMI_RXW && SMI_SA_ENABLE && `TB
.TF_SMI_MUXSW_MUXSW_DLY_TB!=0) begin
#1;
ìfdef GATE_SIM
if (!in_range(muxswoff_time, timing_margin,detect_set_of
f_time+Tdly_SMI_DETECT_MUXSW,0,0)) begin
èlse
if (!in_range(muxswoff_time, timing_margin,detect_set_of
f_time+Tdly_SMI_DETECT_MUXSW,1,0)) begin
èndif
error_pkg::error("SMI_MUX_SWON violated Tdly_SMI
_DETECT_MUXSW");
$display("Tdly_SMI_DETECT_MUXSW:%0t", Tdly_SMI_D
ETECT_MUXSW);
end
end
end
always @(negedge SMI_SA_ENABLE) disable detect_to_muxsw;
///////////////////////////////////////////////////////////////////////
// Cap-discharge to *_SWON time checkers
///////////////////////////////////////////////////////////////////////
// names of all the timing parameters are exactly the same as array spec
defines
// refer to array spec for the most updated values
// so far these are minimum values
`define BLDV_SWON_to_PCHGC 175
`define MUX_SWON_to_PCHGC 175
`define BLDV_SWON_to_CHVOFF 130
`define MUX_SWON_to_CHVOFF 130
`define CHVON_to_BLDV_SWOFF 130
`define PCHGC_to_BLDV_SWOFF 175
`define CHVON_to_MUX_SWOFF 130
`define PCHGC_to_MUX_SWOFF 175
`define WLDV_SWON_to_PCHGR 0 // waiting for spec to update
`define PCHGR_to_WLDV_SWOFF 0 // waiting for spec to update
// SMI_BLDV_SWON and SMI_MUX_SWON on/off times are defined in previous c
hecker
// These signals can wait for skip and thus can take a long time
time pchgc_time,wlswon_time, wlswoff_time, chvon_time, chvoff_time;
always @(SMI_PCHGCOL) pchgc_time = $realtime;
always @(posedge SMI_WLDV_SWON) wlswon_time = $realtime;
always @(negedge SMI_WLDV_SWON) wlswoff_time = $realtime;
always @(posedge SMI_COL_HV_ON) chvon_time = $realtime;
always @(negedge SMI_COL_HV_ON) chvoff_time = $realtime;
always @(posedge SMI_PCHGCOL) begin
#1;
if (!in_range(pchgc_time, timing_margin, blswon_time+`BLDV_SWON_
to_PCHGC,2,0)
&& !SMI_RXW && check_set_mode(16'h02e0)) // mode for bld
v_sw = 5,6,7,9
error_pkg::error("BLDV_SWON_to_PCHGC is out of range of
minimum value.");
if (!in_range(pchgc_time, timing_margin, muxswon_time+`MUX_SWON_
to_PCHGC,2,0)
&& !SMI_RXW && check_set_mode(16'h01d0)) // mode for mux
_sw = 4,6,7,8
error_pkg::error("MUX_SWON_to_PCHGC is out of range of m
inimum value.");
end
always @(negedge SMI_COL_HV_ON) begin
#1;
if (!in_range(chvoff_time, timing_margin, blswon_time+`BLDV_SWON
_to_CHVOFF, 2, 0)
&& !SMI_RXW && check_set_mode(16'h02e0))
error_pkg::error("BLDV_SWON_to_CHVOFF is out of range of
minimum value.");
if (!in_range(chvoff_time, timing_margin, muxswon_time+`MUX_SWON
_to_CHVOFF, 2, 0)
&& !SMI_RXW && check_set_mode(16'h01d0))
error_pkg::error("MUX_SWON_to_CHVOFF is out of range of
minimum value.");
end
reg chvon_to_bldv_swoff_checked, pchgc_to_bldv_swoff_checked;
initial chvon_to_bldv_swoff_checked=0;
initial pchgc_to_bldv_swoff_checked=0;
wire cap_discharge_condition = !SMI_PCHGCOL && SMI_COL_HV_ON && !SMI_PCH
GROW;
#1;
if (!SMI_RXW && cap_discharge_condition) begin
if (!in_range(blswoff_time, timing_margin, chvon_time+`C
HVON_to_BLDV_SWOFF, 2, 0) && !chvon_to_bldv_swoff_checked)
error_pkg::error("CHVON_to_BLDV_SWOFF is out of
range of minimum value.");
chvon_to_bldv_swoff_checked=1;
if (!in_range(blswoff_time, timing_margin, pchgc_time+`P
CHGC_to_BLDV_SWOFF, 2, 0) && !pchgc_to_bldv_swoff_checked)
error_pkg::error("PCHGC_to_BLDV_SWOFF is out of
range of minimum value.");
pchgc_to_bldv_swoff_checked=1;
end
end
reg chvon_to_mux_swoff_checked, pchgc_to_mux_swoff_checked;
initial chvon_to_mux_swoff_checked=0;
initial pchgc_to_mux_swoff_checked=0;
always @(negedge SMI_MUX_SWON) begin
#1;
if(!SMI_RXW && cap_discharge_condition) begin
if (!in_range(muxswoff_time, timing_margin, chvon_time+`
CHVON_to_MUX_SWOFF, 2, 0)
&& !chvon_to_mux_swoff_checked)
error_pkg::error("CHVON_to_MUX_SWOFF is out of r
ange of minimum value.");
chvon_to_mux_swoff_checked=1;
if (!in_range(muxswoff_time, timing_margin, pchgc_time+`
PCHGC_to_MUX_SWOFF, 2, 0)
&& !pchgc_to_mux_swoff_checked)
error_pkg::error("PCHGC_to_MUX_SWOFF is out of r
ange of minimum value.");
pchgc_to_mux_swoff_checked=1;
end
end
always @(negedge cap_discharge_condition) begin // reset status regs
pchgc_to_bldv_swoff_checked=0;
pchgc_to_mux_swoff_checked=0;
end
always @(negedge SMI_COL_HV_ON) begin
chvon_to_bldv_swoff_checked=0;
chvon_to_mux_swoff_checked=0;
end
////////////////////////////////////////////////////////////////////////
/////
// More sa set mode checkers
////////////////////////////////////////////////////////////////////////
/////
// mode = 9,
time Tdly_SMI_BLDV_WLDV;
always @(`TB.TF_SMI_BLDV_WLDV_DLY_TB)
case (`TB.TF_SMI_BLDV_WLDV_DLY_TB)
0: Tdly_SMI_BLDV_WLDV = `smore_clk * 0;
endcase
always @(posedge SMI_WLDV_SWON) begin
#1;
if (check_set_mode(16'h0200) && !SMI_RXW && SMI_SA_ENABLE) begin
ìfdef GATE_SIM
#5;
if (!in_range(wlswon_time, timing_margin,blswoff_time+Td
ly_SMI_BLDV_WLDV,0,0)) begin
èlse
if (!in_range(wlswon_time, timing_margin,blswoff_time+Td
ly_SMI_BLDV_WLDV,1,0)) begin
èndif
error_pkg::error("SMI_WLDV_SWON violated Tdly_SM
I_BLDV_WLDV");
$display("Tdly_SMI_BLDV_WLDV:%0t", Tdly_SMI_BLDV
_WLDV);
end
end
end
// mode = 9
time Tdly_SMI_SAEN_BLDV;
always @(`TB.TF_SMI_SAEN_BLDV_DLY_TB)
case (`TB.TF_SMI_SAEN_BLDV_DLY_TB)
0: Tdly_SMI_SAEN_BLDV = `smore_clk * 0;
endcase
#1;
ìfdef GATE_SIM
#5;
if (!in_range(blswon_time, timing_margin,saenon_time+Tdl
y_SMI_SAEN_BLDV,0,0)) begin
èlse
if (!in_range(blswon_time, timing_margin,saenon_time+Tdl
y_SMI_SAEN_BLDV,1,0)) begin
èndif
error_pkg::error("SMI_BLDV_SWON violated Tdly_SM
I_SAEN_BLDV");
$display("Tdly_SMI_SAEN_BLDV:%0t", Tdly_SMI_SAEN
_BLDV);
end
end
wait (!SMI_SA_ENABLE); //make sure this timing parameter only ap
plies to first bldv pulse
end
// mode = 9,
time Tdly_SMI_WLDV_BLDV;
always @(`TB.TF_SMI_WLDV_BLDV_DLY_TB)
case (`TB.TF_SMI_WLDV_BLDV_DLY_TB)
0: Tdly_SMI_WLDV_BLDV = `smore_clk * 0;
endcase
#1;
if (check_set_mode(16'h0200) && !SMI_RXW && SMI_SA_ENABLE && wls
woff_time > saenon_time ) begin
ìfdef GATE_SIM
#5;
if (!in_range(blswon_time, timing_margin,wlswoff_time+Td
ly_SMI_WLDV_BLDV,0,0)) begin
èlse
if (!in_range(blswon_time, timing_margin,wlswoff_time+Td
ly_SMI_WLDV_BLDV,1,0)) begin
èndif
error_pkg::error("SMI_BLDV_SWON violated Tdly_SM
I_WLDV_BLDV");
$display("Tdly_SMI_WLDV_BLDV:%0t", Tdly_SMI_WLDV
_BLDV);
end
end
end
// mode = 10,
time tWLDV_SWON_PW;
initial tWLDV_SWON_PW = 0;
always @(`TB.TF_SMI_WLDV_SWON_PW_TB)
case (`TB.TF_SMI_WLDV_SWON_PW_TB)
0: tWLDV_SWON_PW = 50;
14: tWLDV_SWON_PW = 1000000;
15: tWLDV_SWON_PW = 2000000;
endcase
always @(negedge SMI_WLDV_SWON) begin
#1;
if (!in_range(wlswoff_time, timing_margin, wlswon_time+t
WLDV_SWON_PW, 1, 0)) begin
error_pkg::error("SMI_WLDV_SWON pulse width viol
ated tWLDV_SWON_PW.");
$display("SMI_WLDV_SWON pulse width:%0t, tWLDV_S
WON_PW:%0t", wlswoff_time-wlswon_time, tWLDV_SWON_PW);
end
end
end
// mode = 10,
time Tdly_SMI_WLDV_BLP;
always @(`TB.TF_SMI_WLDV_BLP_DLY_TB)
case (`TB.TF_SMI_WLDV_BLP_DLY_TB)
0: Tdly_SMI_WLDV_BLP = `smore_clk * 0;
endcase
#1;
ìfdef GATE_SIM
#5; //
woff_time > saenon_time) begin
if (!in_range(blpon_time, timing_margin,wlswoff_time+Tdl
y_SMI_WLDV_BLP,0,0)) begin
error_pkg::error("SMI_BLP violated Tdly_SMI_WLDV
_BLP");
$display("Tdly_SMI_WLDV_BLP:%0t", Tdly_SMI_WLDV_
BLP);
end
end
èlse
woff_time > saenon_time) begin
if (!in_range(blpon_time, timing_margin,wlswoff_time+Tdl
y_SMI_WLDV_BLP,1,0)) begin
error_pkg::error("SMI_BLP violated Tdly_SMI_WLDV
_BLP");
$display("Tdly_SMI_WLDV_BLP:%0t", Tdly_SMI_WLDV_
BLP);
end
end
èndif
end
////////////////////////////////////////////////////////////////////////
////
// Set Modes waveform checkers:
// Making sure the waveform matches the spec
////////////////////////////////////////////////////////////////////////
////
wire [5:0] sa_set_signals = {SMI_BLP, SMI_DETECT_SET, SMI_EQVREF, SMI_MU
X_SWON, SMI_BLDV_SWON, SMI_WLDV_SWON};
// when SMI_SA_ENABLE is high
wire mode4_fail_saenon = SMI_BLP && sa_set_signals != 6'b100011 ||
SMI_MUX_SWON &&
sa_set_signals != 6'b000111;
SMI_BLDV_SWON &&
wire mode6_fail_saenon = SMI_MUX_SWON && sa_set_signals != 6'b100101 ||
SMI_BLDV_SWON &&
sa_set_signals != 6'b100011 ||
SMI_MUX_SWON &&
SMI_BLDV_SWON;
SMI_BLDV_SWON &&
sa_set_signals != 6'b000011 ||
SMI_DETECT_SET &
& sa_set_signals != 6'b010101;
SMI_EQVREF && sa
_set_signals != 6'b001111 ||
SMI_DETECT_SET &
& sa_set_signals != 6'b010111;
wire mode9_fail_saenon = SMI_BLDV_SWON && sa_set_signals != 6'b100110 ||
SMI_WLDV_SWON &&
SMI_WLDV_SWON &&
// when SMI_SA_ENABLE is low
wire col_row_switch = SMI_PCHGCOL | SMI_PCHGROW;
wire mode4_fail_saenoff = sa_set_signals != 6'b000011 && sa_set_signals
!= 6'b000111;
!= 6'b000111;
!= 6'b000111;
!= 6'b000111 && sa_set_signals != 6'b000101;
!= 6'b000111;
wire mode9_fail_saenoff = !col_row_switch && sa_set_signals != 6'b000100
&& sa_set_signals != 6'b000110;
wire mode10_fail_saenoff = sa_set_signals != 6'b000110;
ìfndef GATE_SIM
always @(sa_set_signals) begin
#1;
if (!SMI_RXW && SMI_SA_ENABLE) begin
case (1)
check_set_mode(16'h0010) && mode4_fail_saenon ,
// set_mode=4
// set_mode=5
// set_mode=6
// set_mode=7
// set_mode=8
// set_mode=9
check_set_mode(16'h0400) && mode10_fail_saenon:
// set_mode=10
error_pkg::error("When SA_EN is on, {BLP
, DETECT_SET, EQVREF, MUX_SW, BLDV_SW, WLDV_SW} didn't match the specs");
//;
default:
;
endcase
end
else if (!SMI_RXW && !SMI_SA_ENABLE) begin
case (1)
check_set_mode(16'h0010) && mode4_fail_saenoff ,
// set_mode=4
// set_mode=5
// set_mode=6
// set_mode=7
check_set_mode(16'h0100) && mode8_fail_saenoff :
// set_mode=8
error_pkg::error("When SA_EN is off, {BL
P, DETECT_SET, EQVREF, MUX_SW, BLDV_SW, WLDV_SW} didn't match the specs");
default:
;
endcase
end
end
#1;
if (!SMI_RXW) begin
case (1)
check_set_mode(16'h0010) && sa_set_signals !== 6
'b000011 , // mode 4
'b000101 , // set_mode=5
'b000001 , // set_mode=6
'b000001 , // set_mode=7
'b000011 , // set_mode=8
'b000100 : // set_mode=9
// set_mode=10 is already covered
error_pkg::error("after the SA_ENABLE fa
lls,{BLP, DETECT_SET, EQVREF, MUX_SW, BLDV_SW, WLDV_SW} didn't match the specs")
;
default:
;
endcase
end
end
èndif
//
////////////////////////////////////////////////////////////////////////
/////
// `TB.TF_SMI_PGPULSE_NUM_SET/FORM_TB checker
////////////////////////////////////////////////////////////////////////
/////
// now it's valid for TF_SA_SET_TB == 4, 5, 7, 8, 9, 10
// thus checks SET/FORM only
int blp_pulse_counter, muxsw_pulse_counter, blsw_pulse_counter;
wire cond_form = (check_set_mode(16'h03b0) && !SMI_RXW && !SMI_RCXSC &&
SMI_FORM);
wire cond_set = (check_set_mode(16'h03b0) && !SMI_RXW && !SMI_RCXSC && !
SMI_FORM && !SMI_DIRECT_WR);
wire cond_dw = (check_set_mode(16'h03b0) && !SMI_RXW && SMI_DIRECT_WR &&
!SMI_RCXSC);
wire [1:0] dw_pgpulse_num = `TB.TF_SMI_CONCUR_DW_EN_TB ? ((`TB.TF_SMI_PG
PULSE_NUM_RST_TB>`TB.TF_SMI_PGPULSE_NUM_SET_TB) ? (1<<`TB.TF_SMI_PGPULSE_NUM_RST
_TB) : (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB)) :
(SMI_RCX
SC ? (1<<`TB.TF_SMI_PGPULSE_NUM_RST_TB) : (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB));
int max_blp_pulse, max_muxsw_pulse, max_blsw_pulse;
#1;
wait (!SMI_BLP);
if ((cond_form || cond_set || cond_dw) && SMI_SA_ENABLE ) blp_pu
lse_counter++;
end
#1;
if ((cond_form || cond_set || cond_dw) && SMI_SA_ENABLE ) muxsw_
pulse_counter++;
end
#1;
if ((cond_form || cond_set || cond_dw) && SMI_SA_ENABLE ) blsw_p
ulse_counter++;
end
disable wait_for_write_ok;
if (PR_WRITE_OK && !check_set_mode(16'h0270)) begin // mode != 4
, 5, 6, 9
if (blp_pulse_counter != max_blp_pulse)
error_pkg::error("Too many SMI_BLP pulses since
PR_WRITE_OK is high.");
if (muxsw_pulse_counter != max_muxsw_pulse)
error_pkg::error("Too many SMI_MUX_SWON pulses s
ince PR_WRITE_OK is high.");
if (!check_set_mode(16'h0100) && blsw_pulse_counter != m
ax_blsw_pulse) // excludes 8
error_pkg::error("Too many SMI_BLDV_SWON pulses
since PR_WRITE_OK is high.");
end
else if (check_set_mode(16'h05b0)) begin // check blp, excludes
6,9
if (cond_set && blp_pulse_counter != (1<<`TB.TF_SMI_PGPU
LSE_NUM_SET_TB))
error_pkg::error("SMI_BLP retry pulses(blp_pulse
_counter) are not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB).");
if (cond_form && blp_pulse_counter != (1<<`TB.TF_SMI_PGP
ULSE_NUM_FORM_TB))
error_pkg::error("SMI_BLP retry pulses(blp_pulse
_counter) are not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_FORM_TB).");
if (cond_dw && no_concur_dw && blp_pulse_counter != dw_p
gpulse_num) begin
if (dw_pgpulse_num == (1<<`TB.TF_SMI_PGPULSE_NUM
_SET_TB))
error_pkg::error("SMI_BLP retry pulses(b
lp_pulse_counter) are not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB).");
end
end
else if (check_set_mode(16'h01d0)) begin // check mux, excludes
5,9,10
if (cond_set && muxsw_pulse_counter != (1<<`TB.TF_SMI_PG
PULSE_NUM_SET_TB))
error_pkg::error("SMI_MUX_SWON retry pulses are
not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB).");
if (cond_form && muxsw_pulse_counter != (1<<`TB.TF_SMI_P
GPULSE_NUM_FORM_TB))
error_pkg::error("SMI_MUX_SWON retry pulses are
not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_FORM_TB).");
end
else if (check_set_mode(16'h06e0)) begin // check bldv, excludes
4,8
if (cond_set && blsw_pulse_counter != (1<<`TB.TF_SMI_PGP
ULSE_NUM_SET_TB))
error_pkg::error("SMI_BLDV_SWON retry pulses are
not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB).");
if (cond_form && blsw_pulse_counter != (1<<`TB.TF_SMI_PG
PULSE_NUM_FORM_TB))
error_pkg::error("SMI_BLDV_SWON retry pulses are
not equal to (1<<`TB.TF_SMI_PGPULSE_NUM_FORM_TB).");
end
blp_pulse_counter = 0;
muxsw_pulse_counter = 0;
blsw_pulse_counter = 0;
max_blp_pulse = 0;
max_muxsw_pulse = 0;
max_blsw_pulse = 0;
end
// wait_for_write_ok excludes 4,5,6,9
always @(posedge SMI_BLP) begin : wait_for_write_ok
#1;
if (check_set_mode(16'h0180) && !SMI_RXW && SMI_SA_ENABLE )
wait (PR_WRITE_OK) begin
max_blp_pulse = blp_pulse_counter;
max_muxsw_pulse = blp_pulse_counter; // should h
ave the same num of pulses
max_blsw_pulse = blp_pulse_counter;
end
end
// for mode == 6, BLP is always high, so checks MUX_SWON instead
//////////////////////////////////////////////////////////////////////
// BLP pulse width checker
/////////////////////////////////////////////////////////////////////
always @(*)
case (blpw_pw)
4'b0000 : begin
tBLPW_PW_min = 40;
tBLPW_PW_max = 60;
end
4'b0001 : begin
tBLPW_PW_min = 90;
tBLPW_PW_max = 110;
end
4'b0010 : begin
tBLPW_PW_min = 140;
tBLPW_PW_max = 160;
end
4'b0011 : begin
tBLPW_PW_min = 190;
tBLPW_PW_max = 210;
end
4'b0100 : begin
tBLPW_PW_min = 240;
tBLPW_PW_max = 260;
end
4'b0101 : begin
tBLPW_PW_min = 290;
tBLPW_PW_max = 310;
end
4'b0110 : begin
tBLPW_PW_min = 340;
tBLPW_PW_max = 360;
end
4'b0111 : begin
tBLPW_PW_min = 390;
tBLPW_PW_max = 410;
end
4'b1000 : begin
tBLPW_PW_min = 440;
tBLPW_PW_max = 460;
end
4'b1001 : begin
tBLPW_PW_min = 490;
tBLPW_PW_max = 510;
end
4'b1010 : begin
tBLPW_PW_min = 590;
tBLPW_PW_max = 610;
end
4'b1011 : begin
tBLPW_PW_min = 690;
tBLPW_PW_max = 710;
end
4'b1100 : begin
tBLPW_PW_min = 790;
tBLPW_PW_max = 810;
end
4'b1101 : begin
tBLPW_PW_min = 890;
tBLPW_PW_max = 910;
end
4'b1110 : begin
tBLPW_PW_min = 990;
tBLPW_PW_max = 1010;
end
4'b1111 : begin
tBLPW_PW_min = 1090;
tBLPW_PW_max = 1110;
end
endcase // case(`TB.TF_SMI_BLPSET_PW_TB)
always @(`TB.TF_SMI_BLPREAD_PW_TB)
case (`TB.TF_SMI_BLPREAD_PW_TB)
4'b0000 : begin
tBLPR_PW_min = 40;
tBLPR_PW_max = 60;
end
4'b0001 : begin
tBLPR_PW_min = 90;
tBLPR_PW_max = 110;
end
4'b0010 : begin
tBLPR_PW_min = 140;
tBLPR_PW_max = 160;
end
4'b0011 : begin
tBLPR_PW_min = 190;
tBLPR_PW_max = 210;
end
4'b0100 : begin
tBLPR_PW_min = 240;
tBLPR_PW_max = 260;
end
4'b0101 : begin
tBLPR_PW_min = 290;
tBLPR_PW_max = 310;
end
4'b0110 : begin
tBLPR_PW_min = 340;
tBLPR_PW_max = 360;
end
4'b0111 : begin
tBLPR_PW_min = 390;
tBLPR_PW_max = 410;
end
4'b1000 : begin
tBLPR_PW_min = 440;
tBLPR_PW_max = 460;
end
4'b1001 : begin
tBLPR_PW_min = 490;
tBLPR_PW_max = 510;
end
4'b1010 : begin
tBLPR_PW_min = 590;
tBLPR_PW_max = 610;
end
4'b1011 : begin
tBLPR_PW_min = 690;
tBLPR_PW_max = 710;
end
4'b1100 : begin
tBLPR_PW_min = 790;
tBLPR_PW_max = 810;
end
4'b1101 : begin
tBLPR_PW_min = 890;
tBLPR_PW_max = 910;
end
4'b1110 : begin
tBLPR_PW_min = 990;
tBLPR_PW_max = 1010;
end
4'b1111 : begin
tBLPR_PW_min = 1090;
tBLPR_PW_max = 1110;
end
endcase // case(`TB.TF_SMI_BLPREAD_PW_TB)
reg tBLPW_PW_max_exception; // turn this on for SA modes 6, 9, 10
initial tBLPW_PW_max_exception = 1'b0;
reg tBLPW_PW_min_exception; // turn this on for SA modes 9, 10
initial tBLPW_PW_min_exception = 1'b0;
// DO NOT CHECK PULSE WIDTH FOR mode == 6 as the BLP rises and falls
// together with SA_ENABLE
time effective_blpon_time;
always @(negedge SMI_BLP) begin // if pgpulse_num_set/form are not zero,
count BLP pulse width from the negedge of BLDV
#1;
if (SMI_RXW && ((blpoff_time - blpon_time ) < tBLPR_PW_min) &&
($time > memory_array0.tPOWERON) && memory_array0.checkP
Ws && !`HOST.disable_checkPW)
error_pkg::error("tBLPR_PW_min violated");
if (SMI_RXW && ((blpoff_time - blpon_time) > tBLPR_PW_max) &&
($time > memory_array0.tPOWERON) && memory_array0.checkP
Ws && !`HOST.disable_checkPW)
error_pkg::error("tBLPR_PW_max violated");
// for write it's tricky
if (check_set_mode(16'h0040)) // mode = 6
effective_blpon_time = blswoff_time;
else if (check_set_mode(16'h0200)) // mode = 9
effective_blpon_time = wlswoff_time;
else effective_blpon_time = blpon_time;
if (!SMI_RXW && ((blpoff_time - effective_blpon_time) <
tBLPW_PW_min) &&
!tBLPW_PW_min_exception && !check_set_mode(16'h0
040) &&
($time > memory_array0.tPOWERON) && memory_array
0.checkPWs && !`HOST.disable_checkPW)
error_pkg::error("tBLPW_PW_min violated");
if (!SMI_RXW && ((blpoff_time - effective_blpon_time) >
tBLPW_PW_max) &&
!tBLPW_PW_max_exception && !check_set_mode(16'h0
040) &&
($time > memory_array0.tPOWERON) && memory_array
0.checkPWs && !`HOST.disable_checkPW)
error_pkg::error("tBLPW_PW_max violated");
end
// SFG control MUXES
// Loop counter needed
// rely on blp, bldv, muxsw
int loop_num;
always @(blp_pulse_counter or muxsw_pulse_counter or blsw_pulse_counter)
begin
if (blp_pulse_counter > muxsw_pulse_counter && blp_pulse_counter
> blsw_pulse_counter)
loop_num = blp_pulse_counter;
else if( muxsw_pulse_counter > blsw_pulse_counter)
loop_num = muxsw_pulse_counter;
else
loop_num = blsw_pulse_counter;
if (check_set_mode(16'h0200)) loop_num = blsw_pulse_counter;
else if (check_set_mode(16'h0040)) loop_num = muxsw_pulse_counte
r;
else loop_num = blp_pulse_counter;
//loop_num--; // loop starts from zero
if (loop_num<0) loop_num = 0;
// $display("blp = %0d, muxsw = %0d, blsw = %0d", blp_pulse_counter
, muxsw_pulse_counter, blsw_pulse_counter);
end
always @(posedge SMI_MUX_SWON) begin // when SA_EN is high, mode == 7
if (check_set_mode(16'h0080) && !SMI_RCXSC && !SMI_RXW && muxswo
n_time>= saenon_time && SMI_SA_ENABLE) begin
if (check_form_mode(16'h0080)) begin
if (loop_num == (1<<`TB.TF_SMI_PGPULSE_NUM_FORM_
TB)) begin
wait (!SMI_MUX_SWON); // wait for negedg
e
#1;
if (!in_range(muxswoff_time, 10, muxswon
_time+Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW,0,0))
error_pkg::error("SMI_MUX_SWON p
ulse width violated Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW");
end
end
// if its not form
else if (loop_num == (1<<`TB.TF_SMI_PGPULSE_NUM_SET_TB))
begin
wait (!SMI_MUX_SWON); // wait for negedge
#1;
if (!in_range(muxswoff_time, 10, muxswon_time+Td
ly_SMI_MUXSW_DETECT+tMUX_SWON_PW,0,0))
error_pkg::error("SMI_MUX_SWON pulse wid
th violated Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW");
end
else begin
wait (!SMI_MUX_SWON); // wait for negedge
#1;
if (PR_WRITE_OK) begin
if (!in_range(muxswoff_time, 10, muxswon
_time+Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW,0,0))
error_pkg::error("SMI_MUX_SWON p
ulse width violated Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW");
end
else if(!in_range(muxswoff_time, 10, muxswon_tim
e+Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW+Tdly_SMI_DETECT_BLP+tBLPW_PW_min+10,0,0)) b
egin
$display("blp=%0d, mux=%0d, blsw=%0d", b
lp_pulse_counter , muxsw_pulse_counter , blsw_pulse_counter);
error_pkg::error("SMI_MUX_SWON pulse wid
th violated Tdly_SMI_MUXSW_DETECT+tMUX_SWON_PW+Tdly_SMI_DETECT_BLP+tBLPW_PW");
end
end
end
end
// declaration of mux wires
wire [10:0] smore_mode = {SMI_FORM, SMI_RXW, SMI_RCXSC, SMI_RBRC, SMI_RB
SC, SMI_RBW, SMI_VAW, SMI_RAW, SMI_4VLX2VL, SMI_DIRECT_WR, `TB.TF_SMI_CONCUR_DW_
EN_TB};
reg [2:0] mux1; // SMI_SAVREFA[2:0]
reg [2:0] mux2; // SMI_SAVREFB[2:0]
reg [3:0] mux3; // SMI_SA_ISFGA[3:0]
reg [3:0] mux4; // SMI_SA_ISFGB[3:0]
reg [2:0] mux5;
reg [2:0] mux6;
reg [1:0] mux7;
reg [1:0] mux8;
reg [1:0] mux9;
reg [1:0] mux10;
reg [2:0] mux11, mux11_o, mux11_e; // have all three of them to si
mplify error checking, odd/even only matters in RESET 4VL
reg [2:0] mux12, mux12_o, mux12_e;
reg [1:0] mux13;
reg [1:0] mux14;
reg [2:0] mux15;
reg [2:0] mux16;
reg [1:0] mux17;
reg [1:0] mux18;
reg [1:0] mux19;
reg [1:0] mux20;
task init_all_mux;
begin
mux1 = 'hx;
mux2 = 'hx;
mux3 = 'hx;
mux4 = 'hx;
mux5 = 'hx;
mux6 = 'hx;
mux7 = 'hx;
mux8 = 'hx;
//mux9 = 'hx; // 9 and 10 have to do with zones, need mo
re here
//mux10 = 'hx;
mux11 = 'hx; mux11_o = 'hx; mux11_e = 'hx;// mux11, 12 a
re mostly zero, check sa_smore_interface spreadsheet
mux12 = 'hx; mux12_o = 'hx; mux12_e = 'hx;
mux13 = 'hx;
mux14 = 'hx;
mux15 = 'hx;
mux16 = 'hx;
mux17 = 'hx;
mux18 = 'hx;
mux19 = 'hx;
mux20 = 'hx;
end
endtask
wire [8:0] grow = `MA.SMI_GRAD_in;
always @(grow) begin
// if smore mode is not reset mode, make mux9/mux10 dont-cares
if (smore_mode != 11'b00100000000 && // RST 2VL
smore_mode != 11'b00100000001 &&
smore_mode != 11'b00100000010 &&
smore_mode != 11'b00100000100 && // RST 4vl
smore_mode != 11'b00100000101 &&
smore_mode != 11'b00100000110 &&
smore_mode != 11'b00x00000011 // concurrent write set/re
set
) begin
//$display("shouldn't be here for pwm");
mux9 = 'hx;
mux10 = 'hx;
end
end
always @(*)
case (`TB.SMI_ZONE)
2'b00 : begin
mux9 = `TB.TF_SMI_SASFG_NEAR_TB;
mux10 = `TB.TF_SMI_SASFG_FAR_TB;
end
2'b01 : begin
mux9 = `TB.TF_SMI_SASFG_NEARMID_TB;
mux10 = `TB.TF_SMI_SASFG_MIDFAR_TB;
end
2'b10 : begin
mux9 = `TB.TF_SMI_SASFG_MIDFAR_TB;
mux10 = `TB.TF_SMI_SASFG_NEARMID_TB;
end
2'b11 : begin
mux9 = `TB.TF_SMI_SASFG_FAR_TB;
mux10 = `TB.TF_SMI_SASFG_NEAR_TB;
end
endcase
always @(smore_mode or grow) begin
#1;
if (SMI_STDBY) wait(!SMI_STDBY);
#20; // more delay for gatesim
// Default all muxes to zero for the sake of calculation
init_all_mux();
casex (smore_mode)
11'b01x00000xxx: begin // READ
mux1 = `TB.TF_SMI_SAVREF_RD_TB;
mux3 = `TB.TF_SMI_IRD_TB;
mux5 = `TB.TF_SMI_VRD_TB;
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b10000000xxx: begin // FORM
mux1 = `TB.TF_SMI_SAVREF_SET_TB;
mux3 = `TB.TF_SMI_ISET_TB;
mux5 = `TB.TF_SMI_VFORM_TB[2:0];
mux7 = `TB.TF_SMI_VSET_STEP_TB[1:0];
mux11 = 0;
mux13 = `TB.TF_SMI_VSET_RAMPSPEED_TB;
mux15 = `TB.TF_SMI_ISFG_SET_X_TB;
mux17 = `TB.TF_SMI_SA_VREF_SEL_FORM_TB;
mux18 = `TB.TF_SMI_SA_VREF_SEL_FORM_TB;
mux19 = `TB.TF_SMI_SA_VSFG_SEL_FORM_TB;
mux20 = `TB.TF_SMI_SA_VSFG_SEL_FORM_TB;
end
11'b01100100x00,// RBW_RST
11'b01100100x01,
11'b01100100x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01110000100, // RBRST
11'b01110000101,
11'b01110000110: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b00100000000, // RST 2VL
11'b00100000001,
11'b00100000010: begin
mux2 = `TB.TF_SMI_SAVREF_RST_TB;
mux4 = `TB.TF_SMI_IRST_TB;
mux6 = `TB.TF_SMI_VRST_TB;
mux8 = `TB.TF_SMI_VRST_STEP_TB;
mux12_o = {1'b0,mux9};
mux12_e = {1'b0, mux10};
mux14 = `TB.TF_SMI_VRST_RAMPSPEED_TB;
mux16 = `TB.TF_SMI_ISFG_RST_X_TB;
mux17 = `TB.TF_SMI_SA_VREF_SEL_RST_TB;
mux19 = `TB.TF_SMI_SA_VSFG_SEL_RST_TB;
end
11'b00100000100, // RST 4vl
11'b00100000101,
11'b00100000110: begin
mux1 = `TB.TF_SMI_SAVREF_RSTB_TB;
mux2 = `TB.TF_SMI_SAVREF_RSTA_TB;
mux5 = `TB.TF_SMI_VRSTB_TB;
mux6 = `TB.TF_SMI_VRSTA_TB;
mux11_o = {1'b0, mux9};
mux11_e = {1'b0, mux10};
mux12_o = {1'b0, mux9};
mux12_e = {1'b0, mux10};
end
11'b01100010x00, // VAW_RST
11'b01100010x01,
11'b01100010x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01100001x00, // RAW_RST
11'b01100001x01,
11'b01100001x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01000100x00, // RBW_SET
11'b01000100x01,
11'b01000100x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01001000100, // RBSET
11'b01001000101,
11'b01001000110: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b00000000000, // SET 2VL
11'b00000000001,
11'b00000000010: begin
mux1 = `TB.TF_SMI_SAVREF_SET_TB;
mux5 = `TB.TF_SMI_VSET_TB;
mux7 = `TB.TF_SMI_VSET_STEP_TB;
mux11 = 0;
mux17 = `TB.TF_SMI_SA_VREF_SEL_SET_TB;
mux19 = `TB.TF_SMI_SA_VSFG_SEL_SET_TB;
end
11'b00000000100, // SET 4VL
11'b00000000101,
11'b00000000110: begin
mux1 = `TB.TF_SMI_SAVREF_SETB_TB;
mux2 = `TB.TF_SMI_SAVREF_SETA_TB;
mux5 = `TB.TF_SMI_VSETB_TB;
mux6 = `TB.TF_SMI_VSETA_TB;
mux11 = 0;
end
11'b01000010x00, // VAW_SET
11'b01000010x01,
11'b01000010x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01000001x00, // RAW_SET
11'b01000001x01,
11'b01000001x10: begin
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01x00100x11: begin // RBW_SET/RST
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b00x00000011: begin // SET/RESET
mux1 = `TB.TF_SMI_SAVREF_SET_CDW_TB;
mux2 = `TB.TF_SMI_SAVREF_RST_TB;
mux5 = `TB.TF_SMI_VSET_CDW_TB;
mux6 = `TB.TF_SMI_VRST_CDW_TB;
mux11 = 0;
mux12_o = {1'b0, mux9};
mux12_e = {1'b0, mux10};
end
11'b01x00010x11: begin // VAW_SET/RESET
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
11'b01x00001x11: begin // RAW_SET/RESET
mux7 = 0;
mux11 = 0;
mux15 = 0;
mux16 = 0;
mux17 = 2'b10;
mux18 = 2'b10;
mux19 = 2'b10;
mux20 = 2'b10;
end
default:
error_pkg::error("Undefined SMORE mode");
endcase
end
// mux1,2,3,4 checkers
if (SMI_SA_VREFA != mux1)
error_pkg::error("SMI_SA_VREFA is not equal to mux1");
if (SMI_SA_VREFB != mux2)
error_pkg::error("SMI_SA_VREFB is not equal to mux2");
if (SMI_SA_ISFGA != mux3)
error_pkg::error("SMI_SA_ISFGA is not equal to mux3");
if (SMI_SA_ISFGB != mux4)
error_pkg::error("SMI_SA_ISFGB is not equal to mux4");
end
// SMI_SA_SFGVA checker, maximum = 7,
// SMI_SA_SFGVA_EDGE checker
wire [3:0] retry_num = `TB.smore0.bec_sw_retry_cnt[3:0];
always @(retry_num or SMI_SA_ENABLE) begin
ìfdef GATE_SIM
#5; // for signals to finish transition in gatesim
èndif
if (smore_mode != 11'b00100000000 && smore_mode != 11'b001000000
01 && smore_mode != 11'b00100000010 ) begin
if ((mux5 + mux11_o + mux7 * retry_num > 7 ? SMI_SA_SFGV
A_O != 7 : SMI_SA_SFGVA_O != mux5 + mux11_o + mux7 * retry_num ) && SMI_SA_ENAB
LE) begin
error_pkg::error(" ");
$display("sfgva_o=%0d, mux5=%0d, mux7=%0d, mux11
_o=%0d, loop=%0d", SMI_SA_SFGVA_O, mux5, mux7, mux11_o, retry_num);
end
if ((mux5 + mux11_e + mux7 * retry_num > 7 ? SMI_SA_SFGV
A_E != 7 : SMI_SA_SFGVA_E != mux5 + mux11_e + mux7 * retry_num ) && SMI_SA_ENAB
LE) begin
$display("sfgva_e=%0d, mux5=%0d, mux7=%0d, mux11
_e=%0d, loop=%0d", SMI_SA_SFGVA_E, mux5, mux7, mux11_e, retry_num);
end
end
// for cap-discharge scheme, set = 4 to 10, reset = 4, 5
if (check_set_mode(16'h07f0) || check_reset_mode(8'h30)) begin
if (SMI_BLKAD[5]) begin
if (((SMI_SA_SFGVA_O > `TB.TF_SMI_VSET_EDGE_TB) ?
(SMI_SA_SFGVA_O_EDGE != (SMI_SA_SFGVA_O - `TB.TF_SMI
_VSET_EDGE_TB)) :
(SMI_SA_SFGVA_O_EDGE != 0)) && SMI_SA_ENABLE) begin
$display("cap-discharge mode: sfgva_o_edge=%0d, sfgva_o
=%0d, TF_SMI_VSET_EDGE=%0d BLKAD5=%b (1)",
SMI_SA_SFGVA_O_EDGE, SMI_SA_SFGVA_O, `TB.TF_S
MI_VSET_EDGE_TB, SMI_BLKAD[5]);
end
if ((SMI_SA_SFGVA_E_EDGE != SMI_SA_SFGVA_E) && SMI_SA_ENAB
LE) begin
$display("cap-discharge mode: sfgva_e_edge=%0d, sfgva_
e=%0d, TF_SMI_VSET_EDGE=%0d BLKAD5=%b (2)",
SMI_SA_SFGVA_E_EDGE, SMI_SA_SFGVA_E, `TB.TF_
SMI_VSET_EDGE_TB, SMI_BLKAD[5]);
end
end else begin
if ((SMI_SA_SFGVA_O_EDGE != SMI_SA_SFGVA_O) && S
MI_SA_ENABLE) begin
$display("cap-discharge mode: sfgva_o_edge=%0d, sfgva_o
=%0d, TF_SMI_VSET_EDGE=%0d BLKAD5=%b (2)",
SMI_SA_SFGVA_O_EDGE, SMI_SA_SFGVA_O, `TB.TF_S
MI_VSET_EDGE_TB, SMI_BLKAD[5]);
end
if (((SMI_SA_SFGVA_E > `TB.TF_SMI_VSET_EDGE_TB) ?
(SMI_SA_SFGVA_E_EDGE != (SMI_SA_SFGVA_E - `TB.TF_SM
I_VSET_EDGE_TB)) :
(SMI_SA_SFGVA_E_EDGE != 0)) && SMI_SA_ENABLE) begin
$display("cap-discharge mode: sfgva_e_edge=%0d, sfgva_
e=%0d, TF_SMI_VSET_EDGE=%0d BLKAD5=%b (1)",
SMI_SA_SFGVA_E_EDGE, SMI_SA_SFGVA_E, `TB.TF_
SMI_VSET_EDGE_TB, SMI_BLKAD[5]);
end
end
end
end
// SMI_SA_SFGVB checker, maximum = 7, only checks SET for now
// SMI_SA_SFGVB_EDGE checker
always @(retry_num or SMI_SA_ENABLE) begin
ìfdef GATE_SIM
#5; // for signals to finish transition in gatesim
èndif
if (smore_mode != 11'b00100000000 && smore_mode != 11'b001000000
01 && smore_mode != 11'b00100000010 ) begin
if ((mux6 + mux12_o + mux8 * retry_num > 7 ? SMI_SA_SFGV
B_O != 7 : SMI_SA_SFGVB_O != mux6 + mux12_o + mux8 * retry_num ) && SMI_SA_ENAB
LE) begin
$display("sfgvb_o=%0d, mux6=%0d, mux8=%0d, mux12
_o=%0d, loop=%0d", SMI_SA_SFGVB_O, mux6, mux8, mux12_o, retry_num);
end
if ((mux6 + mux12_e + mux8 * retry_num > 7 ? SMI_SA_SFGV
B_E != 7 : SMI_SA_SFGVB_E != mux6 + mux12_e + mux8 * retry_num ) && SMI_SA_ENAB
LE) begin
$display("sfgvb_e=%0d, mux6=%0d, mux8=%0d, mux12
_e=%0d, loop=%0d", SMI_SA_SFGVB_E, mux6, mux8, mux12_e, retry_num);
end
end
// for cap-discharge scheme, set = 4 to 10, reset = 4, 5
if (check_set_mode(16'h07f0) || check_reset_mode(8'h30)) begin
if (SMI_BLKAD[5]) begin
if (((SMI_SA_SFGVB_O > `TB.TF_SMI_VRST_EDGE_TB) ?
(SMI_SA_SFGVB_O_EDGE != (SMI_SA_SFGVB_O - `TB.TF_SMI
_VRST_EDGE_TB)) :
(SMI_SA_SFGVB_O_EDGE != 0)) && SMI_SA_ENABLE) begin
$display("cap-discharge mode: sfgvb_o_edge=%0d, sfgvb_o
=%0d, TF_SMI_VRST_EDGE=%0d BLKAD5=%b (1)",
SMI_SA_SFGVB_O_EDGE, SMI_SA_SFGVB_O, `TB.TF_S
MI_VRST_EDGE_TB, SMI_BLKAD[5]);
end
if ((SMI_SA_SFGVB_E_EDGE != SMI_SA_SFGVB_E) && SMI_SA_ENAB
LE) begin
$display("cap-discharge mode: sfgvb_e_edge=%0d,
sfgvb_e=%0d, TF_SMI_VRST_EDGE=%0d BLKAD5=%b (2)",
SMI_SA_SFGVB_E_EDGE, SMI_SA_SFGVB_E, `TB.TF_
SMI_VRST_EDGE_TB, SMI_BLKAD[5]);
end
end else begin
if ((SMI_SA_SFGVB_O_EDGE != SMI_SA_SFGVB_O) &&
SMI_SA_ENABLE) begin
$display("cap-discharge mode: sfgvb_o_edge=%0d, sfgvb_o
=%0d, TF_SMI_VRST_EDGE=%0d BLKAD5=%b (2)",
SMI_SA_SFGVB_O_EDGE, SMI_SA_SFGVB_O, `TB.TF_S
MI_VRST_EDGE_TB, SMI_BLKAD[5]);
end
if (((SMI_SA_SFGVB_E > `TB.TF_SMI_VRST_EDGE_TB) ?
(SMI_SA_SFGVB_E_EDGE != (SMI_SA_SFGVB_E - `TB.TF_SM
I_VRST_EDGE_TB)) :
(SMI_SA_SFGVB_E_EDGE != 0)) && SMI_SA_ENABLE) begin
$display("cap-discharge mode: sfgvb_e_edge=%0d, sfgvb_
e=%0d, TF_SMI_VRST_EDGE=%0d BLKAD5=%b (1)",
SMI_SA_SFGVB_E_EDGE, SMI_SA_SFGVB_E, `TB.TF_
SMI_VRST_EDGE_TB, SMI_BLKAD[5]);
end
end
end
end
// mux15, 16 checker
// isfga_2x
if (mux15 === 0 && SMI_SA_ISFGA_2X != 0)
error_pkg::error("SMI_SA_ISFGA_2X is not low when mux15
is all zero");
else if (mux15 != 0 && SMI_SA_ISFGA_2X != 1)
error_pkg::error("SMI_SA_ISFGA_2X is not high when mux15
is not zero");
// isfga_4x
if (mux15 < 2 && SMI_SA_ISFGA_4X != 0)
< 2");
else if (mux15 >= 2 && SMI_SA_ISFGA_4X != 1)
error_pkg::error("SMI_SA_ISFGA_4X is not HIGH when mux15
>= 2");
// isfga_8x
< 3");
>= 3");
// isfga_16x
< 4");
5 >= 4");
// isfga_2x
if (mux16 === 0 && SMI_SA_ISFGB_2X != 0)
error_pkg::error("SMI_SA_ISFGB_2X is not low when mux16
is all zero");
else if (mux16 != 0 && SMI_SA_ISFGB_2X != 1)
error_pkg::error("SMI_SA_ISFGB_2X is not high when mux16
is not zero");
// isfga_4x
if (mux16 < 2 && SMI_SA_ISFGB_4X != 0)
< 2");
else if (mux16 >= 2 && SMI_SA_ISFGB_4X != 1)
error_pkg::error("SMI_SA_ISFGB_4X is not HIGH when mux16
>= 2");
// isfga_8x
< 3");
>= 3");
// isfga_16x
< 4");
6 >= 4");
end
// mux17, 18, 19, 20
if (mux17 != SMI_SA_VREFA_SEL)
error_pkg::error("SMI_SA_VREFA_SEL is not equal to mux17
");
if (mux18 != SMI_SA_VREFB_SEL)
error_pkg::error("SMI_SA_VREFB_SEL is not equal to mux18
");
if (mux19 != SMI_SA_VSFGA_SEL)
error_pkg::error("SMI_SA_VSFGA_SEL is not equal to mux19
");
if (mux20 != SMI_SA_VSFGB_SEL)
error_pkg::error("SMI_SA_VSFGB_SEL is not equal to mux20
");
end
//////////////////////////////////////////////////////////////////////
// SMI_DIRECT_WR checkers for VAW
/////////////////////////////////////////////////////////////////////
reg pg_dw;
initial pg_dw = 1'b0;
pg_dw = 1'b0;
always @(posedge smore0.cenc_full_prog)
pg_dw = 1'b0;
ìfdef GATE_SIM
èlse
èndif
begin
if (smore0.cenc_full_prog)
full_prog = 1'b1;
else
full_prog = 1'b0;
end
always @(posedge SMI_DIRECT_WR)
pg_dw = 1'b1;
always @(posedge `HOST.disable_checkPW)
pg_dw = 1'b0;
always @(posedge `HOST.reset_busy)
pg_dw = 1'b0;
reg double_vaw_exception;
initial double_vaw_exception = 1'b0;
#200;
if (SMI_DOUBLE_VAW &&
!(pg_dw && `TB.TF_SMI_DOUBLEVAW_EN_TB) && !double_vaw_exception)
error_pkg::error("SMI_DOUBLE_VAW is not expected to be high");
else if (!SMI_DOUBLE_VAW &&
(pg_dw && `TB.TF_SMI_DOUBLEVAW_EN_TB) && !double_vaw_exception)
error_pkg::error("SMI_DOUBLE_VAW is expected to be high");
end
#10;
if (SMI_VAW === 1'b1) begin
if (pg_dw && !`TB.TF_SMI_DOUBLEVAW_EN_TB) begin
#200;
if (!SMI_DIRECT_WR && !`HOST.reset_busy && !`HOST.disable_checkPW)
error_pkg::error("direct write and single VAW but SMI_DIRECT_WR
is not high");
if ((SMI_VUXRDMS || SMI_VUXRDMR) && !`HOST.reset_busy && !`HOST.di
sable_checkPW)
error_pkg::error("SMI_VUXRD* not expected high - 3");
pg_dw = 1'b0;
end
else begin
#200;
if (SMI_DIRECT_WR && !pg_dw && !`HOST.reset_busy && !`HOST.disable
_checkPW)
error_pkg::error("SMI_DIRECT_WR is not expected high in this VA
W (1)");
if (`TB.TF_SMI_VAW_NOMARGIN_TB) begin
if (SMI_VUXRDMS || SMI_VUXRDMR) begin
$display("SMI_VAW = %b", SMI_VA
W);
end
end
else begin
if (SMI_RCXSC) begin
if (!SMI_VUXRDMR && !`HOST.disable_checkPW)
error_pkg::error("SMI_VUXRDR expected high");
if (SMI_VUXRDMS)
error_pkg::error("SMI_VUXRDS not expected high - 5");
end
else begin
if (!SMI_VUXRDMS && !`HOST.disable_checkPW)
error_pkg::error("SMI_VUXRDS expected high");
if (SMI_VUXRDMR)
error_pkg::error("SMI_VUXRDR not expected high - 6");
end
end
if (`TB.TF_SMI_DOUBLEVAW_EN_TB && pg_dw) begin
wait (SMI_VAW == 1'b0);
wait (SMI_VAW == 1'b1);
#1000;
if (SMI_DIRECT_WR && `TB.TF_SMI_DOUBLEVAW_EN_TB) begin
error_pkg::error("SMI_DIRECT_WR is not expected high in this
VAW (2)");
$display("%t: `TB.TF_SMI_DOUBLEVAW_EN_TB = %b",
$time, `TB.TF_SMI_DOUBLEVAW_EN_TB);
end
if (`TB.TF_SMI_VAW_NOMARGIN_TB) begin
if (SMI_VUXRDMS || SMI_VUXRDMR)
end
else begin
if (SMI_RCXSC) begin
if (!SMI_VUXRDMR && !`HOST.disable_checkPW)
error_pkg::error("SMI_VUXRDR expected high");
if (SMI_VUXRDMS)
error_pkg::error("SMI_VUXRDS not expected high - 1");
end
else begin
if (!SMI_VUXRDMS && !`HOST.disable_checkPW)
error_pkg::error("SMI_VUXRDS expected high");
if (SMI_VUXRDMR)
error_pkg::error("SMI_VUXRDR not expected high - 2");
end
end
end
pg_dw = 1'b0;
end
end
end
////////////////////////////////////////////////////////////////////////
// SMI_ERASE checker
////////////////////////////////////////////////////////////////////////
if(!SMI_RXW && smore0.cenc_erase_mode) begin
#10;
if(`TB.TF_SMI_RESET_IS_ERASE_TB) begin
if(SMI_RCXSC && !SMI_ERASE)
error_pkg::error("SMI_ERASE not high in erase mode");
end
else begin
if(!SMI_RCXSC && !SMI_ERASE)
error_pkg::error("SMI_ERASE not high in erase mode");
end
end
else begin
if(SMI_ERASE && !smore0.cenc_erase_mode)
error_pkg::error("SMI_ERASE not expected high ");
end
end
////////////////////////////////////////////////////////////////////////
// SA_ENABLE and DR_ER_OFF checker
////////////////////////////////////////////////////////////////////////
always @(SMI_SA_ENABLE or SMI_DR_ER_OFF) begin
#10;
if(SMI_SA_ENABLE && SMI_DR_ER_OFF)
error_pkg::error("SMI_SA_ENABLE and SMI_DR_ER_OFF both high");
end
////////////////////////////////////////////////////////////////////////
// PR DEEPSLEEP checkers
////////////////////////////////////////////////////////////////////////
always @ (posedge YYDEEPSLEEP) begin
#18;
if (!SMI_TL_RXW)
error_pkg::error("wrong value of SMI_TL_RXW during DEEPSLEEP");
if (`TB.TF_SMI_ENABLE_PROFF_TB) begin
if ( !SMI_DR_ER_OFF)
error_pkg::error("wrong value of SMI_DR_ER_OFF during DEEPSLEEP
");
if ( !SMI_SHR_OFF)
error_pkg::error("wrong value of SMI_SHR_OFF during DEEPSLEEP")
;
end
else if (!`TB.TF_SMI_ENABLE_PROFF_TB) begin
if (SMI_DR_ER_OFF)
error_pkg::error("wrong value of SMI_DR_ER_OFF during DEEPSLEEP
");
if (SMI_SHR_OFF)
error_pkg::error("wrong value of SMI_SHR_OFF during DEEPSLEEP")
;
end
end
////////////////////////////////////////////////////////////////////////
// PR STDBY checkers - translated into "end of cycle plus after reset
// plus after POR" instead of STDBY
////////////////////////////////////////////////////////////////////////
always @(negedge SMI_CLKEN or
posedge SP_XPOR_GLOBAL or negedge smore0.cenc_por_mode) begin
#45;
if (SMI_CAD_ARYOP[5:1] != 5'h10)
error_pkg::error("wrong value of SMI_CAD_ARYOP during STDBY");
ìfndef GATE_SIM
if ((SMI_PR_ADR_TOP[11:6] != 6'h21) && !smore0.cenc_ppc_acc)
error_pkg::error("wrong value of SMI_PR_ADR_TOP during STDBY");
if ((SMI_PR_ADR_BOT[11:6] != 6'h21) && !smore0.cenc_ppc_acc)
error_pkg::error("wrong value of SMI_PR_ADR_BOT during STDBY");
èndif
if ({SMI_SPARE_EN, SMI_CAD[4:0]} != 6'h22 && ~SMI_CLKEN && SMI_DR_ER_
OFF && `TB.TF_SMI_ENABLE_PROFF_TB)
error_pkg::error("wrong value of {SMI_SPARE_EN,SMI_CAD} during STD
BY");
if (((SMI_DR_00_TOP || SMI_DR_00_BOT) && !`TB.TF_SMI_DR_00_TMCR) ||
((SMI_DR_FF_TOP || SMI_DR_FF_BOT) && !`TB.TF_SMI_DR_FF_TMCR && `T
B.SP_XPOR_GLOBAL))
error_pkg::error("wrong value of SMI_DR_FF/00_TOP/BOT during STDBY
");
if (((SMI_SHR_00_TOP || SMI_SHR_00_BOT) && !`TB.TF_SMI_SHR_00_TMCR) |
|
((SMI_SHR_FF_TOP || SMI_SHR_FF_BOT) && !`TB.TF_SMI_SHR_FF_TMCR &&
`TB.SP_XPOR_GLOBAL))
if (!SMI_RXBOUT) // discard shr 00/ff in cache ready
error_pkg::error("wrong value of SMI_SHR_FF/00_TOP/BOT during S
TDBY");
if (SMI_DRSHR_COPY_TOP || SMI_DRSHR_COPY_BOT)
error_pkg::error("wrong value of SMI_DRSHR_COPY_TOP/BOT during STD
BY");
if (SMI_SHRDR_COPY_TOP || SMI_SHRDR_COPY_BOT)
error_pkg::error("wrong value of SMI_SHRDR_COPY_TOP/BOT during STD
BY");
if (((SMI_ER_UA_00_TOP || SMI_ER_UA_00_BOT) && !`TB.TF_SMI_ER_UA_00_T
MCR) ||
((SMI_ER_UA_FF_TOP || SMI_ER_UA_FF_BOT) && !`TB.TF_SMI_ER_UA_FF_T
MCR && `TB.SP_XPOR_GLOBAL) ||
((SMI_ER_FC_00_TOP || SMI_ER_FC_00_BOT) && !`TB.TF_SMI_ER_FC_00_T
MCR) ||
((SMI_ER_FC_FF_TOP || SMI_ER_FC_FF_BOT) && !`TB.TF_SMI_ER_FC_FF_T
MCR && `TB.SP_XPOR_GLOBAL))
error_pkg::error("wrong value of SMI_ER_FF/00_UA/FC_TOP/BOT during
STDBY");
if (SMI_DR_ACC && ! `TB.TF_SMI_DR_ACC_TMCR)
error_pkg::error("wrong value of SMI_DR_ACC during STDBY");
if ( SMI_ER_ACC )
error_pkg::error("wrong value of SMI_ER_ACC during STDBY");
if ( SMI_TL_RXW != 2'b11 && ~SMI_CLKEN )
error_pkg::error("wrong value of SMI_TL_RXW during STDBY");
if ( SMI_SAEXWDATA )
error_pkg::error("wrong value of SMI_SAEXWDATA during STDBY");
if ( SMI_TL_CPY )
error_pkg::error("wrong value of SMI_TL_CPY during STDBY");
if ( SMI_RL_INIT )
error_pkg::error("wrong value of SMI_RL_INIT during STDBY");
if ( SMI_CHECK )
error_pkg::error("wrong value of SMI_CHECK during STDBY");
if ( SMI_SA_ENABLE )
error_pkg::error("wrong value of SMI_SA_ENABLE during STDBY");
if ( SMI_PGAD[0] )
error_pkg::error("wrong value of SMI_PGAD[0] during STDBY");
if ( SMI_BAYE !='h00 )
error_pkg::error("wrong value of SMI_BAYE during STDBY");
if ( !SMI_DR_ER_ARYOP && !`TB.TF_SMI_DR_ACC_TMCR && !`TB.TF_SMI_ER_A
CC_TMCR
&& !`TB.TF_SMI_ENABLE_PROFF_TB)
error_pkg::error("wrong value of SMI_DR_ER_ARYOP during STDBY");
ìfndef GATE_SIM
if ( !SMI_DR_ER_OFF && SMI_RXBOUT && `TB.TF_SMI_ENABLE_PROFF_TB
&& !(smore0.central_ctrl0.cache_mode
|| smore0.if_ctrl0.read_cache_mode
|| smore0.if_ctrl0.write_cache_mode)
)
error_pkg::error("wrong value of SMI_DR_ER_OFF during STDBY");
èndif
if ( SMI_DR_ER_OFF && !`TB.TF_SMI_ENABLE_PROFF_TB )
error_pkg::error("wrong value of SMI_DR_ER_OFF during STDBY");
if ( SMI_SHR_ARYOP )
error_pkg::error("wrong value of SMI_SHR_ARYOP during STDBY");
if ( SMI_SHR_OFF )
error_pkg::error("wrong value of SMI_SHR_OFF during STDBY");
if ( SMI_RD2SHR )
error_pkg::error("wrong value of SMI_RD2SHR during STDBY");
ìfndef GATE_SIM
if ( SMI_RD2ER && !smore0.central_ctrl0.cenc_pgbf_shr_wr_pending)
error_pkg::error("wrong value of SMI_RD2ER during STDBY");
èndif
if ( !SMI_RXW )
error_pkg::error("wrong value of SMI_RXW during STDBY");
if (SMI_VAW )
error_pkg::error("wrong value of SMI_VAW during STDBY");
if ( SMI_RAW )
error_pkg::error("wrong value of SMI_RAW during STDBY");
if ( SMI_ERASE )
error_pkg::error("wrong value of SMI_ERASE during STDBY");
if ( SMI_DIRECT_WR )
error_pkg::error("wrong value of SMI_DIRECT_WR during STDBY");
if ( SMI_TRIM_LATCH_EN && !smore0.cenc_por_mode && !smore0.bist_ctrl0
.bist_state[15])
error_pkg::error("wrong value of SMI_TRIM_LATCH_EN during STDBY");
if ( SMI_RBRC )
error_pkg::error("wrong value of SMI_RBRC during STDBY");
if ( SMI_RBSC )
error_pkg::error("wrong value of SMI_RBSC during STDBY");
if ( SMI_4VLX2VL )
error_pkg::error("wrong value of SMI_4VLX2VL during STDBY");
if ( SMI_SWRTR_FLOW )
error_pkg::error("wrong value of SMI_SWRTR_FLOW during STDBY");
if ( SMI_FINAL_RTR )
error_pkg::error("wrong value of SMI_FINAL_RTR during STDBY");
if ( SMI_PR_R2R_ACM_WE && !`TB.TF_SMI_PR_R2R_ACM_WE_TMCR )
error_pkg::error("wrong value of SMI_PR_R2R_ACM_WE during STDBY");
if ( SMI_PR_ACM_EN && SMI_RXBOUT)
error_pkg::error("wrong value of SMI_PR_ACM_EN during STDBY");
if ( SMI_PR_R2R_ACM_EN && SMI_RXBOUT)
error_pkg::error("wrong value of SMI_PR_R2R_ACM_EN during STDBY");
end
always @(posedge SMI_DR_ER_OFF) begin
#10;
if (SMI_DR_ER_OFF === 1'b1 && !`TB.TF_SMI_ENABLE_PROFF_TB)
error_pkg::error("SMI_DR_ER_OFF high when TF_SMI_ENABLE_PROFF_TB low");
end
always @(posedge SMI_SHR_OFF) begin
#10;
if (SMI_SHR_OFF === 1'b1 && !`TB.TF_SMI_ENABLE_PROFF_TB)
error_pkg::error("SMI_SHR_OFF high when TF_SMI_ENABLE_PROFF_TB low");
end
always @(SMI_CAD or SMI_SPARE_EN or SMI_DR_ER_OFF) begin
#20;
if (SMI_DR_ER_OFF) begin
if ({SMI_SPARE_EN, SMI_CAD[4:0]} != 6'h22)
error_pkg::error("wrong SMI_SPARE_EN or SMI_CAD value when SMI_DR_ER
_OFF is high");
end
if (!SMI_DR_ER_OFF) begin
if ({SMI_SPARE_EN, SMI_CAD[4:0]} >= 6'h22)
error_pkg::error("wrong SMI_SPARE_EN or SMI_CAD value when SMI_DR_ER
_OFF is low");
end
end
always @(SMI_PR_ADR_TOP[11:6] or SMI_SHR_OFF) begin
#20;
if (SMI_SHR_OFF) begin
if (SMI_PR_ADR_TOP[11:7]!= 5'h11)
error_pkg::error("wrong SMI_PR_ADR_TOP[11:6] value when SMI_SHR_OFF
is high");
if (SMI_PR_ADR_BOT[11:7]!= 5'h11)
error_pkg::error("wrong SMI_PR_ADR_BOT[11:6] value when SMI_SHR_OFF
is high");
end
if (!SMI_SHR_OFF) begin
if (SMI_PR_ADR_TOP[11:6]>= 6'h22)
error_pkg::error("wrong SMI_PR_ADR_TOP[11:6] value when SMI_SHR_OFF
is low");
if (SMI_PR_ADR_BOT[11:6]>= 6'h22)
error_pkg::error("wrong SMI_PR_ADR_BOT[11:6] value when SMI_SHR_OFF
is low");
end
end
always @ (SMI_DR_ER_ARYOP or SMI_SHR_ARYOP or SMI_PR_RXW or SMI_TL_RXW) begin
#10;
if (SMI_DR_ER_ARYOP && SMI_SHR_ARYOP && SMI_PR_RXW)
error_pkg::error("wrong SMI_PR_RXW value when both SMI_SHR_ARYOP and
SMI_DR_ER_ARYOP are high");
if (!SMI_DR_ER_ARYOP && !SMI_SHR_ARYOP && (SMI_TL_RXW[1:0] != 2'b11))
error_pkg::error("wrong SMI_TL_RXW value when both SMI_SHR_ARYOP and
SMI_DR_ER_ARYOP are low");
end
////////////////////////////////////////////////////////////////////
// SAD_ARYOP checkers
////////////////////////////////////////////////////////////////////
time SAD_change, FLOAT_change;
always @(SMI_SAD_ARYOP) begin
SAD_change = $time;
if ($time - FLOAT_change < 10 && $time > 500)
error_pkg::error("SAD_ARYOP change too close to FLOAT change");
end
always @(SMI_FLOAT) begin
FLOAT_change = $time;
if ($time - SAD_change < 85 && $time > 500)
error_pkg::error("tSAD_FLOAT violation");
end
////////////////////////////////////////////////////////////////////
// FINAL_RTR checkers
////////////////////////////////////////////////////////////////////
reg final_rtr_rose;
initial final_rtr_rose = 1'b0;
reg final_rtr_exception;
initial final_rtr_exception = 1'b0;
always @(negedge SMI_SWRTR_FLOW) begin
if (!final_rtr_rose && ($time > `MA.tPOWERON) && ! final_rtr_exception &&
!`HOST.reset_busy && !`HOST.disable_checkPW)
error_pkg::error("SMI_FINAL_RTR didn't rise for SW_RTR_FLOW");
final_rtr_rose = 1'b0;
end
always @(posedge SMI_FINAL_RTR) begin
final_rtr_rose = 1'b1;
#100;
if (!SMI_SWRTR_FLOW && !SMI_RXW)
error_pkg::error("unexpected SMI_FINAL_RTR during non-SW_RTR_FLOW");
end
////////////////////////////////////////////////////////////////////
// SMI_PR_CNTLIMIT checkers
////////////////////////////////////////////////////////////////////
reg form_rose;
initial form_rose = 1'b0;
always @(posedge SMI_FORM)
form_rose = 1'b1;
always @(negedge SMI_VAW)
form_rose = 1'b0;
if ((SMI_VAW||!SMI_RXW) && !SMI_DIRECT_WR) begin
if (form_rose &&
SMI_PR_CNTLIMIT != `TB.TF_SMI_FORM_ER_LIMIT_TB)
error_pkg::error("unexpected SMI_PR_CNTLIMIT (1)");
if (SMI_RCXSC &&
SMI_PR_CNTLIMIT != `TB.TF_SMI_RST_ER_LIMIT_TB)
if (!SMI_RCXSC && !form_rose &&
SMI_PR_CNTLIMIT != `TB.TF_SMI_SET_ER_LIMIT_TB)
end
if (SMI_VAW && SMI_DIRECT_WR) begin

if (SMI_PR_CNTLIMIT !=
`TB.TF_SMI_RST_ER_LIMIT_TB+`TB.TF_SMI_SET_ER_LIMIT_TB)
end
if (SMI_RAW &&
SMI_PR_CNTLIMIT != `TB.TF_SMI_RAW_ER_LIMIT_TB) begin
end
end
////////////////////////////////////////////////////////////////////
// SMI_SWRTR_FLOW checkers
////////////////////////////////////////////////////////////////////
reg dw_mode;
initial dw_mode = 1'b0;
ìfdef GATE_SIM
begin
#15;
if (smore0.central_ctrl0.cenc_dw_reg.Q)
dw_mode = 1'b1;
else
dw_mode = 1'b0;
end
èlse
begin
#15;
if (smore0.cenc_dw)
dw_mode = 1'b1;
else
dw_mode = 1'b0;
end
èndif
wire rcxsc = smore0.bec_erase_mode ^ !`TB.TF_SMI_RESET_IS_ERASE_TB;
wire pwm_mode = `TB.TF_SA_RST_TB == 3'b010 && rcxsc;
wire expect_swrtr = (`TB.TF_SMI_SW_RETRY_LIMIT_TB != 4'h0) &&
(pwm_mode || !dw_mode && (smore0.bec_form_mode ? `TB.TF_S
MI_SMART_FORM_EN_TB :
rcxsc ? `TB.TF_SMI_SMART_RESET
_EN_TB :
`TB.TF_SMI_SMART_SET_E
N_TB));
if (expect_swrtr && (!SMI_RXW || SMI_VAW) && !SMI_SWRTR_FLOW &&
!`MA.cdchg_mode && !smore0.cenc_do_reset && !full_prog)
error_pkg::error("SMI_SWRTR_FLOW expected to be high");
if (!expect_swrtr && SMI_SWRTR_FLOW &&
!`MA.cdchg_mode && !smore0.cenc_do_reset)
error_pkg::error("SMI_SWRTR_FLOW not expected to be high");
end
always @(posedge SMI_SWRTR_FLOW)
if (full_prog)
error_pkg::error("SMI_SWRTR_FLOW not expected to be high during full pr
ogramming");
////////////////////////////////////////////////////////////////////
// SMI_RBW checkers
////////////////////////////////////////////////////////////////////
wire rbw_expected = ((full_prog||SMI_ERASE) ? 1'b0 :
SMI_FORM ? TF_SMI_FORM_RBW_EN_TB :
dw_mode ? !TF_SMI_BLIND_ERASE_EN_TB && TF_SMI_DW_RB
W_EN_TB :
TF_SMI_AUTOPGM_RBW_EN_TB) &&
!TF_SMI_WR_ONLY_TMCR && !TF_SMI_RAW_ONLY_TMCR &&
!TF_SMI_VAW_ONLY_TMCR && !TF_SMI_REV_STRESS_TMCR &&
!TF_SMI_NO_TIMER_TMCR;
if (!rbw_expected)
error_pkg::error("SMI_RBW unexpected");
#15;
if (rbw_expected && !rbw_rose && !SMI_RXW && !smore0.cenc_do_reset)
error_pkg::error("SMI_RBW expected but didn't rise");
end
////////////////////////////////////////////////////////////////////
// SMI_4VLX2VL checkers
////////////////////////////////////////////////////////////////////
reg expect_4vl, expect_rbrc, expect_rbsc, rbrc_rose, rbsc_rose;
initial begin
expect_4vl = 1'b0;
expect_rbrc= 1'b0;
expect_rbsc= 1'b0;
rbrc_rose = 1'b0;
rbsc_rose = 1'b0;
end
ìfdef GATE_SIM
èlse
èndif
begin
#20;
if (!smore0.cenc_full_prog && !smore0.cenc_dw) begin
#50;
if (rcxsc && TF_SMI_RBRC_EN_TB)
expect_rbrc= 1'b1;
else
expect_rbrc= 1'b0;
if (!rcxsc && TF_SMI_RBSC_EN_TB)
expect_rbsc= 1'b1;
else
expect_rbsc= 1'b0;
if (expect_rbrc || expect_rbsc)
expect_4vl = 1'b1;
else
expect_4vl = 1'b0;
end
end
if (SMI_4VLX2VL &&
(!expect_4vl || SMI_RXW && !SMI_VAW && !SMI_RBSC && !SMI_RBRC))
error_pkg::error("SMI_4VL not expected ");
if (!SMI_4VLX2VL &&
(SMI_RBSC || SMI_RBRC || expect_4vl && (!SMI_RXW || SMI_VAW)))
error_pkg::error("SMI_4VL expected but not asserted ");
end
always @(posedge SMI_RBRC)
rbrc_rose = 1'b1;
always @(posedge SMI_RBSC)
rbsc_rose = 1'b1;
always @(posedge smore0.bec_done) begin
if (expect_rbrc && !rbrc_rose)
error_pkg::error("SMI_RBRC expected but didn't rise ");
if (!expect_rbrc && rbrc_rose)
error_pkg::error("SMI_RBRC not expected but did rise ");
if (expect_rbsc && !rbsc_rose)
error_pkg::error("SMI_RBSC expected but didn't rise ");
if (!expect_rbsc && rbsc_rose)
error_pkg::error("SMI_RBSC not expected but did rise ");
if (rbrc_rose && rbsc_rose)
error_pkg::error("SMI_RBSC and SMI_RBSC both rose ");
rbrc_rose = 1'b0;
rbsc_rose = 1'b0;
expect_rbrc = 1'b0;
expect_rbsc = 1'b0;
end
////////////////////////////////////////////////////////////////////
// TF_SMI_BLP_WLDV_DLY checkers
////////////////////////////////////////////////////////////////////
time blp2wldv_dly;
always @(*)
case (TF_SMI_BLP_WLDV_DLY_TB)
2'b00: blp2wldv_dly = 0;
endcase
always @(posedge SMI_WLDV_SWON) begin
#10;
if (SMI_SA_ENABLE && !SMI_BLP && !SMI_RXW && SMI_RCXSC &&
!(dw_mode && TF_SMI_CONCUR_DW_EN_TB)) begin
if ((($time - `MA.BLP_fall) - blp2wldv_dly < 0 ||
($time - `MA.BLP_fall) - blp2wldv_dly > 20) &&
!smore0.cenc_do_reset)
error_pkg::error("TF_SMI_BLP_WLDV_DLY violated");
end
end
////////////////////////////////////////////////////////////////////
// Smart Write checkers
////////////////////////////////////////////////////////////////////
integer hit;
initial hit = 0;
parameter max_hit = 0;
wire sw_ok = PR_WRITE_OK && (SMI_DETECT_RST || SMI_DETECT_SET);
always @(posedge sw_ok)
if (sw_ok!==1'bx) begin
if (hit < max_hit) begin
$display("%t: smart write done by 0ns: SMI_DETECT_RST = %0b SMI_DE
TECT_SET = %0b SMI_SA_ENABLE = %0b",
$time, SMI_DETECT_RST, SMI_DETECT_SET, SMI_SA_ENABLE);
end
#200;
if (SMI_DETECT_RST || SMI_DETECT_SET || SMI_SA_ENABLE)
error_pkg::error("smart write done by 200ns but write pulse still on
");
else
if (hit < max_hit) begin
$display("%t: smart write done by 200ns: SMI_DETECT_RST = %0b SMI
_DETECT_SET = %0b SMI_SA_ENABLE = %0b",
$time, SMI_DETECT_RST, SMI_DETECT_SET, SMI_SA_ENABLE);
hit = hit + 1;
end
end
////////////////////////////////////////////////////////////////////
// exceptions for the ADR_to_REN checkers
////////////////////////////////////////////////////////////////////
always @ (posedge smore0.cenc_ppc_acc) begin
ADR_to_REN_exception =1;
#15;
ADR_to_REN_exception =0;
end
////////////////////////////////////////////////////////////////////
// PR_ACM_EN checkers
////////////////////////////////////////////////////////////////////
time pr_acm_en_rise_time, rxw_fall_time, vaw_rise_time, double_vaw_rise_time;
time raw_rise_time, rbw_fall_time;
time sw_retry_cnt_change_time, rbrc_rise_time, rbsc_rise_time, final_rtr_rise
_time;
reg first_double_vaw;
initial first_double_vaw = 1'b0;
ìfdef GATE_SIM
èlse
èndif
first_double_vaw = 1'b0;
always @(posedge SMI_DOUBLE_VAW) begin
if (!first_double_vaw)
double_vaw_rise_time = $time;
first_double_vaw = !first_double_vaw;
end
always @(posedge SMI_PR_ACM_EN) begin
#10;
pr_acm_en_rise_time = $time;
end
always @(posedge SMI_VAW)
vaw_rise_time = $time;
always @(posedge SMI_RAW)
raw_rise_time = $time;
always @(negedge SMI_RXW)
rxw_fall_time = $time;
always @(posedge SMI_RBRC)
rbrc_rise_time = $time;
always @(posedge SMI_RBSC)
rbsc_rise_time = $time;
always @(posedge SMI_FINAL_RTR)
final_rtr_rise_time = $time;
always @(smore0.bec_sw_retry_cnt)
final_rtr_rise_time = $time;
time delta, max_delta = 200;
always @(SMI_SA_ENABLE) begin
if (SMI_DOUBLE_VAW && !smore0.cenc_do_reset &&
($time > `MA.tPOWERON)) begin
delta = pr_acm_en_rise_time - double_vaw_rise_time + max_delta;
if (delta > 2*max_delta)
error_pkg::error("(1) there was no SMI_PR_ACM_EN near the beginning
of DOUBLE VAW");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the beginning of D
OUBLE VAW");
end
if (SMI_VAW && !SMI_DOUBLE_VAW && !smore0.cenc_do_reset &&
delta = pr_acm_en_rise_time - vaw_rise_time + max_delta;
of VAW");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the beginning of V
AW");
end
if (SMI_RAW && ($time > `MA.tPOWERON) && !smore0.cenc_do_reset && !TF_SMI_
RAW_ONLY_TMCR) begin
delta = pr_acm_en_rise_time - raw_rise_time + max_delta;
of RAW");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the beginning of R
AW");
end
if (!SMI_RXW && SMI_SWRTR_FLOW &&
(smore0.bec_sw_retry_cnt == 3'h0) && !SMI_FINAL_RTR &&
delta = pr_acm_en_rise_time - rxw_fall_time + max_delta;
of SWRTR write");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the beginning of S
WRTR write");
end
if (SMI_RBRC && ($time > `MA.tPOWERON)) begin
delta = pr_acm_en_rise_time - rbrc_rise_time + max_delta;
of RBRC");
if (delta < 0)
BRC");
end
if (SMI_RBSC && ($time > `MA.tPOWERON)) begin
delta = pr_acm_en_rise_time - rbsc_rise_time + max_delta;
of RBSC");
if (delta < 0)
BSC");
end
// for final VAW, only check the rising edge of SMI_VAW
if (SMI_FINAL_RTR && !SMI_VAW && ($time > `MA.tPOWERON)) begin
delta = pr_acm_en_rise_time - final_rtr_rise_time + max_delta;
of FINAL_RTR");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the beginning of F
INAL_RTR");
end
if ((smore0.bec_sw_retry_cnt > 0) && ($time > `MA.tPOWERON)) begin
delta = pr_acm_en_rise_time - sw_retry_cnt_change_time + max_delta;
error_pkg::error("(1) there was no SMI_PR_ACM_EN near the changing o
f sw_retry_cnt");
if (delta < 0)
error_pkg::error("there was no SMI_PR_ACM_EN near the changing of sw
_retry_cnt");
end
end
////////////////////////////////////////////////////////////////////
// SHR_FF/00 checkers
////////////////////////////////////////////////////////////////////
time shr_ff_top_rise;
time shr_00_top_rise;
reg shr_ff_bot_rose;
reg shr_00_bot_rose;
always @(posedge SMI_SHR_FF_TOP)
shr_ff_top_rise = $time;
always @(posedge SMI_SHR_00_TOP)
shr_00_top_rise = $time;
always @(posedge SMI_SHR_FF_BOT) begin
shr_ff_bot_rose = 1'b1;
delta = $time - shr_ff_top_rise;
if ((delta > 1000) && ($time > `MA.tPOWERON))
error_pkg::error("SMI_SHR_FF_TOP too far from SMI_SHR_FF_BOT");
end
always @(posedge SMI_SHR_00_BOT) begin
shr_00_bot_rose = 1'b1;
delta = $time - shr_00_top_rise;
if ((delta > 1000) && ($time > `MA.tPOWERON))
error_pkg::error("SMI_SHR_00_TOP too far from SMI_SHR_00_BOT");
end
reg data_cycle;
reg shr_ff_exception;
initial shr_ff_exception = 1'b0;
always @(posedge YYXWE)
if (YYCLE && YYIO[7:0] == 8'h80 && YYXWP) begin
data_cycle = 1'b0;
while (!data_cycle) begin
wait (YYXWE === 1'b0);
wait (YYXWE === 1'b1);
if (!YYCLE && !YYALE)
data_cycle = 1'b1;
end
if (!shr_ff_exception) begin
if (`TB.TF_SMI_RESET_IS_ERASE_TB && !shr_ff_bot_rose && SMI_CHPSEL)
error_pkg::error("SMI_SHR_FF_TOP/BOT didn't rise");
if (!`TB.TF_SMI_RESET_IS_ERASE_TB && !shr_00_bot_rose && SMI_CHPSEL)
error_pkg::error("SMI_SHR_00_TOP/BOT didn't rise");
end
shr_ff_bot_rose = 1'b0;
shr_00_bot_rose = 1'b0;
end
//ìfdef GATE_SIM
// èlse
////////////////////////////////////////////////////////////////////
// state checkers
////////////////////////////////////////////////////////////////////
always @(posedge smore0.cenc_state[0] or posedge SP_XPOR_GLOBAL)
if (smore0.cenc_state[0]=== 1'b1 && SP_XPOR_GLOBAL===1'b1) begin
#10;
if (smore0.bist_state[0] !== 1'b1)
error_pkg::error("bist not idle after cenc went to idle");
if (smore0.bec_state[0] !== 1'b1)
error_pkg::error("bec not idle after cenc went to idle");
if (smore0.prc_state[0] !== 1'b1)
error_pkg::error("prc not idle after cenc went to idle");
if (smore0.aryc_state[0] !== 1'b1)
error_pkg::error("aryc not idle after cenc went to idle");
end
/*always @(posedge smore0.bist_state[0] or posedge SP_XPOR_GLOBAL)
if (smore0.bist_state[0]=== 1'b1 && SP_XPOR_GLOBAL===1'b1) begin
#10;
if (smore0.bec_state[0] !== 1'b1)
error_pkg::error("bec not idle after bist went to idle");
if (smore0.prc_state[0] !== 1'b1)
error_pkg::error("prc not idle after bist went to idle");
error_pkg::error("aryc not idle after bist went to idle");
end */
always @(posedge smore0.bec_state[0] or posedge SP_XPOR_GLOBAL)
if (smore0.bec_state[0]=== 1'b1 && SP_XPOR_GLOBAL===1'b1) begin
#10;
error_pkg::error("aryc not idle after bec went to idle");
end
// checkers for trimfuse write during slow ramp
reg [4:0] old_tf_vwr_form;
reg [7:0] orig_tf_byte76;
initial begin
orig_tf_byte76 = 0;
old_tf_vwr_form =0;
end
always @ (posedge smore0.cenc_do_read_vwr_byte) begin
#150;
old_tf_vwr_form = trim_fuse0.TF_CP_VWR_FORM_TB;
orig_tf_byte76 = trim_fuse0.TF_DATA[615:608];
end
always @ (posedge smore0.aryc_do_restore_vwr_byte) begin
#150;
if ( trim_fuse0.TF_DATA[615:608] != orig_tf_byte76 )
error_pkg::error("TF BYTE 76 not restored ");
end
always @ (posedge smore0.aryc_do_incr_vwr_byte) begin
#150;
if ( (old_tf_vwr_form == 'd31) &&(trim_fuse0.TF_CP_VWR_FORM_TB != 'd31) )
error_pkg::error("aryc_do_incr_vwr_byte causing TF_CP_VWR_FORM_TB to
increase over limit ");
if ( (old_tf_vwr_form != 'd31) &&(trim_fuse0.TF_CP_VWR_FORM_TB != (old_tf_
vwr_form +1) ))
error_pkg::error("TF_CP_VWR_FORM_TB not increased @ aryc_do_incr_vwr
_byte ");
end
always @ (posedge YYRXB) begin
#150;
if ( trim_fuse0.TF_DATA[615:608] != orig_tf_byte76 )
error_pkg::error("TF BYTE 76 not restored ");
orig_tf_byte76 ='bx;
old_tf_vwr_form ='bx;
end
always @(posedge CO_SMICLKB) begin
#30;
if (!$onehot(smore0.prc_state) && SP_XPOR_GLOBAL===1'b1)
error_pkg::error("prc not 1-hot");
if (!$onehot(smore0.aryc_state) && SP_XPOR_GLOBAL===1'b1)
error_pkg::error("aryc not 1-hot");
if (!$onehot(smore0.cenc_state) && SP_XPOR_GLOBAL===1'b1)
error_pkg::error("cenc not 1-hot");
if (!$onehot(smore0.bec_state) && SP_XPOR_GLOBAL===1'b1)
error_pkg::error("bec not 1-hot");
if (!$onehot(smore0.bist_state) && SP_XPOR_GLOBAL===1'b1)
error_pkg::error("bist not 1-hot");
end
ìfdef GATE_SIM
/*
wire ifc_chbw_read_pw_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_read_grp.ifc_chbw_read_pw_reg_0_.R
STn &&
!smore0.if_ctrl0.ifc_chbw_read_grp.ifc_chbw_read_pw_reg_0_.S
ETn;
always @(posedge ifc_chbw_read_pw_reg_0_race) begin
#5;
if (ifc_chbw_read_pw_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_read_pw_reg_0_ set and reset raced");
end
STn &&
ETn;
#5;
end
STn &&
ETn;
#5;
end
STn &&
ETn;
#5;
end
wire ifc_chbw_set_pw_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_set_grp.ifc_chbw_set_pw_reg_0_.RST
n &&
!smore0.if_ctrl0.ifc_chbw_set_grp.ifc_chbw_set_pw_reg_0_.SET
n;
always @(posedge ifc_chbw_set_pw_reg_0_race) begin
#5;
if (ifc_chbw_set_pw_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_set_pw_reg_0_ set and reset raced");
end
n &&
n;
#5;
end
n &&
n;
#5;
end
n &&
n;
#5;
end
wire ifc_chbw_rst_pw_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_rst_grp.ifc_chbw_rst_pw_reg_0_.RST
n &&
!smore0.if_ctrl0.ifc_chbw_rst_grp.ifc_chbw_rst_pw_reg_0_.SET
n;
always @(posedge ifc_chbw_rst_pw_reg_0_race) begin
#5;
if (ifc_chbw_rst_pw_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_rst_pw_reg_0_ set and reset raced");
end
n &&
n;
#5;
end
n &&
n;
#5;
end
n &&
n;
#5;
end
wire ifc_chbw_read_parlbay_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_read_grp.ifc_chbw_read_parlbay_reg
_0_.RSTn &&
_0_.SETn;
always @(posedge ifc_chbw_read_parlbay_reg_0_race) begin
#5;
if (ifc_chbw_read_parlbay_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_read_parlbay_reg_0_ set and reset raced");
end
wire ifc_chbw_read_parlbay_reg_1_race = SP_XPOR_GLOBAL &&
_1_.RSTn &&
_1_.SETn;
always @(posedge ifc_chbw_read_parlbay_reg_1_race) begin
#5;
if (ifc_chbw_read_parlbay_reg_1_race === 1'b1)
error_pkg::error("ifc_chbw_read_parlbay_reg_1_ set and reset raced");
end
wire ifc_chbw_set_parlbay_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_set_grp.ifc_chbw_set_parlbay_reg_0
_.RSTn &&
_.SETn;
always @(posedge ifc_chbw_set_parlbay_reg_0_race) begin
#5;
if (ifc_chbw_set_parlbay_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_set_parlbay_reg_0_ set and reset raced");
end
wire ifc_chbw_set_parlbay_reg_1_race = SP_XPOR_GLOBAL &&
_.RSTn &&
_.SETn;
always @(posedge ifc_chbw_set_parlbay_reg_1_race) begin
#5;
if (ifc_chbw_set_parlbay_reg_1_race === 1'b1)
error_pkg::error("ifc_chbw_set_parlbay_reg_1_ set and reset raced");
end
wire ifc_chbw_rst_parlbay_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_rst_grp.ifc_chbw_rst_parlbay_reg_0
_.RSTn &&
_.SETn;
always @(posedge ifc_chbw_rst_parlbay_reg_0_race) begin
#5;
if (ifc_chbw_rst_parlbay_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_rst_parlbay_reg_0_ set and reset raced");
end
wire ifc_chbw_rst_parlbay_reg_1_race = SP_XPOR_GLOBAL &&
_.RSTn &&
_.SETn;
always @(posedge ifc_chbw_rst_parlbay_reg_1_race) begin
#5;
if (ifc_chbw_rst_parlbay_reg_1_race === 1'b1)
error_pkg::error("ifc_chbw_rst_parlbay_reg_1_ set and reset raced");
end
wire ifc_chbw_set_mode_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_set_grp.ifc_chbw_set_mode_reg_0_.R
STn &&
!smore0.if_ctrl0.ifc_chbw_set_grp.ifc_chbw_set_mode_reg_0_.S
ETn;
always @(posedge ifc_chbw_set_mode_reg_0_race) begin
#5;
if (ifc_chbw_set_mode_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_set_mode_reg_0_ set and reset raced");
end
STn &&
ETn;
#5;
end
STn &&
ETn;
#5;
end
wire ifc_chbw_rst_mode_reg_0_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chbw_rst_grp.ifc_chbw_rst_mode_reg_0_.R
STn &&
!smore0.if_ctrl0.ifc_chbw_rst_grp.ifc_chbw_rst_mode_reg_0_.S
ETn;
always @(posedge ifc_chbw_rst_mode_reg_0_race) begin
#5;
if (ifc_chbw_rst_mode_reg_0_race === 1'b1)
error_pkg::error("ifc_chbw_rst_mode_reg_0_ set and reset raced");
end
STn &&
ETn;
#5;
end
STn &&
ETn;
#5;
end
*/
wire ifc_do_reset_reg_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_do_reset_reg.RSTn &&
!smore0.if_ctrl0.ifc_do_reset_reg.SETn;
always @(posedge ifc_do_reset_reg_race) begin
#5;
if (ifc_do_reset_reg_race === 1'b1)
error_pkg::error("ifc_do_reset_reg set and reset raced");
end
wire ifc_do_power_on_read_reg_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_do_power_on_read_reg.RSTn &&
!smore0.if_ctrl0.ifc_do_power_on_read_reg.SETn;
always @(posedge ifc_do_power_on_read_reg_race) begin
#5;
if (ifc_do_power_on_read_reg_race === 1'b1)
error_pkg::error("ifc_do_power_on_read_reg set and reset raced");
end
wire ifc_wake_osc_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_wake_osc_reg.RSTn &&
!smore0.if_ctrl0.ifc_wake_osc_reg.SETn;
always @(posedge ifc_wake_osc_race) begin
#5;
if (ifc_wake_osc_race === 1'b1)
error_pkg::error("ifc_wake_osc set and reset raced");
end
wire ifc_chpsel_race = SP_XPOR_GLOBAL &&
!smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.RSTn &&
!smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.SETn;
always @(posedge ifc_chpsel_race) begin
#5;
if (ifc_chpsel_race === 1'b1)
error_pkg::error("ifc_chpsel_reg set and reset raced");
end
wire ppc_PR_RXW_reg_race = SP_XPOR_GLOBAL &&
!smore0.pipe_ctrl0.ppc_PR_RXW_reg.RSTn &&
!smore0.pipe_ctrl0.ppc_PR_RXW_reg.SETn;
always @(posedge ppc_PR_RXW_reg_race) begin
#5;
if (ppc_PR_RXW_reg_race === 1'b1)
end
wire SMI_RXBOUT_normal_reg_race = SP_XPOR_GLOBAL &&
!smore0.central_ctrl0.SMI_RXBOUT_normal_reg.RSTn &&
!smore0.central_ctrl0.SMI_RXBOUT_normal_reg.SETn;
always @(posedge SMI_RXBOUT_normal_reg_race) begin
#5;
if (SMI_RXBOUT_normal_reg_race === 1'b1)
end
wire SMI_CLKEN_reg_race = SP_XPOR_GLOBAL &&
!smore0.central_ctrl0.SMI_CLKEN_reg.RSTn &&
!smore0.central_ctrl0.SMI_CLKEN_reg.SETn;
always @(posedge SMI_CLKEN_reg_race) begin
#5;
if (SMI_CLKEN_reg_race === 1'b1)
end
// glitch checkers
// CENC:
time SMI_CLKEN_RSTn_fall;
time SMI_CLKEN_SETn_fall;
always @(negedge smore0.central_ctrl0.SMI_CLKEN_reg.RSTn)
SMI_CLKEN_RSTn_fall = $time;
always @(posedge smore0.central_ctrl0.SMI_CLKEN_reg.RSTn)
if (SMI_CLKEN_RSTn_fall - $time < 5)
error_pkg::error("SMI_CLKEN_reg.RSTn glitched");
always @(negedge smore0.central_ctrl0.SMI_CLKEN_reg.SETn)
SMI_CLKEN_SETn_fall = $time;
always @(posedge smore0.central_ctrl0.SMI_CLKEN_reg.SETn)
if (SMI_CLKEN_SETn_fall - $time < 5)
error_pkg::error("SMI_CLKEN_reg.SETn glitched");
// PPC:
time ppc_PR_RXW_RSTn_fall;
time ppc_PR_RXW_SETn_fall;
always @(negedge smore0.pipe_ctrl0.ppc_PR_RXW_reg.RSTn)
ppc_PR_RXW_RSTn_fall = $time;
always @(posedge smore0.pipe_ctrl0.ppc_PR_RXW_reg.RSTn)
if (ppc_PR_RXW_RSTn_fall - $time < 5)
error_pkg::error("ppc_PR_RXW_reg.RSTn glitched");
always @(negedge smore0.pipe_ctrl0.ppc_PR_RXW_reg.SETn)
ppc_PR_RXW_SETn_fall = $time;
always @(posedge smore0.pipe_ctrl0.ppc_PR_RXW_reg.SETn)
if (ppc_PR_RXW_SETn_fall - $time < 5)
error_pkg::error("ppc_PR_RXW_reg.SETn glitched");
time ppc_PR_WE_TOP_RSTn_fall;
always @(negedge smore0.pipe_ctrl0.ppc_PR_WE_TOP_reg.RSTn)
ppc_PR_WE_TOP_RSTn_fall = $time;
always @(posedge smore0.pipe_ctrl0.ppc_PR_WE_TOP_reg.RSTn)
if (ppc_PR_WE_TOP_RSTn_fall - $time < 5)
error_pkg::error("ppc_PR_WE_TOP_reg.RSTn glitched");
time ppc_PR_WE_BOT_RSTn_fall;
always @(negedge smore0.pipe_ctrl0.ppc_PR_WE_BOT_reg.RSTn)
ppc_PR_WE_BOT_RSTn_fall = $time;
always @(posedge smore0.pipe_ctrl0.ppc_PR_WE_BOT_reg.RSTn)
if (ppc_PR_WE_BOT_RSTn_fall - $time < 5)
error_pkg::error("ppc_PR_WE_BOT_reg.RSTn glitched");
time ppc_do_pr_write_RSTn_fall;
always @(negedge smore0.pipe_ctrl0.ppc_do_pr_write_reg_reg.RSTn)
ppc_do_pr_write_RSTn_fall = $time;
always @(posedge smore0.pipe_ctrl0.ppc_do_pr_write_reg_reg.RSTn)
if (ppc_do_pr_write_RSTn_fall - $time < 5)
error_pkg::error("ppc_do_pr_write_reg_reg.RSTn glitched");
// PRC:
time SMI_SHR_ARYOP_RSTn_fall;
always @(negedge smore0.pr_ctrl0.SMI_SHR_ARYOP_reg.RSTn)
SMI_SHR_ARYOP_RSTn_fall = $time;
always @(posedge smore0.pr_ctrl0.SMI_SHR_ARYOP_reg.RSTn)
if (SMI_SHR_ARYOP_RSTn_fall - $time < 5)
error_pkg::error("SMI_SHR_ARYOP_reg.RSTn glitched");
// BIST:
time trimcnt_reg_0_RSTn_fall;
always @(negedge smore0.bist_ctrl0.trimcnt_reg_0_.RSTn)
trimcnt_reg_0_RSTn_fall = $time;
always @(posedge smore0.bist_ctrl0.trimcnt_reg_0_.RSTn)
if (trimcnt_reg_0_RSTn_fall - $time < 5)
// IFC:
time ifc_do_reset_RSTn_fall;
time ifc_do_reset_SETn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_reset_reg.RSTn)
ifc_do_reset_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_reset_reg.RSTn)
if (ifc_do_reset_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_reset_reg.RSTn glitched");
always @(negedge smore0.if_ctrl0.ifc_do_reset_reg.SETn)
ifc_do_reset_SETn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_reset_reg.SETn)
if (ifc_do_reset_SETn_fall - $time < 5)
error_pkg::error("ifc_do_reset_reg.SETn glitched");
time SMI_CMD_BI_RSTn_fall;
always @(negedge smore0.if_ctrl0.SMI_CMD_BI_reg.RSTn)
SMI_CMD_BI_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.SMI_CMD_BI_reg.RSTn)
if (SMI_CMD_BI_RSTn_fall - $time < 5)
error_pkg::error("SMI_CMD_BI_reg.RSTn glitched");
time SMI_CMD_HSI_RSTn_fall;
always @(negedge smore0.if_ctrl0.SMI_CMD_HSI_reg.RSTn)
SMI_CMD_HSI_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.SMI_CMD_HSI_reg.RSTn)
if (SMI_CMD_HSI_RSTn_fall - $time < 5)
error_pkg::error("SMI_CMD_HSI_reg.RSTn glitched");
time hsi_wr_mode_RSTn_fall;
always @(negedge smore0.if_ctrl0.hsi_wr_mode_reg.RSTn)
hsi_wr_mode_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.hsi_wr_mode_reg.RSTn)
if (hsi_wr_mode_RSTn_fall - $time < 5)
error_pkg::error("hsi_wr_mode_reg.RSTn glitched");
time ifc_do_stepupen_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_stepupen_reg.RSTn)
ifc_do_stepupen_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_stepupen_reg.RSTn)
if (ifc_do_stepupen_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_stepupen_reg.RSTn glitched");
time ifc_do_power_on_read_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_power_on_read_reg.RSTn)
ifc_do_power_on_read_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_power_on_read_reg.RSTn)
if (ifc_do_power_on_read_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_power_on_read_reg.RSTn glitched");
time ifc_do_power_on_read_SETn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_power_on_read_reg.SETn)
ifc_do_power_on_read_SETn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_power_on_read_reg.SETn)
if (ifc_do_power_on_read_SETn_fall - $time < 5)
error_pkg::error("ifc_do_power_on_read_reg.SETn glitched");
time ifc_wake_osc_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_wake_osc_reg.RSTn)
ifc_wake_osc_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_wake_osc_reg.RSTn)
if (ifc_wake_osc_RSTn_fall - $time < 5)
error_pkg::error("ifc_wake_osc_reg.RSTn glitched");
time ifc_wake_osc_SETn_fall;
always @(negedge smore0.if_ctrl0.ifc_wake_osc_reg.SETn)
ifc_wake_osc_SETn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_wake_osc_reg.SETn)
if (ifc_wake_osc_SETn_fall - $time < 5)
error_pkg::error("ifc_wake_osc_reg.SETn glitched");
time ifc_do_read_page_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_read_page_reg.RSTn)
ifc_do_read_page_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_read_page_reg.RSTn)
if (ifc_do_read_page_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_read_page_reg.RSTn glitched");
time ifc_do_read_page_flag_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_read_page_flag_reg.RSTn)
ifc_do_read_page_flag_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_read_page_flag_reg.RSTn)
if (ifc_do_read_page_flag_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_read_page_reg.RSTn glitched");
time ifc_do_read_partial_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_read_partial_reg.RSTn)
ifc_do_read_partial_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_read_partial_reg.RSTn)
if (ifc_do_read_partial_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_read_partial_reg.RSTn glitched");
time ifc_do_prog_page_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_prog_page_reg.RSTn)
ifc_do_prog_page_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_prog_page_reg.RSTn)
if (ifc_do_prog_page_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_prog_page_reg.RSTn glitched");
time ifc_do_prog_page_drct_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_prog_page_drct_reg.RSTn)
ifc_do_prog_page_drct_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_prog_page_drct_reg.RSTn)
if (ifc_do_prog_page_drct_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_prog_page_drct_reg.RSTn glitched");
time ifc_do_pr_decode_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_pr_decode_reg.RSTn)
ifc_do_pr_decode_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_pr_decode_reg.RSTn)
if (ifc_do_pr_decode_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_pr_decode_reg.RSTn glitched");
time ifc_do_pr_encode_RSTn_fall;
always @(negedge smore0.if_ctrl0.ifc_do_pr_encode_reg.RSTn)
ifc_do_pr_encode_RSTn_fall = $time;
always @(posedge smore0.if_ctrl0.ifc_do_pr_encode_reg.RSTn)
if (ifc_do_pr_encode_RSTn_fall - $time < 5)
error_pkg::error("ifc_do_pr_encode_reg.RSTn glitched");
time ifc_chpsel_RSTn_fall;
always @(negedge !smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.RSTn) begin
ifc_chpsel_RSTn_fall = $time;
//$display("DEBUG: ifc_chpsel_RSTn_fall = %t", $time);
end
always @(posedge smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.RSTn)
if (ifc_chpsel_RSTn_fall - $time < 5 &&
ifc_chpsel_RSTn_fall - $time > 0)
error_pkg::error("SMI_CHPSEL_reg.RSTn glitched");
time ifc_chpsel_SETn_fall;
always @(negedge !smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.SETn) begin
ifc_chpsel_SETn_fall = $time;
//$display("DEBUG: ifc_chpsel_SETn_fall = %t", $time);
end
always @(posedge smore0.if_ctrl0.ifc_chpsel_reg0.SMI_CHPSEL_reg.SETn)
if (ifc_chpsel_SETn_fall - $time < 5 &&
ifc_chpsel_SETn_fall - $time > 0)
error_pkg::error("SMI_CHPSEL_reg.SETn glitched");
èndif
time stdbylo_st_rise;
always @(posedge smore0.bec_state[1])
stdbylo_st_rise = $time;
always @(negedge smore0.bec_state[1])
if (!smore0.cenc_do_reset && !smore0.bec_page_timeout &&
$time - stdbylo_st_rise < 100ns && $time > 200ns)
error_pkg::error("STDBYLO_ST did not stay for 2 clocks");
checkers.v
checkers.v~
page_register.v
text.txt
total 926
drwxr-xr-x 2 jpakhale s3dicdes 512 Mar 9 10:34 ./
drwxr-xr-x 17 jpakhale s3dicdes 1024 Mar 9 10:34 ../
-rw-r--r-- 1 jpakhale s3dicdes 173994 Feb 24 09:54 checkers.v
-rw-r--r-- 1 jpakhale s3dicdes 173993 Feb 23 18:53 checkers.v~
-rw-r--r-- 1 jpakhale s3dicdes 157166 Feb 18 15:17 page_register.v
-rw-r--r-- 1 jpakhale s3dicdes 192512 Feb 18 15:17 .page_register.v.swp
-rw-r--r-- 1 jpakhale s3dicdes 174042 Mar 9 10:34 text.txt
-rw-r--r-- 1 jpakhale s3dicdes 16384 Mar 9 10:34 .text.txt.swp

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// another check if test is using full program, disable unnecessary PR_SAE check

// only 8 reset modes, 3 bits

always @(posedge SMI_BAYE_7) begin

time saenoff_time, muxswon_time, muxswoff_time, saenon_time, blswon_time

always @(negedge SMI_MUX_SWON) begin // mode = 4, 6, 7, 8

always @(posedge SMI_MUX_SWON) begin : muxsw_pulse_3// when SA_ENABLE is

if (SMI_VAW && SMI_DIRECT_WR) begin

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