ARITHEMATIC LOGIC UNIT:

entity alu is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

C : in STD_LOGIC;

Cin : in STD_LOGIC;

AndG : out STD_LOGIC;

OrG : out STD_LOGIC;

NotG : out STD_LOGIC;

NorG : out STD_LOGIC;

NandG : out STD_LOGIC;

XnorG : out STD_LOGIC;

Carryhalf : out STD_LOGIC;

Sumhalf : out STD_LOGIC;

Carryfull : out STD_LOGIC;

Sumfull : out STD_LOGIC;

Sumsub : out STD_LOGIC;

Carrysub : out STD_LOGIC);

end alu;

architecture Behavioral of alu is

begin

process(A,B,C,Cin)

begin

AndG<= A and B;

OrG<= A or B;

NotG<= not (A);

NorG<= not (A or B);

NandG<= not (A and B);

XnorG<= A xnor B;

Sumhalf<= A xor B;

Carryhalf<= A and B;

Sumfull<= A xor ( B xor C);

Carryfull<= (C and ( A xor B )) or ( A and B);

Sumsub<=A xor ( not (B) xor Cin);

Carrysub<= not ('0');

end process;

end Behavioral;

ARITHEMATIC LOGIC UNIT SIMULATION: