FPGA Guide For Beginners

Introduction:
FPGA stands for Field Programmable Gate Array .The purpose of FPGA is to develop ASIC
(Application Specific IC) and used in VLSI (Very Large Scale Integration). As obvious from the name,
FPGA is an arrangement of logic gates or more technically logic units which are interconnected
according to the user’s requirement. The FPGA configuration is generally specified using a hardware
description language (HDL). It is like a one-chip programmable breadboard. Logic blocks can be
configured to perform complex combinational functions & simple logic gates like AND, OR & XOR.
Well enough of these petty details now we will look forward on how FPGA are used for some small
application.

Using FPGAs:
There are two most popular companies which manufacture FPGAs

XILINX FPGA
Chip

XILINX FPGA BOARD I

 On/Off
Push
Button

ALTERA’s
FPGA Chip

Run/Program
Switch

DIP
Switches for
LED’s For Input
Output
ALTERA'S FPGA BOARD 1
(The fig1.1 shows an FPGAs kits of both Xilinx and Altera)

• XILINX: A Pioneer in FPGA. Kits manufactured by them are more advance. Xilinx is the
leader in the digital programmable logic device (PLD) market.

• ALTERA: A competitor to Xilinx, their FPGA’s are relatively less complex and easier in use
but limited in applications.

Note: Both Altera & Xilinx produce FPGA chips & development Boards. The one shown in
figure 1.1 are FPGA Development Boards having an FPGA chip.

Guidelines for Installation:

• As a beginner we would recommend to use Altera’s FPGAs.
• The software used for programming FPGAs are included with the kit but the user needs to set
up the license.
• For Alteras’s FPGAs the software used is Quartus II.
• The company does not provide a license with FPGA board. The user needs to register on their
website in order to retrieve a license.
• For beginners, the first step is to install the software QUARTUS II from the CD included in the
package. You can also download the latest version from their website: www.altera.com

NED University
Electronics Department
 • After signing up you can request a license from the company (Note: this whole procedure is
absolutely free)
• To request the license the company would prompt you for the physical address or MAC address
of your computer’ LAN card. To get Physical/MAC address, type ipconfig/all in the command
prompt. For command prompt Go to (Start Button > Run ) and type cmd and then enter it.

NOW Press OK

NED University
Electronics Department
 • Check the use of license for academic use and submit your request.

MAC
Address

• You will soon receive your license file through E-mail. Check out your inbox, copy the license
file in to the Quartus II 6.0 folder( C:/program Files/Altera/Quartus60)
• Now run Quartus II 6.0 and select the option specify the valid license file.
• Click the browse tab and include the path to your license file and click OK.
• Congratulations! You have successfully set up your license.

Programming your FPGA:

NED University
Electronics Department
Now you have installed Quartus II and you are ready to program your FPGA kit. Before moving on
any further it is necessary that you know the methods and languages by which you can program your
FPGA.

A. Hardware Description Language (HDL)

The languages used for programming FPGAs are hardware description languages:
1) Verilog HDL
2) VHDL
For beginners verilog HDL is used as it is much easier to understand and its constructs are similar
to C/C++.

B. Schematic or Block diagram:

As a start you can build your circuit by making a schematic diagram. The software itself will
interpret the logic and program the FPGA.

Your Very First Example Using FPGA:

The easiest way to understand is by implementing your circuit yourself. In this tutorial we would first
use schematic/block diagram method and then using verilog HDL to implement the same example.

S.R Latch:
Hope that the reader has some knowledge about the S-R latch (set-reset latch) here we would
program the FPGA for S-R latch.

STEPS:
1) Run Quartus II software

NED University
Electronics Department
2) Select File>New Project wizard

NED University
Electronics Department
3) Click Next

NED University
Electronics Department
4) Make a working directory for example: C:\Program Files\Altera\Quartus\sr_latch

NED University
Electronics Department
5) Write sr_latch (in above fig where the ‘light’ is mentioned) as a name of the project and top-
level entity
6) Click Next. If warning message displays for creating directory click Yes

7) Leave next windows blank and click NEXT

NED University
Electronics Department
8) Now select family as Cyclone II (might be different according to your kit for details visit
www.altera.com)

NED University
Electronics Department
9) From available devices EP2C35F672C6 and Click Next>Next

NED University
Electronics Department
10) Now click Finish

CREATING DESIGN:
11) Now press file and select NEW. This will open a window. Choose block diagram/schematic file
under the device design files tab and click OK

NED University
Electronics Department
12) A graphitic editor window will open

NED University
Electronics Department
 13) Select Symbol Tool (having a AND Gate icon on the left panel), go to quartus60/liabraries >
Primitives > Logic and then select you require gates ( here you can found logic gates with
number of inputs specified.)

14) Since, sr_latch is formed using two nand gates connected in a cross linkage has shown

Make the circuit shown above

NED University
Electronics Department
Tip: the input and output pins can be found in primitives>pin library
15) Mark or label the terminals as shown in the figure
16) Now compile your design (compiling means checking your code or design) by clicking the
(PLAY) button or go to Processing Tab > Start Compilation.
17)

18) After compilation is completed now go to Assignments tab and select Assignment editor.
19) Pin Assignment is necessary as we have about 100 Pins on the FPGA chip, but for our
application we have to choose output & input pins.

NED University
Electronics Department
20) Choose category as pin and double click on the entry <<new>> and choose a pin from the drop
down menu.
21) Now double click on location tab and select the location for your input and output pins on
FPGA.(Detail of FPGA’s different I/O ports addresses is provided you with the kit, which is
usually in .xls or MS Excel format)

NED University
Electronics Department
 22) In this example we have chosen for inputs, S-bar and R-bar as pins PIN_N25 and PIN_N26
respectively (there are 2-way switches) on the board
23) For output we have assigned Q and Q-bar as PIN_AE23(RED LED # 1) and PIN_AF23(RED
LED # 2) leds respectively
24) Now Re-compile your design as explained in Step # 15

Dumping a Program in JTAG mode:

25) You are almost done now. To program your FPGA board, click the second last icon from the
right named as Programmer or go to Tools> Programmer

26) A programmer will window open. Now select the programming mode as JTAG (also make sure
that your device should also set up for JTAG programming or set up you device by sliding a 2-
way switch on the board to RUN position)

NED University
Electronics Department
 Note: There are two modes of programming into FPGA named as JTAG and AS (ACTIVE
SERIAL) mode which can be selected manually by a 2-way sliding button on the board by keeping
its position on RUN or PROG respectively. The only advantage of AS mode is just to keep your
program save in to the flash memory of FPGA ,in this mode your program will not be lost even
after turning of the device and you may be able to access it by powering up it again.

27) Select the hardware by clicking hardware setup. You must connect your FPGA and install the
driver named USB master blaster

28) Select hardware device as USB master blaster

29) Now check the option Program/Configure and hit the start button

30) Congratulations! You have dumped you first program sr_latch. Now test it on hardware

Dumping a Program by Active Serial (AS) mode:

NED University
Electronics Department
31) Click on the tab Assignments>Devices, then click on Device and Pin Option and go to in
Configuration tab then set the EPCS16 as Configuration Devices from a drop down list now
click OK and upon returning to your main schematic page Recompile it

NED University
Electronics Department
32) Now follow the previous procedure as followed for JTAG mode.
33) Set the programming mode in programmer dialog box as Active Serial Programming,
34) A warning message in a pop-up window will appear, Click on Yes.

NED University
Electronics Department
35) If there is no any Configuration file shown in the window so click on the Add File and then add
your file having a .pof extension (Programmer Object File)

36) Now slide the RUN/PROG button on the board to the PROG position.
37) Then place a check in the box in a column of Program/Configuration and finally click on the
START button.

NED University
Electronics Department
38) Congratulations! You have successfully dumped your program in your board’s flash memory.

Using VerilogHDL for Programming:

Now once you have implemented your design of S-R Latch we are glad to take you further towards
the first example code of VerilogHDL. Here we would not explain you about the constructs of the
Verilog, but there is plenty of literature available for this. We would recommend the book
VerilogHDL by Samir Palnithkar for learning Verilog. As a beginner you must implement the
following steps to get the idea that how programming is done in Verilog:

39) Now follow the previous steps for making a new project file under name of sr_latch.

NED University
Electronics Department
40) Press file and select NEW. This will open a window. This time Choose “Verilog HDL file”
under the device design files tab and click OK (refer to the figure of step 11).
41) Now copy-paste the following code in the main body.

module sr_latch(q,qbar,s,r);
output q,qbar;
input s,r;
nand g1(q,s,qbar);
nand g2(qbar,r,q);
endmodule

42) Now follow the same procedure from step #16 for pin assignment and dumping of program.

NED University
Electronics Department
Author:
Shehzad Saleem El-023 (Batch 2008-09).

Edited & Compiled by:

Syed Shahbaz Ali El-043 (Batch 2008-09).

Co-workers:
Adeel Amin El-015 (Batch 2008-09).
Ahsan Saeed El-054 (Batch 2008-09).

NED University
Electronics Department