-Bus structures can be somewhat confusing but at the same time it can help you understand most of the

board. There are two type buses that you will find on the system board. There are internal and external. Below is a light description of both. Internal- is basically the lines of communication of the board. The highway so to speak of the motherboard, its infrastructure. Looking at the board you will be able to recognize the bus by all the gold lines of wires running throughout board. A 64bit bus is described as 64 wires or lines in the board. The idea of the internal bus is to transfer information across to all components of motherboard especially the external bus, which is covered later. What are the components of the internal bus and what lines are used for what? The control bus, Address Bus, Data Bus which are all located in the internal bus of the motherboard. Control Bus- a signal that is sent by the CPU that coordinates actions of the system. Address Bus- this is where data and instructions are sent from one component to another using the address bus. This is done by using memory location addresses to recognize the location of data in the system memory (RAM). Data Bus- this is the lines or paths for actual data, instructions to be sent to components. Power- this type bus is used to send power to components of the system. Types of bus The internal bus is just an internal line of communication sending data and instruction among itself. Not only this but providing power and addressing service for the system. Most of the time you don t even think about this type of bus and it goes on in the background without your intervention. The funny thing about this bus is the dynamic properties of it. It almost seems that the motherboard should be more expensive than it is just for all the work it has to do. Thankfully it is not at this time. Now lets look at external bus. Most of you have messed with this at one point or another. Ever heard of a PCI slot or installed maybe a modem? This utilizes the external bus.

Control Bus The control bus is used by the CPU to direct and monitor the actions of the other functional areas of the computer. It is used to transmit a variety of individual signals (read, write, interrupt, acknowledge, and so forth) necessary to control and coordinate the operations of the computer. The individual signals transmitted over the control bus and their functions are covered in the appropriate functional area description.

Address Bus The address bus consists of all the signals necessary to define any of the possible memory address locations within the computer, or for modular memories any of the possible memory address locations within a module. An address is defined as a label, symbol, or other set of characters used to designate a location or register where information is stored. Before data or instructions can be written into or read from memory by the CPU or I/O sections, an address must be transmitted to memory over the address bus. Data Bus The bidirectional data bus, sometimes called the memory bus, handles the transfer of all data and instructions between functional areas of the computer. The bidirectional data bus can only transmit in one direction at a time. The data bus is used to transfer instructions memory at the address defined by the address bus or consists of data read from the memory address specified by the address bus. Figure 5-17 is an example of a computers bus system; control, address, and data buses.

Instruction (I) Bus The instruction (I) bus allows communication between the CPU and memory. It carries to the CPU the program instruction words to be operated on by the CPU from memory or returns instructions to memory. The I bus is controlled by the CPU. It is capable of sending or receiving data while the operand(O) bus is receiving or sending data at the same time, but only in one direction at a time.

Operand (O) Bus The operand (O) bus allows communication between the CPU and memory or the CPU and an I/O Controller (IOC). The CPU controls the operation in both cases. The O bus is capable of sending or receiving data, while the I bus is receiving or sending data at the same time, but only in one direction at a time. The direction of the data depends on whether the CPU is reading data from memory or data is being written back into memory. I/O MEM Bus or Input/Output Controllerfrom memory to the CPU for execution. It carries data (operands) to and from the CPU and memory as required by instruction translation. The data bus is also used to transfer data between memory and the I/O section during input/output operations. The information on the data bus is either written into 5-24

read

To input into the computer from a peripheral device (keyboard, mouse, disk, tape, etc.). Like reading a book or playing an audio cassette or videotape, reading does not destroy what is being read. The term also refers to accessing memory. Read Out and Write Into Every transfer of data is a "read out" from some place and a "write into" some other place. Reading a disk means output from the disk drive and input to the computer (write to memory). When data are copied from one memory area to another, the data are "read out" of memory and "written into" memory. See write. read/write head

A device that reads (senses) and writes (records) data on a magnetic disk or tape. For writing, the surface of the disk or tape is moved past the read/write head. By

discharging electrical impulses at the appropriate times, bits are recorded as tiny, magnetized spots of positive or negative polarity. For reading, the surface is moved past the read/write head, and the bits that are present induce an electrical current across the gap.

write

To store data in memory or onto a storage medium, such as disk and tape. Every write operation in the computer implies a read operation from some other place. For example, to write a file to a disk requires reading it from somewhere else. Write is analogous to record on an audio recorder or videotape recorder. See read. Types of instructions Three main types of instructions are found in the source code of a program written in Assembler. [edit] Machine instructions (Mnemonic) As with any language, the heart of Assembler programming is understanding the instructions that usually have, in this case, a "one-to-one" relationship with machine instructions. The full mnemonic instruction set is described in the Principles of Operation manual for each processor. In most instructions, the target for an instruction appears first, then the source on the right (as with "a = 6" in C or Algol programming). After one or more blanks, any comment may follow on the same line. A line starting with an asterisk (*) is considered entirely comments. Examples: * This is a comment line * Load the fullword integer stored at location labeled 'ZIGGY' into general register 3:

L 3,ZIGGY SLA 4,5 shift the value in general register 4 left by 5 bits

MVC TARGET,SOURCE move characters from memory location 'SOURCE' to 'TARGET' AP COUNT,=P'1' decimal format) B NEXT HERE EQU * add 1 to value in memory location 'COUNT' (packed

unconditional branch to label 'NEXT' This is a label

CLC TARGET,=C'ADDRESS' Compare memory location 'TARGET' to string 'ADDRESS' BE THERE branch if equal to program label 'THERE'

Generally accepted standards, although by no means mandatory, include the identification of General Purpose Registers with the nemonic '"R" through EQU statements elsewhere in the program to ease the readability of Assember language programs. Thus typically you may see the following in an assembler program:L R3,ZIGGY [edit] Assembler instructions The assembler itself needs instructions from the programmer too. For instance, CSECT means "start a section of code here"; DC defines a constant to be placed in the object code. [edit] Macros and conditional assembly The programmer can group instructions together into macros and add them to a library, which can then be invoked in other programs, usually with parameters, like the preprocessor facilities in C and related languages. Macros can include conditional assembler instructions, such as AIF (an IF construct), used to generate

different code according to the chosen parameters. That makes the macro facility of this Assembler very powerful. While multiline macro's in C are an exception, macro definitions in Assembler can easily be hundreds of lines. [edit] Operating system macros Most programs will require services from the operating system, and the OS provides standard macros for requesting those services. These are analogous to Unix system calls. For instance, in MVS (later z/OS), STORAGE (with the OBTAIN parameter) dynamically allocates a block of memory, and GET retrieves the next logical record from a file. Unlike Unix system calls, macros are not standardized across operating systems though. Even something as simple as writing a "sequential file" is coded differently e.g. in Z/OS than in Z/VSE.

Types of instructions. Data movement In any program it is necessary to move the data in the memory and in the CPU registers; there are several ways to do this: it can copy data in the memory to some register, from register to register, from a register to a stack, from a stack to a register, to transmit data to external devices as well as vice versa. This movement of data is subject to rules and restrictions. The following are some of them: *It is not possible to move data from a memory locality to another directly; it is necessary to first move the data of the origin locality to a register and then from the register to the destiny locality. *It is not possible to move a constant directly to a segment register; it first must be moved to a register in the CPU.

It is possible to move data blocks by means of the movs instructions, which copies a chain of bytes or words; movsb which copies n bytes from a locality to another; and movsw copies n words from a locality to another. The last two instructions take the values from the defined addresses by DS:SI as a group of data to move and ES:DI as the new localization of the data. To move data there are also structures called batteries, where the data is introduced with the push instruction and are extracted with the pop instruction. In a stack the first data to be introduced is the last one we can take, this is, if in our program we use these instructions: PUSH PUSH PUSH CX AX BX

To return the correct values to each register at the moment of taking them from the stack it is necessary to do it in the following order: POP POP POP AX CX BX

For the communication with external devices the out command is used to send information to a port and the in command to read the information received from a port. The syntax of the out command is: OUT DX,AX Where DX contains the value of the port which will be used for the communication and AX contains the information which will be sent. The syntax of the in command is: IN AX,DX

Where AX is the register where the incoming information will be kept and DX contains the address of the port by which the information will arrive. Logic and arithmetic operations The instructions of the logic operations are: and, not, or and xor. These work on the bits of their operators. To verify the result of the operations we turn to the cmp and test instructions. The instructions used for the algebraic operations are: to add, to subtract sub, to multiply mul and to divide div.Almost all the comparison instructions are based on the information contained in the flag register. Normally the flags of this register which can be directly handled by the programmer are the data direction flag DF, used to define the operations about chains. Another one which can also be handled is the IF flag by means of the sti and cli instructions, to activate and deactivate the interruptions. Jumps, loops and procedures The unconditional jumps in a written program in assembler language are given by the jmp instruction; a jump is to moves the flow of the execution of a program by sending the control to the indicated address. A loop, known also as iteration, is the repetition of a process a certain number of times until a condition is fulfilled.

The instruction sets can be differentiated by Operand storage Number of explicit Operand Operations Type and size of operands in operands the per CPU instruction location

The type of internal storage in the CPU is the most basic differentiation. The major choices are

a an

stack (the

operands

are

implicitly is

on

top

of the

the

stack)

accumulator (one

operand

implicitly

accumulator)

a set of registers (all operands are explicit either registers or memory locations) The code segment C = A + B how it would appear on the classes of instruction sets Stack PUSH A PUSH B ADD POP C While most early machines used stack or accumulator-style architectures, all machines designed in the past ten years use a general purpose architecture. The reason is the registers are: faster easier for a can be used more effectively then compiler to memory use Accumulator Load A ADD B Store C Register Load R1,A ADD R1,B Store C,R1

Primary advantages and disadvantages of each class of machine Machine Type Advantages Disadvantages

Stack

Simple model of expression A stack can't be randomly accessed. It evaluation. Good code makes it difficult to generate efficient density. code.

Accumulator

Minimizes internal state of Since accumulator is only temporary machine. Short instructions storage, memory traffic is highest. Most general model for All operands must be named, leading code generation to longer instructions.

Register

Classification of General Purpose Register Machines There are two major instruction set characteristics that divide GPR architectures. They concern whether an ALU instruction has two or three operands ADD R3, R1, R3 <-R1 + R2 R2 or ADD R1, R2 R1 <- R1 + R2

how many of the operands may be memory addressed in ALU instruction Register- Register (Load/Store) ADD R3, R1, R2 (R3 <- R1 + R2)

Register - Memory ADD R1, A (R1 <- R1 + A)

Memory - Memory ADD C, A, B (C <- A + B)

M. Krishna Kumar MAM/M6/LU14,15/2004 1 Classification of Instructions M. Krishna Kumar MAM/M6/LU14,15/2004 2

Data transfer Instructions Mov A, Mov A, Mov A, Mov A, Rn Direct @Ri #Data8

Mov Dptr, #Data16

M. Krishna Kumar MAM/M6/LU14,15/2004 3 Data transfer Instructions contd. Mov Rn, Mov Rn, Mov Rn, A Direct #Data8

Mov Direct, A Mov Direct, Rn Mov Direct, #Data8 Mov Direct, DirectM. Krishna Kumar MAM/M6/LU14,15/2004 4 Data Transfer Instructions contd. Mov Direct, @Ri Mov Direct, # Data8 Mov @Ri, A Mov @Ri, Direct Mov @Ri, #Data8 Krishna Kumar MAM/M6/LU14,15/2004 5 Movx A, Movx A, @Ri @Dptr

Movx @Ri, A Movx @dptr, A Movc A, @A+Dptr

Movc A,

@A+Pc

Data transfer Instructions contd.M. Krishna Kumar MAM/M6/LU14,15/2004 6 Data transfer Instructions contd. Push Pop Xch A, Direct Direct Rn

Xch A, Direct Xch A, @Ri Xchd A, @RiM. Krishna Kumar MAM/M6/LU14,15/2004 7 Boolean Instructions Clr C Clr Bit Setb C Setb Bit Cpl C Cpl Bit M. Krishna Kumar MAM/M6/LU14,15/2004 8 Boolean Instructions contd. Anl C, Bit Anl C, /Bit Orl C, Bit Orl C, /Bit Mov C, Bit

Mov Bit, C M. Krishna Kumar MAM/M6/LU14,15/2004 9 Branch Instructions contd. Jc Reladdr Jnc Reladdr Jb Bit, Reladdr Jnb Bit, Reladdr Jbc Bit, ReladdrM. Krishna Kumar MAM/M6/LU14,15/2004 10 Arithmetic Instructions Add A, Rn Add A, Direct Add A, @Ri Add A, #Data 8M. Krishna Kumar MAM/M6/LU14,15/2004 11 Addc A, Rn Addc A, Direct Addc A, @Ri Addc A, #Data 8 Arithmetic Instructions contd. M. Krishna Kumar MAM/M6/LU14,15/2004 12 Subb A, Rn Subb A, Direct Subb A, @Ri

Subb A, #Data 8 Arithmetic Instructions contd. M. Krishna Kumar MAM/M6/LU14,15/2004 13 Inc A Inc Rn Inc Direct Inc @Ri Inc Dptr Arithmetic Instructions contd. M. Krishna Kumar MAM/M6/LU14,15/2004 14 Dec A Dec Rn Dec Direct Dec @Ri Arithmetic Instructions contd. M. Krishna Kumar MAM/M6/LU14,15/2004 15 Arithmetic Instructions contd. Mul AB Div AB DA A M. Krishna Kumar MAM/M6/LU14,15/2004 16

Logical Instructions Anl A, Rn Anl A, Direct Anl A, @Ri

Anl A, #Data 8 Anl Direct, A Anl Direct, #Data 8M. Krishna Kumar MAM/M6/LU14,15/2004 17 Orl A, Rn Orl A, Direct Orl A, @Ri Orl A, #Data 8 Orl Direct, A Orl Direct, #Data 8 Logical Instructions contd. Xrl A, Rn Xrl A, Direct Xrl A, @Ri Xrl A, #Data 8 Xrl Direct, A Xrl Direct, #Data 8 M. Krishna Kumar MAM/M6/LU14,15/2004 18

Logical Instructions contd. Logical Instructions contd. Clr A Cpl A Rl A Rlc A Rr A Rrc A

M. Krishna Kumar MAM/M6/LU14,15/2004 19

Swap AM. Krishna Kumar MAM/M6/LU14,15/2004 20 Branch Instructions Acall Addr11 Lcall Addr16 Ret Reti Ajmp Addr11 Ljmp Addr16 Sjmp ReladdrM. Krishna Kumar MAM/M6/LU14,15/2004 21 Branch Instructions Jmp @A+Dptr Jz Reladdr Jnz ReladdrM. Krishna Kumar MAM/M6/LU14,15/2004 22 Branch Instructions contd

Cjne Rn, #Data, Reladdr Cjne @Ri, #Data, Reladdr Cjne A, #Data, Reladdr Cjne A, Direct, ReladdrM. Krishna Kumar MAM/M6/LU14,15/2004 23 Branch Instructions contd Djnz Rn, Reladdr Djnz Direct, Reladdr NopM. Krishna Kumar MAM/M6/LU14,15/2004 24 Assembly directives Directives: ?FILE Directive ?LINE Directive ?SYMB Directive BSEG Directive CODE Directive CSEG Directive DATA Directive DB Directive DBIT DirectiveM. Krishna Kumar MAM/M6/LU14,15/2004 25 DS Directive DSEG Directive DW Directive

END Directive EQU Directive EXTRN Directive IDATA Directive ISEG Directive Assembly directivesM. Krishna Kumar MAM/M6/LU14,15/2004 26 NAME Directive ORG Directive PUBLIC Directive RSEG Directive SEGMENT Directive SET Directive USING Directive XDATA Directive XSEG Directive Assembly directives

Bus structure: The simplest and most common way of interconnecting various p a r t s o f t h e computer.To achieve a reasonable speed of operation, a computer must be organized so thatall its units can handle one full word of data at a given time.A group of lines that serve as a connecting port for several devices is called abus. In addition to the lines that carry the data, the bus must have

lines for address andcontrol purpose.Simplest way to interconnect is to use the single bus as shown

The external bus is also referred to as the expansion bus. There are six major types of external bus s found on the common motherboard. Only a few of these are actually found on the home PC such as ISA, PCI, AGP, USB and IDE. These slots are easily recognized on the board. They are usually covered with pins on the inside channel. Some of these pins are made of tin or gold. The pins themselves actually mount into the internal bus. Some pins provide power to you component or connect to the data, address bus s. Here is a description of some common buses ISA (Industry Standard Architecture), This bus is the low speed work horse of the system. You will commonly find a Sound Card hooked up this type BUS. PCI (Peripheral Component Interconnect), Supports 32-64 bit bus and is the reigning standard of external buses. The PCI is fast and is slowly making the ISA fade away. Go with a PCI Bus Card when possible. AGP (Accelerated Graphics Port), This Bus provides from 2 to 4 times the speed of the PCI and is used for video expansion only. If you have this slot on your motherboard make sure and use it for you video card. This is great way to go and takes a lot of stress off the CPU, thus gaining in performance all the way around. USB (Universal Serial Bus), This is something that is fairly new and allows you to hook up to 127 devices. This is probably going to wipe out PS/2 ports and more. The USB is allows you to hot swap devices or plug and unplug devices while system is running. This is a great feature and is incorporated on most new motherboards. IDE (Intelligent Drive Electronics), This bus is used mostly for disk drives and connects up to two devices on one connection. More than likely you re hard drive and CD-ROM are connected through this type bus.

There are a few more bus types that are not very common and some are not even in uses in modern computers. The buses above are the most common and found in modern motherboards. -So what are the slots mad up off? We already know that there are little pins made out of gold and tin, but what else? Check out the Slot's Makeup.

5-2 INSTRUCTION SET SUMMARY 5.1. GENERAL-PURPOSE INSTRUCTIONS The general-purpose instructions preform basic data movement, arithmetic, logic, program flow, and string operations that programmers commonly use to write application and system software to run on IA-32 processors. They operate on data contained in memory, in the general-purpose registers (EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP) and in the EFLAGS register. They also operate on address information contained in memory, the general-purpose registers, and the segment registers (CS, DS, SS, ES, FS, and GS). This group of instructions includes the

following subgroups: data transfer, binary integer arithmetic, decimal arithmetic, logic operations, shift and rotate, bit and byte operations, program control, string, flag control, segment register operations, and miscellaneous. 5.1.1. Data Transfer Instructions The data transfer instructions move data between memory and the generalpurpose and segment registers. They also perform specific operations such as conditional moves, stack access, and data conversion. MOV Move data between general-purpose registers; move data between memory and general-purpose or segment registers; move immediates to general-purpose registers CMOVE/CMOVZ Conditional move if equal/Conditional move if zero CMOVNE/CMOVNZ Conditional move if not equal/Conditional move if not zero CMOVA/CMOVNBE Conditional move if above/Conditional move if not below or equal CMOVAE/CMOVNB Conditional move if above or equal/Conditional move if not below CMOVB/CMOVNAE Conditional move if below/Conditional move if not above or equal CMOVBE/CMOVNA Conditional move if below or equal/Conditional move if not above CMOVG/CMOVNLE Conditional move if greater/Conditional move if not less or equal

CMOVGE/CMOVNL Conditional move if greater or equal/Conditional move if not less CMOVL/CMOVNGE Conditional move if less/Conditional move if not greater or equal CMOVLE/CMOVNG Conditional move if less or equal/Conditional move if not greater CMOVC Conditional move if carry5-3 INSTRUCTION SET SUMMARY CMOVNC Conditional move if not carry CMOVO Conditional move if overflow CMOVNO Conditional move if not overflow CMOVS Conditional move if sign (negative) CMOVNS Conditional move if not sign (non-negative) CMOVP/CMOVPE Conditional move if parity/Conditional move if parity even CMOVNP/CMOVPO Conditional move if not parity/Conditional move if parity odd XCHG Exchange BSWAP Byte swap XADD Exchange and add CMPXCHG Compare and exchange CMPXCHG8B Compare and exchange 8 bytes PUSH Push onto stack POP Pop off of stack

PUSHA/PUSHAD Push general-purpose registers onto stack POPA/POPAD Pop general-purpose registers from stack IN Read from a port OUT Write to a port CWD/CDQ Convert word to doubleword/Convert doubleword to quadword CBW/CWDE Convert byte to word/Convert word to doubleword in EAX register MOVSX Move and sign extend MOVZX Move and zero extend 5.1.2. Binary Arithmetic Instructions The binary arithmetic instructions perform basic binary integer computations on byte, word, and double word integers located in memory and/or the general purpose registers. ADD Integer add ADC Add with carry SUB Subtract SBB Subtract with borrow IMUL Signed multiply5-4 INSTRUCTION SET SUMMARY MUL Unsigned multiply IDIV Signed divide DIV Unsigned divide INC Increment

DEC Decrement NEG Negate CMP Compare 5.1.3. Decimal Arithmetic The decimal arithmetic instructions perform decimal arithmetic on binary coded decimal (BCD) data. DAA Decimal adjust after addition DAS Decimal adjust after subtraction AAA ASCII adjust after addition AAS ASCII adjust after subtraction AAM ASCII adjust after multiplication AAD ASCII adjust before division 5.1.4. Logical Instructions The logical instructions perform basic AND, OR, XOR, and NOT logical operations on byte, word, and double word values. AND Perform bitwise logical AND OR Perform bitwise logical OR XOR Perform bitwise logical exclusive OR NOT Perform bitwise logical NOT 5.1.5. Shift and Rotate Instructions The shift and rotate instructions shift and rotate the bits in word and doubleword operands SAR Shift arithmetic right

SHR Shift logical right SAL/SHL Shift arithmetic left/Shift logical left5-5 INSTRUCTION SET SUMMARY SHRD Shift right double SHLD Shift left double ROR Rotate right ROL Rotate left RCR Rotate through carry right RCL Rotate through carry left 5.1.6. Bit and Byte Instructions The bit and instructions test and modify individual bits in the bits in word and double word operands. The byte instructions set the value of a byte operand to indicate the status of flags in the EFLAGS register. BT Bit test BTS Bit test and set BTR Bit test and reset BTC Bit test and complement BSF Bit scan forward BSR Bit scan reverse SETE/SETZ Set byte if equal/Set byte if zero SETNE/SETNZ Set byte if not equal/Set byte if not zero SETA/SETNBE Set byte if above/Set byte if not below or equal

SETAE/SETNB/SETNC Set byte if above or equal/Set byte if not below/Set byte if not carry SETB/SETNAE/SETC Set byte if below/Set byte if not above or equal/Set byte if carry SETBE/SETNA Set byte if below or equal/Set byte if not above SETG/SETNLE Set byte if greater/Set byte if not less or equal SETGE/SETNL Set byte if greater or equal/Set byte if not less SETL/SETNGE Set byte if less/Set byte if not greater or equal SETLE/SETNG Set byte if less or equal/Set byte if not greater SETS Set byte if sign (negative) SETNS Set byte if not sign (non-negative) SETO Set byte if overflow5-6 INSTRUCTION SET SUMMARY SETNO Set byte if not overflow SETPE/SETP Set byte if parity even/Set byte if parity SETPO/SETNP Set byte if parity odd/Set byte if not parity TEST Logical compare 5.1.7. Control Transfer Instructions The control transfer instructions provide jump, conditional jump, loop, and call and return operations to control program flow. JMP Jump JE/JZ Jump if equal/Jump if zero

JNE/JNZ Jump if not equal/Jump if not zero JA/JNBE Jump if above/Jump if not below or equal JAE/JNB Jump if above or equal/Jump if not below JB/JNAE Jump if below/Jump if not above or equal JBE/JNA Jump if below or equal/Jump if not above JG/JNLE Jump if greater/Jump if not less or equal JGE/JNL Jump if greater or equal/Jump if not less JL/JNGE Jump if less/Jump if not greater or equal JLE/JNG Jump if less or equal/Jump if not greater JC Jump if carry JNC Jump if not carry JO Jump if overflow JNO Jump if not overflow JS Jump if sign (negative) JNS Jump if not sign (non-negative) JPO/JNP Jump if parity odd/Jump if not parity JPE/JP Jump if parity even/Jump if parity JCXZ/JECXZ Jump register CX zero/Jump register ECX zero LOOP Loop with ECX counter LOOPZ/LOOPE Loop with ECX and zero/Loop with ECX and equal LOOPNZ/LOOPNE Loop with ECX and not zero/Loop with ECX and not equal5-7 INSTRUCTION SET SUMMARY

CALL Call procedure RET Return IRET Return from interrupt INT Software interrupt INTO Interrupt on overflow BOUND Detect value out of range ENTER High-level procedure entry LEAVE High-level procedure exit 5.1.8. String Instructions The string instructions operate on strings of bytes, allowing them to be moved to and from memory. MOVS/MOVSB Move string/Move byte string MOVS/MOVSW Move string/Move word string MOVS/MOVSD Move string/Move doubleword string CMPS/CMPSB Compare string/Compare byte string CMPS/CMPSW Compare string/Compare word string CMPS/CMPSD Compare string/Compare doubleword string SCAS/SCASB Scan string/Scan byte string SCAS/SCASW Scan string/Scan word string SCAS/SCASD Scan string/Scan doubleword string LODS/LODSB Load string/Load byte string LODS/LODSW Load string/Load word string

LODS/LODSD Load string/Load doubleword string STOS/STOSB Store string/Store byte string STOS/STOSW Store string/Store word string STOS/STOSD Store string/Store doubleword string REP Repeat while ECX not zero REPE/REPZ Repeat while equal/Repeat while zero REPNE/REPNZ Repeat while not equal/Repeat while not zero INS/INSB Input string from port/Input byte string from port5-8 INSTRUCTION SET SUMMARY INS/INSW Input string from port/Input word string from port INS/INSD Input string from port/Input doubleword string from port OUTS/OUTSB Output string to port/Output byte string to port OUTS/OUTSW Output string to port/Output word string to port OUTS/OUTSD Output string to port/Output doubleword string to port 5.1.9. Flag Control Instructions The flag control instructions operate on the flags in the EFLAGS register. STC Set carry flag CLC Clear the carry flag CMC Complement the carry flag CLD Clear the direction flag STD Set direction flag LAHF Load flags into AH register

SAHF Store AH register into flags PUSHF/PUSHFD Push EFLAGS onto stack POPF/POPFD Pop EFLAGS from stack STI Set interrupt flag CLI Clear the interrupt flag 5.1.10. Segment Register Instructions The segment register instructions allow far pointers (segment addresses) to be loaded into the segment registers. LDS Load far pointer using DS LES Load far pointer using ES LFS Load far pointer using FS LGS Load far pointer using GS LSS Load far pointer using SS5-9 INSTRUCTION SET SUMMARY 5.1.11. Miscellaneous Instructions The miscellaneous instructions provide such functions as loading an effective address, executing a no-operation, and retrieving processor identification information. LEA Load effective address NOP No operation UD2 Undefined instruction XLAT/XLATB Table lookup translation

CPUID Processor Identification 5.2. X87 FPU INSTRUCTIONS The x87 FPU instructions are executed by the processor s x87 FPU. These instructions operate on floating-point, integer, and binary-coded decimal (BCD) operands. 5.2.1. Data Transfer The data transfer instructions move floating-point, integer, and BCD values between memory and the x87 FPU registers. They also perform conditional move operations on floating-point operands. FLD Load floating-point value FST Store floating-point value FSTP Store floating-point value and pop FILD Load integer FIST Store integer FISTP Store integer and pop FBLD Load BCD FBSTP Store BCD and pop FXCH Exchange registers FCMOVE Floating-point conditional move if equal FCMOVNE Floating-point conditional move if not equal FCMOVB Floating-point conditional move if below FCMOVBE Floating-point conditional move if below or equal FCMOVNB Floating-point conditional move if not below

FCMOVNBE Floating-point conditional move if not below or equal 1.6 Instruction Set: Computers provide an extensive set of instructions to give the user the flexibility to carry out various computational tasks. The instruction set of different computers differ from each other mostly in the operands are determined from the address and mode field. The basic set of operations available in a typical computer is covered in this and in the next section. Most of computer instructions can be classified into three categories: 1 Data transfer instructions. 2 Data manipulation instructions. 3 Program control instructions. In the next three sections we will briefly describe those and list some sample instructions based on the instruction format of the ATMEL Microcontroller instruction set. Figure 1.8 ATMEL AVR Microcontroller 1.6.1 Data transfer instructions Data transfer instructions move data in a computer from one place to another without changing the data content. The most common transfers are between memory and processor registers, between processor registers and input or output, and between the processor registers themselves. The following is a list of some data transfer instructions used in many computers. Name Mnemonic Load LD Store ST Move MOV Exchange XCH Input IN

Output OUT Push PUSH Pop POP Table 1.5 Typical Data Transfer instructions Selected ATMEL Microcontroller Data Transfer instructions are listed below: LD Load Indirect from Data Space to Register Example: clr r27 ; Clear X high byte ldi r26,$60 ; Set X low byte to $60 SPM Store Program Memory ST (STD) Store Indirect From Register to Data Space Example: clr r27 ; Clear X high byte ldi r26,$60 ; Set X low byte to $60 st X+,r0 ; Store r0 in data ;space loc. ;$60(X post ;inc) st X,r1 ; Store r1 in data ;space loc. $61 ldi r26,$63 ; Set X low byte to $63 st X,r2 ; Store r2 in data ;space loc. $63

st -X,r3 ; Store r3 in data ;space loc. ;$62(X pre dec) MOV Copy Register MOVW Copy RegisterWord IN - Load an I/O Location to Register OUT Store Register to I/O Location PUSH Push Register on Stack POP Pop Register from Stack 1.6.2 Data Manipulation Instructions Data manipulation instructions perform operations on data and provide the computational capabilities for the computer. They are usually divided into three basic types: 1 Arithmetic instructions. 2 Logical and bit manipulation instructions. 3 Shift instructions. 1.6.2.1 Arithmetic instructions The four basic arithmetic operations are addition, subtraction, multiplication and division. A list of typical arithmetic instructions is given in Table 1-5. The increment instruction adds one to the value stored in a register or memory word. One common characteristic of the increment operations is that a binary number of all 1's when incremented produces a result of all 0's. The decrement instruction subtracts 1 from a value stored in a register or memory word. A number of all 0's when decremented produces a result of all ones.

Name Mnemonic Increment INC Decrement DEC Add ADD Subtract SUB Multiply MUL Divide DIV Add with carry ADDC Subtract with borrow SUBB Negate (2's Complement) NEG Table 1.6 Typical Arithmetic instructions Selected ATMEL Microcontroller Arithmetic instructions are listed below: INC Increment Example: clr r22 ; clear r22 inc r22 ; increment r22 DEC Decrement Example: ldi r17,$10 ; Load constant in r17 add r1,r2 ; Add r2 to r1 dec r17 ; Decrement r17 ADC Add with Carry

ADD Add without Carry Example: add r1,r2 ; Add r2 to r1 (r1=r1+r2) add r28,r28 ; Add r28 to itself (r28=r28+r28) ADIW Add Immediate to Word SUB Subtract without Carry Example: sub r13,r12 ; Subtract r12 from r13 SUBI Subtract Immediate MUL Multiply Unsigned Example: mul r5,r4 ; Multiply unsigned r5 and r4 movw r4,r0 ; Copy result back in r5:r4 MULS Multiply Signed NEG Two s Complement 1.6.2.2 Logical and bit manipulation instructions Logical instructions perform binary operations on strings of bits stored in registers. Some typical logical and bit manipulation instructions are listed in Table 1-7. Name Mnemonic Clear CLR Complement COM

AND AND OR OR Exclusive-OR XOR Clear carry CLRC Set Carry SETC Complement Carry COMC Enable interrupt EI Disable interrupt DI Table 1.6 Typical Logical and bit manipulation instructions Selected ATMEL Microcontroller Logical and bit manipulation instructions are listed below: CBI Clear Bit in I/O Register Example: cbi $12,7 ; Clear bit 7 in Port D CBR Clear Bits in Register COM One s Complement Example: com r4 ; Take one s complement of r4 AND Logical AND Example: and r2,r3 ; Bitwise and r2 and r3, result in ;r2 ANDI Logical AND with Immediate OR Logical OR

Example: or r15,r16 ; Do bitwise or between registers ORI Logical OR with Immediate EOR Exclusive OR CLC Clear Carry Flag Example: add r0,r0 ; Add r0 to itself clc ; Clear Carry Flag SEC Set Carry Flag SEI Set Global Interrupt Flag CLI Clear Global Interrupt Flag 1.6.2.3 Shift Instructions Shifts are operations in which the bits of a word are moved to the left or right. Shift instructions may specify eithe logical shifts, arithmetic shifts, or rotate-type operations. Table 1-7 lists four types of shift instructions and four types of rotate instructions. Name Mnemonic Logical shift right SHR Logical shift left SHL Arithmetic shift right SHRA Arithmetic shift left SHLA Rotate right ROR Rotate left ROL

Rotate right through carry RORC Rotate left through carry ROLC Table 1.7 Typical Shift and Rotate instructions Selected ATMEL Microcontroller Shift and Rotate instructions are listed below: LSL Logical Shift Left Example: add r0,r4 ; Add r4 to r0 lsl r0 ; Multiply r0 by 2 LSR Logical Shift Right ASR Arithmetic Shift Right Example: ldi r16,$10 ; Load decimal 16 into r16 asr r16 ; r16=r16 / 2 ldi r17,$FC ; Load -4 in r17 asr r17 ; r17=r17/2 ROL Rotate Left trough Carry ROR Rotate Right through Carry Example: lsr r19 ; Divide r19:r18 by two ror r18 ; r19:r18 is an unsigned two-byte ;integer

1.6.3 Program Control Instructions Program flow can be altered by instructions that modify the value of the program counter: important feature of a digital computer provides a control over the program flow and capability for branching to different program segments. Typical program control instructions are shown in Table 1-8. Table 1.8 Typical program control instructions Branch and jump instructions may be conditional or unconditional. An unconditional branch instruction causes a branch to the specific address without any conditions, e.g.: The conditional branch specifies a condition, e.g. branch if zero: only when the condition is met, the program counter is loaded with the branch address, e.g.: Compare and test instructions can be used in setting conditions for subsequent conditional branch instructions. Name Mnemonic Branch BR Jump JMP Skip SKP Call CALL Return RET Compare (by subtraction) CMP Test (by ANDing) Compare performs an arithmetic subtraction: result is not saved only status bit conditions are set as a result of operation. Similarly test performs logical AND of two operands and updates certain status bits. Selected ATMEL Microcontroller Shift and Rotate instructions are listed below:

BRCC Branch if Carry Cleared Example: add r22,r23 ; Add r23 to r22 brcc nocarry ; Branch if carry cleared ... nocarry: nop ; Branch destination (do nothing) BRCS Branch if Carry Set BRID Branch if Global Interrupt is Disabled BRIE Branch if Global Interrupt is Enabled BRVC Branch if Overflow Cleared Example: add r3,r4 ; Add r4 to r3 brvc noover ; Branch if no overflow ... noover: nop ; Branch destination (do nothing) BRVS Branch if Overflow Set JMP Jump Example: mov r1,r0 ; Copy r0 to r1 jmp farplc ; Unconditional jump ... farplc: nop ; Jump destination (do nothing)

SBI Set Bit in I/O Register SBIC Skip if Bit in I/O Register is Cleared CALL Long Call to a Subroutine RCALL Relative Call to Subroutine RET Return from Subroutine CP Compare Example: cp r4,r19 ; Compare r4 with r19 brne noteq ; Branch if r4 <> r19 ... noteq: nop ; Branch destination (do nothing) TST Test for Zero or Minus 1.6.4 Status Bit Conditions The status register stores the values of the status bits (status register is composed of the status bits). Bits of the status register are modified as a result of an operation performed in the ALU. Figure 1.9 shows the block diagram of an 8-bit ALU with a 4-bit status register. Figure 1.9 Status register bitsStatus bits can be checked after ALU operation to determine certain relationships that exist between the values of A and B. V indicates overflow i.e. for 8-bit ALU the result is greater than 127 or less than -127. If Z is set, the result is zero: we can use e.g. XOR operation to compare to numbers (the result is zero if A = B) and Z indicates the result of comparison. A single bit in A can be checked with a mask that contains 1 in that particular bit position (others being 0 s) and by using AND operation.

1.6.5 Conditional Branch Instruction Conditional branch instructions use the status bits for checking conditions for branching. Table 1.9 gives a list of the most common branch instruction. Table 1.9 Conditional branch instructions. Some conditional branch instructions of ATMEL AVR have been listed in section 1.6.3 1.6.6 Numerical Example Let A = 11110000 and B = 00010100. Perform A list the conditional branch instructions. B, update the status bits, and

1. The ALU takes the 2's complement of B and adds it to A. A: 11110000 B + 1: 11101100 A B: 11011100 2. The status bits are C = 1, S = 1, V = 0, and Z = 0 3. For unsigned numbers: A = 240, and B = 20 Then we have that A>B and A B, i.e. the instructions that will cause a branch are BHI, BHE, and BNE. 4. For signed numbers: A = - 16, and B = 20 Then we have that A<B and A B, i.e. the instructions that will cause a branch are BLT, BLE, and BNE.

1.6.7 Subroutine Call and Return For subroutine calls, different computers can use a different temporary location for storing the return address, some computers use the first memory location of the subroutine (like the Basic Computer ), some store the return address in a fixed memory location, and some computers use a processor register. Stack memory is yet another possibility (the most efficient way): when a succession of subroutines is called (nested calls), the sequential return addresses can be pushed into the stack. The return from subroutine instruction pops the return address (and assigns to program counter) from the top of the stack: we always have the return address for the last called subroutine. Subroutine call (stack based) microoperations: Subroutine return microoperations: By using subroutine stack each return address (in nested calls) can be pushed into the stack without destroying any previous values. In basic computer a recursive subroutine call would destroy the previous return address stored in the first memory location of the subroutine. 1.6.8 Program Interrupts In computer science, an interrupt is a signal from a device which typically results in a context switch: that is, the processor sets aside what it's doing and does something else.Digital computers usually provide a way to start software routines in response to asynchronous electronic events. These events are signaled to the processor via interrupt requests (IRQ). The processor and interrupt code make a context switch into a specifically written piece of software to handle the interrupt. This software is called the interrupt service routine, or interrupt handler. The addresses of these handlers are termed interrupt vectors and are generally stored in a table in RAM, allowing them to be modified if required. Interrupts were originated to avoid wasting the computer's valuable time in software loops (called polling loops) waiting for electronic events. Instead, the computer was able to do other useful work while the event was pending. The interrupt would signal the computer when the event occurred, allowing efficient accommodation for slow mechanical devices. Interrupts allow modern computers to respond promptly to electronic events, while other work is being performed. Computer architectures also provide instructions to permit processes to initiate software interrupts or traps. These can be used, for instance,

to implement co-operative multitasking. A well-designed interrupt mechanism arranges the design of the computer bus, software and interrupting device so that if some single part of the interrupt sequence fails, the interrupt restarts and runs to completion. Usually there is an electronic request, an electronic response, and a software operation to turn off the device's interrupt, to prevent another request. Program interrupt is similar to subroutine call, except: 1. The interrupt is (usually) initiated by an internal of external signal rather than an execution of an instruction (software interrupts are exceptions). 2. The address of the interrupt service program (routine) is determined by hardware rather than the address field of an instruction: the CPU must possess some form of HW procedure for selecting a branch address servicing the interrupt. 3. Interrupt routine stores all the information (not just PC) necessary to recover the state of the CPU prior the return from the interrupt routine. After the interrupt routine the CPU must return exactly the same state that is was when the interrupt occurred. The state of the CPU at the end of the execute cycle (the interrupt is recognized in this phase) is determined from: 1. The content of PC 2. The content of all processor registers 3. The content of status conditions status bits (program status word PSW) stored in a separate status register. contains status information about the state of the CPU: bits from ALU operation, interrupt enable bits, and CPU operation mode (system mode, user mode), for example. Some computer store only program counter (and PSW) prior entering to an interrupt routine. The interrupt routine must take care of storing and restoring the CPU status. CPU does not respond to an interrupt until the end of an instruction execution. Interrupt cycle Contents of PC and PSW are pushed onto stack. The branch address is transferred to PC and new PSW is loaded into the status register. The

interrupt routine can now be executed starting from the branch address (which may contain a branch instruction to a user defined service routine). Return from interrupt The stack is popped to retrieve PWS to status register and return address to PC. CPU state is restored and the interrupted program can proceed like nothing had happen. 1.6.8.1 Interrupt types There are three major types of interrupts that cause a break in the normal execution of a program. They can be classified as: 1. External interrupts Come from I/O, timing, or any other external source. e.g.: I/O device requesting new data, elapsed time of an event, power failure, etc. 2. Internal interrupts (traps) Come from illegal or erroneous use of an instruction or data. e.g.overflow, division by zero, invalid operation code, stack overflow, and protection violation. Usually occur as a result of a premature termination of the instruction execution: the service program determines the corrective measure to be taken (e.g. terminates the program). 3. Software interrupts Initiated by an instruction (rather than HW signals). A special call instruction that behaves like an interrupt. Can be used by a programmer to initiate an interrupt routine at any desired point in the program. Can be used for accessing operating system services. 1.6.8.2 Practical Example Using INT-instruction (i.e. INT 21h) for invoking a DOS interrupt (see 80x86 example code shown earlier). The DOS interrupt example shown in Figure 1.9. Figure 1.9 DOS interrupt example