Usb 3

USB 3.
0 Overview
Roy Chestnut Director- Product Line Management P&W
USB Constants
LeCroyconfidential2009
Transactions & Transfers

Packet
USB lowest level data exchange
Transaction
sequence of one or more packets
Transfer
sequence of one or more transactions
USB Device Abstractions

End Point
connection point, source or sink of all data at the USB/device interface unique address (with Device Address) transfer characteristics
Pipe
data stream to or from an endpoint
Default Pipe
Always present Endpoint 0 Shared by all Interfaces
USB Objectives
Single connector / Many peripherals Low cost Hot plug Plug and Play Enhanced performance Low power Eliminate device system resource requirements: IRQs, I/O address space
Sharing Bus Bandwidth
USB 3.0 Features

10x performance increase over USB 2.0 Backward compatible
Legacy devices continue to work when plugged into new host connector New devices work when plugged in legacy systems albeit at USB 2.0 speeds Existing class drivers continue to work
Same USB Device Modes

Pipe Model USB Framework Transfer Types
Power Efficient
Provides excellent power characteristics (especially for idle links)
Both on the device and platform
Eliminate need for polling
Extensible
Protocol designed to efficiently scale up
USB 3.0 Architecture

Dual-bus Architecture SuperSpeed bus operates concurrently with USB2.0
Electrically/mechanically backward & forward compatible Devices discovered/configured at fastest signaling rate Hubs provide additional connection points
SuperSpeed USB
Dual simplex signaling Packets routed to device Hubs store and forward Asynchronous notifications
USB 3.0 Cable and Connectors

Composite 2.0 / 3.0 cable & connector
Embeds physical USB2 bus in parallel with the USB3 SuperSpeed bus USB 2.0 and 3.0 packets in-flight concurrently
LeCroy Confidential
USB 3.0 Physical Layer

Supports up to 3 Meter cables Based on existing specs
Signaling similar to other high-speed serial buses (PCIe/SATA)
2 differential pairs dual simplex
Retain sideband functionality ( reset, wake) without additional wires

Low Frequency Periodic Signaling (LFPS) similar to PCIe beaconing
Retain USB Hot Plug functionality

Rx termination for connect/disconnect detect
Link Training Status State Machine

(LTSSM)
SS Disabled SS Inactive RX Detect Polling U0 Active U1, U2, U3 Compliance Recovery Loop Back Hot Reset
Power Management
Link State U0 U1 U2 U3 Description Link Active Link Idle, Fast Exit Link idle, Slow Exit Suspend Key Charactersitcs RX & TX Circuit Quiesced Clock Generation Circuit also Quiesced Portions of device power removed Exit Latency NA s range Low ms range Higher ms range
U0 to U1 entry based on 1. Downstream port inactivity time Port_U1_TimeOut ( Can be as low as 10us ) 2. Device hardware initiated Based on implementation specific knowledge In both cases - Always initiated with Link command LGO_U1 -> LAU
USB 3.0 Link Layer

Robust & Reliable
Redundancy, advanced encoding techniques and retries >10-20 undetectable error rate for link commands
Effective Power Management

Four link power states Either port can initiate power state change Low Frequency Periodic Signaling (LFPS)
Link Commands
Link flow control Link power state change
Packets
Header packets
Store and forward Link level retries guarantee reliability Contain information consumed by link or host or device
Data packet
Compound packets contains header plus data payload
Link Commands (LCs) Format

Link Commands enable all link layer functions
Link power management (ie: LGO_U1, etc) Successful transfer of a packet (ie: LGOOD _n) Link flow control (ie: LCRD_x) Signals presence of link in U0 (ie: LUP, LDN)
Robust design of link commands

Begin with 4 SLC Start Ordered Sets Link Command Word (LCMD) sent twice Receiver Only needs to receive 3 out of 4 SLC & one LCMD
USB 3.0 Protocol Layer

Preserved legacy SW stack
USB 2.0 transfer types (bulk, control, interrupt, iscochronous)
Streams enhance bulks capabilities

Multiple commands on a pipe Out of order completion
Optimized for good power management

Routable Packet Architecture Asynchronous notifications
Efficient use of bandwidth

Simultaneous IN/ OUTs
USB 3.0 Packet Basics

Header & Data Packets
Move between the host and device Address triple: device address, endpoint number, direction Route string describes path between host and device
Host initiates ALL data transfers Devices

Either respond immediately or defer the packet Hubs proxy for target device by deferring packets routed to a downstream port whose link is not active
Deferred requests restarted asynchronously

Device notifies host which responds with a new transfer request
Bus active only when moving data
Streaming Protocol
Up to 64K Streams Supported per End Point Built on top of SuperSpeed Bulk protocol
Requires a Stream ID field (SID) in DPH and ACK TP
Think Tags
Available on IN and OUT pipes Transfer Level multiplexing of Data Streams Minimizes device and host hardware requirements
Not available on Control, Interrupt or ISO endpoints
USB 3.0 Stream Transfers

USB Attached Storage (UASP) decoding
SuperSpeed Multiplexing of streams at the Transfer level
Multiple Pending Mass Storage Commands Out of Order completions StreamID (tag) for grouping queued transfers
LeCroy Confidential
Burst Transactions
Back to back sequences of data packets Burst multiple packets while receiver ACKs without interrupting flow of data Number of packets in a burst is scheduled by the host Multiple OUTs at the Same time as Multiple Ins NumP Field in TP Header indicates the number of packets a device can receive Host sets NumP to Max burst size as long as there is space to receive data
Sample USB 3.0 Trace View on LeCroy Voyager
Voyager USB 3.0 System
USB 3.0 Product Overview Integrated Analyzer / Exerciser system

Analyzer provides Bi-lingual recording capability
3.0 & 2.0 simultaneous
Exerciser provides Transmit / Receive capability

Generate traffic while recording real response
USB 3.0 Link Mgmnt, Data & Transaction layer packets USB 2.0 and GBe interface to host 1 or 4GB capture memory 2ns timing resolution
LeCroyconfidential2009 LeCroy Confidential
LeCroy USB 3.0 Voyager Overview
2.0 & 3.0 Recording Simultaneously
SMA Differential Input/Output
External Clock Input
USB 2.0 and GBe interface to host
Rec, Trigger, Native 3.0 Connectors Link, LEDs
Integrated 2.0 & 3.0 Exerciser (optional with software key)
Trigger In/Out
LeCroy Confidential LeCroyconfidential2009
Preliminary subject to change
Tapping Interface
3.0 SuperSpeed Front End
Vitesse Crossbar Switch
Minimally Intrusive Tap (passive repeater) at 5Gbps
Xilinx Virtex4 FX series (Programmable SERDES)

8B/10B Encoding LFSR Scrambling (enable / disable) Spread Spectrum Clocking (enable / disable) Polarity Inversion (enable / disable)
2.0 Low / Full / High-Speed Front End

Philips PHY
Non-intrusive tap Autodetect speed (Low / Full / High speed)
Preliminary subject
Additional Hardware Features

Link Tracker Raw 10-bit recording mode Captures every transition
Power Tracker
Monitors VBus for voltage and current draw
Slow clock generation & recording

for emulation or FPGA prototypes Frequency as low as 1Mhz
Cascade Analyzers
Multi-channel Recording (up to 8)
Exerciser
1 port USB 3.0 / 2.0 Generation (non-concurrent) Host or Device Emulation Compliance Test Suite
Preliminary subject
Exerciser Overview:
Integrated Analyzer & Exerciser
Record and Transmit Simultaneously USB 2.0 & 3.0 Host & Device Emulation Micro Processor-based
512MB exerciser memory Bulk Out Operations
Limited to 16 1K packets per burst -(then reload)
ReadyLink - MAC layer emulation

Automatically maintains link handshaking
Script-based execution
Compile and download to hardware
Frame templates Include Files Variables
Error Injection Commands

Exerciser Allows Single Tap Point Exerciser Port Transmits & Records with single connection point
Reduces signal integrity issues for 5GHz signaling
Voyager Transaction Manager

Intelligent Transaction layer state machines:
Retry after RX NRDY TP
Exerciser automatically wait for ERDY and then retry Header TP or ACK TP
Upon RX of Data burst packets

Exerciser will automatically send ACK TP with proper header sequence num for all received packets
Upon RX of DP with out of order SEQ num

Exerciser will send ACK TP with missing SEQ number and Retry bit set to 1
Upon RX of DP with Host Error bit set

Exerciser (dev mode) automatically wait for ERDY and then retry packet
Upon RX of Stream Transfer with out of order commands

Exerciser will send ACK TP with correct Stream ID and SEQ number
USB 3.0 Protocol Market and Technology Update
USB 3.0 Industry Time Line
LeCroy Confidential
USB 3.0 Market Update

Testing Gearing Up
PDK ships to USB-IF Members
Fresco & NEC HBAs
Device Development Kits

Lucid Port, Fresco Logic/Fujitsu, Symwave
Intel Vague about USB 3.0 Adoption

No commitment to launch USB 3.0 in 2010 Microsoft drivers will be late ~ 2011 ASUS and VIA may lead motherboard integration
USB 3.0 Market Update (cont.) Silicon Building Blocks

Lots of Players.
Over dozen IP Providers Engaged Plus big-name SoC Vendors
Motherboard Chipset Vendors

Increasing Activity: Intel, AMD, Via
Original Design Manufacturers (ODMs)

ODMs begin receiving prototypes
High volume sampling starts this quarter
PDK: USB IF ships in August (Fresco & NEC HBAs) Device Dev Kits: Symwave, Fresco Logic, NEC
2010 Looking Forward

Broader market starting development More repeat customers for Voyager 3.0
Intel, Lucidport, Synopsys, Fresco Logic
Link Layer Compliance Spec due from SIG

Voyager Compliance Suite will be updated to provide max coverage
Key Challenge higher ASPs

Power Tracker for USB 2.0 - $2500 CSV import for USB 3.0 - $5000 Compliance Suite for USB 3.0 - $2500
PR from Intel2007/9 IDF

USB3.0 Promoter Group
Target for USB3.0

Very high-speed data transfer (5Gbps range) 10 times higher performance than USB2.0 Backward compatible with USB2.0 Adequate speed for next 5 years
Target schedule
2007
Promoters Group
2008
USB 3.0 spec Standards Development Product Development
2009
USB3.0 LSI Initial Deployment
2010
2011
PC with Chipset integration Chipset Broad Deployment
Attendance at DevCon in US: 500; in Japan: 300. LeCroyconfidential downloaded by around 80K times. Spec was
2009
USB3.0 Contributors 1/2
USB3.0 Contributors 2/2
USB3.0 PC forecast
USB3.0 PC
100% 80%
PC with USB2.0
60% 40% 20% 0% 2001 2009
PC with USB3.0
USB2.0 USB3.0
2002
2010
2011
2003 2011
2004
2012
2009
2010
2012
CY
Target Market for USB3.0

More and more USB3.0 applications are emerging
20122010 -2011
USB Memory HDD SSD
HDD SSD Flash Drive Mobile Media player SDXC 1000BASE-T
Media Player
Card reader
Docking Station DVC

Wireless USB Modem
DSC
1000BASE-T Cell Phone
Hub
Monitor
Scanners
USB3.0 device in 1st stage

: Needs higher data rate : Replacing for HDD market. And needs higher data rate : Needs higher data rate : Internal flash will become higher density. : For video streaming : Card Reader : dongle, docking station
USB3.0 device in 2nd stage and later

DSC, DVC Monitor LeCroyconfidential2009 DVD/HDD may be replaced by flash memory. Replacement for RGB interface by USB3.0
USB 3.0 End-product Development

3.0 Host Controllers
PCIe Host Adapters SOC Motherboard Host Implementation
First target applications

External disk storage Digital still cameras / camcorders Media players High-end mobile phones
60% of USB 3.0 devices shipped during the next two years will be Mass Storage devices Symwave and LeCroy Demonstrate Worlds Fastest USB 3.0 System at CES, Data Transfer Speed of 435MB/sec
Using the LeCroy Voyager USB3.0 Exerciser, LeCroy was able to initiate and monitor traffic at sustained speeds of over 400MB/sec
LeCroy Confidential
USB 3.0 Implementations

Certified Host Chips
NEC FrescoLogic
Certified Device Chips

Symwave First device chipset certified LucidPort Certified a week later
USB 3.0 Shipping Now

ASUS and GigaByte Motherboards NEC Host Controllers
Multiple Companies implementing the NEC Chipset
$40.00
Buffalo External Hard Drive

1TB $189.00 Fujitsu Chipset
SIIG Hard Drive Enclosure

ASMedia Chip
USB 3.0 Products
Super Speed USB (USB 3.0)

End-to-end interoperability and compliance test
USB 3.0 Compliance Update

Electrical Layer
USB 3.0 Electrical masks & fixture defined in Draft (.9) Compliance Spec
Command Layer
USB-CV prototype software demod at Dev Con; Expected in 2010 Runs on top of PDK
Link Layer Assertions (FQ1-10)

Still not published. No new date Complete Test Spec by First of year (What year?)
First Plugfest for certification Early 2010 FYI testing available at the last and the next USB-IF workshop Devices can be certified now through the PIL operated by Intel LeCroy Protocol Compliance Suite released as BETA until the compliance spec is delivered.
LeCroy Confidential
LeCroy USB Solution

Only Vendor to offer a full USB 3.0 solution
USB Single Family Solution

Includes TX Testing RX Testing TDR Tests Protocol Analysis and Generation
LeCroy USB 3.0 Solution

SDA813 or SDA816Zi oscilloscope (TX tests) WE100H with 2 ea. ST-20 sampling/TDR heads (cable, TX impedance) PERT3 (RX tests) USB 3.0 fixtures QualiPhy software for USB3.0 (automates tests)
51 LeCroyconfidential2009
Transmitter Testing
USB3 Clocking and Jitter Jitter Transfer Function SSC and CDR Slew Transmitter Compliance Compliance Test Channels and Reference Cable Equalization Eye Pattern Differential Impedance Cable Measurements
Receiver Testing
Required for compliance
No longer optional
Signal quality/receiver tolerance margins Loopback

Internal BER External BER
Low Frequency Periodic Signaling Sinusoidal Jitter

With/Without SSC
Summary of LeCroy USB 3.0 compliance test solution Complete set of instruments for compliance and development
13 GHz real time oscilloscope for transmitter tests PERT3 for receiver tolerance test Sampling oscilloscope with TDR and s-parameters for TX/RX impedance and cable testing QualiPhy software automates all tests and generates report
Cost-effective solution
Two instruments cover all PHY tests PERT3 provides complete receiver tolerance testing at less than the cost of traditional BERT systems
54 LeCroyconfidential2009
LeCroy USB 3.0 Protocol Compliance Suite Command Layer & Link Layer Testing
Includes Chapter 9 Framework
Supports USB 2.0 and USB 3.0
Stand Alone Application

API based
Uses VB scripts Traffic Generation Scripts VSE Scripts
LeCroy USB 3.0 Protocol Compliance Suite Description:

Complete USB 3.0 Link & Protocol Layer Compliance Suite
Host Exerciser & Verification Scripts Compliance console generates pass/fail
Benefit:
Designed for Device Compliance pre-testing Comprehensive Superset of Test Spec > 100% coverage Intelligent host emulation Turnkey operation
USB 3.0 Protocol Layer Validation and Test Issues
Key Protocol Test Challenges: Probing & Signal Lock issues USB 3.0 Link Layer issues
Power Management Link Commands Error Recovery
Transaction Layer Retries Compliance Testing
Protocol Verification for USB 3.0

Critical success factors
Non-Intrusive
Minimal Effect on Link
Accuracy:
Record every bit
Valid & Invalid Data Packets, Ordered Sets Bus Events
Non-data (LFPS, Logical State changes)
Data Analysis
Error and Timing Reports
USB 3.0: Fast Signal Locking 5Gbps Similar to PCIe 2.0

8b10b, Data Scrambling (LFSR), SSC, Polarity
Link Initialization
Low Frequency Periodic Signaling (LFPS)
Out of Band Signaling
Dynamic Equalization (TSEQ) Training Sequence (TS1 & TS2)

Time Time
LFPS
TSEQ
TS1
TS2
LMP .
Link Bring Up Sequence Link Bring Up Sequence

Link Training Status State Machine

(LTSSM)
SS Disabled SS Inactive RX Detect Polling U0 Active U1, U2, U3 Compliance Recovery Loop Back Hot Reset
Link Polling Sub-states (LTSSM)
RX Detect LFPS Polling
Detects Far-End Termination Low Frequency Periodic Signaling LFPS will Automatically transition to RX_EQ Training Sequence Equalization Both devices must send 65,536 TSEQ
TSEQ (RX_EQ)
TS1 Polling Active TS2 Polling Configuration Detect Logical Idle Must Detect Logical Idle before exiting to U0 Exit Polling to U0
Link Polling Substate (LTSSM)

LFPS_Polling
Polling RX_EQ (TSEQ)
Polling Active (TS1)
Polling Configuration (TS2) Exit to U0 Link Tracker Shows actual bits
USB 3.0 Link Layer Link Training

Synchronization of Link partners
Link power state changes

Manage Entry / Exit for low power states
Inband Reset
Initiate and manage Reset
Flow Control and Buffer Management

Header Packet (HP) Integrity Manage HP Flow Control (FC) Link Layer Error recovery
Packets
Build and Transmit Packets Receive and Unpack Packets
Power Management
Link State Description Key Charactersitcs Exit Latency
U0 U1 U2 U3
Link Active Link Idle, Fast Exit Link idle, Slow Exit Suspend RX & TX Circuit Quiesced Clock Generation Circuit also Quiesced Portions of device power removed
NA s range Low ms range Higher ms range
U0 to U1 entry based on 1. Downstream port inactivity timer Port_U1_TimeOut ( Can be as low as 10us ) 2. Device hardware initiated Based on implementation specific knowledge
In both cases - Always initiated with Link command LGO_U1 -> LAU
Power Management Testing

Numerous rules affect PM at every level Physical layer (remote wake) Link Layer (LGO_Un) Protocol Layer (EP Busy,) Devices (function suspend) Hubs (echo PM states US)
LTSSM View Synchronized to trace view Shows all LTSSM State Changes Counts LTSSM State Changes
Link State Timing View
Shows Up / Downstream port state changes

Generated Automatically for Every Recording Allows easy Time Delta Measurements
PowerTracker: Measures vBus Power Draw
PowerTracker: Show timing between states
Link Commands (LCs) Format

Link Commands enable all link layer functions
Link power management (ie: LGO_U1, etc) Successful transfer of a packet (ie: LGOOD _n) Link flow control (ie: LCRD_x) Signals presence of link in U0 (ie: LUP, LDN)
Robust design of link commands

Begin with 4 SLC Start Symbols Link Command Word (LCMD) sent twice Receiver Only needs to receive 3 out of 4 SLC & one LCMD
Header Ack and Flow Control LCs
LGOOD_n :
HP ACK LC
HP; Hseq:2
Sent in both directions Must be sequential

Where n = HSEQ number
LGOOD_2 LCRD_A
HP; Hseq:3
Only ACK Headers (not data) LGOOD_Pending_Timer: 3us
LGOOD_3 LCRD_B
HP; Hseq:4
LCRD_x :
HP flow control LC
Send 1 Buffer Credit for each HP Rcvd. LCRD_Pending_Timer: 5ms
LGOOD_4 LCRD_C
Packet Header Format

Route String Define s target port for End Point downstream from hub Seqence Num Implicitly acknowledges pkts with preceeding Seq. Numbers
HSEQ Num Used by Link Layer to synchronize LGOOD_n
Header and Data Packet Structure
Bulk_In Transaction Example

Host sends: TP_ACK (OK to send Data) Device sends: LGOOD Acknowledgment of TP ACK from device DPP Data payload Host sends: LGOOD Acknowledgment of DPH and DPP from Device
Setup Transaction w/ CRC16 error Example
Host sends: DPH & Payload Device sends: LGOOD Acknowledgment of DPH Device sends: ACK TP with CRC Error Host Responds: LBAD Bad TP Device sends: LRTY and Resends ACK TP Host sends: LGOOD Acknowledgment
Transaction Layer Protocol

Endpoint should ignore invalid transactions
Ie: TP ACK with incorrect Address
If Endpoint unable to respond to valid transaction:

Send STALL Transaction Packet (If endpoint error) Send NRDY Transaction Packet (Not ready to respond)
Triggering: Essential for Efficient Debug

Trigger on Packet Types
Trigger on Header & TP fields
Trigger on Sequences of Packets and Patterns

Ie: Address = 3; Retry bit = 1
USB 3.0 Compliance Program Compliance Testing Today

Exclusively at PIL (Peripheral Integration Lab)
USB-IF Compliance Program
Electrical Test Spec draft .90 Device (& hub) Frame Work USB Command Verifier - USB-CV draft .90 Interop Tests
Compliance Testing Future

Official USB Compliance Workshops (starting 2010)
USB-IF Compliance tests above plus:
Link Layer Test Spec draft .80 Supplemental Hub Tests Cable & Connector Test Spec
LeCroy USB 3.0 Compliance Suite

Exerciser Scripts Verify USB 3.0 Link & Framework Layers
Saves Trace record for any failed test cases
Automated Compliance Test Console

USB 3.0 Product Overview

Integrated Analyzer / Exerciser system
Analyzer provides Bi-lingual recording capability
3.0 & 2.0 simultaneous
Exerciser provides Transmit / Receive capability

Generate traffic while recording real response
USB 3.0 Link Mgmnt, Data & Transaction layer packets USB 2.0 and GBe interface to host 1 or 4GB capture memory 2ns timing resolution

Usb 3

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USB 3.

Transactions & Transfers

USB Device Abstractions

Sharing Bus Bandwidth

USB 3.0 Features

Same USB Device Modes

Eliminate need for polling

USB 3.0 Architecture

USB 3.0 Cable and Connectors

USB 3.0 Physical Layer

Retain sideband functionality ( reset, wake) without additional wires

Retain USB Hot Plug functionality

Link Training Status State Machine

USB 3.0 Link Layer

Effective Power Management

Link Commands (LCs) Format

Robust design of link commands

USB 3.0 Protocol Layer

Streams enhance bulks capabilities

Optimized for good power management

Efficient use of bandwidth

USB 3.0 Packet Basics

Host initiates ALL data transfers Devices

Deferred requests restarted asynchronously

Bus active only when moving data

Not available on Control, Interrupt or ISO endpoints

USB 3.0 Stream Transfers

Sample USB 3.0 Trace View on LeCroy Voyager

Voyager USB 3.0 System

USB 3.0 Product Overview Integrated Analyzer / Exerciser system

Exerciser provides Transmit / Receive capability

LeCroyconfidential2009 LeCroy Confidential

LeCroy USB 3.0 Voyager Overview

2.0 & 3.0 Recording Simultaneously

SMA Differential Input/Output

External Clock Input

USB 2.0 and GBe interface to host

Rec, Trigger, Native 3.0 Connectors Link, LEDs

Integrated 2.0 & 3.0 Exerciser (optional with software key)

LeCroy Confidential LeCroyconfidential2009

Preliminary subject to change

Xilinx Virtex4 FX series (Programmable SERDES)

2.0 Low / Full / High-Speed Front End

LeCroyconfidential2009 LeCroy Confidential

Additional Hardware Features

Slow clock generation & recording

ReadyLink - MAC layer emulation

Error Injection Commands

LeCroyconfidential2009 LeCroy Confidential

Voyager Transaction Manager

Upon RX of Data burst packets

Upon RX of DP with out of order SEQ num

Upon RX of DP with Host Error bit set

Upon RX of Stream Transfer with out of order commands

USB 3.0 Protocol Market and Technology Update

USB 3.0 Industry Time Line

USB 3.0 Market Update

Device Development Kits

Intel Vague about USB 3.0 Adoption

LeCroyconfidential2009 LeCroy Confidential

USB 3.0 Market Update (cont.) Silicon Building Blocks

Motherboard Chipset Vendors

Original Design Manufacturers (ODMs)