Op-code ADC A,(HL) ADC A,n8 ADC A,r8 ADD A,(HL) ADD A,n8 ADD A,r8 ADD HL,r16

ADD SP,e8 AND (HL) AND n8 AND r8 BIT n3,(HL) BIT n3,r8 CALL cc,n16 CALL n16 CCF CP (HL) CP n8 CP r8 CPL DAA DEC (HL) DEC r16 DEC r8 DI EI HALT INC (HL) INC r16 INC r8 JP (HL) JP cc,n16 JP n16 JR cc,n8 JR n8 LD (C),A LD (HL),n8 LD (HL),r8 LD (n16),A LD (n16),SP LD (r16),A LD A,(C) LD A,(n16) LD A,(r16) LD HL,SP+e8 LD r16,n16 LD r8,(HL) LD r8,n8 LD r8,r8 LD SP,HL LDD (HL),A LDD A,(HL) LDH (n8),A LDH A,(n8) LDI (HL),A LDI A,(HL) NOP OR (HL) OR n8 OR r8 POP r16 PUSH r16 RES n3,(HL) RES n3,r8 RET RET cc RETI RL (HL) RL r8 RLA RLC (HL) RLC r8 RLCA RR (HL) RR r8 RRA RRC (HL) RRC r8 RRCA RST f SBC A,(HL) SBC A,n8 SBC A,r8 SCF SET n3,(HL) SET n3,r8 SLA (HL) SLA r8 SRA (HL) SRA r8 SRL (HL) SRL r8 STOP SUB (HL) SUB n8 SUB r8 SWAP (HL) SWAP r8 XOR (HL) XOR n8 XOR r8

RLC Rotates & Shifts Stack Pointer Program Counter RR RRC SLA SRA SRL

CY

CY 7 CY 7 0 7 0 7 0

0 CY 0 CY 0

Instruction Descriptions (except shifts & rotates)

FFFF FF80 FF00

Interrupt Enable Flag Zero Page (127 Bytes) Hardware Registers OAM

FE00 Echo RAM (Not Useable) E000 Game Unit WRAM Bank 1-7 (Switchable) 4 KBytes Game Unit WRAM Bank 0 (Fixed)

CY
Address 014F 014E 014D 014C 014B 014A 0149 0148 0147 0146 0145 0144 0143 0134 0104 0101 0100

D000

C000

A000 Background Display Data 2 Tile Indices/Attributes (Bank Switched) Background Display Data 1 Tile Indices/Attributes (Bank Switched) Bank 0 and 1 Character Data (Bank Switched) 8000 User Program Area Bank 1 to n (switchable) 16KBytes User Program Area Bank 0 (fixed) 16KBytes ROM Registration Data Area Interrupt Vectors RST Vectors

9C00

9800

VRAM Attributes

Z 7 Zero - Set when the result of a math operation is zero, or two values match for a CP operation. N 6 Subtract - Set if a subtraction was performed in the last math operation. H 5 Half-Carry - Set if a carry occurred from the lower nibble in the last math operation. C 4 Carry - Set if a carry occurred in the last math operation, or if the accumulator A is less than value for a CP operation. X 3 Not Used X 2 Not Used X 1 Not Used X 0 Not Used Tile Map 2 Tile Map 1 Tiles 00-7F (FF40, bit4=0) Tiles 80-FF Tiles 00-7f (FF40, bit 4=1) Interrupt Enable High RAM I/O Registers OAM RAM Low RAM Cart RAM Video RAM ROM Bank #1 to n ROM BANK #0 RAM/ROM Select (MBC1) RAM Bank Select ROM Bank Select MSB (MBC5) ROM Bank Select LSB RAM Bank Enable R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W W W W W 9C00 9800 9000 8800 8000 FFFF FF80 FF00 FE00 C000 A000 8000 4000 0000 6000 4000 3000 2000 0000 9FFF 9BFF 97FF 8FFF 87FF FFFF FFFE FF7F FE9F DFFF BFFF 9FFF 7FFF 3FFF 7FFF 5FFE 3FFF 2FFF 1FFF

Z80 Status Flags

Byte Bit 0 1 2 3 7 3 6 3 5 3 4 3 3 3 0-2 Byte Bit 0 1 7 1 6 1 5 1 4 1 3 1 0-2

Purpose Y Coord X Coord Tile Index Priority Y Flip X Flip Palette Bank Tile Bank Palette Index Purpose Tile Index Priority Y Flip X Flip Not Used Tile Bank Palette Index

OAM RAM Attributes

Comment

0 = in front of background 1 = Sprite flipped vertically 1 = Sprite flipped horizontally 0 = OBJ0PAL / 1 = OBJ1P AL 0 = Lower tile bank Comment 1 = Tile is in front of objects 1 = Tile is flippy vertically 1 = Tile is flipped horizontally Should be set to 0 1 = Upper tile bank (GBC only)

0150 0100 0000

VRAM Memory Map

Memory Map (Write Only)

Description Horizontal Scanline Time V-Blank Period (10 scanlines) Mode 10 Mode 11 Mode 0 with 10 sprites per scanline Mode 0 with no sprites per scanline CPU Clock Speed Horizontal Sync Frequency Vertical Sync Frequency Register RAMG ROMB RAMB CLKL SEC ($08) MIN ($09) HRS ($0A) DAYL ($0B) DAYH ($0C) Purpose RAM/Clock write protect ROM Bank Select RAM Bank/Clock Select Clock latch Seconds Counter Minutes Counter Hours Counter Day Counter Day Counter/Control

Frequency/Time 1x Clocks 2x Clocks 108.7 s 114 228 1087 s 1140 2280 19.31 s 41.37 s to 70.69 s 18.72 s 48.64 s 4.194/8.838 Mhz 1,048,576/sec 2,209,715/sec 9198 Hz 59.73 Hz 17555/frame 36995/frame Comment Write $0A to enable $00 to $7F = ROM Bank # Note 1 Note 2

Clocks & Timings

Memory Map (R/W)

VRAM Width VRAM Height Screen Width Screen Height

Pixels 256 256 160 144

Tiles 32 32 20 18 Gameboy Type

Video Sizes

Value Gameboy Type 01 DMG (SGB) FF MGB (SGB2) 11 CGB The initial value in the Accumulator identifies the type of Gameboy unit.

MBC5 Controller

Bit 15 14-10 9-5 4-0

Meaning Unused Blue Colour value (0 to 31) Green Colour Value (0 to 31) Red Colour Value (0 to 31)

RGB Colour

Bit Addr Range 0000 1FFF 2000 3FFF 4000 5FFF 6000 7FFF 4000 5FFF 4000 5FFF 4000 5FFF LSB of Day Counter 4000 5FFF MSB of Day Counter 0 4000 5FFF Start/Stop Clock Counter 6 4000 5FFF Day Counter Carry (Note 3) 7 4000 5FFF Note 1 : Writing values $00 to $03 select the RAM Bank #. Values $08 to $0C select a clock register. Note 2 : Writing $00 and then $01 to this register latches the clock data. Another write of $00 and then $01 is required to latch the updated clock data. Note 3 : Bit 7 of clock register DAYH remains set until zero is written to it. General Notes: To access the clock counter the RAM bank must first be enabled. Due to a slow MBC3 interface, 4 clock cycles are required between each register access. Register Purpose Comment Bit Addr Range RAMG External RAM Select Write $0A to enable 0000 1FFF ROMB0 ROM Bank Select LSB of ROM Bank # 2000 3FFF ROMB1 ROM Bank Select MSB of ROM Bank # 0 3000 3FFF RAMB RAM Bank Select Ram Bank # (Note 1) 0-3 4000 5FFF General Notes: Unused bit positions in registers should be filled with zero when writing. Note 1 : When a Rumble Pak is installed, bits 0 & 1 select the RAM Bank (maximum of 4 banks). Bit 3 controls the Rumble Pak. Bit 2 is unused. A MOTOR ON (set bit 3) must be issued for 2 frames to start the Rumble Pak motor if it has not yet been started, or if it has been idle for more than 3 frames. Interrupt Addr Comment Vertical Blank $40 Occurs ~59.7 times per second, lasts ~1.1ms LCD Control $48 See STAT register Timer Overflow $50 TIMA register has changed from $FF to $00 Serial I/O Complete $58 Serial Transfer is complete Joypad Pressed $60 High to low transition on pins P10-P13 Interrupts

MBC3 Memory Controller Registers

Gameboy Crib Sheet V1.1 00/01/27

GamePak WRAM 8KBytes Memory Map

Purpose Checksum LSB Checksum MSB Complement Checksum Mask ROM Version Old Licensee Code Destination Code Cartridge RAM Size Cartridge ROM Size Cart Type GB/SGB Function New Licensee Code LSB New Licensee Code MSB Colour Compatibility Game Title Nintendo Logo JP $XXXX NOP

OTAKU NO GAMEBOY

Cartridge Header

Destination A A A A A A HL SP A A A Zero Flag Zero Flag PC PC Carry Flag Flags Flags Flags A A (HL) BC,DE,HL,SP A,B,C,D,E,H,L

ZNHC R0RR2 R0RR2 R0RR1 R0RR2 R0RR2 R0RR1 0RR2 00RR4 R0102 R0102 R0101 R01 3 R01 2 6/3 6 00R1 (HL) R1RR2 8-bit integer R1RR2 A,B,C,D,E,H,L R 1 R R 1 A 11 1 A R 0R1 (HL) R1R 3 2 A,B,C,D,E,H,L R 1 R 1 1 1 1 (HL) (HL) R0R 3 BC,DE,HL,SP 2 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 R 1 PC (HL) 1 PC 16-bit addr 4/3 PC 16-bit addr 4 PC 8-bit integer 3/2 PC 8-bit integer 3 (C) A 2 (HL) 8-bit integer 3 (HL) A,B,C,D,E,H,L 2 (16-bit addr) A 4 (16-bit addr) SP 5 (BC),(DE),(HL) A 2 A (C) 2 A (16-bit addr) 4 A (BC),(DE),(HL) 2 HL SP+8-bit off 00RR3 BC,DE,HL,SP 16-bit int 3 A,B,C,D,E,H,L (HL) 2 A,B,C,D,E,H,L 8-bit integer 2 A,B,C,D,E,H,L A,B,C,D,E,H,L 1 SP HL 2 (HL) A 2 A (HL) 2 (8-bit off) A 3 A (8-bit off) 3 (HL) A 2 A (HL) 2 1 A (HL) R0002 A 8-bit integer R0002 A A,B,C,D,E,H,L R 0 0 0 1 AF,BC,DE,HL (SP) 3 (SP) AF,BC,DE,HL 4 Bit in Memory (HL) 3 Bit in Register A,B,C,D,E,H,L 2 PC 4 PC Condition Flag 5/2 PC 4 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 A A 000R1 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 A A 000R1 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 A A 000R1 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 A A 000R1 PC 4 A (HL) R1RR2 A 8-bit integer R1RR2 A A,B,C,D,E,H,L R 1 R R 1 Carry Flag 0011 Bit in Memory (HL) 3 Bit in Register A,B,C,D,E,H,L 2 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 (HL) (HL) R00R4 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 R 2 1 A (HL) R1RR2 A 8-bit integer R1RR2 A A,B,C,D,E,H,L R 1 R R 1 (HL) (HL) R0004 A,B,C,D,E,H,L A,B,C,D,E,H,L R 0 0 0 2 A (HL) R0002 A 8-bit integer R0002 A A,B,C,D,E,H,L R 0 0 0 1

Source (HL) 8-bit integer A,B,C,D,E,H,L (HL) 8-bit integer A,B,C,D,E,H,L BC,DE,SP 8-bit offset (HL) 8-bit integer A,B,C,D,E,H,L (HL) A,B,C,D,E,H,L 16-bit addr 16-bit addr

1 2 1 1 2 1 1 2 1 2 1 2 2 3 3 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 2 2 1 2 1 3 3 1 1 3 1 2 3 1 2 1 1 1 1 2 2 1 1 1 1 2 1 1 1 2 2 1 1 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 2 1 1 2 2 2 2 2 2 2 2 2 1 2 1 2 2 1 2 1

ADC x,y ADD x,y AND x BIT b,x CALL c,x CALL x CCF CP x CPL DAA DEC x DI EI HALT INC x JP c,x JP x JR c,d JR d LD x,y LDD x,y LDI x,y NOP OR x POP x PUSH x RES b,x RET RET c RETI RST x SBC x SCF SET b,x STOP SUB x SWAP x XOR x

Add Y+CY to x Add y to x AND x to A Test bit b of x If condition c is true call subroutine at x Call subroutine at x (push PC and jump to x) Complement carry flag Compare A with x Complement A (1's complement) Decimal adjust A (after add/sub of BCD data) Decrement x by 1 Disable interrupts Enable interrupts Halt (wait for interrupt or reset) Increment x by 1 If condition c is true jump to location x Jump to location x If condition c is true jump relative by d Jump relative by d Load x with y (move y to x) Load A with (HL), DEC HL Load A with (HL), INC HL No operation OR x to A Pop x from top of stack updating SP Push x onto top of stack updating SP Reset bit b of x (to 0) Return from subroutine (POP PC) If condition c is true return from subroutine Return from interrupt Call subroutine at x (1 byte instruction) Subtract y+CY from x Set carry flag (to 1) Set bit b of x (to 1)instruction) Stop CPU until P1-P10 go high Subtract x from A Swap register nibbles XOR x to A

158 70 A F B C D E H L SP PC

Z80 Registers

Accumulator/Flags

RL

CY

http://www.otakunozoku.com

CE 8E 8F 88 89 8A 8B 8C 8D C6 86 87 80 81 82 83 84 85 09 19 29 39 E8 E6 A6 A7 A0 A1 A2 A3 A4 A5 CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CD DC D4 C4 CC 3F FE BE BF B8 B9 BA BB BC BD 2F 27 35 3D 05 0B 0D 15 1B 1D 25 2B 2D

Cart Type ROM RAM MBC MMM01 Battery Timer Rumble

xx

xx

xx xx

46 47 40 41 42 43 44 45 4E 4F 48 49 4A 4B 4C 4D 56 57 50 51 52 53 54 55 5E 5F 58 59 5A 5B 5C 5D 66 67 60 61 62 63 64 65 6E 6F 68 69 6A 6B 6C 6D 76 77 70 71 72 73 74 75 7D 7F 78 79 7A 7B 7C bb bb bb bb bb xx

aa aa aa aa aa

ADC A,$xx ADC A,(HL) ADC A,A ADC A,B ADC A,C ADC A,D ADC A,E ADC A,H ADC A,L ADD A,$xx ADD A,(HL) ADD A,A ADD A,B ADD A,C ADD A,D ADD A,E ADD A,H ADD A,L ADD HL,BC ADD HL,DE ADD HL,HL ADD HL,SP ADD SP,xx AND $xx AND (HL) AND A AND B AND C AND D AND E AND H AND L BIT 0,(HL) BIT 0,A BIT 0,B BIT 0,C BIT 0,D BIT 0,E BIT 0,H BIT 0,L BIT 1,(HL) BIT 1,A BIT 1,B BIT 1,C BIT 1,D BIT 1,E BIT 1,H BIT 1,L BIT 2,(HL) BIT 2,A BIT 2,B BIT 2,C BIT 2,D BIT 2,E BIT 2,H BIT 2,L BIT 3,(HL) BIT 3,A BIT 3,B BIT 3,C BIT 3,D BIT 3,E BIT 3,H BIT 3,L BIT 4,(HL) BIT 4,A BIT 4,B BIT 4,C BIT 4,D BIT 4,E BIT 4,H BIT 4,L BIT 5,(HL) BIT 5,A BIT 5,B BIT 5,C BIT 5,D BIT 5,E BIT 5,H BIT 5,L BIT 6,(HL) BIT 6,A BIT 6,B BIT 6,C BIT 6,D BIT 6,E BIT 6,H BIT 6,L BIT 7,(HL) BIT 7,A BIT 7,B BIT 7,C BIT 7,D BIT 7,E BIT 7,H CALL $aabb CALL C,$aabb CALL NC,$aabb CALL NZ,$aabb CALL Z,$aabb CCF CP $xx CP (HL) CP A CP B CP C CP D CP E CP H CP L CPL DAA DEC (HL) DEC A DEC B DEC BC DEC C DEC D DEC DE DEC E DEC H DEC HL DEC L

3B F3 FB 76 34 3C 04 03 0C 14 13 1C 24 23 2C 33 C3 E9 DA D2 C2 CA 18 38 30 20 28 EA 08 E0 02 E2 12 36 77 70 71 72 73 74 75 32 22 3E FA F0 0A F2 1A 7E 3A 2A 7F 78 79 7A 7B 7C 7D 06 46 47 40 41 42 43 44 45 01 0E 4E 4F 48 49 4A 4B 4C 4D 16 56 57 50 51 52 53 54 55 11 1E 5E 5F 58 59 5A 5B 5C 5D 26 66 67 6F 60 61 62 63 64 65 21 F8 2E 6E 68 69 6A 6B 6C 6D 31 F9 00 F6 B6 B7

bb aa bb bb bb bb xx xx xx xx xx bb bb xx aa aa aa aa

xx

xx bb aa xx

Twos Complement

xx

Feature ~mA Idle Consumption 55 Audio 15.5 No Halt 3.5 2x CPU 7.5 IR Receive 2 IR Transmit 107 Audio, No HALT, 2x CPU 83 Everything 162 MBits MBytes Banks None 16Kb 2KB 1 64Kb 8KB 1 256Kb 32KB 4 1Mb 128KB 16 MBits 256Kb 512Kb 1Mb 2Mb 4Mb 8Mb 16Mb 32Mb 64Mb 9Mb 10Mb 12Mb MBytes Banks 32KB 2 64KB 4 128KB 8 256KB 16 512KB 32 1MB 64 2MB 128 4MB 256 8MB 512 1.1MB 72 1.2MB 80 1.5MB 96

bb aa bb aa bb aa xx

RAM Sizes

bb aa xx

xx

bb aa xx

16 17 10 11 12 13 14 15 06 07 00 01 02 03 04 05 1E 1F 18 19 1A 1B 1C 1D 0E 0F 08 09 0A 0B 0C 0D

xx

bb aa xx

37 xx

bb aa

xx

bb aa 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B

0 0000 0 0000 NUL 1 0001 SOH 2 0010 STX 3 0011 ETX 4 0100 EOT 5 0101 ENQ 6 0110 ACK 7 0111 BEL 8 1000 BS 9 1001 HT A 1010 LF B 1011 VT C 1100 FF D 1101 CR E 1110 SO F 1111 SI

1 2 3 4 5 6 7 0001 0010 0011 0100 0101 0110 0111 DEL SP 0 @ P ` p DC1 ! 1 A Q a q DC2 2 B R b r DC3 # 3 C S c s DC4 $ 4 D T d t NAK % 5 E U e u SYN & 6 F V f v ETB 7 G W g w CAN ( 8 H X h x EM ) 9 I Y i y SUB * : J Z j z ESC + ; K [ k { FS , < L \ l | GS = M ] m } RS . > N ^ n ~ US / ? O _ o DEL

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8172 16384 32768

$0001 $0002 $0004 $0008 $0010 $0020 $0040 $0080 $0100 $0200 $0400 $0800 $1000 $2000 $4000 $8000

16 65536 $10000 17 131072 $20000 18 262144 $40000 19 524288 $80000 20 1048576 $100000 21 2097152 $200000 22 4194304 $400000 23 8388608 $800000 24 16777216 $1000000 25 33554432 $2000000 26 67108864 $4000000 27 134217728 $8000000 28 268435456 $10000000 29 536870912 $20000000 30 1073741824 $40000000 31 2147483648 $80000000

Button BG Colour OBJ0 Colour OBJ1 Colour None Green & Blue Red Red Up Brown Brown Brown Up+A Red Green Blue Up+B Dark Brown Brown Brown Left Blue Red Green Left+A Dark Blue Red Brown Left+B Grey Grey Grey Down Yellow, Red, Blue Yellow, Red, Blue Yellow, Red, Blue Down+A Yelow & Red Yellow & Red Yellow & Red Down+B Yellow Blue Green Right Green & Red Green & Red Green & Red Right+A Green & Blue Red Red Right+B Reverse Reverse Reverse

ASCII Character Set

Built-in Colour Palettes

Powers of Two

ROM Sizes

Power Consumption

Type 00 01 02 03 06 Type 00 01 02 03 04 05 06 07 08 52 53 54

Copyright (C) 1999 Otaku No Zoku. No part of this work may be sold for profit.

aa aa

DEC SP DI EI HALT INC (HL) INC A INC B INC BC INC C INC D INC DE INC E INC H INC HL INC L INC SP JP $aabb JP (HL) JP C,$aabb JP NC,$aabb JP NZ,$aabb JP Z,$aabb JR $xx JR C,$xx JR NC,$xx JR NZ,$xx JR Z,$xx LD ($aabb),A LD ($aabb),SP LD ($xx),A LD (BC),A LD (C),A LD (DE),A LD (HL),$xx LD (HL),A LD (HL),B LD (HL),C LD (HL),D LD (HL),E LD (HL),H LD (HL),L LD (HLD),A LD (HLI),A LD A,$xx LD A,($aabb) LD A,($xx) LD A,(BC) LD A,(C) LD A,(DE) LD A,(HL) LD A,(HLD) LD A,(HLI) LD A,A LD A,B LD A,C LD A,D LD A,E LD A,H LD A,L LD B,$xx LD B,(HL) LD B,A LD B,B LD B,C LD B,D LD B,E LD B,H LD B,L LD BC,$aabb LD C,$xx LD C,(HL) LD C,A LD C,B LD C,C LD C,D LD C,E LD C,H LD C,L LD D,$xx LD D,(HL) LD D,A LD D,B LD D,C LD D,D LD D,E LD D,H LD D,L LD DE,$aabb LD E,$xx LD E,(HL) LD E,A LD E,B LD E,C LD E,D LD E,E LD E,H LD E,L LD H,$xx LD H,(HL) LD H,A LD H,A LD H,B LD H,C LD H,D LD H,E LD H,H LD H,L LD HL,$aabb LD HL,SP LD L,$xx LD L,(HL) LD L,B LD L,C LD L,D LD L,E LD L,H LD L,L LD SP,$aabb LD SP,HL NOP OR $xx OR (HL) OR A

B0 B1 B2 B3 B4 B5 F1 C1 D1 E1 F5 C5 D5 E5 CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB C9 D8 D0 C0 C8 D9 CB CB CB CB CB CB CB CB 17 CB CB CB CB CB CB CB CB 07 CB CB CB CB CB CB CB CB 1F CB CB CB CB CB CB CB CB 0F C7 CF D7

86 87 80 81 82 83 84 85 8E 8F 88 89 8A 8B 8C 8D 96 97 90 91 92 93 94 95 9E 9F 98 99 9A 9B 9C 9D A6 A7 A0 A1 A2 A3 A4 A5 AE AF A8 A9 AA AB AC AD B6 B7 B0 B1 B2 B3 B4 B5 BE BF B8 B9 BA BB BC BD

OR B OR C OR D OR E OR H OR L POP AF POP BC POP DE POP HL PUSH AF PUSH BC PUSH DE PUSH HL RES 0,(HL) RES 0,A RES 0,B RES 0,C RES 0,D RES 0,E RES 0,H RES 0,L RES 1,(HL) RES 1,A RES 1,B RES 1,C RES 1,D RES 1,E RES 1,H RES 1,L RES 2,(HL) RES 2,A RES 2,B RES 2,C RES 2,D RES 2,E RES 2,H RES 2,L RES 3,(HL) RES 3,A RES 3,B RES 3,C RES 3,D RES 3,E RES 3,H RES 3,L RES 4,(HL) RES 4,A RES 4,B RES 4,C RES 4,D RES 4,E RES 4,H RES 4,L RES 5,(HL) RES 5,A RES 5,B RES 5,C RES 5,D RES 5,E RES 5,H RES 5,L RES 6,(HL) RES 6,A RES 6,B RES 6,C RES 6,D RES 6,E RES 6,H RES 6,L RES 7,(HL) RES 7,A RES 7,B RES 7,C RES 7,D RES 7,E RES 7,H RES 7,L RET RET C RET NC RET NZ RET Z RETI RL (HL) RL A RL B RL C RL D RL E RL H RL L RLA RLC (HL) RLC A RLC B RLC C RLC D RLC E RLC H RLC L RLCA RR (HL) RR A RR B RR C RR D RR E RR H RR L RRA RRC (HL) RRC A RRC B RRC C RRC D RRC E RRC H RRC L RRCA RST $00 RST $08 RST $10

DF E7 EF F7 FF DE 9E 9F 98 99 9A 9B 9C 9D 37 CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB 10 D6 97 90 91 92 93 94 95 CB EE AE AF A8 A9 AA AB AC AD

xx

C6 C7 C0 C1 C2 C3 C4 C5 CE CF C8 C9 CA CB CC CD D6 D7 D0 D1 D2 D3 D4 D5 DE DF D8 D9 DA DB DC DD E6 E7 E0 E1 E2 E3 E4 E5 EE EF E8 E9 EA EB EC ED F6 F7 F0 F1 F2 F3 F4 F5 FE FF F8 F9 FA FB FC FD 26 27 20 21 22 23 24 25 2E 2F 28 29 2A 2B 2C 2D 3E 3F 38 39 3A 3B 3C 3D 00 xx

RST $18 RST $20 RST $28 RST $30 RST $38 SBC A,$xx SBC A,(HL) SBC A,A SBC A,B SBC A,C SBC A,D SBC A,E SBC A,H SBC A,L SCF SET 0,(HL) SET 0,A SET 0,B SET 0,C SET 0,D SET 0,E SET 0,H SET 0,L SET 1,(HL) SET 1,A SET 1,B SET 1,C SET 1,D SET 1,E SET 1,H SET 1,L SET 2,(HL) SET 2,A SET 2,B SET 2,C SET 2,D SET 2,E SET 2,H SET 2,L SET 3,(HL) SET 3,A SET 3,B SET 3,C SET 3,D SET 3,E SET 3,H SET 3,L SET 4,(HL) SET 4,A SET 4,B SET 4,C SET 4,D SET 4,E SET 4,H SET 4,L SET 5,(HL) SET 5,A SET 5,B SET 5,C SET 5,D SET 5,E SET 5,H SET 5,L SET 6,(HL) SET 6,A SET 6,B SET 6,C SET 6,D SET 6,E SET 6,H SET 6,L SET 7,(HL) SET 7,A SET 7,B SET 7,C SET 7,D SET 7,E SET 7,H SET 7,L SLA (HL) SLA A SLA B SLA C SLA D SLA E SLA H SLA L SRA (HL) SRA A SRA B SRA C SRA D SRA E SRA H SRA L SRL (HL) SRL A SRL B SRL C SRL D SRL E SRL H SRL L STOP SUB $xx SUB A SUB B SUB C SUB D SUB E SUB H SUB L SWAP A XOR $xx XOR (HL) XOR A XOR B XOR C XOR D XOR E XOR H XOR L

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A

NOP bb aa LD BC,$aabb LD (BC),A INC BC INC B DEC B xx LD B,$xx RLCA bb aa LD ($aabb),SP ADD HL,BC LD A,(BC) DEC BC INC C DEC C xx LD C,$xx RRCA 00 STOP bb aa LD DE,$aabb LD (DE),A INC DE INC D DEC D xx LD D,$xx RLA xx JR $xx ADD HL,DE LD A,(DE) DEC DE INC E DEC E xx LD E,$xx RRA xx JR NZ,$xx bb aa LD HL,$aabb LD (HLI),A INC HL INC H DEC H xx LD H,$xx DAA xx JR Z,$xx ADD HL,HL LD A,(HLI) DEC HL INC L DEC L xx LD L,$xx CPL xx JR NC,$xx bb aa LD SP,$aabb LD (HLD),A INC SP INC (HL) DEC (HL) xx LD (HL),$xx SCF xx JR C,$xx ADD HL,SP LD A,(HLD) DEC SP INC A DEC A xx LD A,$xx CCF LD B,B LD B,C LD B,D LD B,E LD B,H LD B,L LD B,(HL) LD B,A LD C,B LD C,C LD C,D LD C,E LD C,H LD C,L LD C,(HL) LD C,A LD D,B LD D,C LD D,D LD D,E LD D,H LD D,L LD D,(HL) LD D,A LD E,B LD E,C LD E,D LD E,E LD E,H LD E,L LD E,(HL) LD E,A LD H,B LD H,C LD H,D LD H,E LD H,H LD H,L LD H,(HL) LD H,A LD L,B LD L,C LD L,D LD L,E LD L,H LD L,L LD L,(HL) LD H,A LD (HL),B LD (HL),C LD (HL),D LD (HL),E LD (HL),H LD (HL),L HALT LD (HL),A LD A,B LD A,C LD A,D

7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB

LD A,E LD A,H LD A,L LD A,(HL) LD A,A ADD A,B ADD A,C ADD A,D ADD A,E ADD A,H ADD A,L ADD A,(HL) ADD A,A ADC A,B ADC A,C ADC A,D ADC A,E ADC A,H ADC A,L ADC A,(HL) ADC A,A SUB B SUB C SUB D SUB E SUB H SUB L SUB A SBC A,B SBC A,C SBC A,D SBC A,E SBC A,H SBC A,L SBC A,(HL) SBC A,A AND B AND C AND D AND E AND H AND L AND (HL) AND A XOR B XOR C XOR D XOR E XOR H XOR L XOR (HL) XOR A OR B OR C OR D OR E OR H OR L OR (HL) OR A CP B CP C CP D CP E CP H CP L CP (HL) CP A RET NZ POP BC JP NZ,$aabb JP $aabb CALL NZ,$aabb PUSH BC ADD A,$xx RST $00 RET Z RET JP Z,$aabb RLC B RLC C RLC D RLC E RLC H RLC L RLC (HL) RLC A RRC B RRC C RRC D RRC E RRC H RRC L RRC (HL) RRC A RL B RL C RL D RL E RL H RL L RL (HL) RL A RR B RR C RR D RR E RR H RR L RR (HL) RR A SLA B SLA C SLA D SLA E SLA H SLA L SLA (HL) SLA A SRA B SRA C SRA D SRA

CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB

2C 2D 2E 2F 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE

SRA H SRA L SRA (HL) SRA A SWAP A SRL B SRL C SRL D SRL E SRL H SRL L SRL (HL) SRL A BIT 0,B BIT 0,C BIT 0,D BIT 0,E BIT 0,H BIT 0,L BIT 0,(HL) BIT 0,A BIT 1,B BIT 1,C BIT 1,D BIT 1,E BIT 1,H BIT 1,L BIT 1,(HL) BIT 1,A BIT 2,B BIT 2,C BIT 2,D BIT 2,E BIT 2,H BIT 2,L BIT 2,(HL) BIT 2,A BIT 3,B BIT 3,C BIT 3,D BIT 3,E BIT 3,H BIT 3,L BIT 3,(HL) BIT 3,A BIT 4,B BIT 4,C BIT 4,D BIT 4,E BIT 4,H BIT 4,L BIT 4,(HL) BIT 4,A BIT 5,B BIT 5,C BIT 5,D BIT 5,E BIT 5,H BIT 5,L BIT 5,(HL) BIT 5,A BIT 6,B BIT 6,C BIT 6,D BIT 6,E BIT 6,H BIT 6,L BIT 6,(HL) BIT 6,A BIT 7,B BIT 7,C BIT 7,D BIT 7,E BIT 7,H BIT 7,(HL) BIT 7,A RES 0,B RES 0,C RES 0,D RES 0,E RES 0,H RES 0,L RES 0,(HL) RES 0,A RES 1,B RES 1,C RES 1,D RES 1,E RES 1,H RES 1,L RES 1,(HL) RES 1,A RES 2,B RES 2,C RES 2,D RES 2,E RES 2,H RES 2,L RES 2,(HL) RES 2,A RES 3,B RES 3,C RES 3,D RES 3,E RES 3,H RES 3,L RES 3,(HL) RES 3,A RES 4,B RES 4,C RES 4,D RES 4,E RES 4,H RES 4,L RES 4,(HL) RES 4,A RES 5,B RES 5,C RES 5,D RES 5,E RES 5,H RES 5,L RES 5,(HL)

CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CB CC CD CE CF D0 D1 D2 D4 D5 D6 D7 D8 D9 DA DC DE DF E0 E1 E2 E5 E6 E7 E8 E9 EA EE EF F0 F1 F2 F3 F5 F6 F7 F8 F9 FA FB FE FF

AF RES 5,A B0 RES 6,B B1 RES 6,C B2 RES 6,D B3 RES 6,E B4 RES 6,H B5 RES 6,L B6 RES 6,(HL) B7 RES 6,A B8 RES 7,B B9 RES 7,C BA RES 7,D BB RES 7,E BC RES 7,H BD RES 7,L BE RES 7,(HL) BF RES 7,A C0 SET 0,B C1 SET 0,C C2 SET 0,D C3 SET 0,E C4 SET 0,H C5 SET 0,L C6 SET 0,(HL) C7 SET 0,A C8 SET 1,B C9 SET 1,C CA SET 1,D CB SET 1,E CC SET 1,H CD SET 1,L CE SET 1,(HL) CF SET 1,A D0 SET 2,B D1 SET 2,C D2 SET 2,D D3 SET 2,E D4 SET 2,H D5 SET 2,L D6 SET 2,(HL) D7 SET 2,A D8 SET 3,B D9 SET 3,C DA SET 3,D DB SET 3,E DC SET 3,H DD SET 3,L DE SET 3,(HL) DF SET 3,A E0 SET 4,B E1 SET 4,C E2 SET 4,D E3 SET 4,E E4 SET 4,H E5 SET 4,L E6 SET 4,(HL) E7 SET 4,A E8 SET 5,B E9 SET 5,C EA SET 5,D EB SET 5,E EC SET 5,H ED SET 5,L EE SET 5,(HL) EF SET 5,A F0 SET 6,B F1 SET 6,C F2 SET 6,D F3 SET 6,E F4 SET 6,H F5 SET 6,L F6 SET 6,(HL) F7 SET 6,A F8 SET 7,B F9 SET 7,C FA SET 7,D FB SET 7,E FC SET 7,H FD SET 7,L FE SET 7,(HL) FF SET 7,A bb aa CALL Z,$aabb bb aa CALL $aabb xx ADC A,$xx RST $08 RET NC POP DE bb aa JP NC,$aabb bb aa CALL NC,$aabb PUSH DE xx SUB $xx RST $10 RET C RETI bb aa JP C,$aabb bb aa CALL C,$aabb xx SBC A,$xx RST $18 xx LD ($xx),A POP HL LD (C),A PUSH HL xx AND $xx RST $20 xx ADD SP,xx JP (HL) bb aa LD ($aabb),A xx XOR $xx RST $28 xx LD A,($xx) POP AF LD A,(C) DI PUSH AF xx OR $xx RST $30 LD HL,SP LD SP,HL bb aa LD A,($aabb) EI xx CP $xx RST $38

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 48 64 80 96 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 -128 -127 -126 -125 -124 -123 -122 -121 -120 -119 -118 -117 -116 -115 -114 -113 -112 -96 -80 -64 -48 -32 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1

$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $20 $30 $40 $50 $60 $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A $7B $7C $7D $7E $7F $80 $81 $82 $83 $84 $85 $86 $87 $88 $89 $8A $8B $8C $8D $8E $8F $90 $A0 $B0 $C0 $D0 $E0 $F0 $F1 $F2 $F3 $F4 $F5 $F6 $F7 $F8 $F9 $FA $FB $FC $FD $FE $FF

00 X X X X X X X 01X 1 02X X 1 03X X 1 X 05X 2 06X 2 X 08X X 09X X X 0BX X 0CX X X 0D X X X X 0FX 3 X X 10X X 3 X X 11X 3 12X X 3 13X X 3 X 15X 4 16X X 4 17X X 4 X 19X 5 1AX X 5 1BX X 5 X 1CX X X 1DX X 5 X 1EX X 5 X X FC Camera FD Bandai TAMA 5 FE HuC 3 FF HuC1/RAM/Batt

OTAKU NO GAMEBOY

MBC Features

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FF11 FF12

SB SC DIV TIMA TMA TAC IF LCDC

Serial Transfer Data Serial I/O Control Timer Divider Timer Counter Timer Modulo Timer Control Interrupt Flag LCD Control

2 0-1 7 6 5 3-4 2 1 0 6 5 4 3 2 0-1

FF01 FF02 FF04 FF05 FF06 FF07 FF0F FF40

7 6 0-2 6-7 0-5 4-7 3 0-2 7 6 0-2 7 5-6 7 6 0-2 0-5 4-7 3 0-2 4-7 3 0-2 7 6 7 4-6 3 0-2 7 6 5 4 3 2 1 0 7 3 2 1 0

FF13 FF14

FF16 FF17

STAT Hardware Registers

LCD Status

FF41

FF1A FF1B FF1C FF1D FF1E

SCY SCX LY LYC DMA BGP OBP0 OBP1 WY WX KEY1 VBK HDMA1 HDMA2 HDMA3 HDMA4 HDMA5 RP BCPS BCPD OCPS OCPD SVBK IE

Scroll Screen Y Scroll Screen X LCDC Y-Coord LY Compare DMA Transfer BG Palette Data Obj Palette 0 Data Obj Palette 1 Data Window Y Pos Window X Pos CPU Speed Select VRAM Bank Select HBL General DMA HBL General DMA HBL General DMA HBL General DMA HBL General DMA Infrared Comms Bkg Colour Index Bkg Colour Data Obj Colour Index Obj Colour Data RAM Bank Select Interrupt Enable

4 3 2 1 0

FF42 FF43 FF44 FF45 FF46 FF47 FF48 FF49 FF4A FF4B FF4D FF4F FF51 FF52 FF53 FF54 FF55 FF56 FF68 FF69 FF6A FF6B FF70 FFFF

FF20 FF21

FF22 Note C0 C# 0 D0 D# 0 E0 F0 F# 0 G0 G# 0 A0 A# 0 B0 C1 C# 1 D1 D# 1 E1 F1 F# 1 G1 G# 1 A1 A# 1 B1 C2 C# 2 D2 D# 2 E2 F2 F# 2 G2 G# 2 A2 A# 2 B2 C3 C# 3 D3 D# 3 E3 F3 F# 3 G3 G# 3 A3 A# 3 B3 C4 C# 4 D4 D# 4 E4 F4 F# 4 G4 G# 4 A4 A# 4 B4 C5 C# 5 D5 D# 5 GB Hz 8.176 8.662 9.177 9.723 10.301 10.913 11.562 12.250 12.978 13.750 14.568 15.434 16.352 17.324 18.354 19.445 20.601 21.826 23.124 24.499 25.956 27.500 29.135 30.867 32.703 34.648 36.708 38.890 41.203 43.653 46.249 48.999 51.913 55.000 58.270 61.735 65.406 69.295 73.416 77.781 82.406 87.307 92.499 97.998 103.82 110.00 116.54 123.47 130.81 138.59 146.83 155.56 164.81 174.61 184.99 195.99 207.65 220.00 233.08 246.94 261.63 277.18 293.66 311.13 Note E5 F5 F# 5 G5 G# 5 A5 A# 5 B5 C6 C# 6 D6 D# 6 E6 F6 F# 6 G6 G# 6 A6 A# 6 B6 C7 C# 7 D7 D# 7 E7 F7 F# 7 G7 G# 7 A7 A# 7 B7 C8 C# 8 D8 D# 8 E8 F8 F# 8 G8 G# 8 A8 A# 8 B8 C9 C# 9 D9 D# 9 E9 F9 F# 9 G9 G# 9 A9 A# 9 B9 C 10 C# 10 D 10 D# 10 E 10 F 10 F# 10 G 10 GB 1650 1673 1694 1714 1732 1750 1767 1783 1798 1812 1825 1837 1849 1860 1871 1881 1890 1899 1907 1915 1923 1930 1936 1943 1949 1954 1959 1964 1969 1974 1978 1982 1985 1988 1992 1995 1998 2001 2004 2006 2009 2011 2013 2015

FF23 FF24

FF25

FF26

FF3F

Do not switch ROM Banks if the DMA source address is in the high ROM. Do not switch RAM Banks if the DMA source address is in the WRAM. Do not switch VRAM Banks until HDMA has completed. Source & Destination address must be 256byte aligned. HALT cannot be used while a HDMA transfer is taking place. HDMA must complete before another is initiated or HDMA registers are altered. Transfer length must be correct. $80 = 16 bytes, $81 = 32 bytes, $82 = 48 bytes. Bit 7 of HDMA 5 is clear during HDMA transfer, set on completion. GDMA is only reliable during VBL when LCD is enabled. CPU halts until GDMA completes.

4000-7FFF D000-DFFF 8000-9FFF xx00 Tone Conversion Table

FF55

GDMA transfer time in 1xCPU mode. n = 220+n*7.63s # of 16-bytes block to transfer. GDMA transfer time in 2xCPU mode. n = 110+n*7.63s # of 16-byte blocks to transfer.

44 156 262 363 457 547 631 710 786 854 923 986 1046 1102 1155 1205 1253 1297 1339 1379 1417 1452 1486 1517 1546 1575 1602 1627

Hz 329.63 349.23 369.99 391.99 415.31 440.00 466.16 493.88 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.32 987.77 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.7 1975.5 2093.0 2217.5 2349.3 2489.0 2637.0 2793.8 2960.0 3136.0 3322.4 3520.0 3729.3 3951.1 4186.0 4434.9 4698.6 4978.0 5274.0 5587.7 5919.9 6271.9 6644.9 7040.0 7458.6 7902.1 8372.0 8869.8 9397.3 9956.1 10548.1 11175.3 11839.8 12543.9

DMA Precautions

Copyright (C) 1999 Otaku No Zoku. No part of this work may be sold for profit.

FF18 FF19

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Register P1

Purpose Read Joypad Info

Access W W R R R R R/W R/W R/W R/W R/W Timer start/stop R/W Timer speed R/W R/W LCD On/Off R/W Window Addr R/W Window On/Off R/W Background Addr R/W Object Size R/W Object On/Off R/W Background On/Off R/W LYCEQUL Coincidence R/W Y Mode 10 R/W Mode 01 (V-Blank) R/W Mode 00 (H-Blank) R/W Coincidence Flag R/W OAM/VRAM Lock R/W Vertical scroll R/W Horizontal scroll R/W R/W R/W R/W R/W R/W R/W R/W R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W GBC only R/W HILO Transition R/W Serial I/O Transfer Done R/W Timer Overflow R/W LCDC R/W VBL R/W

Comment P1F_5 P1F_4 P1F_3 P1F_2 P1F_1 P1F_0

Bit 5 4 3 2 1 0

Address Register FF00 NR10

Comment Access Sweep time R/W Sweep increase/decrease R/W Sweep shift R/W NR11 Audio Chan #1 Wave pattern duty R/W Sound length data R/W NR12 Envelope Chan #1 Initial value of envelope R/W Envelope Up/Down R/W Number of envelope sweep R/W NR13 Sound Freq #1 Frequency LSB W NR14 Sound Freq #1 Initialise W Counter/consecutive selection W Frequency significant 3 bits W NR21 Audio Chan #2 Wave pattern duty R/W Sound length data R/W NR22 Envelope Chan #2 Initial value of envelope R/W Envelope Up/Down R/W Number of envelope sweep R/W NR23 Sound Freq #2 Frequency LSB W NR24 Sound Freq #2 Initialise W Counter/consecutive selection W Frequency significant 3 bits W NR30 Audio Chan #3 Sound On/Off R/W NR31 Sound Len #2 Sound length R/W NR32 Volume #3 Select output level R/W NR33 Sond Freq #3 Frequency LSB W NR34 Sound Freq #3 Initialise W Counter/consecutive selection W Frequency significant 3 bits W NR41 Sound Len #4 Sound length R/W NR42 Envelope #4 Initial value of envelope R/W Envelope Up/Down R/W Number of envelope sweep R/W NR43 Audio Counter Freq of polynomial counter R/W Polynomial counter's step R/W Dividing ratio of freq R/W NR44 Audio Control Initialise audio R/W Counter/consecutive selection R/W NR50 Channel Control Vin SO2 On/Off R/W SO2 ouput volume R/W Vin SO1 On/Off R/W SO1 ouput volume R/W NR51 Sound Output Output sound 4 to SO2 R/W Output sound 3 to SO2 R/W Output sound 2 to SO2 R/W Output sound 1 to SO2 R/W Output sound 4 to SO1 R/W Output sound 3 to SO1 R/W Output sound 2 to SO1 R/W Output sound 0 to SO1 R/W NR52 Sound On/Off All Channels On/Off R/W Channel #4 On/Off R/W Channel #3 On/Off R/W Channel #2 On/Off R/W Channel #1 On/Off R/W AUD3WA VERAM Sound sample RAM(16 bytes) R/W

Purpose Audio Sweep

Bit 4-6 3 0-2 6-7 0-5 4-7 3 0-2

Address FF10

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X < Y

is_greater: JR CALL not_less_than: X == Y LD CP JR LD CP JR CALL not_equal: X <= Y LD CP JR LD CP is_less_than: JR CALL not_lt_or_eq: Unsigned 16-bit Compare NC,not_less_than condition_true A,C E NZ,not_equal A,B D NZ,not_equal condition_true A,B D NZ,is_less_than A,C E C,not_lt_or_eq condition_true ; LSB/MSB not less than, expr not equal ; X < Y, condition is true ; ; ; ; ; ; ; ; ; ; ; ; get LSB of value X compare with LSB of value Y not equal, condition failed get MSB of value X compare with MSB of value Y LSB/MSB not less than, expr not equal X == Y, condition is true get MSB of value compare with MSB not equal? Maybe get LSB of value compare with LSB X of value Y less than X of value Y

OTAKU NO GAMEBOY

BC contains 16-bit unsigned value X DE contains 16-bit unsigned value Y LD A,B ; get MSB of value X CP D ; compare with MSB of value Y JR NZ,is_greater ; not equal, test for greater than LD A,C ; get LSB of value X CP E ; compare with LSB of value Y

Handling VRAM Col/Row Vertical Col & Row To VRAM Addr Wrap Horizontal VRAM Wrap VRAM Wrap

; LSB/MSB not less than or equal? ; X <= Y, condition is true

X < Y

BC contains 16-bit signed value X DE contains 16-bit signed value Y LD A,B ; get MSB of value X ADD $80 ; flip sign bit of MSB LD L,A ; save signed MSB value for later LD A,D ; get MSB of value Y ADD $80 ; flip sign bit of MSB CP L ; compare LSB of value X & value Y JR NZ,.different ; equal? no, so test for less than LD A,E ; get LSB of value Y CP C ; compare LSB of value X & value Y JP CALL NC,.greater condition_true A,C E NZ,.different A,B D NZ,.different condition_true A,D $80 L,A A,B $80 L NZ,.different A,C E C,.greater condition_true ; less than? no, so value X >= value Y ; X < Y, condition is true ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; get LSB of value X compare with LSB of value Y equal? No, so test is false get MSB of value X compare with MSB of value Y equal? no, so test is false X == Y, condition is true get MSB of value Y flip sign bit of MSB save signed MSB value for later get MSB of value X flip sign bit of MSB compare MSB of value X & value Y equal? no, so test for greater than get LSB of value X compare with LSB of value Y 8-bit Unsigned Comp A<B JP A<=B JP JP A=B JP A<>B JP A>=B JP A>B JR JP

.different: Signed 16-bit Compare

.greater: X == Y

LD CP JP LD CP JP CALL

.different: X <= Y LD ADD LD LD ADD CP JR LD CP .different: JP CALL .greater:

C,yes C,yes Z,yes Z,yes NZ,yes NC,yes C,3 NZ,yes

; greater? yes, so value X > value Y ; X <= Y, condition is true

X < Y

A contains an unsigned 8-bit number C contains an unsigned 8-bit number CP C ; compare X & Y JP NC,.less ; carry? no, so Y >= X JP Z,.equal ; equal? yes, so X == Y CALL condition_true ; X < Y, condition is true

.less: .equal: X <= Y

CP JP CALL CP JP CALL

C NC,.greater condition_true C NZ,.not_equal condition_true C Z,.equal condition_true C C,.greater Z,.equal condition_true

; compare X & Y ; carry? no, so Y > X ; X <= Y, condition is true ; compare X & Y ; equal? No, so X <> Y ; X == Y, condition is true ; compare X & Y ; equal? yes, so X == Y ; X <> Y, condition is true ; ; ; ; compare X & Y carry? yes, so Y > X equal? yes, so X == Y X == Y, condition is true

.greater: X == Y

.not_equal: X <> Y CP JP CALL .equal: X > Y CP JP JP CALL .greater: .equal: X >= Y CP JP CALL .greater:

C C,.less condition_true

; compare X & Y ; carry? yes, so Y > X ; X >= Y, condition is true

Copyright (C) 1999 Otaku No Zoku. No part of this work may be sold for profit.

vram_addr = 0x9800 | (vram_addr & 0x0300) ; LD A,[vram_addr_MSB] ; get msb of vram addr AND $03 ; vram is $9800 to $9BFF OR $98 ; add on start of vram LD [vram_addr_MSB],A ; store msb of vram addr (4) vram_addr = (vram_addr & 0xFFE0) | (vram_addr & 0x1F) LD A,[vram_addr_LSB] ; get lsb of vram addr (4) LD B,A ; copy lsb of vram addr (1) AND $E0 ; mask row start addr (2) LD C,A ; save result (1) LD A,B ; get lsb of vram addr (1) AND $1F ; calculate col offset (1) OR C ; add row start addr (1) LD [vram_addr_LSB],A ; store lsb of vram addr (4) col = col & 0x1F ; // row = row & 0x1F ; LD A,[col] ; get column (or row) (4) AND $1F ; keep it inside of vram (2) LD [col],A ; store column (or row) (4) vram_addr = 0x9800 | (col | ((UWORD)(row) << 5)) ; LD A,[row] ; get row (4) SWAP ; x 16 (2) RLC ; x 32 (2) LD C,A ; save result for later (1) AND $03 ; calc msb vram row start (2) ADD $98 ; add start of vram (2) LD B,A ; set msb of vram ptr (1) LD A,$E0 ; lsb vram row start mask (2) AND C ; calc lsb vram row start (1) LD C,A ; save lsb vram row start (1) LD A,[col] ; get column (4) ADD C ; add lsb vram row start (1) LD C,A ; BC contains vram addr (1)

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