Cong Nghe FPGA

FPGA Synthesizer
講師：林木山
聯絡電話：03-5773693 ext 166
Email: tony@cic.edu.tw
CIC Training Manual HDL Design Flow & Tools - 1

Course Outline
uHDL Design Flow & Tools
uHDL Coding Hints
uExplore Synopsys FPGA Express Tool

HDL Design Flow & Tools
u FPGA Design Flow
• Design Ideas
• Detailed Design
• Functional Simulation
• Synthesis & Implementation
• Timing Simulation
• Device Programming
u Altera HDL Design Flow & Tools
u Xilinx HDL Design Flow & Tools

FPGA/CPLD Design Flow
Design
Design Detailed
Detailed Functional
Functional
Ideas
Ideas Design
Design Simulation
Simulation
Device
Device Timing
Timing Synthesis
Synthesis&&
Programming
Programming Simulation
Simulation Implementation
Implementation
FPGA
CPLD t pd=22.1ns
f max=47.1MHz

Design Ideas
u What are the main design considerations?
• Design feasibility?
• Design spec?
• Cost?
• FPGA/CPLD or ASIC?
• Which FPGA/CPLD vendor?
• Which device family?
• Development time?

Detailed Design
u Choose the design entry method
• Schematic
– Gate level design
– Intuitive & easy to debug
• HDL (Hardware Description Language), e.g. Verilog & VHDL
– Descriptive & portable
– Easy to modify
• Mixed HDL & schematic
u Manage the design hierarchy
• Design partitioning
– Chip partitioning
– Logic partitioning
• Use vendor-supplied libraries or parameterized libraries to reduce design time
• Create & manage user-created libraries (circuits)

Functional Simulation
u Preparation for simulation
• Generate simulation patterns
– Waveform entry
– HDL testbench
• Generate simulation netlist
u Functional simulation
• To verify the functionality of your design only
u Simulation results
• Waveform display
• Text output
u Challenge
• Sufficient & efficient test patterns

HDL Synthesis
assign z=a&b
a
u Synthesis = Translation + Optimization

z
b
• Translate HDL design files into gate-level netlist

• Optimize according to your design constraints
– Area constraints
– Timing constraints
– Power constraints
– ...
u Main challenges
• Learn synthesizable coding style
• Write correct & synthesizable HDL design files
• Specify reasonable design constraints
• Use HDL synthesis tool efficiently

Design Implementation
a
z
b
u Implementation flow
FPGA
CPLD
01011...
• Netlist merging, flattening, data base building

• Design rule checking
• Logic optimization
• Block mapping & placement
• Net routing
• Configuration bitstream generation
u Implementation results
• Design error or warnings
• Device utilization
• Timing reports
u Challenge
• How to reach high performance & high utilization implementation?

Timing Analysis & Simulation
t pd=22.1ns
uTiming analysis
f max=47.1MHz
• Timing analysis is static, i.e., independent of input & output patterns

• To examine the timing constraints
• To show the detailed timing paths
• Can find the critical path
u Timing simulation
• To verify both the functionality & timing of the design

Device Programming
u Choose the appropriate configuration scheme FPGA
• SRAM-based FPGA/CPLD devices CPLD
– Downloading the bitstream via a download cable

– Programming onto a non-volatile memory device & attaching it on the circuit board
• OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices
– Using hardware programmer
– ISP
u Finish the board design
u Program the device
u Challenge
• Board design
• System considerations

Our Focus: HDL Design Flow
u Why HDL?
• Can express digital systems in behavior or structure domain, shortening the design time
• Can support all level of abstraction, including algorithm, RTL, gate and switch level
• Both VHDL & Verilog are formal hardware description languages, thus portable
u Typical HDL design flow
• Use VHDL or Verilog to express digital systems
– VHDL or Verilog simulation tool is required to simulate your project
• Use high-level synthesis tool to obtain structural level design
• Then use FPGA placement & routing tools to obtain physical FPGA netlist
u We assume you are familiar with VHDL or Verilog...
• In this course, we’ll emphasize on FPGA HDL coding techniques for synthesis
– It’s the key issue to reduce area and achieve high performance for your project
• We assume you know how to use VHDL or Verilog simulator too

Altera HDL Design Flow
Design Functional Simulation

DesignEntry:
Entry: Design
DesignVerification
Verification
Verilog/VHDL
Verilog/VHDL (Verilog-XL/VSS)
(Verilog-XL/VSS)
Timing Simulation
HDL
HDLSynthesis
Synthesis
(FPGA
(FPGACompiler)
Compiler)
Third-Party
Altera MAX+PLUS
MAX+PLUSIIII
Timing
TimingAnalyzer
Analyzer
MAX+PLUS
MAX+PLUSIIII
Compiler
Compiler Timing Analysis
Synthesis & Fitting, MAX+PLUS

Partitioning, MAX+PLUSIIII
Placement, Routing Programmer
Programmer
Device Programming

Xilinx HDL Design Flow
Design Functional Simulation

DesignEntry:
Entry: Design
DesignVerification
Verification
Verilog/VHDL
Verilog/VHDL (Verilog-XL/VSS)
(Verilog-XL/VSS)
Timing Simulation
Logic
LogicSynthesis
Synthesis
(FPGA
(FPGACompiler)
Compiler)
Third-Party
Xilinx M1
M1Timing
Timing
Analyzer
Analyzer
Alliance
AllianceSeries
Series
XACTstep
XACTstepM1 M1 Timing Analysis
Optimization, Mapping, M1
Placement & Routing M1Hardware
Hardware
Debugger
Debugger
Device Programming

Design Entry
u Write HDL design files
• Must learn synthesizable RTL Verilog or VHDL coding style for the synthesis tool
• Tool: text editor library IEEE;
use IEEE.STD_LOGIC_1164.all;
– xedit, textedit, vi, joe, ... entity converter is
port ( i3, i2, i1, i0: in STD_LOGIC;
a, b, c, d, e, f, g: out STD_LOGIC);
end converter;
module converter(i3,i2,i1,i0,a,b,c,d,e,f,g); architecture case_description of converter is
input i3, i2, i1, i0 ; begin
output a, b, c, d, e, f, g; P1: process(i3, i2, i1, i0)
reg a,b,c,d,e,f,g; variable tmp_in: STD_LOGIC_VECTOR(3 downto 0);
begin
always @(i3 or i2 or i1 or i0) begin tmp_in := i3 & i2 & i1 & i0;
case({i3,i2,i1,i0}) case tmp_in is
4'b0000: {a,b,c,d,e,f,g}=7'b1111110; when "0000" => (a,b,c,d,e,f,g) <= STD_LOGIC_VECTOR'("1111110");
endcase when others => (a,b,c,d,e,f,g) <= STD_LOGIC_vector'("0000000");
end end case;
end process P1;
endmodule end case_description;

HDL Functional Simulation
u Write HDL testbench files
u Prepare technology-dependent simulation model, if necessary
u Verilog functional simulation
• Tool: Verilog simulator
FCadence Verilog-XL
– Viewlogic VCS
u VHDL functional simulation
• Tool: VHDL simulator
FSynopsys VSS
– Viewlogic SpeedWave
– Cadence LeapFrog

Verilog Functional Simulation

VHDL Functional Simulation

HDL Synthesis
u Prepare synthesis library
u Transfer HDL design file into gate-level netlist
• Tool: HDL synthesis software
FSynopsys: Design Analyzer, HDL/VHDL Compiler & FPGA Compiler
– Viewlogic ViewSynthesis (for VHDL only)
– Cadence Synergy
• Generate EDIF netlist file (*.edf) for Altera design
• Generate XNF netlist files (*.sxnf) for Xilinx design

FPGA Implementation
u Gate-level netlist -> configuration bitstream & timing information
• Altera development tool: Altera MAX+PLUS II software
– MAX+PLUS II Compiler
– MAX+PLUS II Floorplan Editor
• Xilinx development tool: Xilinx XACTstep M1 software
– Xilinx Design Manager
– Flow Engine
– EPIC Design Editor

Altera Implementation

Xilinx Implementation

Timing Analysis
u Check critical timing path & clock rate
• Altera timing analysis tool: Altera MAX+PLUS II Timing Analyzer
• Xilinx timing analysis tool: Xilinx Timing Analyzer

Altera Timing Analysis

Xilinx Timing Analysis

Timing Simulation
u Generate timing HDL files and delay back-annotation files
• Altera tool: MAX+PLUS II Compiler
• Xilinx tool: ngdanno, ngd2vhd, ngd2ver utilities
u Prepare testbench files
u Prepare technology-dependent simulation model, if necessary
u Verilog timing simulation
• Tool: Verilog simulator
u VHDL timing simulation
• Tool: VHDL simulator

Verilog Timing Simulation

VHDL Timing Simulation

Device Programming
u Prepare the configuration bitstream file
u Configure FPGA device(s)
• By downloading the configuration bitstream via a download cable
• By programming the configuration bitstream onto a non-volatile memory device & attaching
it on the circuit board
download cable
FPGA
output display

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FPGA Synthesizer

CIC Training Manual HDL Design Flow & Tools - 1

CIC Training Manual HDL Design Flow & Tools - 2

CIC Training Manual HDL Design Flow & Tools - 3

CIC Training Manual HDL Design Flow & Tools - 4

CIC Training Manual HDL Design Flow & Tools - 5

CIC Training Manual HDL Design Flow & Tools - 6

CIC Training Manual HDL Design Flow & Tools - 7

u Synthesis = Translation + Optimization

• Translate HDL design files into gate-level netlist

CIC Training Manual HDL Design Flow & Tools - 8

• Netlist merging, flattening, data base building

CIC Training Manual HDL Design Flow & Tools - 9

• Timing analysis is static, i.e., independent of input & output patterns

CIC Training Manual HDL Design Flow & Tools - 10

• SRAM-based FPGA/CPLD devices CPLD

– Downloading the bitstream via a download cable

CIC Training Manual HDL Design Flow & Tools - 11

CIC Training Manual HDL Design Flow & Tools - 12

Design Functional Simulation

Synthesis & Fitting, MAX+PLUS

CIC Training Manual HDL Design Flow & Tools - 13

Design Functional Simulation

CIC Training Manual HDL Design Flow & Tools - 14

CIC Training Manual HDL Design Flow & Tools - 15

CIC Training Manual HDL Design Flow & Tools - 16

CIC Training Manual HDL Design Flow & Tools - 17

CIC Training Manual HDL Design Flow & Tools - 18

CIC Training Manual HDL Design Flow & Tools - 19

CIC Training Manual HDL Design Flow & Tools - 20

CIC Training Manual HDL Design Flow & Tools - 21

CIC Training Manual HDL Design Flow & Tools - 22

CIC Training Manual HDL Design Flow & Tools - 23

CIC Training Manual HDL Design Flow & Tools - 24

CIC Training Manual HDL Design Flow & Tools - 25

CIC Training Manual HDL Design Flow & Tools - 26

CIC Training Manual HDL Design Flow & Tools - 27

CIC Training Manual HDL Design Flow & Tools - 28

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