VHDL

VHDL
VHDL
VHDL

6.1 VHDL
6.1.1
IEEE
IEEESTD_LOGIC_1164NUMERIC_STD
NUMERIC_BIT 3STD_LOGIC_1164

STD

STANDARDTEXTIO

WORK

WORKWORK WORK
VHDL

VITAL

VITALIEEE,IEEE
VITAL_TIMINGVITAL_PRIMITIVES

6.1 VHDL
6.1.2
LIBRARY
USE
USE

USE ..
USE ..ALL

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

6.2 VHDL

PACKAGE
-- Type Declaration (optional)
-- Subtype Declaration (optional)
-- Constant Declaration (optional)
-- Signal Declaration (optional)
-- Component Declaration (optional)
-- Subprogram Declaration (optional)
END ;

PACKAGE BODY IS
-- Type Declaration (optional)
-- Subtype Declaration (optional)
-- Constant Declaration (optional)
-- Function Declaration (optional)
-- Procedure Declaration (optional)
-- Function Body (optional)
-- Procedure Body (optional)
END

6.2 VHDL1
6.1
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
PACKAGE my_pkg IS --
TYPE byte IS INTEGER RANGE 0 TO 255;
SUBTYPE helf_byte IS byte RANGE 0 TO 15;
CONSTANT byte_max: byte:= 255;
FUNCTION min (left, right: INTEGER) RETURN INTEGER;
COMPONENT signed_adder --WORK
GENERIC( data_width : NATURAL := 8);
PORT(
a
: IN SIGNED((data_width-1) DOWNTO 0);
b
: IN SIGNED((data_width-1) DOWNTO 0);
result : OUT SIGNED ((data_width-1) DOWNTO 0));
END COMPONENT;
END my_pkg;
PACKAGE BODY my_pkg IS --
FUNCTION min (left, right: INTEGER) RETURN INTEGER IS
BEGIN
IF left < right THEN RETURN left;
ELSE RETURN right;
END IF;
END min;
END my_pkg;

6.2 VHDL2
6.2
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE seg7 IS
TYPE bcd IS INTEGER RANGE 0 TO 9;
SUBTYPE segments IS STD_LOGIC_VECTOR(0 TO 6);
END seg7;
USE WORK.seg7.ALL;
ENTITY bcd_to_segments IS
PORT(
input: IN bcd;
drive: OUT segments
);
END bcd_to_segments;

6.2

VHDL3

6.2
ARCHITECTURE bev OF bcd_to_segments IS
BEGIN
WITH input SELECT
drive <= b"0000001" WHEN 0,
b"1001111" WHEN 1,
b"0010010" WHEN 2,
b"0000110" WHEN 3,
b"1001100" WHEN 4,
b"0010010" WHEN 5,
b"0010000" WHEN 6,
b"0001111" WHEN 7,
b"0000000" WHEN 8,
b"0001100" WHEN 9,
b"1111111" WHEN OTHERS;
END bev;

6.3 VHDL
6.3.1

VHDL

FUNCTION RETURN

FUNCTION RETURN IS --

BEGIN

END FUNCTION
--

6.3.1

VHDL1

6.3
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
--
PACKAGE pack_exam IS
FUNCTION max(a, b: IN STD_LOGIC_VECTOR )
RETURN STD_LOGIC_VECTOR;
END pack_exam;
--
PACKAGE BODY pack_exam IS
FUNCTION max(a, b: IN STD_LOGIC_VECTOR )
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF a > b THEN
RETURN a; --
ELSE RETURN b;
END IF;
END FUNCTION C;
END pack_exam;

6.3.1 VHDL2
6.4
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.pack_exam.ALL;
ENTITY func_exam IS
PORT(data1, data2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data3, data4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out1, out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END func_exam;
ARCHITECTURE behavioral OF func_exam IS
BEGIN
out1 <= max( data1, data2 );
PROCESS(data3, data4)
BEGIN
out2 <= max( data3, data4 );
END PROCESS;
END behavioral;

6.3.1

VHDL3

6.4
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.pack_exam.ALL;
ENTITY func_exam IS
PORT(data1, data2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
data3, data4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
out1, out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END func_exam;
ARCHITECTURE behavioral OF func_exam IS
BEGIN
out1 <= max( data1, data2 );
PROCESS(data3, data4)
BEGIN
out2 <= max( data3, data4 );
END PROCESS;
END behavioral;

LessThan1

data4[3..0]
data3[3..0]

A[3..0]
B[3..0]

OUT

LESS_THAN

max~[7..4]
SEL
DATAA
DATAB

OUT0

out2[3..0]

LessThan0
MUX21

data2[3..0]
data1[3..0]

A[3..0]
B[3..0]

OUT
max~[3..0]
LESS_THAN

SEL
DATAA
DATAB

OUT0

MUX21

6.1 6.3RTL

out1[3..0]

6.3.2

VHDL

VHDL

Overloaded Function
6.5
PACKAGE STD_LOGIC_UNSIGNED IS
FUNCTION "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;

PACKAGE BODY STD_LOGIC_UNSIGNED IS

FUNCTION "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
CONSTANT length: INTEGER := maximum(L'length, R'length);
VARIABLE result : STD_LOGIC_VECTOR (LENGTH-1 DOWNTO 0);
BEGIN
result := UNSIGNED(L) + UNSIGNED(R);
RETURN STD_LOGIC_VECTOR(result);
END;

6.3.3

VHDL

VHDL
VHDL

6.3.3 VHDL1
1.
PROCEDURE ( );

2.
PROCEDURE ( ) IS

BEGIN

END PROCEDURE

PROCEDURE produ1 ( VARIABLE a, b: INOUT STD_LOGIC );

3.
( )

6.3.3

VHDL2

6.6
PROCEDURE count_zeros (A: IN BIT_VECTOR;
SIGNAL Q: OUT INTEGER) IS
VARIABLE zeros : INTEGER;
BEGIN

zeros := 0;
FOR i IN A'RANGE LOOP
IF A(i) = '0' THEN
zeros := zeros +1;

END IF;
END LOOP;
Q <= zeros;
END count_zeros;

6.3.3

VHDL3

6.7
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
PACKAGE pkg IS
PROCEDURE nand_4 (
SIGNAL s1, s2, s3, s4: IN STD_LOGIC;
SIGNAL y
: OUT STD_LOGIC);
END pkg;
PACKAGE BODY pkg IS
PROCEDURE nand_4 (
SIGNAL s1, s2, s3, s4: IN STD_LOGIC;
SIGNAL y
: OUT STD_LOGIC) IS
BEGIN
y <= NOT( s1 AND s2 AND s3 AND s4 );
RETURN;
END nand_4;
END pkg;

6.3.3

VHDL4

6.7
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.pkg.ALL;
ENTITY nand_8 IS
PORT( a1, a2, a3, a4: IN STD_LOGIC;
a5, a6, a7, a8: IN STD_LOGIC;
f
: OUT STD_LOGIC);
END;
ARCHITECTURE data_flow OF nand_8 IS
SIGNAL middle1, middle2: STD_LOGIC;
BEGIN
nand_4( a1, a2, a3, a4, middle1); --
nand_4( a5, a6, a7, a8, middle2); --
f <= middle1 OR middle2;
END data_flow;

6.3.3

VHDL5

6.7
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE WORK.pkg.ALL;
ENTITY nand_8 IS
PORT( a1, a2, a3, a4: IN STD_LOGIC;
a5, a6, a7, a8: IN STD_LOGIC;
f
: OUT STD_LOGIC);
END;

a1
a2
a3
a4
f
a5
a6
a7
a8

ARCHITECTURE data_flow OF nand_8 IS

SIGNAL middle1, middle2: STD_LOGIC;
BEGIN
nand_4( a1, a2, a3, a4, middle1); --
nand_4( a5, a6, a7, a8, middle2); --
f <= middle1 OR middle2;
END data_flow;

6.2 6.7 RTL

6.3.3

VHDL

6.8
PROCEDURE read(l:INOUT line; value: OUT BIT; good : OUT boolean);
PROCEDURE read(l:INOUT line; value: OUT BIT);
PROCEDURE read(l:INOUT line; value: OUT BIT_VECTOR; good : OUT
boolean);
PROCEDURE read(l:INOUT line; value: OUT BIT_VECTOR);
PROCEDURE read(l:INOUT line; value: OUT boolean; good : OUT boolean);
PROCEDURE read(l:INOUT line; value: OUT boolean);


VHDL

VHDL