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BI 5: TIMER
MC CH
Gip sinh vin kho st cc vn sau: S dng phn mm Proteus m phng mch in. Tm hiu cch s dng Timer trong 89C51. My vi tnh. Phn mm Proteus
THIT B S DNG
1. C s l thuyt
Vi iu khin 89C51 c hai thanh ghi timer/counter 16 bit. Cc thanh ghi ny c th hot ng mt trong hai trng thi timer hoc counter. Mi thanh ghi gm 2 thanh ghi 8 bit ghp li:
PULSE INPUT THx : 8 BIT TLx : 8 BIT
Thanh ghi TCON (timer control): L thanh ghi 8 bit, c th truy xut byte hoc bit dng iu khin hot ng ca Timer.
7 TF1 6 5 4 TR0 3 IE1 2 1 0 IT0
TR1 TF0
IT1 IE0
TF1: bo trng thi trn cho b Timer/Counter1 TR1: iu khin cp xung cho b Timer/Counter1 TF0: bo trng thi trn cho b Timer/Counter0 TR0: iu khin cp xung cho b Timer/Counter0 IE1, IT1, IE0, IT0: s dng cho ngt ngoi 1 v ngt ngoi 0 (khng dng cho Timer). Thanh ghi TMOD (timer mode): L thanh ghi 8 bit, ch c th truy xut byte dng xc nh ch hot ng ca Timer.
7 GATE 6 5 4 M0 3 GATE 2 C/T 1 M1 0 M0
C/T M1
GATE, C/ T : iu khin trng thi hot ng cho Timer/ M1, M0: chn ch hot ng cho Timer/Counter M1 M0 CH 0 0 0 0 1 1 1 0 2 1 1 3 a/ Ch 0:
PULSE INPUT THx : 8 BIT TLx : 5 BIT TFx
M T Timer/Counter 13 bit Timer/Counter 16 bit Timer/Counter 8 bit, auto reload Timer/Counter 8 bit
Thanh ghi THx v TLx kt hp to thnh b Timer/Counter 13 bit, khi trn 13 bit th c TFx s t ln logic 1.
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b/ Ch 1 (16 bit):
PULSE INPUT THx : 8 BIT TLx : 8 BIT TFx
c/ Ch 2 (8 bit Auto-Reload):
PULSE INPUT TLx : 8 BIT TFx
OVERFLOW
THx : 8 BIT
TLx c np gi tr ban u t THx v bt u m t gi tr ny khi c xung ng vo, khi trn th TFx s t ln logic 1 ng thi kch hot b kha np gi tr trong THx vo TLx. d/ Ch 4:
PULSE INPUT TL0 : 8 BIT TF0
OSC:12
TH0 : 8 BIT
TF1
TR1
Trong ch ny, TH1 v TL1 khng c s dng thay vo l TH0 v TL0 hot ng nh 2 b Timer 8 bit (TL0) v Timer/Counter 8 bit (TL0). Tuy nhin, tn hiu m xung cho TH0 khng phi l TR0 m l TR1.
- Thc hin chng trnh sau (to mt mch ng h m pht, giy): MOV MOV MOV Lap: MOV MOV DIV MOV MOVC MOV CLR SETB MOV MOVC MOV A,30H B,#10 AB DPTR,#Maled7 A,@A+DPTR P2,A P1.1 P1.1 A,B A,@A+DPTR P2,A
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CLR SETB MOV MOV DIV MOV MOVC MOV CLR SETB MOV MOVC MOV CLR SETB CALL INC MOV CJNE MOV INC MOV CJNE MOV SJMP Delay: PUSH MOV SETB MOV MOV
P1.0 P1.0 A,31H B,#10 AB DPTR,#Maled7 A,@A+DPTR P2,A P1.3 P1.3 A,B A,@A+DPTR P2,A P1.2 P1.2 Delay 31H A,31H A,#60,Lap 31H,#0 30H A,30H A,#60,Lap 30H,#0 Lap ; 60 pht th ; pht = 0 ; 60s (1 pht) th ; giy = 0 ; v tng pht ln 1
JNB CLR DJNZ CLR POP RET END CALL INC MOV CJNE MOV INC MOV CJNE MOV SJMP PUSH SETB MOV MOV JNB CLR CLR POP RET END
Sa chng trnh thc hin m giy v %giy. Delay 31H A,31H A,#100,Lap ; 100% s (1 s) th 31H,#0 30H A,30H A,#60,Lap 30H,#0 Lap 07 TR0 TH0,#HIGH(-10000) TL0,#LOW(-10000) TF0,$ TF0 TR0 07 ; 60 s th ; giy = 0 ; %giy = 0 ; v tng giy ln 1
Delay: ; To tr 10ms
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