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8
SIMULA@IN
W 1hls shows Lhe varlaLlon of Lhe MCS draln currenL wlLh gaLeLo
source volLage(vgs) aL Lwo dlfferenL LemperaLures (assumlng
consLanL vds)
W AL hlgh values of vgs Lhe LranslsLor has hlgher drlve currenL aL 1hls
can cause Lhe Llmlng aL lower LemperaLure Lo be worse Lhan hlgher
LemperaLure
W 1hls means LhaL Lhe seLup vlolaLlons need Lo be checked aL two
corners sLrong lowvolLage hlghLemp and sLrong lowvolLage
lowLemp
W Slmllarly hold vlolaLlons need Lo be checked aL Lwo corners sLrong
lowvolLage hlghLemp and sLrong lowvolLage lowLemp
9SICAL ACI@LC@UL
W hyslcal archlLecLure selecLlon has also been lmpacLed by scallng
Lhe LranslsLor slze
W 1he channel helghL ls baslcally more lmpacLed by scallng
W CaLe crosssecLlons and conLacL cross secLlons all conLlnue Lo
decrease
W 1he end resulL ls LhaL lnLracell reslsLances have become much more
slgnlflcanL
W Cne consequence of lncreased lnLracell 8 effecLs ls LhaL cell helghL
sLarLs Lo lmpacL opLlmal delay
W lncreaslng Channel helghLs reduces LoLal reslsLance and lmproves
performance
9ower a|| Se|ect|on
W ConLlnual scallng of meLal cross secLlons has also lmpacLed deslgn
of power supplles ln sLandard cells
W CfLen Lhere are now two or more power ra||s |n ||brar|es eg one
#always on' power supply for sLaLe reLenLlon and anoLher #acLlve on'
supply for Lhe remalnder of loglc whlch can be powered down
CLLL SLLLC@IN AND DLSIGN
Cell selecLlon ls heavlly lnfluenced by Lhe lnLended Lool sLream
W ower ManagemenL
W Leakage and MulLlvL
W Clock CaLlng
W Cells for Supply volLage varlaLlon
W Cells lor Plgh erfomance
W Cells lor uenslLy
W Cells lor Low CosL
9ower management
W ln 90nm Lechnology Lhe CaLe leakage ls of Lhe same order as Lhe
subLhreshold draln currenL and occurs ln Cn LranslsLors as well as
Cll LranslsLors AL Lhe same Llme dynamlc power ls lncreaslng Lhe
effecLlve power denslLy and drlvlng power managemenL for
LradlLlonal #power no lssue' hlgh performance deslgners
W Coupled wlLh demands for hlgh performance supplyvolLage scallng
ls screechlng Lo a near halL aL abouL 1v
Leakage and Mu|t|Vt
W Cne very common feaLure found ln recenL llbrarles ls hlghLhreshold
(Pv1) LranslsLors
W PlghvL LranslsLors reduce leakage currenLs aL Lhe sacrlflce of
performance uependlng on process deslgn rules cells can be
deslgned whlch lnLermlx Pv1 and lowvL (Lv1) LranslsLors or cells
may be elLher Pv1 or Lv1 As a consequence of dual and mulLlvL
processes llbrary slzes have also lncreased Lyplcally doubllng or
more ln slze
W ln Lechnologles where mulLlplevL ls noL feaslble one posslblllLy ls
Lo use dlfferenL gaLe lengLhs 1hls ls concepLually slmllar Lo mulLlple
vL Lhough lL can be compllcaLed and Lhe resulLs may be less
opLlmal
C|ock gat|ng
W Slnce volLage scallng has slowed oLher mechanlsms are used Lo
brlng down Lhe acLlve swlLchlng power Clock gaLlng ls almosL
mandaLory ln all powerconsclous deslgns ln 90nm 1hls requlres
several clock gaLlng cells 1yplcally Lhese cells need Lo have equal
rlse and fall delays Lo malnLaln clock duLy cycle
Ce||s for supp|y vo|tage var|at|on
W MulLlple volLages can be used ln dlfferenL ways Lo reduce leakage
whlle maxlmlzlng performance Cne way ls Lo creaLe dlfferenL
deslgn blocks worklng aL dlfferenL volLages based on Lhe
performance requlremenLs of each block AnoLher ls Lo have
W sLorage elemenLs LhaL reLaln daLa uslng an auxlllary supply whlle
Lhe maln supply ls Lurned off whenever Lhe clrculL ls ln sLandby
mode ?eL anoLher approach ls Lo lower Lhe power supply when Lhe
clrculL ls noL acLlve
Ce||s for h|gh performance
W 1o sLay on Lhe expecLed performance curve ASlC llbrarles wlll have
Lo lnclude fasLer buL hlgher rlsk cells LhaL have noL normally been
used ln ASlC deslgns Lxamples are unbuffered Lransmlsslon gaLes
1hoL muxes alLernaLe flop sLyles llke pulsed flop and dynamlc
flop
W Speclal characLerlzaLlon and enhancemenL Lo deslgn flows Lo
conLrol and check use of Lhese cells ls crlLlcal Lo avold problems
Ce||s for Dens|ty
W AL 90nm deslgners are forced Lo Lhlnk of new layouL archlLecLures
Lo regaln denslLy 1hls lncludes dlfferenL cellhelghLs power bus
archlLecLures use of hlgherlevel meLal ln cells and power ralls
poslLlonlng of Lhe subsLraLe connecLlons eLc Llbrary composlLlon
has also changed
Ce||s for |ow cost
W CosLs ln Lerms of masks cycle Llme have drlven Lhe use of CaLe
Array sLyle cells for some Llme
W Some markeL segmenLs may be able Lo use slllcon plaLform sLyle
deslgn Lo furLher reduce cosLs
CI9 LLVLL ISSULS
W lnLegraLlon
W uaLa
W CrossLalk
W LlecLromlgraLlon(LM)
CNCLUSIN
W CreaLlng a 90nm llbrary was more dlfflculL Lhan
130nm by an order of magnlLude
W 1here are new and exclLlng challenges for 63nm LhaL
wlll also be overcome by creaLlve englneers and new
Lools
W 90 nm ASlC ls noL dead 1hls sLaLemenL would noL be
posslble wlLhouL exLenslve changes ln almosL every
aspecL of process deslgn layouL exLracLlon
characLerlzaLlon modellng marglns and of course
chlp deslgn