UNIT III

INTRODUCTION TO VHDL
 TOPICS TO BE COVERED

• DIGITAL SYSTEM DESIGN HIERARCHY

• DESIGN FLOW

• TOP-DOWN & BOTTOM-UP DESIGN FLOW

 SYSTEM DI
O F G
IT

le
Cell­Based

Se
FPGA
D

ab
AL

m
L

m
Co

i­C
m
r
R o ASIC Gate  ntr

ra
ss PLD

us
e oll

og
O oc Arrays e
IC

t
e r C

om
r
os

Pr
op hip
W Micr
rp Full­Custom
AS
  Pu MODULE S P
ral Mo
e

DECODER
G en RAM de
m
 &
  S Combinational Sequential  C
hip
AM R
DR E
X G
LOGIC GATE
Dynamic

M
Static

EM
∑ D Q M
B
A

OR
U
Ci
Basic X

Y
FA
S
CIRCUIT Co
Simple Complex
Parallel Series
Connection CMOS Inverter Connection

DEVICE
n+ n+ n p
p
n+ p n+

Bipolar Diode
MOSFET
Copy Right Dept of Electronics
August 2002 Carleton University
Maitham Shams Ottawa, CANADA
 IC Design Steps
High-level Structural
Specifications
Description Description

Behavioral Structural
VHDL, C VHDL

Figs. [©Sherwani]
 IC Design Steps (cont.)
High-level Structural
Specifications
Description Description

Synthesis
Physical Technology
Design Mapping
Placed Logic
& Routed Gate-level
Design Description
Design

Packaging Fabri- X=(AB*CD)+

cation (A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))

Figs. [©Sherwani]
 IC Design Steps (cont.)
High-level Structural
Specifications
Description Description

Synthesis
Physical Technology
Design Mapping
Placed Logic
& Routed Gate-level
Design Description
Design

Packaging Fabri-
cation
 The IC Design Methods
Design Cost / Quality % Companies
Methods Development involved
Time
Full Custom

Standard Cell
Library Design

ASIC – Standard
Cell Design

RTL-Level Design
Design abstraction levels
High
System Specification

Level of Abstraction System

Functional Module +

Gate

Circuit

G
Device S D

Low